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ARM: meson: dts: add basic Meson/Meson6/Meson6-atv1200 DTSI/DTS The Meson6 SoC is produced by Amlogic inc. and it is based on 2 Cortex A9 and an ARM Mali-400 GPU. This patch adds two basic DTSI for the preliminary support of Meson and Meson6 SoCs. Another DTS is also added for supporting the atv1200 board, produced by Geniatech inc. Signed-off-by: Carlo Caione <carlo@caione.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-09-10 04:12:56 +08:00
/*
* Copyright 2014 Carlo Caione <carlo@caione.org>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this library; if not, write to the Free
* Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
ARM: dts: meson: use GIC_SPI and IRQ_TYPE_EDGE_RISING macros This makes meson.dtsi easier to read as we are not using magic numbers for the GIC interrupt type (GIC_SPI) and the interrupt polarity (IRQ_TYPE_EDGE_RISING). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-06-16 05:33:44 +08:00
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
ARM: meson: dts: add basic Meson/Meson6/Meson6-atv1200 DTSI/DTS The Meson6 SoC is produced by Amlogic inc. and it is based on 2 Cortex A9 and an ARM Mali-400 GPU. This patch adds two basic DTSI for the preliminary support of Meson and Meson6 SoCs. Another DTS is also added for supporting the atv1200 board, produced by Geniatech inc. Signed-off-by: Carlo Caione <carlo@caione.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-09-10 04:12:56 +08:00
/include/ "skeleton.dtsi"
/ {
interrupt-parent = <&gic>;
ARM: meson: DTS: enable L2 cache This enables the L2 cache controller available in Amlogic SoCs. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Carlo Caione <carlo@caione.org>
2014-11-18 22:30:35 +08:00
L2: l2-cache-controller@c4200000 {
compatible = "arm,pl310-cache";
reg = <0xc4200000 0x1000>;
cache-unified;
cache-level = <2>;
};
ARM: meson: dts: add basic Meson/Meson6/Meson6-atv1200 DTSI/DTS The Meson6 SoC is produced by Amlogic inc. and it is based on 2 Cortex A9 and an ARM Mali-400 GPU. This patch adds two basic DTSI for the preliminary support of Meson and Meson6 SoCs. Another DTS is also added for supporting the atv1200 board, produced by Geniatech inc. Signed-off-by: Carlo Caione <carlo@caione.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-09-10 04:12:56 +08:00
gic: interrupt-controller@c4301000 {
compatible = "arm,cortex-a9-gic";
reg = <0xc4301000 0x1000>,
<0xc4300100 0x0100>;
interrupt-controller;
#interrupt-cells = <3>;
};
soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
ARM: dts: meson: organize devices in their corresponding busses The Amlogic Meson SoCs have most of the internal peripherals organized in busses. Use them to make the dts easier to read and to avoid duplicated register (bus) offset definitions. The bus information is taken from the vendor kernel: #define IO_CBUS_PHY_BASE 0xc1100000 ///2M #define IO_AOBUS_PHY_BASE 0xc8100000 ///1M There are more internal busses (such as the abp bus which seems to contain audio, HDMI and Mali registers), but since we don't have drivers for them yet these are not added (yet). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> [khilman: minor whitespace fix] Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-04-18 05:39:37 +08:00
cbus: cbus@c1100000 {
compatible = "simple-bus";
reg = <0xc1100000 0x200000>;
ARM: dts: meson: add I2C controller nodes Add nodes for I2C controllers A,B,AO, which are available in both Meson6 and Meson8. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Signed-off-by: Carlo Caione <carlo@caione.org>
2014-11-14 03:32:03 +08:00
#address-cells = <1>;
ARM: dts: meson: organize devices in their corresponding busses The Amlogic Meson SoCs have most of the internal peripherals organized in busses. Use them to make the dts easier to read and to avoid duplicated register (bus) offset definitions. The bus information is taken from the vendor kernel: #define IO_CBUS_PHY_BASE 0xc1100000 ///2M #define IO_AOBUS_PHY_BASE 0xc8100000 ///1M There are more internal busses (such as the abp bus which seems to contain audio, HDMI and Mali registers), but since we don't have drivers for them yet these are not added (yet). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> [khilman: minor whitespace fix] Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-04-18 05:39:37 +08:00
#size-cells = <1>;
ranges = <0x0 0xc1100000 0x200000>;
ARM: dts: meson: add the hardware random number generator All supported Meson SoCs have a random number generator in CBUS. Newer SoCs (GXBB, GXL and GXM) provide only one 32-bit random number register, whereas the older SoCs (Meson6, Meson8 and Meson8b) have two 32-bit random number registers. The existing meson-rng driver only supports the lower 32-bit - but it still works fine on the older SoCs apart from this small limitation. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-06-16 05:33:49 +08:00
hwrng: rng@8100 {
compatible = "amlogic,meson-rng";
reg = <0x8100 0x8>;
};
ARM: dts: meson: organize devices in their corresponding busses The Amlogic Meson SoCs have most of the internal peripherals organized in busses. Use them to make the dts easier to read and to avoid duplicated register (bus) offset definitions. The bus information is taken from the vendor kernel: #define IO_CBUS_PHY_BASE 0xc1100000 ///2M #define IO_AOBUS_PHY_BASE 0xc8100000 ///1M There are more internal busses (such as the abp bus which seems to contain audio, HDMI and Mali registers), but since we don't have drivers for them yet these are not added (yet). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> [khilman: minor whitespace fix] Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-04-18 05:39:37 +08:00
uart_A: serial@84c0 {
compatible = "amlogic,meson-uart";
reg = <0x84c0 0x18>;
ARM: dts: meson: use GIC_SPI and IRQ_TYPE_EDGE_RISING macros This makes meson.dtsi easier to read as we are not using magic numbers for the GIC interrupt type (GIC_SPI) and the interrupt polarity (IRQ_TYPE_EDGE_RISING). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-06-16 05:33:44 +08:00
interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
ARM: dts: meson: organize devices in their corresponding busses The Amlogic Meson SoCs have most of the internal peripherals organized in busses. Use them to make the dts easier to read and to avoid duplicated register (bus) offset definitions. The bus information is taken from the vendor kernel: #define IO_CBUS_PHY_BASE 0xc1100000 ///2M #define IO_AOBUS_PHY_BASE 0xc8100000 ///1M There are more internal busses (such as the abp bus which seems to contain audio, HDMI and Mali registers), but since we don't have drivers for them yet these are not added (yet). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> [khilman: minor whitespace fix] Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-04-18 05:39:37 +08:00
status = "disabled";
};
uart_B: serial@84dc {
compatible = "amlogic,meson-uart";
reg = <0x84dc 0x18>;
ARM: dts: meson: use GIC_SPI and IRQ_TYPE_EDGE_RISING macros This makes meson.dtsi easier to read as we are not using magic numbers for the GIC interrupt type (GIC_SPI) and the interrupt polarity (IRQ_TYPE_EDGE_RISING). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-06-16 05:33:44 +08:00
interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
ARM: dts: meson: organize devices in their corresponding busses The Amlogic Meson SoCs have most of the internal peripherals organized in busses. Use them to make the dts easier to read and to avoid duplicated register (bus) offset definitions. The bus information is taken from the vendor kernel: #define IO_CBUS_PHY_BASE 0xc1100000 ///2M #define IO_AOBUS_PHY_BASE 0xc8100000 ///1M There are more internal busses (such as the abp bus which seems to contain audio, HDMI and Mali registers), but since we don't have drivers for them yet these are not added (yet). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> [khilman: minor whitespace fix] Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-04-18 05:39:37 +08:00
status = "disabled";
};
i2c_A: i2c@8500 {
compatible = "amlogic,meson6-i2c";
reg = <0x8500 0x20>;
ARM: dts: meson: use GIC_SPI and IRQ_TYPE_EDGE_RISING macros This makes meson.dtsi easier to read as we are not using magic numbers for the GIC interrupt type (GIC_SPI) and the interrupt polarity (IRQ_TYPE_EDGE_RISING). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-06-16 05:33:44 +08:00
interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
ARM: dts: meson: organize devices in their corresponding busses The Amlogic Meson SoCs have most of the internal peripherals organized in busses. Use them to make the dts easier to read and to avoid duplicated register (bus) offset definitions. The bus information is taken from the vendor kernel: #define IO_CBUS_PHY_BASE 0xc1100000 ///2M #define IO_AOBUS_PHY_BASE 0xc8100000 ///1M There are more internal busses (such as the abp bus which seems to contain audio, HDMI and Mali registers), but since we don't have drivers for them yet these are not added (yet). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> [khilman: minor whitespace fix] Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-04-18 05:39:37 +08:00
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
ARM: dts: meson: add the SAR ADC This adds the SAR ADC to meson.dtsi and configures the clocks on Meson8 and Meson8b to allow boards to use it. Some boards use it to connect a button to it. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-06-16 05:33:47 +08:00
saradc: adc@8680 {
compatible = "amlogic,meson-saradc";
reg = <0x8680 0x34>;
#io-channel-cells = <1>;
interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
};
ARM: dts: meson: organize devices in their corresponding busses The Amlogic Meson SoCs have most of the internal peripherals organized in busses. Use them to make the dts easier to read and to avoid duplicated register (bus) offset definitions. The bus information is taken from the vendor kernel: #define IO_CBUS_PHY_BASE 0xc1100000 ///2M #define IO_AOBUS_PHY_BASE 0xc8100000 ///1M There are more internal busses (such as the abp bus which seems to contain audio, HDMI and Mali registers), but since we don't have drivers for them yet these are not added (yet). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> [khilman: minor whitespace fix] Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-04-18 05:39:37 +08:00
uart_C: serial@8700 {
compatible = "amlogic,meson-uart";
reg = <0x8700 0x18>;
ARM: dts: meson: use GIC_SPI and IRQ_TYPE_EDGE_RISING macros This makes meson.dtsi easier to read as we are not using magic numbers for the GIC interrupt type (GIC_SPI) and the interrupt polarity (IRQ_TYPE_EDGE_RISING). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-06-16 05:33:44 +08:00
interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
ARM: dts: meson: organize devices in their corresponding busses The Amlogic Meson SoCs have most of the internal peripherals organized in busses. Use them to make the dts easier to read and to avoid duplicated register (bus) offset definitions. The bus information is taken from the vendor kernel: #define IO_CBUS_PHY_BASE 0xc1100000 ///2M #define IO_AOBUS_PHY_BASE 0xc8100000 ///1M There are more internal busses (such as the abp bus which seems to contain audio, HDMI and Mali registers), but since we don't have drivers for them yet these are not added (yet). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> [khilman: minor whitespace fix] Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-04-18 05:39:37 +08:00
status = "disabled";
};
i2c_B: i2c@87c0 {
compatible = "amlogic,meson6-i2c";
reg = <0x87c0 0x20>;
ARM: dts: meson: use GIC_SPI and IRQ_TYPE_EDGE_RISING macros This makes meson.dtsi easier to read as we are not using magic numbers for the GIC interrupt type (GIC_SPI) and the interrupt polarity (IRQ_TYPE_EDGE_RISING). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-06-16 05:33:44 +08:00
interrupts = <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>;
ARM: dts: meson: organize devices in their corresponding busses The Amlogic Meson SoCs have most of the internal peripherals organized in busses. Use them to make the dts easier to read and to avoid duplicated register (bus) offset definitions. The bus information is taken from the vendor kernel: #define IO_CBUS_PHY_BASE 0xc1100000 ///2M #define IO_AOBUS_PHY_BASE 0xc8100000 ///1M There are more internal busses (such as the abp bus which seems to contain audio, HDMI and Mali registers), but since we don't have drivers for them yet these are not added (yet). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> [khilman: minor whitespace fix] Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-04-18 05:39:37 +08:00
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
ARM: dts: meson: add USB support on Meson8 and Meson8b This adds the DWC2 USB controller nodes and the corresponding USB2 PHY nodes to meson.dtsi (as the same - or at least a very similar) IP block is used on all SoCs (at the same physical address). Additionally meson8.dtsi and meson8b.dtsi add the required clocks to the DWC2 and USB2 PHY nodes, otherwise the DWC2 controller cannot be initialized by the dwc2 driver. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-06-16 05:33:50 +08:00
usb0_phy: phy@8800 {
compatible = "amlogic,meson-mx-usb2-phy";
#phy-cells = <0>;
reg = <0x8800 0x20>;
status = "disabled";
};
usb1_phy: phy@8820 {
compatible = "amlogic,meson-mx-usb2-phy";
#phy-cells = <0>;
reg = <0x8820 0x20>;
status = "disabled";
};
ARM: dts: meson: organize devices in their corresponding busses The Amlogic Meson SoCs have most of the internal peripherals organized in busses. Use them to make the dts easier to read and to avoid duplicated register (bus) offset definitions. The bus information is taken from the vendor kernel: #define IO_CBUS_PHY_BASE 0xc1100000 ///2M #define IO_AOBUS_PHY_BASE 0xc8100000 ///1M There are more internal busses (such as the abp bus which seems to contain audio, HDMI and Mali registers), but since we don't have drivers for them yet these are not added (yet). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> [khilman: minor whitespace fix] Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-04-18 05:39:37 +08:00
spifc: spi@8c80 {
compatible = "amlogic,meson6-spifc";
reg = <0x8c80 0x80>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
wdt: watchdog@9900 {
compatible = "amlogic,meson6-wdt";
reg = <0x9900 0x8>;
ARM: dts: meson: use GIC_SPI and IRQ_TYPE_EDGE_RISING macros This makes meson.dtsi easier to read as we are not using magic numbers for the GIC interrupt type (GIC_SPI) and the interrupt polarity (IRQ_TYPE_EDGE_RISING). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-06-16 05:33:44 +08:00
interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
ARM: dts: meson: organize devices in their corresponding busses The Amlogic Meson SoCs have most of the internal peripherals organized in busses. Use them to make the dts easier to read and to avoid duplicated register (bus) offset definitions. The bus information is taken from the vendor kernel: #define IO_CBUS_PHY_BASE 0xc1100000 ///2M #define IO_AOBUS_PHY_BASE 0xc8100000 ///1M There are more internal busses (such as the abp bus which seems to contain audio, HDMI and Mali registers), but since we don't have drivers for them yet these are not added (yet). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> [khilman: minor whitespace fix] Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-04-18 05:39:37 +08:00
};
timer@9940 {
compatible = "amlogic,meson6-timer";
reg = <0x9940 0x18>;
ARM: dts: meson: use GIC_SPI and IRQ_TYPE_EDGE_RISING macros This makes meson.dtsi easier to read as we are not using magic numbers for the GIC interrupt type (GIC_SPI) and the interrupt polarity (IRQ_TYPE_EDGE_RISING). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-06-16 05:33:44 +08:00
interrupts = <GIC_SPI 10 IRQ_TYPE_EDGE_RISING>;
ARM: dts: meson: organize devices in their corresponding busses The Amlogic Meson SoCs have most of the internal peripherals organized in busses. Use them to make the dts easier to read and to avoid duplicated register (bus) offset definitions. The bus information is taken from the vendor kernel: #define IO_CBUS_PHY_BASE 0xc1100000 ///2M #define IO_AOBUS_PHY_BASE 0xc8100000 ///1M There are more internal busses (such as the abp bus which seems to contain audio, HDMI and Mali registers), but since we don't have drivers for them yet these are not added (yet). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> [khilman: minor whitespace fix] Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-04-18 05:39:37 +08:00
};
ARM: dts: meson: add I2C controller nodes Add nodes for I2C controllers A,B,AO, which are available in both Meson6 and Meson8. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Signed-off-by: Carlo Caione <carlo@caione.org>
2014-11-14 03:32:03 +08:00
};
media updates for v3.19-rc1 -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJUhxhbAAoJEAhfPr2O5OEV4JwP/2I7D2KGz5tdNGDAh1H8+swR hoj3tX7HLhwBmF6XIUlMYbk5L/ClDace6kcjT6OjwJ9SktrrKks6ZSsYsBjCIyOC yS7xNQArUKzWk4vV+uJVAvtF8V57LLFul8dhHk0JJwAxrkWnPvDdfJNs4PhUAkgn 1i0PPshNo5Ow/+4YMiOjEDR+q9TMSUUzaq5zkPF7AFCnykuJ1wUJwUE0qjTfGi+4 gl1yMye0TEawTYSM8h/+Lh7wosNFZYcXg85r04A6a8h6GLgg0h6KSOJjyPITmQ+j hLdtyiYs8a6XT+Y8o416zxpbSozo7KXCUTtet/N5g+lgQMqZqSd9WxE52SOY+kfd UVeob0VfWR0xdDzaJp5rLQ/MQ16RTHaHppgUidFxxGe9D5f9JM/88I0OfwNzl4uO cv2cyeNktHH6bcjfOGqxSVmZWgAm6q6qU7MN07PoN+5TcUlYTAOi1WLE5K+7HGgw CxzOZ61oxi/OO1FapaVoipq6ycjltTql2kbcARvmrRrbge0ocAqHxHqFyUbDDhNw Wn/O6VzLfpW0vGTacC6+xcUSpIhwajJ80UJAOqJP8sw0Xtmian5Lcs6gVzxwkOdU 36Po4RRGFqsG6Sq3HR+toNwKt/nHNEFkJwYcNFHdvBiXTEYYkMe6MccUxxb3i/iI KxB1s51zVy9t3PqjP+3J =i7gx -----END PGP SIGNATURE----- Merge tag 'media/v3.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media Pull media updates from Mauro Carvalho Chehab: - Two new dvb frontend drivers: mn88472 and mn88473 - A new driver for some PCIe DVBSky cards - A new remote controller driver: meson-ir - One LIRC staging driver got rewritten and promoted to mainstream: igorplugusb - A new tuner driver (m88rs6000t) - The old omap2 media driver got removed from staging. This driver uses an old DMA API and it is likely broken on recent kernels. Nobody cared enough to fix it - Media bus format moved to a separate header, as DRM will also use the definitions there - mem2mem_testdev were renamed to vim2m, in order to use the same naming convention taken by the other virtual test driver (vivid) - Added a new driver for coda SoC (coda-jpeg) - The cx88 driver got converted to use videobuf2 core - Make DMABUF export buffer to work with DMA Scatter/Gather and Vmalloc cores - Lots of other fixes, improvements and cleanups on the drivers. * tag 'media/v3.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media: (384 commits) [media] mn88473: One function call less in mn88473_init() after error [media] mn88473: Remove uneeded check before release_firmware() [media] lirc_zilog: Deletion of unnecessary checks before vfree() [media] MAINTAINERS: Add myself as img-ir maintainer [media] img-ir: Don't set driver's module owner [media] img-ir: Depend on METAG or MIPS or COMPILE_TEST [media] img-ir/hw: Drop [un]register_decoder declarations [media] img-ir/hw: Fix potential deadlock stopping timer [media] img-ir/hw: Always read data to clear buffer [media] redrat3: ensure dma is setup properly [media] ddbridge: remove unneeded check before dvb_unregister_device() [media] si2157: One function call less in si2157_init() after error [media] tuners: remove uneeded checks before release_firmware() [media] arm: omap2: rx51-peripherals: fix build warning [media] stv090x: add an extra protetion against buffer overflow [media] stv090x: Remove an unreachable code [media] stv090x: Some whitespace cleanups [media] em28xx: checkpatch cleanup: whitespaces/new lines cleanups [media] si2168: add support for firmware files in new format [media] si2168: debug printout for firmware version ...
2014-12-12 03:49:23 +08:00
ARM: dts: meson: organize devices in their corresponding busses The Amlogic Meson SoCs have most of the internal peripherals organized in busses. Use them to make the dts easier to read and to avoid duplicated register (bus) offset definitions. The bus information is taken from the vendor kernel: #define IO_CBUS_PHY_BASE 0xc1100000 ///2M #define IO_AOBUS_PHY_BASE 0xc8100000 ///1M There are more internal busses (such as the abp bus which seems to contain audio, HDMI and Mali registers), but since we don't have drivers for them yet these are not added (yet). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> [khilman: minor whitespace fix] Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-04-18 05:39:37 +08:00
aobus: aobus@c8100000 {
compatible = "simple-bus";
reg = <0xc8100000 0x100000>;
ARM: dts: meson: add node for SPIFC This adds a node for the SPI Flash Controller to the Amlogic Meson DTS. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Signed-off-by: Carlo Caione <carlo@endlessm.com> Acked-by: Mark Brown <broonie@kernel.org>
2015-03-02 03:39:51 +08:00
#address-cells = <1>;
ARM: dts: meson: organize devices in their corresponding busses The Amlogic Meson SoCs have most of the internal peripherals organized in busses. Use them to make the dts easier to read and to avoid duplicated register (bus) offset definitions. The bus information is taken from the vendor kernel: #define IO_CBUS_PHY_BASE 0xc1100000 ///2M #define IO_AOBUS_PHY_BASE 0xc8100000 ///1M There are more internal busses (such as the abp bus which seems to contain audio, HDMI and Mali registers), but since we don't have drivers for them yet these are not added (yet). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> [khilman: minor whitespace fix] Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-04-18 05:39:37 +08:00
#size-cells = <1>;
ranges = <0x0 0xc8100000 0x100000>;
ir_receiver: ir-receiver@480 {
compatible= "amlogic,meson6-ir";
reg = <0x480 0x20>;
ARM: dts: meson: use GIC_SPI and IRQ_TYPE_EDGE_RISING macros This makes meson.dtsi easier to read as we are not using magic numbers for the GIC interrupt type (GIC_SPI) and the interrupt polarity (IRQ_TYPE_EDGE_RISING). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-06-16 05:33:44 +08:00
interrupts = <GIC_SPI 15 IRQ_TYPE_EDGE_RISING>;
ARM: dts: meson: organize devices in their corresponding busses The Amlogic Meson SoCs have most of the internal peripherals organized in busses. Use them to make the dts easier to read and to avoid duplicated register (bus) offset definitions. The bus information is taken from the vendor kernel: #define IO_CBUS_PHY_BASE 0xc1100000 ///2M #define IO_AOBUS_PHY_BASE 0xc8100000 ///1M There are more internal busses (such as the abp bus which seems to contain audio, HDMI and Mali registers), but since we don't have drivers for them yet these are not added (yet). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> [khilman: minor whitespace fix] Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-04-18 05:39:37 +08:00
status = "disabled";
};
uart_AO: serial@4c0 {
compatible = "amlogic,meson-uart";
reg = <0x4c0 0x18>;
ARM: dts: meson: use GIC_SPI and IRQ_TYPE_EDGE_RISING macros This makes meson.dtsi easier to read as we are not using magic numbers for the GIC interrupt type (GIC_SPI) and the interrupt polarity (IRQ_TYPE_EDGE_RISING). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-06-16 05:33:44 +08:00
interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
ARM: dts: meson: organize devices in their corresponding busses The Amlogic Meson SoCs have most of the internal peripherals organized in busses. Use them to make the dts easier to read and to avoid duplicated register (bus) offset definitions. The bus information is taken from the vendor kernel: #define IO_CBUS_PHY_BASE 0xc1100000 ///2M #define IO_AOBUS_PHY_BASE 0xc8100000 ///1M There are more internal busses (such as the abp bus which seems to contain audio, HDMI and Mali registers), but since we don't have drivers for them yet these are not added (yet). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> [khilman: minor whitespace fix] Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-04-18 05:39:37 +08:00
status = "disabled";
};
i2c_AO: i2c@500 {
compatible = "amlogic,meson6-i2c";
reg = <0x500 0x20>;
ARM: dts: meson: use GIC_SPI and IRQ_TYPE_EDGE_RISING macros This makes meson.dtsi easier to read as we are not using magic numbers for the GIC interrupt type (GIC_SPI) and the interrupt polarity (IRQ_TYPE_EDGE_RISING). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-06-16 05:33:44 +08:00
interrupts = <GIC_SPI 92 IRQ_TYPE_EDGE_RISING>;
ARM: dts: meson: organize devices in their corresponding busses The Amlogic Meson SoCs have most of the internal peripherals organized in busses. Use them to make the dts easier to read and to avoid duplicated register (bus) offset definitions. The bus information is taken from the vendor kernel: #define IO_CBUS_PHY_BASE 0xc1100000 ///2M #define IO_AOBUS_PHY_BASE 0xc8100000 ///1M There are more internal busses (such as the abp bus which seems to contain audio, HDMI and Mali registers), but since we don't have drivers for them yet these are not added (yet). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> [khilman: minor whitespace fix] Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-04-18 05:39:37 +08:00
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
ARM: dts: meson: add node for SPIFC This adds a node for the SPI Flash Controller to the Amlogic Meson DTS. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Signed-off-by: Carlo Caione <carlo@endlessm.com> Acked-by: Mark Brown <broonie@kernel.org>
2015-03-02 03:39:51 +08:00
};
ARM: dts: meson: enable Ethernet controller Add a node for the Ethernet controller to Meson DTS file and enable it on the Geniatech ATV1200 board. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Signed-off-by: Carlo Caione <carlo@endlessm.com>
2015-03-02 03:45:37 +08:00
ARM: dts: meson: add USB support on Meson8 and Meson8b This adds the DWC2 USB controller nodes and the corresponding USB2 PHY nodes to meson.dtsi (as the same - or at least a very similar) IP block is used on all SoCs (at the same physical address). Additionally meson8.dtsi and meson8b.dtsi add the required clocks to the DWC2 and USB2 PHY nodes, otherwise the DWC2 controller cannot be initialized by the dwc2 driver. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-06-16 05:33:50 +08:00
usb0: usb@c9040000 {
compatible = "snps,dwc2";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xc9040000 0x40000>;
interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>;
phys = <&usb0_phy>;
phy-names = "usb2-phy";
dr_mode = "host";
status = "disabled";
};
usb1: usb@c90c0000 {
compatible = "snps,dwc2";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xc90c0000 0x40000>;
interrupts = <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>;
phys = <&usb1_phy>;
phy-names = "usb2-phy";
dr_mode = "host";
status = "disabled";
};
ARM: dts: meson: enable Ethernet controller Add a node for the Ethernet controller to Meson DTS file and enable it on the Geniatech ATV1200 board. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Signed-off-by: Carlo Caione <carlo@endlessm.com>
2015-03-02 03:45:37 +08:00
ethmac: ethernet@c9410000 {
compatible = "amlogic,meson6-dwmac", "snps,dwmac";
reg = <0xc9410000 0x10000
0xc1108108 0x4>;
ARM: dts: meson: use GIC_SPI and IRQ_TYPE_EDGE_RISING macros This makes meson.dtsi easier to read as we are not using magic numbers for the GIC interrupt type (GIC_SPI) and the interrupt polarity (IRQ_TYPE_EDGE_RISING). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-06-16 05:33:44 +08:00
interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>;
ARM: dts: meson: enable Ethernet controller Add a node for the Ethernet controller to Meson DTS file and enable it on the Geniatech ATV1200 board. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Signed-off-by: Carlo Caione <carlo@endlessm.com>
2015-03-02 03:45:37 +08:00
interrupt-names = "macirq";
status = "disabled";
};
ARM: meson: dts: add basic Meson/Meson6/Meson6-atv1200 DTSI/DTS The Meson6 SoC is produced by Amlogic inc. and it is based on 2 Cortex A9 and an ARM Mali-400 GPU. This patch adds two basic DTSI for the preliminary support of Meson and Meson6 SoCs. Another DTS is also added for supporting the atv1200 board, produced by Geniatech inc. Signed-off-by: Carlo Caione <carlo@caione.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-09-10 04:12:56 +08:00
};
}; /* end of / */
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