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90 lines
1.2 KiB
Plaintext
90 lines
1.2 KiB
Plaintext
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2016 PHYTEC Messtechnik GmbH
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* Author: Christian Hemp <c.hemp@phytec.de>
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*/
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/dts-v1/;
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#include "imx6ul-phytec-pcl063.dtsi"
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#include "imx6ul-phytec-phyboard-segin.dtsi"
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#include "imx6ul-phytec-peb-eval-01.dtsi"
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/ {
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model = "Phytec phyBOARD-Segin i.MX6 UltraLite Full Featured";
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compatible = "phytec,imx6ul-pbacd10", "phytec,imx6ul-pcl063", "fsl,imx6ul";
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};
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&adc1 {
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status = "okay";
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};
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&can1 {
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status = "okay";
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};
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&tlv320 {
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status = "okay";
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};
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&ecspi3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ecspi3>;
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cs-gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>;
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status = "okay";
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};
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&fec2 {
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status = "okay";
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};
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&i2c_rtc {
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status = "okay";
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};
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®_can1_en {
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status = "okay";
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};
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®_sound_1v8 {
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status = "okay";
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};
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®_sound_3v3 {
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status = "okay";
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};
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&sai2 {
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status = "okay";
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};
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&sound {
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status = "okay";
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};
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&uart5 {
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status = "okay";
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};
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&usbotg1 {
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status = "okay";
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};
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&usbotg2 {
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status = "okay";
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};
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&usdhc1 {
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status = "okay";
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};
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&iomuxc {
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pinctrl_ecspi3: ecspi3grp {
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fsl,pins = <
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MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x10b0
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MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x10b0
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MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x10b0
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MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x10b0
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>;
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};
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};
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