License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default
license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license
identifiers to apply.
- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:
SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became
the concluded license(s).
- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.
In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.
Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 22:07:57 +08:00
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// SPDX-License-Identifier: GPL-2.0
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2014-09-05 06:20:35 +08:00
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/dts-v1/;
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2015-03-18 17:52:17 +08:00
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#include "tegra124-nyan.dtsi"
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2014-09-05 06:20:35 +08:00
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2015-03-12 22:48:08 +08:00
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#include "tegra124-nyan-big-emc.dtsi"
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2014-09-05 06:20:35 +08:00
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/ {
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model = "Acer Chromebook 13 CB5-311";
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2017-01-22 23:47:50 +08:00
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compatible = "google,nyan-big-rev7", "google,nyan-big-rev6",
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"google,nyan-big-rev5", "google,nyan-big-rev4",
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"google,nyan-big-rev3", "google,nyan-big-rev2",
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"google,nyan-big-rev1", "google,nyan-big-rev0",
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"google,nyan-big", "google,nyan", "nvidia,tegra124";
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2014-09-05 06:20:35 +08:00
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2015-03-18 17:52:17 +08:00
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panel: panel {
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compatible = "auo,b133xtn01";
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2014-09-05 06:20:35 +08:00
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2015-03-18 17:52:17 +08:00
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backlight = <&backlight>;
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ddc-i2c-bus = <&dpaux>;
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2014-09-05 06:20:35 +08:00
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};
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2016-06-30 06:21:37 +08:00
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sdhci@700b0400 { /* SD Card on this bus */
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2015-03-18 17:52:17 +08:00
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wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
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};
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2014-09-05 06:20:35 +08:00
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2015-03-18 17:52:17 +08:00
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sound {
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compatible = "nvidia,tegra-audio-max98090-nyan-big",
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"nvidia,tegra-audio-max98090-nyan",
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"nvidia,tegra-audio-max98090";
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nvidia,model = "GoogleNyanBig";
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2014-09-05 06:20:35 +08:00
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};
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2016-06-30 06:21:37 +08:00
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pinmux@70000868 {
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2014-09-05 06:20:35 +08:00
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pinctrl-names = "default";
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pinctrl-0 = <&pinmux_default>;
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pinmux_default: common {
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2015-03-18 17:52:22 +08:00
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clk_32k_out_pa0 {
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nvidia,pins = "clk_32k_out_pa0";
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2014-09-05 06:20:35 +08:00
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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2015-03-18 17:52:22 +08:00
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uart3_cts_n_pa1 {
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nvidia,pins = "uart3_cts_n_pa1";
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nvidia,function = "gmi";
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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2014-09-05 06:20:35 +08:00
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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};
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2015-03-18 17:52:22 +08:00
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dap2_fs_pa2 {
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nvidia,pins = "dap2_fs_pa2";
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nvidia,function = "i2s1";
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2014-09-05 06:20:35 +08:00
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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2015-03-18 17:52:22 +08:00
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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2014-09-05 06:20:35 +08:00
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};
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2015-03-18 17:52:22 +08:00
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dap2_sclk_pa3 {
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nvidia,pins = "dap2_sclk_pa3";
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nvidia,function = "i2s1";
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2014-09-05 06:20:35 +08:00
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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2015-03-18 17:52:22 +08:00
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dap2_din_pa4 {
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nvidia,pins = "dap2_din_pa4";
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nvidia,function = "i2s1";
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2014-09-05 06:20:35 +08:00
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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2015-03-18 17:52:22 +08:00
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dap2_dout_pa5 {
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nvidia,pins = "dap2_dout_pa5";
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nvidia,function = "i2s1";
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2014-09-05 06:20:35 +08:00
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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2015-03-18 17:52:22 +08:00
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sdmmc3_clk_pa6 {
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nvidia,pins = "sdmmc3_clk_pa6";
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nvidia,function = "sdmmc3";
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2014-09-05 06:20:35 +08:00
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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2015-03-18 17:52:22 +08:00
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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2014-09-05 06:20:35 +08:00
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};
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2015-03-18 17:52:22 +08:00
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sdmmc3_cmd_pa7 {
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nvidia,pins = "sdmmc3_cmd_pa7";
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nvidia,function = "sdmmc3";
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2014-09-05 06:20:35 +08:00
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nvidia,pull = <TEGRA_PIN_PULL_UP>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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2015-03-18 17:52:22 +08:00
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pb0 {
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nvidia,pins = "pb0";
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nvidia,function = "rsvd2";
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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2014-09-05 06:20:35 +08:00
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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};
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2015-03-18 17:52:22 +08:00
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pb1 {
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nvidia,pins = "pb1";
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nvidia,function = "rsvd2";
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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2014-09-05 06:20:35 +08:00
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};
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2015-03-18 17:52:22 +08:00
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sdmmc3_dat3_pb4 {
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nvidia,pins = "sdmmc3_dat3_pb4";
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2014-09-05 06:20:35 +08:00
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nvidia,function = "sdmmc3";
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2015-03-18 17:52:22 +08:00
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nvidia,pull = <TEGRA_PIN_PULL_UP>;
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2014-09-05 06:20:35 +08:00
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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2015-03-18 17:52:22 +08:00
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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2014-09-05 06:20:35 +08:00
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};
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2015-03-18 17:52:22 +08:00
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sdmmc3_dat2_pb5 {
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nvidia,pins = "sdmmc3_dat2_pb5";
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2014-09-05 06:20:35 +08:00
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nvidia,function = "sdmmc3";
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nvidia,pull = <TEGRA_PIN_PULL_UP>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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2015-03-18 17:52:22 +08:00
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sdmmc3_dat1_pb6 {
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nvidia,pins = "sdmmc3_dat1_pb6";
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nvidia,function = "sdmmc3";
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2014-09-05 06:20:35 +08:00
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nvidia,pull = <TEGRA_PIN_PULL_UP>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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2015-03-18 17:52:22 +08:00
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sdmmc3_dat0_pb7 {
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nvidia,pins = "sdmmc3_dat0_pb7";
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nvidia,function = "sdmmc3";
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2014-09-05 06:20:35 +08:00
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nvidia,pull = <TEGRA_PIN_PULL_UP>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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2015-03-18 17:52:22 +08:00
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uart3_rts_n_pc0 {
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nvidia,pins = "uart3_rts_n_pc0";
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nvidia,function = "gmi";
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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2014-09-05 06:20:35 +08:00
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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};
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2015-03-18 17:52:22 +08:00
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uart2_txd_pc2 {
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nvidia,pins = "uart2_txd_pc2";
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nvidia,function = "irda";
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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2014-09-05 06:20:35 +08:00
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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};
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2015-03-18 17:52:22 +08:00
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uart2_rxd_pc3 {
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nvidia,pins = "uart2_rxd_pc3";
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nvidia,function = "irda";
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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2014-09-05 06:20:35 +08:00
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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};
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2015-03-18 17:52:22 +08:00
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gen1_i2c_scl_pc4 {
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nvidia,pins = "gen1_i2c_scl_pc4";
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nvidia,function = "i2c1";
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2014-09-05 06:20:35 +08:00
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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2015-03-18 17:52:22 +08:00
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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nvidia,open-drain = <TEGRA_PIN_ENABLE>;
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2014-09-05 06:20:35 +08:00
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};
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gen1_i2c_sda_pc5 {
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2015-03-18 17:52:22 +08:00
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nvidia,pins = "gen1_i2c_sda_pc5";
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2014-09-05 06:20:35 +08:00
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nvidia,function = "i2c1";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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2015-03-18 17:52:22 +08:00
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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2014-09-05 06:20:35 +08:00
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nvidia,open-drain = <TEGRA_PIN_ENABLE>;
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};
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2015-03-18 17:52:22 +08:00
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pc7 {
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nvidia,pins = "pc7";
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2014-09-05 06:20:35 +08:00
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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2015-03-18 17:52:22 +08:00
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};
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pg0 {
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nvidia,pins = "pg0";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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2014-09-05 06:20:35 +08:00
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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2015-03-18 17:52:22 +08:00
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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2014-09-05 06:20:35 +08:00
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};
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2015-03-18 17:52:22 +08:00
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pg1 {
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nvidia,pins = "pg1";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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2014-09-05 06:20:35 +08:00
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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2015-03-18 17:52:22 +08:00
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};
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pg2 {
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nvidia,pins = "pg2";
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2014-09-05 06:20:35 +08:00
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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2015-03-18 17:52:22 +08:00
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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2014-09-05 06:20:35 +08:00
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};
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2015-03-18 17:52:22 +08:00
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pg3 {
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nvidia,pins = "pg3";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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2014-09-05 06:20:35 +08:00
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
2015-03-18 17:52:22 +08:00
|
|
|
pg4 {
|
|
|
|
nvidia,pins = "pg4";
|
|
|
|
nvidia,function = "spi4";
|
2014-09-05 06:20:35 +08:00
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
2015-03-18 17:52:22 +08:00
|
|
|
pg5 {
|
|
|
|
nvidia,pins = "pg5";
|
|
|
|
nvidia,function = "spi4";
|
2014-09-05 06:20:35 +08:00
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
2015-03-18 17:52:22 +08:00
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
2014-09-05 06:20:35 +08:00
|
|
|
};
|
2015-03-18 17:52:22 +08:00
|
|
|
pg6 {
|
|
|
|
nvidia,pins = "pg6";
|
|
|
|
nvidia,function = "spi4";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
pg7 {
|
|
|
|
nvidia,pins = "pg7";
|
|
|
|
nvidia,function = "spi4";
|
2014-09-05 06:20:35 +08:00
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
2015-03-18 17:52:22 +08:00
|
|
|
ph0 {
|
|
|
|
nvidia,pins = "ph0";
|
2014-09-05 06:20:35 +08:00
|
|
|
nvidia,function = "gmi";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
2015-03-18 17:52:22 +08:00
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
2014-09-05 06:20:35 +08:00
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
2015-03-18 17:52:22 +08:00
|
|
|
ph1 {
|
|
|
|
nvidia,pins = "ph1";
|
|
|
|
nvidia,function = "pwm1";
|
2014-09-05 06:20:35 +08:00
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
2015-03-18 17:52:22 +08:00
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
2014-09-05 06:20:35 +08:00
|
|
|
};
|
2015-03-18 17:52:22 +08:00
|
|
|
ph2 {
|
|
|
|
nvidia,pins = "ph2";
|
2014-09-05 06:20:35 +08:00
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
2015-03-18 17:52:22 +08:00
|
|
|
ph3 {
|
|
|
|
nvidia,pins = "ph3";
|
2014-09-05 06:20:35 +08:00
|
|
|
nvidia,function = "gmi";
|
2015-03-18 17:52:22 +08:00
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
ph4 {
|
|
|
|
nvidia,pins = "ph4";
|
2014-09-05 06:20:35 +08:00
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
2015-03-18 17:52:22 +08:00
|
|
|
ph5 {
|
|
|
|
nvidia,pins = "ph5";
|
|
|
|
nvidia,function = "rsvd2";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
2014-09-05 06:20:35 +08:00
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
2015-03-18 17:52:22 +08:00
|
|
|
ph6 {
|
|
|
|
nvidia,pins = "ph6";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
2014-09-05 06:20:35 +08:00
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
2015-03-18 17:52:22 +08:00
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
2014-09-05 06:20:35 +08:00
|
|
|
};
|
|
|
|
ph7 {
|
|
|
|
nvidia,pins = "ph7";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
2015-03-18 17:52:22 +08:00
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
2014-09-05 06:20:35 +08:00
|
|
|
};
|
2015-03-18 17:52:22 +08:00
|
|
|
pi0 {
|
|
|
|
nvidia,pins = "pi0";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
2014-09-05 06:20:35 +08:00
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
2015-03-18 17:52:22 +08:00
|
|
|
pi1 {
|
|
|
|
nvidia,pins = "pi1";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
2014-09-05 06:20:35 +08:00
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
2015-03-18 17:52:22 +08:00
|
|
|
pi2 {
|
|
|
|
nvidia,pins = "pi2";
|
2014-09-05 06:20:35 +08:00
|
|
|
nvidia,function = "rsvd4";
|
2015-03-18 17:52:22 +08:00
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
pi3 {
|
|
|
|
nvidia,pins = "pi3";
|
|
|
|
nvidia,function = "spi4";
|
2014-09-05 06:20:35 +08:00
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
2015-03-18 17:52:22 +08:00
|
|
|
pi4 {
|
|
|
|
nvidia,pins = "pi4";
|
2014-09-05 06:20:35 +08:00
|
|
|
nvidia,function = "gmi";
|
2015-03-18 17:52:22 +08:00
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
pi5 {
|
|
|
|
nvidia,pins = "pi5";
|
2014-09-05 06:20:35 +08:00
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
2015-03-18 17:52:22 +08:00
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
2014-09-05 06:20:35 +08:00
|
|
|
};
|
2015-03-18 17:52:22 +08:00
|
|
|
pi6 {
|
2014-09-05 06:20:35 +08:00
|
|
|
nvidia,pins = "pi6";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
2015-03-18 17:52:22 +08:00
|
|
|
pi7 {
|
|
|
|
nvidia,pins = "pi7";
|
2014-09-05 06:20:35 +08:00
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
2015-03-18 17:52:22 +08:00
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
2014-09-05 06:20:35 +08:00
|
|
|
};
|
2015-03-18 17:52:22 +08:00
|
|
|
pj0 {
|
|
|
|
nvidia,pins = "pj0";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
pj2 {
|
|
|
|
nvidia,pins = "pj2";
|
|
|
|
nvidia,function = "rsvd1";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
2014-09-05 06:20:35 +08:00
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
2015-03-18 17:52:22 +08:00
|
|
|
uart2_cts_n_pj5 {
|
|
|
|
nvidia,pins = "uart2_cts_n_pj5";
|
|
|
|
nvidia,function = "gmi";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
uart2_rts_n_pj6 {
|
|
|
|
nvidia,pins = "uart2_rts_n_pj6";
|
|
|
|
nvidia,function = "gmi";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
pj7 {
|
|
|
|
nvidia,pins = "pj7";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
pk0 {
|
|
|
|
nvidia,pins = "pk0";
|
|
|
|
nvidia,function = "rsvd1";
|
2014-09-05 06:20:35 +08:00
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
2015-03-18 17:52:22 +08:00
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
pk1 {
|
|
|
|
nvidia,pins = "pk1";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
2014-09-05 06:20:35 +08:00
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
2015-03-18 17:52:22 +08:00
|
|
|
pk2 {
|
|
|
|
nvidia,pins = "pk2";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
pk3 {
|
|
|
|
nvidia,pins = "pk3";
|
2014-09-05 06:20:35 +08:00
|
|
|
nvidia,function = "gmi";
|
2015-03-18 17:52:22 +08:00
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
pk4 {
|
|
|
|
nvidia,pins = "pk4";
|
2014-09-05 06:20:35 +08:00
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
2015-03-18 17:52:22 +08:00
|
|
|
spdif_out_pk5 {
|
|
|
|
nvidia,pins = "spdif_out_pk5";
|
|
|
|
nvidia,function = "rsvd2";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
spdif_in_pk6 {
|
|
|
|
nvidia,pins = "spdif_in_pk6";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
pk7 {
|
|
|
|
nvidia,pins = "pk7";
|
2014-09-05 06:20:35 +08:00
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
2015-03-18 17:52:22 +08:00
|
|
|
dap1_fs_pn0 {
|
|
|
|
nvidia,pins = "dap1_fs_pn0";
|
|
|
|
nvidia,function = "rsvd4";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
dap1_din_pn1 {
|
|
|
|
nvidia,pins = "dap1_din_pn1";
|
|
|
|
nvidia,function = "rsvd4";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
dap1_dout_pn2 {
|
|
|
|
nvidia,pins = "dap1_dout_pn2";
|
|
|
|
nvidia,function = "i2s0";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
dap1_sclk_pn3 {
|
|
|
|
nvidia,pins = "dap1_sclk_pn3";
|
|
|
|
nvidia,function = "rsvd4";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
usb_vbus_en0_pn4 {
|
|
|
|
nvidia,pins = "usb_vbus_en0_pn4";
|
|
|
|
nvidia,function = "usb";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
usb_vbus_en1_pn5 {
|
|
|
|
nvidia,pins = "usb_vbus_en1_pn5";
|
|
|
|
nvidia,function = "usb";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
hdmi_int_pn7 {
|
|
|
|
nvidia,pins = "hdmi_int_pn7";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
ulpi_data7_po0 {
|
|
|
|
nvidia,pins = "ulpi_data7_po0";
|
|
|
|
nvidia,function = "ulpi";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
ulpi_data0_po1 {
|
|
|
|
nvidia,pins = "ulpi_data0_po1";
|
|
|
|
nvidia,function = "ulpi";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
ulpi_data1_po2 {
|
|
|
|
nvidia,pins = "ulpi_data1_po2";
|
|
|
|
nvidia,function = "ulpi";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
ulpi_data2_po3 {
|
|
|
|
nvidia,pins = "ulpi_data2_po3";
|
|
|
|
nvidia,function = "ulpi";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
ulpi_data3_po4 {
|
|
|
|
nvidia,pins = "ulpi_data3_po4";
|
|
|
|
nvidia,function = "ulpi";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
ulpi_data4_po5 {
|
|
|
|
nvidia,pins = "ulpi_data4_po5";
|
|
|
|
nvidia,function = "ulpi";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
ulpi_data5_po6 {
|
|
|
|
nvidia,pins = "ulpi_data5_po6";
|
|
|
|
nvidia,function = "ulpi";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
ulpi_data6_po7 {
|
|
|
|
nvidia,pins = "ulpi_data6_po7";
|
|
|
|
nvidia,function = "ulpi";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
dap3_fs_pp0 {
|
|
|
|
nvidia,pins = "dap3_fs_pp0";
|
|
|
|
nvidia,function = "i2s2";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
dap3_din_pp1 {
|
|
|
|
nvidia,pins = "dap3_din_pp1";
|
|
|
|
nvidia,function = "i2s2";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
dap3_dout_pp2 {
|
|
|
|
nvidia,pins = "dap3_dout_pp2";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
dap3_sclk_pp3 {
|
|
|
|
nvidia,pins = "dap3_sclk_pp3";
|
|
|
|
nvidia,function = "rsvd3";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
dap4_fs_pp4 {
|
|
|
|
nvidia,pins = "dap4_fs_pp4";
|
|
|
|
nvidia,function = "rsvd4";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
dap4_din_pp5 {
|
|
|
|
nvidia,pins = "dap4_din_pp5";
|
|
|
|
nvidia,function = "rsvd3";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
dap4_dout_pp6 {
|
|
|
|
nvidia,pins = "dap4_dout_pp6";
|
|
|
|
nvidia,function = "rsvd4";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
dap4_sclk_pp7 {
|
|
|
|
nvidia,pins = "dap4_sclk_pp7";
|
|
|
|
nvidia,function = "rsvd3";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
kb_col0_pq0 {
|
|
|
|
nvidia,pins = "kb_col0_pq0";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
kb_col1_pq1 {
|
|
|
|
nvidia,pins = "kb_col1_pq1";
|
2014-09-05 06:20:35 +08:00
|
|
|
nvidia,function = "rsvd2";
|
2015-03-18 17:52:22 +08:00
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
kb_col2_pq2 {
|
|
|
|
nvidia,pins = "kb_col2_pq2";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
kb_col3_pq3 {
|
|
|
|
nvidia,pins = "kb_col3_pq3";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
kb_col4_pq4 {
|
|
|
|
nvidia,pins = "kb_col4_pq4";
|
|
|
|
nvidia,function = "sdmmc3";
|
2014-09-05 06:20:35 +08:00
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
2015-03-18 17:52:22 +08:00
|
|
|
kb_col5_pq5 {
|
|
|
|
nvidia,pins = "kb_col5_pq5";
|
|
|
|
nvidia,function = "rsvd2";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
kb_col6_pq6 {
|
|
|
|
nvidia,pins = "kb_col6_pq6";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
kb_col7_pq7 {
|
|
|
|
nvidia,pins = "kb_col7_pq7";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
kb_row0_pr0 {
|
|
|
|
nvidia,pins = "kb_row0_pr0";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
kb_row1_pr1 {
|
|
|
|
nvidia,pins = "kb_row1_pr1";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
kb_row2_pr2 {
|
|
|
|
nvidia,pins = "kb_row2_pr2";
|
|
|
|
nvidia,function = "rsvd2";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
kb_row3_pr3 {
|
|
|
|
nvidia,pins = "kb_row3_pr3";
|
|
|
|
nvidia,function = "kbc";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
kb_row4_pr4 {
|
|
|
|
nvidia,pins = "kb_row4_pr4";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
kb_row5_pr5 {
|
|
|
|
nvidia,pins = "kb_row5_pr5";
|
|
|
|
nvidia,function = "rsvd3";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
kb_row6_pr6 {
|
|
|
|
nvidia,pins = "kb_row6_pr6";
|
|
|
|
nvidia,function = "kbc";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
kb_row7_pr7 {
|
|
|
|
nvidia,pins = "kb_row7_pr7";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
kb_row8_ps0 {
|
|
|
|
nvidia,pins = "kb_row8_ps0";
|
|
|
|
nvidia,function = "rsvd2";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
kb_row9_ps1 {
|
|
|
|
nvidia,pins = "kb_row9_ps1";
|
|
|
|
nvidia,function = "uarta";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
kb_row10_ps2 {
|
|
|
|
nvidia,pins = "kb_row10_ps2";
|
|
|
|
nvidia,function = "uarta";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
kb_row11_ps3 {
|
|
|
|
nvidia,pins = "kb_row11_ps3";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
kb_row12_ps4 {
|
|
|
|
nvidia,pins = "kb_row12_ps4";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
kb_row13_ps5 {
|
|
|
|
nvidia,pins = "kb_row13_ps5";
|
|
|
|
nvidia,function = "rsvd2";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
kb_row14_ps6 {
|
|
|
|
nvidia,pins = "kb_row14_ps6";
|
|
|
|
nvidia,function = "rsvd2";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
kb_row15_ps7 {
|
|
|
|
nvidia,pins = "kb_row15_ps7";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
kb_row16_pt0 {
|
|
|
|
nvidia,pins = "kb_row16_pt0";
|
|
|
|
nvidia,function = "rsvd2";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
kb_row17_pt1 {
|
|
|
|
nvidia,pins = "kb_row17_pt1";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
gen2_i2c_scl_pt5 {
|
|
|
|
nvidia,pins = "gen2_i2c_scl_pt5";
|
|
|
|
nvidia,function = "i2c2";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
gen2_i2c_sda_pt6 {
|
|
|
|
nvidia,pins = "gen2_i2c_sda_pt6";
|
|
|
|
nvidia,function = "i2c2";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
sdmmc4_cmd_pt7 {
|
|
|
|
nvidia,pins = "sdmmc4_cmd_pt7";
|
|
|
|
nvidia,function = "sdmmc4";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
pu0 {
|
|
|
|
nvidia,pins = "pu0";
|
|
|
|
nvidia,function = "rsvd4";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
pu1 {
|
|
|
|
nvidia,pins = "pu1";
|
|
|
|
nvidia,function = "rsvd1";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
pu2 {
|
|
|
|
nvidia,pins = "pu2";
|
|
|
|
nvidia,function = "rsvd1";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
pu3 {
|
|
|
|
nvidia,pins = "pu3";
|
|
|
|
nvidia,function = "gmi";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
pu4 {
|
|
|
|
nvidia,pins = "pu4";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
pu5 {
|
|
|
|
nvidia,pins = "pu5";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
pu6 {
|
|
|
|
nvidia,pins = "pu6";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
pv0 {
|
|
|
|
nvidia,pins = "pv0";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
pv1 {
|
|
|
|
nvidia,pins = "pv1";
|
|
|
|
nvidia,function = "rsvd1";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
sdmmc3_cd_n_pv2 {
|
|
|
|
nvidia,pins = "sdmmc3_cd_n_pv2";
|
|
|
|
nvidia,function = "sdmmc3";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
sdmmc1_wp_n_pv3 {
|
|
|
|
nvidia,pins = "sdmmc1_wp_n_pv3";
|
|
|
|
nvidia,function = "sdmmc1";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
ddc_scl_pv4 {
|
|
|
|
nvidia,pins = "ddc_scl_pv4";
|
|
|
|
nvidia,function = "i2c4";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
ddc_sda_pv5 {
|
|
|
|
nvidia,pins = "ddc_sda_pv5";
|
|
|
|
nvidia,function = "i2c4";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
gpio_w2_aud_pw2 {
|
|
|
|
nvidia,pins = "gpio_w2_aud_pw2";
|
|
|
|
nvidia,function = "rsvd2";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
gpio_w3_aud_pw3 {
|
|
|
|
nvidia,pins = "gpio_w3_aud_pw3";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
dap_mclk1_pw4 {
|
|
|
|
nvidia,pins = "dap_mclk1_pw4";
|
|
|
|
nvidia,function = "extperiph1";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
clk2_out_pw5 {
|
|
|
|
nvidia,pins = "clk2_out_pw5";
|
|
|
|
nvidia,function = "rsvd2";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
uart3_txd_pw6 {
|
|
|
|
nvidia,pins = "uart3_txd_pw6";
|
|
|
|
nvidia,function = "rsvd2";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
uart3_rxd_pw7 {
|
|
|
|
nvidia,pins = "uart3_rxd_pw7";
|
|
|
|
nvidia,function = "rsvd2";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
dvfs_pwm_px0 {
|
|
|
|
nvidia,pins = "dvfs_pwm_px0";
|
|
|
|
nvidia,function = "cldvfs";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
gpio_x1_aud_px1 {
|
|
|
|
nvidia,pins = "gpio_x1_aud_px1";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
dvfs_clk_px2 {
|
|
|
|
nvidia,pins = "dvfs_clk_px2";
|
|
|
|
nvidia,function = "cldvfs";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
gpio_x3_aud_px3 {
|
|
|
|
nvidia,pins = "gpio_x3_aud_px3";
|
|
|
|
nvidia,function = "rsvd4";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
gpio_x4_aud_px4 {
|
|
|
|
nvidia,pins = "gpio_x4_aud_px4";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
gpio_x5_aud_px5 {
|
|
|
|
nvidia,pins = "gpio_x5_aud_px5";
|
|
|
|
nvidia,function = "rsvd4";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
gpio_x6_aud_px6 {
|
|
|
|
nvidia,pins = "gpio_x6_aud_px6";
|
|
|
|
nvidia,function = "gmi";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
gpio_x7_aud_px7 {
|
|
|
|
nvidia,pins = "gpio_x7_aud_px7";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
ulpi_clk_py0 {
|
|
|
|
nvidia,pins = "ulpi_clk_py0";
|
|
|
|
nvidia,function = "spi1";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
ulpi_dir_py1 {
|
|
|
|
nvidia,pins = "ulpi_dir_py1";
|
|
|
|
nvidia,function = "spi1";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
ulpi_nxt_py2 {
|
|
|
|
nvidia,pins = "ulpi_nxt_py2";
|
|
|
|
nvidia,function = "spi1";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
ulpi_stp_py3 {
|
|
|
|
nvidia,pins = "ulpi_stp_py3";
|
|
|
|
nvidia,function = "spi1";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
sdmmc1_dat3_py4 {
|
|
|
|
nvidia,pins = "sdmmc1_dat3_py4";
|
|
|
|
nvidia,function = "sdmmc1";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
sdmmc1_dat2_py5 {
|
|
|
|
nvidia,pins = "sdmmc1_dat2_py5";
|
|
|
|
nvidia,function = "sdmmc1";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
sdmmc1_dat1_py6 {
|
|
|
|
nvidia,pins = "sdmmc1_dat1_py6";
|
|
|
|
nvidia,function = "sdmmc1";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
sdmmc1_dat0_py7 {
|
|
|
|
nvidia,pins = "sdmmc1_dat0_py7";
|
|
|
|
nvidia,function = "sdmmc1";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
sdmmc1_clk_pz0 {
|
|
|
|
nvidia,pins = "sdmmc1_clk_pz0";
|
|
|
|
nvidia,function = "sdmmc1";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
sdmmc1_cmd_pz1 {
|
|
|
|
nvidia,pins = "sdmmc1_cmd_pz1";
|
|
|
|
nvidia,function = "sdmmc1";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
pwr_i2c_scl_pz6 {
|
|
|
|
nvidia,pins = "pwr_i2c_scl_pz6";
|
|
|
|
nvidia,function = "i2cpwr";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
pwr_i2c_sda_pz7 {
|
|
|
|
nvidia,pins = "pwr_i2c_sda_pz7";
|
|
|
|
nvidia,function = "i2cpwr";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
sdmmc4_dat0_paa0 {
|
|
|
|
nvidia,pins = "sdmmc4_dat0_paa0";
|
|
|
|
nvidia,function = "sdmmc4";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
sdmmc4_dat1_paa1 {
|
|
|
|
nvidia,pins = "sdmmc4_dat1_paa1";
|
|
|
|
nvidia,function = "sdmmc4";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
sdmmc4_dat2_paa2 {
|
|
|
|
nvidia,pins = "sdmmc4_dat2_paa2";
|
|
|
|
nvidia,function = "sdmmc4";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
sdmmc4_dat3_paa3 {
|
|
|
|
nvidia,pins = "sdmmc4_dat3_paa3";
|
|
|
|
nvidia,function = "sdmmc4";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
sdmmc4_dat4_paa4 {
|
|
|
|
nvidia,pins = "sdmmc4_dat4_paa4";
|
|
|
|
nvidia,function = "sdmmc4";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
sdmmc4_dat5_paa5 {
|
|
|
|
nvidia,pins = "sdmmc4_dat5_paa5";
|
|
|
|
nvidia,function = "sdmmc4";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
sdmmc4_dat6_paa6 {
|
|
|
|
nvidia,pins = "sdmmc4_dat6_paa6";
|
|
|
|
nvidia,function = "sdmmc4";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
sdmmc4_dat7_paa7 {
|
|
|
|
nvidia,pins = "sdmmc4_dat7_paa7";
|
|
|
|
nvidia,function = "sdmmc4";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
pbb0 {
|
|
|
|
nvidia,pins = "pbb0";
|
|
|
|
nvidia,function = "vgp6";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
cam_i2c_scl_pbb1 {
|
|
|
|
nvidia,pins = "cam_i2c_scl_pbb1";
|
2017-01-22 23:47:52 +08:00
|
|
|
nvidia,function = "i2c3";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
|
2015-03-18 17:52:22 +08:00
|
|
|
};
|
|
|
|
cam_i2c_sda_pbb2 {
|
|
|
|
nvidia,pins = "cam_i2c_sda_pbb2";
|
2017-01-22 23:47:52 +08:00
|
|
|
nvidia,function = "i2c3";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
|
2015-03-18 17:52:22 +08:00
|
|
|
};
|
|
|
|
pbb3 {
|
|
|
|
nvidia,pins = "pbb3";
|
|
|
|
nvidia,function = "vgp3";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
pbb4 {
|
|
|
|
nvidia,pins = "pbb4";
|
|
|
|
nvidia,function = "vgp4";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
pbb5 {
|
|
|
|
nvidia,pins = "pbb5";
|
|
|
|
nvidia,function = "rsvd3";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
pbb6 {
|
|
|
|
nvidia,pins = "pbb6";
|
|
|
|
nvidia,function = "rsvd2";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
pbb7 {
|
|
|
|
nvidia,pins = "pbb7";
|
|
|
|
nvidia,function = "rsvd2";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
cam_mclk_pcc0 {
|
|
|
|
nvidia,pins = "cam_mclk_pcc0";
|
|
|
|
nvidia,function = "vi";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
pcc1 {
|
|
|
|
nvidia,pins = "pcc1";
|
|
|
|
nvidia,function = "rsvd2";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
pcc2 {
|
|
|
|
nvidia,pins = "pcc2";
|
|
|
|
nvidia,function = "rsvd2";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
sdmmc4_clk_pcc4 {
|
|
|
|
nvidia,pins = "sdmmc4_clk_pcc4";
|
|
|
|
nvidia,function = "sdmmc4";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
clk2_req_pcc5 {
|
|
|
|
nvidia,pins = "clk2_req_pcc5";
|
|
|
|
nvidia,function = "rsvd2";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
pex_l0_rst_n_pdd1 {
|
|
|
|
nvidia,pins = "pex_l0_rst_n_pdd1";
|
|
|
|
nvidia,function = "rsvd2";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
pex_l0_clkreq_n_pdd2 {
|
|
|
|
nvidia,pins = "pex_l0_clkreq_n_pdd2";
|
|
|
|
nvidia,function = "rsvd2";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
pex_wake_n_pdd3 {
|
|
|
|
nvidia,pins = "pex_wake_n_pdd3";
|
|
|
|
nvidia,function = "rsvd2";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
pex_l1_rst_n_pdd5 {
|
|
|
|
nvidia,pins = "pex_l1_rst_n_pdd5";
|
|
|
|
nvidia,function = "rsvd2";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
pex_l1_clkreq_n_pdd6 {
|
|
|
|
nvidia,pins = "pex_l1_clkreq_n_pdd6";
|
|
|
|
nvidia,function = "rsvd2";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
clk3_out_pee0 {
|
|
|
|
nvidia,pins = "clk3_out_pee0";
|
|
|
|
nvidia,function = "rsvd2";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
clk3_req_pee1 {
|
|
|
|
nvidia,pins = "clk3_req_pee1";
|
|
|
|
nvidia,function = "rsvd2";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
dap_mclk1_req_pee2 {
|
|
|
|
nvidia,pins = "dap_mclk1_req_pee2";
|
|
|
|
nvidia,function = "rsvd4";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
hdmi_cec_pee3 {
|
|
|
|
nvidia,pins = "hdmi_cec_pee3";
|
|
|
|
nvidia,function = "cec";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
sdmmc3_clk_lb_out_pee4 {
|
|
|
|
nvidia,pins = "sdmmc3_clk_lb_out_pee4";
|
|
|
|
nvidia,function = "sdmmc3";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
sdmmc3_clk_lb_in_pee5 {
|
|
|
|
nvidia,pins = "sdmmc3_clk_lb_in_pee5";
|
|
|
|
nvidia,function = "sdmmc3";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
dp_hpd_pff0 {
|
|
|
|
nvidia,pins = "dp_hpd_pff0";
|
|
|
|
nvidia,function = "dp";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
usb_vbus_en2_pff1 {
|
|
|
|
nvidia,pins = "usb_vbus_en2_pff1";
|
|
|
|
nvidia,function = "rsvd2";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
pff2 {
|
|
|
|
nvidia,pins = "pff2";
|
|
|
|
nvidia,function = "rsvd2";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
core_pwr_req {
|
|
|
|
nvidia,pins = "core_pwr_req";
|
|
|
|
nvidia,function = "pwron";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
cpu_pwr_req {
|
|
|
|
nvidia,pins = "cpu_pwr_req";
|
|
|
|
nvidia,function = "cpu";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
pwr_int_n {
|
|
|
|
nvidia,pins = "pwr_int_n";
|
|
|
|
nvidia,function = "pmi";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
reset_out_n {
|
|
|
|
nvidia,pins = "reset_out_n";
|
|
|
|
nvidia,function = "reset_out_n";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
owr {
|
|
|
|
nvidia,pins = "owr";
|
|
|
|
nvidia,function = "rsvd2";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
clk_32k_in {
|
|
|
|
nvidia,pins = "clk_32k_in";
|
|
|
|
nvidia,function = "clk";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
jtag_rtck {
|
|
|
|
nvidia,pins = "jtag_rtck";
|
|
|
|
nvidia,function = "rtck";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
2014-09-05 06:20:35 +08:00
|
|
|
};
|
|
|
|
};
|
|
|
|
};
|