2021-10-11 17:20:12 +08:00
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2017 Pengutronix, Oleksij Rempel <kernel@pengutronix.de>
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* Copyright 2021 NXP
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*/
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#ifndef _IMX_RPROC_H
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#define _IMX_RPROC_H
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/* address translation table */
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struct imx_rproc_att {
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u32 da; /* device address (From Cortex M4 view)*/
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u32 sa; /* system bus address */
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u32 size; /* size of reg range */
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int flags;
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};
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/* Remote core start/stop method */
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enum imx_rproc_method {
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IMX_RPROC_NONE,
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/* Through syscon regmap */
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IMX_RPROC_MMIO,
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/* Through ARM SMCCC */
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IMX_RPROC_SMC,
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2021-10-11 17:20:13 +08:00
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/* Through System Control Unit API */
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IMX_RPROC_SCU_API,
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2021-10-11 17:20:12 +08:00
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};
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struct imx_rproc_dcfg {
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u32 src_reg;
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u32 src_mask;
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u32 src_start;
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u32 src_stop;
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2023-07-25 06:24:18 +08:00
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u32 gpr_reg;
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u32 gpr_wait;
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2021-10-11 17:20:12 +08:00
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const struct imx_rproc_att *att;
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size_t att_size;
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enum imx_rproc_method method;
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};
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#endif /* _IMX_RPROC_H */
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