2019-05-27 14:55:01 +08:00
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// SPDX-License-Identifier: GPL-2.0-or-later
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2006-03-24 19:18:17 +08:00
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/*
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2007-07-12 02:04:50 +08:00
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* linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
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2006-03-24 19:18:17 +08:00
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*
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2008-03-09 06:44:25 +08:00
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* Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
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2006-03-24 19:18:17 +08:00
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*
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2007-12-03 02:58:16 +08:00
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* Thanks to the following companies for their support:
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*
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* - JMicron (hardware and technical support)
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2006-03-24 19:18:17 +08:00
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*/
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2020-03-12 19:00:50 +08:00
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#include <linux/bitfield.h>
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2006-03-24 19:18:17 +08:00
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#include <linux/delay.h>
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2020-01-16 18:51:47 +08:00
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#include <linux/dmaengine.h>
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2017-03-21 01:50:31 +08:00
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#include <linux/ktime.h>
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2006-03-24 19:18:17 +08:00
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#include <linux/highmem.h>
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2008-03-19 00:35:49 +08:00
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#include <linux/io.h>
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2011-07-04 03:15:51 +08:00
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#include <linux/module.h>
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2006-03-24 19:18:17 +08:00
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#include <linux/dma-mapping.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 16:04:11 +08:00
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#include <linux/slab.h>
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2007-10-24 02:42:11 +08:00
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#include <linux/scatterlist.h>
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2018-01-29 07:44:53 +08:00
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#include <linux/sizes.h>
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2017-11-27 18:28:50 +08:00
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#include <linux/swiotlb.h>
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2010-08-11 09:01:59 +08:00
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#include <linux/regulator/consumer.h>
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2011-10-03 20:33:34 +08:00
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#include <linux/pm_runtime.h>
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2016-11-02 23:26:16 +08:00
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#include <linux/of.h>
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2006-03-24 19:18:17 +08:00
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2008-03-17 17:29:38 +08:00
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#include <linux/leds.h>
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2010-12-15 15:14:24 +08:00
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#include <linux/mmc/mmc.h>
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2006-03-24 19:18:17 +08:00
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#include <linux/mmc/host.h>
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2012-07-03 17:27:49 +08:00
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#include <linux/mmc/card.h>
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2015-02-10 08:06:29 +08:00
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#include <linux/mmc/sdio.h>
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2012-09-17 16:45:10 +08:00
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#include <linux/mmc/slot-gpio.h>
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2006-03-24 19:18:17 +08:00
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#include "sdhci.h"
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#define DRIVER_NAME "sdhci"
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#define DBG(f, x...) \
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2017-03-21 01:50:39 +08:00
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pr_debug("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
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2006-03-24 19:18:17 +08:00
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2017-03-21 01:50:42 +08:00
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#define SDHCI_DUMP(f, x...) \
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pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
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2011-05-05 14:49:04 +08:00
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#define MAX_TUNING_LOOP 40
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2006-06-30 17:22:31 +08:00
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static unsigned int debug_quirks = 0;
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2011-10-03 20:33:34 +08:00
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static unsigned int debug_quirks2;
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2006-06-30 17:22:31 +08:00
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2013-01-31 11:31:37 +08:00
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static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
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2006-03-24 19:18:17 +08:00
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2020-04-12 17:03:49 +08:00
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static bool sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd);
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2020-04-12 17:03:46 +08:00
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2017-03-21 01:50:43 +08:00
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void sdhci_dumpregs(struct sdhci_host *host)
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2006-03-24 19:18:17 +08:00
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{
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2017-03-21 01:50:42 +08:00
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SDHCI_DUMP("============ SDHCI REGISTER DUMP ===========\n");
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SDHCI_DUMP("Sys addr: 0x%08x | Version: 0x%08x\n",
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sdhci_readl(host, SDHCI_DMA_ADDRESS),
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sdhci_readw(host, SDHCI_HOST_VERSION));
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SDHCI_DUMP("Blk size: 0x%08x | Blk cnt: 0x%08x\n",
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sdhci_readw(host, SDHCI_BLOCK_SIZE),
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sdhci_readw(host, SDHCI_BLOCK_COUNT));
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SDHCI_DUMP("Argument: 0x%08x | Trn mode: 0x%08x\n",
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sdhci_readl(host, SDHCI_ARGUMENT),
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sdhci_readw(host, SDHCI_TRANSFER_MODE));
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SDHCI_DUMP("Present: 0x%08x | Host ctl: 0x%08x\n",
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sdhci_readl(host, SDHCI_PRESENT_STATE),
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sdhci_readb(host, SDHCI_HOST_CONTROL));
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SDHCI_DUMP("Power: 0x%08x | Blk gap: 0x%08x\n",
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sdhci_readb(host, SDHCI_POWER_CONTROL),
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sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
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SDHCI_DUMP("Wake-up: 0x%08x | Clock: 0x%08x\n",
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sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
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sdhci_readw(host, SDHCI_CLOCK_CONTROL));
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SDHCI_DUMP("Timeout: 0x%08x | Int stat: 0x%08x\n",
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sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
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sdhci_readl(host, SDHCI_INT_STATUS));
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SDHCI_DUMP("Int enab: 0x%08x | Sig enab: 0x%08x\n",
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sdhci_readl(host, SDHCI_INT_ENABLE),
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sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
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2018-11-15 21:53:42 +08:00
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SDHCI_DUMP("ACmd stat: 0x%08x | Slot int: 0x%08x\n",
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sdhci_readw(host, SDHCI_AUTO_CMD_STATUS),
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2017-03-21 01:50:42 +08:00
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sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
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SDHCI_DUMP("Caps: 0x%08x | Caps_1: 0x%08x\n",
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sdhci_readl(host, SDHCI_CAPABILITIES),
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sdhci_readl(host, SDHCI_CAPABILITIES_1));
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SDHCI_DUMP("Cmd: 0x%08x | Max curr: 0x%08x\n",
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sdhci_readw(host, SDHCI_COMMAND),
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sdhci_readl(host, SDHCI_MAX_CURRENT));
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SDHCI_DUMP("Resp[0]: 0x%08x | Resp[1]: 0x%08x\n",
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2017-03-21 01:50:40 +08:00
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sdhci_readl(host, SDHCI_RESPONSE),
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sdhci_readl(host, SDHCI_RESPONSE + 4));
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2017-03-21 01:50:42 +08:00
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SDHCI_DUMP("Resp[2]: 0x%08x | Resp[3]: 0x%08x\n",
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2017-03-21 01:50:40 +08:00
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sdhci_readl(host, SDHCI_RESPONSE + 8),
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sdhci_readl(host, SDHCI_RESPONSE + 12));
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2017-03-21 01:50:42 +08:00
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SDHCI_DUMP("Host ctl2: 0x%08x\n",
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sdhci_readw(host, SDHCI_HOST_CONTROL2));
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2006-03-24 19:18:17 +08:00
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2014-11-04 18:42:46 +08:00
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if (host->flags & SDHCI_USE_ADMA) {
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2017-03-21 01:50:42 +08:00
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if (host->flags & SDHCI_USE_64_BIT_DMA) {
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SDHCI_DUMP("ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
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sdhci_readl(host, SDHCI_ADMA_ERROR),
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sdhci_readl(host, SDHCI_ADMA_ADDRESS_HI),
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sdhci_readl(host, SDHCI_ADMA_ADDRESS));
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} else {
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SDHCI_DUMP("ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
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sdhci_readl(host, SDHCI_ADMA_ERROR),
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sdhci_readl(host, SDHCI_ADMA_ADDRESS));
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}
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2014-11-04 18:42:46 +08:00
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}
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2009-06-09 06:33:52 +08:00
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2020-05-22 17:32:29 +08:00
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if (host->ops->dump_vendor_regs)
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host->ops->dump_vendor_regs(host);
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2017-03-21 01:50:42 +08:00
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SDHCI_DUMP("============================================\n");
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2006-03-24 19:18:17 +08:00
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}
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2017-03-21 01:50:43 +08:00
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EXPORT_SYMBOL_GPL(sdhci_dumpregs);
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2006-03-24 19:18:17 +08:00
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/*****************************************************************************\
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* *
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* Low level functions *
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* *
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\*****************************************************************************/
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2018-08-30 16:21:38 +08:00
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static void sdhci_do_enable_v4_mode(struct sdhci_host *host)
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{
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u16 ctrl2;
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2018-12-14 04:34:06 +08:00
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ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
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2018-08-30 16:21:38 +08:00
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if (ctrl2 & SDHCI_CTRL_V4_MODE)
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return;
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ctrl2 |= SDHCI_CTRL_V4_MODE;
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2018-12-14 04:34:06 +08:00
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sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
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2018-08-30 16:21:38 +08:00
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}
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/*
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* This can be called before sdhci_add_host() by Vendor's host controller
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* driver to enable v4 mode if supported.
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*/
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void sdhci_enable_v4_mode(struct sdhci_host *host)
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{
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host->v4_mode = true;
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sdhci_do_enable_v4_mode(host);
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}
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EXPORT_SYMBOL_GPL(sdhci_enable_v4_mode);
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2016-06-29 21:24:32 +08:00
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static inline bool sdhci_data_line_cmd(struct mmc_command *cmd)
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{
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return cmd->data || cmd->flags & MMC_RSP_BUSY;
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}
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2009-03-17 05:13:48 +08:00
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static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
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{
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2014-04-25 19:57:02 +08:00
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u32 present;
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2009-03-17 05:13:48 +08:00
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2011-12-27 21:48:42 +08:00
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if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
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2020-02-19 16:22:40 +08:00
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!mmc_card_is_removable(host->mmc) || mmc_can_gpio_cd(host->mmc))
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2011-10-03 20:33:34 +08:00
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return;
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2014-04-25 19:57:02 +08:00
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if (enable) {
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present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
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SDHCI_CARD_PRESENT;
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2011-06-21 22:41:48 +08:00
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2014-04-25 19:57:02 +08:00
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host->ier |= present ? SDHCI_INT_CARD_REMOVE :
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SDHCI_INT_CARD_INSERT;
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} else {
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host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
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}
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2014-04-25 19:56:01 +08:00
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sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
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sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
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2009-03-17 05:13:48 +08:00
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}
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static void sdhci_enable_card_detection(struct sdhci_host *host)
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{
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sdhci_set_card_detection(host, true);
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}
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static void sdhci_disable_card_detection(struct sdhci_host *host)
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{
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sdhci_set_card_detection(host, false);
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}
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2016-04-11 21:32:41 +08:00
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static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
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{
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if (host->bus_on)
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return;
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host->bus_on = true;
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pm_runtime_get_noresume(host->mmc->parent);
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}
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static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
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{
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if (!host->bus_on)
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return;
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host->bus_on = false;
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pm_runtime_put_noidle(host->mmc->parent);
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}
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2014-04-25 19:57:12 +08:00
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void sdhci_reset(struct sdhci_host *host, u8 mask)
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2006-03-24 19:18:17 +08:00
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{
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2017-03-21 01:50:31 +08:00
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ktime_t timeout;
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2011-01-22 03:26:40 +08:00
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2009-03-17 05:13:46 +08:00
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sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
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2006-03-24 19:18:17 +08:00
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2013-05-06 17:17:32 +08:00
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if (mask & SDHCI_RESET_ALL) {
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2006-03-24 19:18:17 +08:00
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host->clock = 0;
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2013-05-06 17:17:32 +08:00
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/* Reset-all turns off SD Bus Power */
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if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
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sdhci_runtime_pm_bus_off(host);
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}
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2006-03-24 19:18:17 +08:00
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2006-06-30 17:22:24 +08:00
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/* Wait max 100 ms */
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2017-03-21 01:50:31 +08:00
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timeout = ktime_add_ms(ktime_get(), 100);
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2006-06-30 17:22:24 +08:00
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/* hw clears the bit when it's done */
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2018-12-06 17:24:59 +08:00
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while (1) {
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bool timedout = ktime_after(ktime_get(), timeout);
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if (!(sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask))
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break;
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|
if (timedout) {
|
2011-10-11 14:14:09 +08:00
|
|
|
pr_err("%s: Reset 0x%x never completed.\n",
|
2006-06-30 17:22:24 +08:00
|
|
|
mmc_hostname(host->mmc), (int)mask);
|
|
|
|
sdhci_dumpregs(host);
|
|
|
|
return;
|
|
|
|
}
|
2017-03-21 01:50:31 +08:00
|
|
|
udelay(10);
|
2006-03-24 19:18:17 +08:00
|
|
|
}
|
2014-04-25 19:57:12 +08:00
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(sdhci_reset);
|
|
|
|
|
|
|
|
static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
|
|
|
|
{
|
|
|
|
if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
|
2016-06-29 21:24:14 +08:00
|
|
|
struct mmc_host *mmc = host->mmc;
|
|
|
|
|
|
|
|
if (!mmc->ops->get_cd(mmc))
|
2014-04-25 19:57:12 +08:00
|
|
|
return;
|
|
|
|
}
|
2009-03-17 05:14:02 +08:00
|
|
|
|
2014-04-25 19:57:12 +08:00
|
|
|
host->ops->reset(host, mask);
|
2011-01-22 03:26:40 +08:00
|
|
|
|
2014-04-25 20:00:12 +08:00
|
|
|
if (mask & SDHCI_RESET_ALL) {
|
|
|
|
if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
|
|
|
|
if (host->ops->enable_dma)
|
|
|
|
host->ops->enable_dma(host);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Resetting the controller clears many */
|
|
|
|
host->preset_enabled = false;
|
2011-12-29 16:33:00 +08:00
|
|
|
}
|
2006-03-24 19:18:17 +08:00
|
|
|
}
|
|
|
|
|
2017-03-21 01:50:46 +08:00
|
|
|
static void sdhci_set_default_irqs(struct sdhci_host *host)
|
2006-03-24 19:18:17 +08:00
|
|
|
{
|
2014-04-25 19:56:01 +08:00
|
|
|
host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
|
|
|
|
SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
|
|
|
|
SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
|
|
|
|
SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
|
|
|
|
SDHCI_INT_RESPONSE;
|
|
|
|
|
2016-07-12 15:46:17 +08:00
|
|
|
if (host->tuning_mode == SDHCI_TUNING_MODE_2 ||
|
|
|
|
host->tuning_mode == SDHCI_TUNING_MODE_3)
|
|
|
|
host->ier |= SDHCI_INT_RETUNE;
|
|
|
|
|
2014-04-25 19:56:01 +08:00
|
|
|
sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
|
|
|
|
sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
|
2017-03-21 01:50:46 +08:00
|
|
|
}
|
|
|
|
|
2018-08-30 16:21:40 +08:00
|
|
|
static void sdhci_config_dma(struct sdhci_host *host)
|
|
|
|
{
|
|
|
|
u8 ctrl;
|
|
|
|
u16 ctrl2;
|
|
|
|
|
|
|
|
if (host->version < SDHCI_SPEC_200)
|
|
|
|
return;
|
|
|
|
|
|
|
|
ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Always adjust the DMA selection as some controllers
|
|
|
|
* (e.g. JMicron) can't do PIO properly when the selection
|
|
|
|
* is ADMA.
|
|
|
|
*/
|
|
|
|
ctrl &= ~SDHCI_CTRL_DMA_MASK;
|
|
|
|
if (!(host->flags & SDHCI_REQ_USE_DMA))
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
/* Note if DMA Select is zero then SDMA is selected */
|
|
|
|
if (host->flags & SDHCI_USE_ADMA)
|
|
|
|
ctrl |= SDHCI_CTRL_ADMA32;
|
|
|
|
|
|
|
|
if (host->flags & SDHCI_USE_64_BIT_DMA) {
|
|
|
|
/*
|
|
|
|
* If v4 mode, all supported DMA can be 64-bit addressing if
|
|
|
|
* controller supports 64-bit system address, otherwise only
|
|
|
|
* ADMA can support 64-bit addressing.
|
|
|
|
*/
|
|
|
|
if (host->v4_mode) {
|
|
|
|
ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
|
|
|
|
ctrl2 |= SDHCI_CTRL_64BIT_ADDR;
|
|
|
|
sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
|
|
|
|
} else if (host->flags & SDHCI_USE_ADMA) {
|
|
|
|
/*
|
|
|
|
* Don't need to undo SDHCI_CTRL_ADMA32 in order to
|
|
|
|
* set SDHCI_CTRL_ADMA64.
|
|
|
|
*/
|
|
|
|
ctrl |= SDHCI_CTRL_ADMA64;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
out:
|
|
|
|
sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
|
|
|
|
}
|
|
|
|
|
2017-03-21 01:50:46 +08:00
|
|
|
static void sdhci_init(struct sdhci_host *host, int soft)
|
|
|
|
{
|
|
|
|
struct mmc_host *mmc = host->mmc;
|
2020-04-15 17:00:55 +08:00
|
|
|
unsigned long flags;
|
2017-03-21 01:50:46 +08:00
|
|
|
|
|
|
|
if (soft)
|
|
|
|
sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
|
|
|
|
else
|
|
|
|
sdhci_do_reset(host, SDHCI_RESET_ALL);
|
|
|
|
|
2018-08-30 16:21:38 +08:00
|
|
|
if (host->v4_mode)
|
|
|
|
sdhci_do_enable_v4_mode(host);
|
|
|
|
|
2020-04-15 17:00:55 +08:00
|
|
|
spin_lock_irqsave(&host->lock, flags);
|
2017-03-21 01:50:46 +08:00
|
|
|
sdhci_set_default_irqs(host);
|
2020-04-15 17:00:55 +08:00
|
|
|
spin_unlock_irqrestore(&host->lock, flags);
|
2010-03-06 05:43:32 +08:00
|
|
|
|
2017-03-21 01:50:47 +08:00
|
|
|
host->cqe_on = false;
|
|
|
|
|
2010-03-06 05:43:32 +08:00
|
|
|
if (soft) {
|
|
|
|
/* force clock reconfiguration */
|
|
|
|
host->clock = 0;
|
2016-06-29 21:24:14 +08:00
|
|
|
mmc->ops->set_ios(mmc, &mmc->ios);
|
2010-03-06 05:43:32 +08:00
|
|
|
}
|
2009-03-17 05:13:48 +08:00
|
|
|
}
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2009-03-17 05:13:48 +08:00
|
|
|
static void sdhci_reinit(struct sdhci_host *host)
|
|
|
|
{
|
2019-09-05 00:46:24 +08:00
|
|
|
u32 cd = host->ier & (SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
|
|
|
|
|
2010-03-06 05:43:32 +08:00
|
|
|
sdhci_init(host, 0);
|
2009-03-17 05:13:48 +08:00
|
|
|
sdhci_enable_card_detection(host);
|
2019-09-05 00:46:24 +08:00
|
|
|
|
|
|
|
/*
|
|
|
|
* A change to the card detect bits indicates a change in present state,
|
|
|
|
* refer sdhci_set_card_detection(). A card detect interrupt might have
|
|
|
|
* been missed while the host controller was being reset, so trigger a
|
|
|
|
* rescan to check.
|
|
|
|
*/
|
|
|
|
if (cd != (host->ier & (SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT)))
|
|
|
|
mmc_detect_change(host->mmc, msecs_to_jiffies(200));
|
2006-03-24 19:18:17 +08:00
|
|
|
}
|
|
|
|
|
2016-04-12 19:25:09 +08:00
|
|
|
static void __sdhci_led_activate(struct sdhci_host *host)
|
2006-03-24 19:18:17 +08:00
|
|
|
{
|
|
|
|
u8 ctrl;
|
|
|
|
|
2018-12-11 21:10:42 +08:00
|
|
|
if (host->quirks & SDHCI_QUIRK_NO_LED)
|
|
|
|
return;
|
|
|
|
|
2009-03-17 05:13:46 +08:00
|
|
|
ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
|
2006-03-24 19:18:17 +08:00
|
|
|
ctrl |= SDHCI_CTRL_LED;
|
2009-03-17 05:13:46 +08:00
|
|
|
sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
|
2006-03-24 19:18:17 +08:00
|
|
|
}
|
|
|
|
|
2016-04-12 19:25:09 +08:00
|
|
|
static void __sdhci_led_deactivate(struct sdhci_host *host)
|
2006-03-24 19:18:17 +08:00
|
|
|
{
|
|
|
|
u8 ctrl;
|
|
|
|
|
2018-12-11 21:10:42 +08:00
|
|
|
if (host->quirks & SDHCI_QUIRK_NO_LED)
|
|
|
|
return;
|
|
|
|
|
2009-03-17 05:13:46 +08:00
|
|
|
ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
|
2006-03-24 19:18:17 +08:00
|
|
|
ctrl &= ~SDHCI_CTRL_LED;
|
2009-03-17 05:13:46 +08:00
|
|
|
sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
|
2006-03-24 19:18:17 +08:00
|
|
|
}
|
|
|
|
|
2016-04-14 12:19:39 +08:00
|
|
|
#if IS_REACHABLE(CONFIG_LEDS_CLASS)
|
2008-03-17 17:29:38 +08:00
|
|
|
static void sdhci_led_control(struct led_classdev *led,
|
2016-04-12 19:25:09 +08:00
|
|
|
enum led_brightness brightness)
|
2008-03-17 17:29:38 +08:00
|
|
|
{
|
|
|
|
struct sdhci_host *host = container_of(led, struct sdhci_host, led);
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&host->lock, flags);
|
|
|
|
|
2011-10-03 20:33:34 +08:00
|
|
|
if (host->runtime_suspended)
|
|
|
|
goto out;
|
|
|
|
|
2008-03-17 17:29:38 +08:00
|
|
|
if (brightness == LED_OFF)
|
2016-04-12 19:25:09 +08:00
|
|
|
__sdhci_led_deactivate(host);
|
2008-03-17 17:29:38 +08:00
|
|
|
else
|
2016-04-12 19:25:09 +08:00
|
|
|
__sdhci_led_activate(host);
|
2011-10-03 20:33:34 +08:00
|
|
|
out:
|
2008-03-17 17:29:38 +08:00
|
|
|
spin_unlock_irqrestore(&host->lock, flags);
|
|
|
|
}
|
2016-04-12 19:25:09 +08:00
|
|
|
|
|
|
|
static int sdhci_led_register(struct sdhci_host *host)
|
|
|
|
{
|
|
|
|
struct mmc_host *mmc = host->mmc;
|
|
|
|
|
2018-12-11 21:10:42 +08:00
|
|
|
if (host->quirks & SDHCI_QUIRK_NO_LED)
|
|
|
|
return 0;
|
|
|
|
|
2016-04-12 19:25:09 +08:00
|
|
|
snprintf(host->led_name, sizeof(host->led_name),
|
|
|
|
"%s::", mmc_hostname(mmc));
|
|
|
|
|
|
|
|
host->led.name = host->led_name;
|
|
|
|
host->led.brightness = LED_OFF;
|
|
|
|
host->led.default_trigger = mmc_hostname(mmc);
|
|
|
|
host->led.brightness_set = sdhci_led_control;
|
|
|
|
|
|
|
|
return led_classdev_register(mmc_dev(mmc), &host->led);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void sdhci_led_unregister(struct sdhci_host *host)
|
|
|
|
{
|
2018-12-11 21:10:42 +08:00
|
|
|
if (host->quirks & SDHCI_QUIRK_NO_LED)
|
|
|
|
return;
|
|
|
|
|
2016-04-12 19:25:09 +08:00
|
|
|
led_classdev_unregister(&host->led);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void sdhci_led_activate(struct sdhci_host *host)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void sdhci_led_deactivate(struct sdhci_host *host)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
|
|
|
#else
|
|
|
|
|
|
|
|
static inline int sdhci_led_register(struct sdhci_host *host)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void sdhci_led_unregister(struct sdhci_host *host)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void sdhci_led_activate(struct sdhci_host *host)
|
|
|
|
{
|
|
|
|
__sdhci_led_activate(host);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void sdhci_led_deactivate(struct sdhci_host *host)
|
|
|
|
{
|
|
|
|
__sdhci_led_deactivate(host);
|
|
|
|
}
|
|
|
|
|
2008-03-17 17:29:38 +08:00
|
|
|
#endif
|
|
|
|
|
2019-04-05 20:40:17 +08:00
|
|
|
static void sdhci_mod_timer(struct sdhci_host *host, struct mmc_request *mrq,
|
|
|
|
unsigned long timeout)
|
|
|
|
{
|
|
|
|
if (sdhci_data_line_cmd(mrq->cmd))
|
|
|
|
mod_timer(&host->data_timer, timeout);
|
|
|
|
else
|
|
|
|
mod_timer(&host->timer, timeout);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void sdhci_del_timer(struct sdhci_host *host, struct mmc_request *mrq)
|
|
|
|
{
|
|
|
|
if (sdhci_data_line_cmd(mrq->cmd))
|
|
|
|
del_timer(&host->data_timer);
|
|
|
|
else
|
|
|
|
del_timer(&host->timer);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline bool sdhci_has_requests(struct sdhci_host *host)
|
|
|
|
{
|
|
|
|
return host->cmd || host->data_cmd;
|
|
|
|
}
|
|
|
|
|
2006-03-24 19:18:17 +08:00
|
|
|
/*****************************************************************************\
|
|
|
|
* *
|
|
|
|
* Core functions *
|
|
|
|
* *
|
|
|
|
\*****************************************************************************/
|
|
|
|
|
2006-07-02 23:50:59 +08:00
|
|
|
static void sdhci_read_block_pio(struct sdhci_host *host)
|
2006-03-24 19:18:17 +08:00
|
|
|
{
|
2008-07-21 06:32:11 +08:00
|
|
|
unsigned long flags;
|
|
|
|
size_t blksize, len, chunk;
|
2008-10-01 16:50:25 +08:00
|
|
|
u32 uninitialized_var(scratch);
|
2008-07-21 06:32:11 +08:00
|
|
|
u8 *buf;
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2006-07-02 23:50:59 +08:00
|
|
|
DBG("PIO reading\n");
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2006-07-02 23:50:59 +08:00
|
|
|
blksize = host->data->blksz;
|
2008-07-21 06:32:11 +08:00
|
|
|
chunk = 0;
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2008-07-21 06:32:11 +08:00
|
|
|
local_irq_save(flags);
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2006-07-02 23:50:59 +08:00
|
|
|
while (blksize) {
|
2015-05-10 05:44:51 +08:00
|
|
|
BUG_ON(!sg_miter_next(&host->sg_miter));
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2008-07-21 06:32:11 +08:00
|
|
|
len = min(host->sg_miter.length, blksize);
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2008-07-21 06:32:11 +08:00
|
|
|
blksize -= len;
|
|
|
|
host->sg_miter.consumed = len;
|
2007-04-14 01:04:38 +08:00
|
|
|
|
2008-07-21 06:32:11 +08:00
|
|
|
buf = host->sg_miter.addr;
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2008-07-21 06:32:11 +08:00
|
|
|
while (len) {
|
|
|
|
if (chunk == 0) {
|
2009-03-17 05:13:46 +08:00
|
|
|
scratch = sdhci_readl(host, SDHCI_BUFFER);
|
2008-07-21 06:32:11 +08:00
|
|
|
chunk = 4;
|
2006-07-02 23:50:59 +08:00
|
|
|
}
|
2008-07-21 06:32:11 +08:00
|
|
|
|
|
|
|
*buf = scratch & 0xFF;
|
|
|
|
|
|
|
|
buf++;
|
|
|
|
scratch >>= 8;
|
|
|
|
chunk--;
|
|
|
|
len--;
|
2006-03-24 19:18:17 +08:00
|
|
|
}
|
2006-07-02 23:50:59 +08:00
|
|
|
}
|
2008-07-21 06:32:11 +08:00
|
|
|
|
|
|
|
sg_miter_stop(&host->sg_miter);
|
|
|
|
|
|
|
|
local_irq_restore(flags);
|
2006-07-02 23:50:59 +08:00
|
|
|
}
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2006-07-02 23:50:59 +08:00
|
|
|
static void sdhci_write_block_pio(struct sdhci_host *host)
|
|
|
|
{
|
2008-07-21 06:32:11 +08:00
|
|
|
unsigned long flags;
|
|
|
|
size_t blksize, len, chunk;
|
|
|
|
u32 scratch;
|
|
|
|
u8 *buf;
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2006-07-02 23:50:59 +08:00
|
|
|
DBG("PIO writing\n");
|
|
|
|
|
|
|
|
blksize = host->data->blksz;
|
2008-07-21 06:32:11 +08:00
|
|
|
chunk = 0;
|
|
|
|
scratch = 0;
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2008-07-21 06:32:11 +08:00
|
|
|
local_irq_save(flags);
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2006-07-02 23:50:59 +08:00
|
|
|
while (blksize) {
|
2015-05-10 05:44:51 +08:00
|
|
|
BUG_ON(!sg_miter_next(&host->sg_miter));
|
2006-07-02 23:50:59 +08:00
|
|
|
|
2008-07-21 06:32:11 +08:00
|
|
|
len = min(host->sg_miter.length, blksize);
|
|
|
|
|
|
|
|
blksize -= len;
|
|
|
|
host->sg_miter.consumed = len;
|
|
|
|
|
|
|
|
buf = host->sg_miter.addr;
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2008-07-21 06:32:11 +08:00
|
|
|
while (len) {
|
|
|
|
scratch |= (u32)*buf << (chunk * 8);
|
|
|
|
|
|
|
|
buf++;
|
|
|
|
chunk++;
|
|
|
|
len--;
|
|
|
|
|
|
|
|
if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
|
2009-03-17 05:13:46 +08:00
|
|
|
sdhci_writel(host, scratch, SDHCI_BUFFER);
|
2008-07-21 06:32:11 +08:00
|
|
|
chunk = 0;
|
|
|
|
scratch = 0;
|
2006-03-24 19:18:17 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2008-07-21 06:32:11 +08:00
|
|
|
|
|
|
|
sg_miter_stop(&host->sg_miter);
|
|
|
|
|
|
|
|
local_irq_restore(flags);
|
2006-07-02 23:50:59 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static void sdhci_transfer_pio(struct sdhci_host *host)
|
|
|
|
{
|
|
|
|
u32 mask;
|
|
|
|
|
2008-07-21 06:32:11 +08:00
|
|
|
if (host->blocks == 0)
|
2006-07-02 23:50:59 +08:00
|
|
|
return;
|
|
|
|
|
|
|
|
if (host->data->flags & MMC_DATA_READ)
|
|
|
|
mask = SDHCI_DATA_AVAILABLE;
|
|
|
|
else
|
|
|
|
mask = SDHCI_SPACE_AVAILABLE;
|
|
|
|
|
2008-07-29 06:11:16 +08:00
|
|
|
/*
|
|
|
|
* Some controllers (JMicron JMB38x) mess up the buffer bits
|
|
|
|
* for transfers < 4 bytes. As long as it is just one block,
|
|
|
|
* we can ignore the bits.
|
|
|
|
*/
|
|
|
|
if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
|
|
|
|
(host->data->blocks == 1))
|
|
|
|
mask = ~0;
|
|
|
|
|
2009-03-17 05:13:46 +08:00
|
|
|
while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
|
2009-03-17 05:14:00 +08:00
|
|
|
if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
|
|
|
|
udelay(100);
|
|
|
|
|
2006-07-02 23:50:59 +08:00
|
|
|
if (host->data->flags & MMC_DATA_READ)
|
|
|
|
sdhci_read_block_pio(host);
|
|
|
|
else
|
|
|
|
sdhci_write_block_pio(host);
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2008-07-21 06:32:11 +08:00
|
|
|
host->blocks--;
|
|
|
|
if (host->blocks == 0)
|
2006-07-02 23:50:59 +08:00
|
|
|
break;
|
|
|
|
}
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2006-07-02 23:50:59 +08:00
|
|
|
DBG("PIO transfer complete.\n");
|
2006-03-24 19:18:17 +08:00
|
|
|
}
|
|
|
|
|
2016-01-26 21:40:16 +08:00
|
|
|
static int sdhci_pre_dma_transfer(struct sdhci_host *host,
|
2016-01-26 21:40:27 +08:00
|
|
|
struct mmc_data *data, int cookie)
|
2016-01-26 21:40:16 +08:00
|
|
|
{
|
|
|
|
int sg_count;
|
|
|
|
|
2016-01-26 21:40:37 +08:00
|
|
|
/*
|
|
|
|
* If the data buffers are already mapped, return the previous
|
|
|
|
* dma_map_sg() result.
|
|
|
|
*/
|
|
|
|
if (data->host_cookie == COOKIE_PRE_MAPPED)
|
2016-01-26 21:40:16 +08:00
|
|
|
return data->sg_count;
|
|
|
|
|
2018-01-29 07:44:53 +08:00
|
|
|
/* Bounce write requests to the bounce buffer */
|
|
|
|
if (host->bounce_buffer) {
|
|
|
|
unsigned int length = data->blksz * data->blocks;
|
|
|
|
|
|
|
|
if (length > host->bounce_buffer_size) {
|
|
|
|
pr_err("%s: asked for transfer of %u bytes exceeds bounce buffer %u bytes\n",
|
|
|
|
mmc_hostname(host->mmc), length,
|
|
|
|
host->bounce_buffer_size);
|
|
|
|
return -EIO;
|
|
|
|
}
|
|
|
|
if (mmc_get_dma_dir(data) == DMA_TO_DEVICE) {
|
|
|
|
/* Copy the data to the bounce buffer */
|
2020-05-19 03:17:40 +08:00
|
|
|
if (host->ops->copy_to_bounce_buffer) {
|
|
|
|
host->ops->copy_to_bounce_buffer(host,
|
|
|
|
data, length);
|
|
|
|
} else {
|
|
|
|
sg_copy_to_buffer(data->sg, data->sg_len,
|
|
|
|
host->bounce_buffer, length);
|
|
|
|
}
|
2018-01-29 07:44:53 +08:00
|
|
|
}
|
|
|
|
/* Switch ownership to the DMA */
|
|
|
|
dma_sync_single_for_device(host->mmc->parent,
|
|
|
|
host->bounce_addr,
|
|
|
|
host->bounce_buffer_size,
|
|
|
|
mmc_get_dma_dir(data));
|
|
|
|
/* Just a dummy value */
|
|
|
|
sg_count = 1;
|
|
|
|
} else {
|
|
|
|
/* Just access the data directly from memory */
|
|
|
|
sg_count = dma_map_sg(mmc_dev(host->mmc),
|
|
|
|
data->sg, data->sg_len,
|
|
|
|
mmc_get_dma_dir(data));
|
|
|
|
}
|
2016-01-26 21:40:16 +08:00
|
|
|
|
|
|
|
if (sg_count == 0)
|
|
|
|
return -ENOSPC;
|
|
|
|
|
|
|
|
data->sg_count = sg_count;
|
2016-01-26 21:40:27 +08:00
|
|
|
data->host_cookie = cookie;
|
2016-01-26 21:40:16 +08:00
|
|
|
|
|
|
|
return sg_count;
|
|
|
|
}
|
|
|
|
|
2008-06-29 00:28:51 +08:00
|
|
|
static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
|
|
|
|
{
|
|
|
|
local_irq_save(*flags);
|
2011-11-27 13:27:00 +08:00
|
|
|
return kmap_atomic(sg_page(sg)) + sg->offset;
|
2008-06-29 00:28:51 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
|
|
|
|
{
|
2011-11-27 13:27:00 +08:00
|
|
|
kunmap_atomic(buffer);
|
2008-06-29 00:28:51 +08:00
|
|
|
local_irq_restore(*flags);
|
|
|
|
}
|
|
|
|
|
2018-08-28 17:47:23 +08:00
|
|
|
void sdhci_adma_write_desc(struct sdhci_host *host, void **desc,
|
|
|
|
dma_addr_t addr, int len, unsigned int cmd)
|
2010-03-06 05:43:26 +08:00
|
|
|
{
|
2018-08-28 17:47:23 +08:00
|
|
|
struct sdhci_adma2_64_desc *dma_desc = *desc;
|
2010-03-06 05:43:26 +08:00
|
|
|
|
2014-11-04 18:42:46 +08:00
|
|
|
/* 32-bit and 64-bit descriptors have these members in same position */
|
2014-11-04 18:42:45 +08:00
|
|
|
dma_desc->cmd = cpu_to_le16(cmd);
|
|
|
|
dma_desc->len = cpu_to_le16(len);
|
2019-08-29 19:22:06 +08:00
|
|
|
dma_desc->addr_lo = cpu_to_le32(lower_32_bits(addr));
|
2014-11-04 18:42:46 +08:00
|
|
|
|
|
|
|
if (host->flags & SDHCI_USE_64_BIT_DMA)
|
2019-08-29 19:22:06 +08:00
|
|
|
dma_desc->addr_hi = cpu_to_le32(upper_32_bits(addr));
|
2018-08-28 17:47:23 +08:00
|
|
|
|
|
|
|
*desc += host->desc_sz;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(sdhci_adma_write_desc);
|
|
|
|
|
|
|
|
static inline void __sdhci_adma_write_desc(struct sdhci_host *host,
|
|
|
|
void **desc, dma_addr_t addr,
|
|
|
|
int len, unsigned int cmd)
|
|
|
|
{
|
|
|
|
if (host->ops->adma_write_desc)
|
|
|
|
host->ops->adma_write_desc(host, desc, addr, len, cmd);
|
2018-09-17 13:30:41 +08:00
|
|
|
else
|
|
|
|
sdhci_adma_write_desc(host, desc, addr, len, cmd);
|
2010-03-06 05:43:26 +08:00
|
|
|
}
|
|
|
|
|
2014-11-04 18:42:40 +08:00
|
|
|
static void sdhci_adma_mark_end(void *desc)
|
|
|
|
{
|
2014-11-04 18:42:46 +08:00
|
|
|
struct sdhci_adma2_64_desc *dma_desc = desc;
|
2014-11-04 18:42:40 +08:00
|
|
|
|
2014-11-04 18:42:46 +08:00
|
|
|
/* 32-bit and 64-bit descriptors have 'cmd' in same position */
|
2014-11-04 18:42:45 +08:00
|
|
|
dma_desc->cmd |= cpu_to_le16(ADMA2_END);
|
2014-11-04 18:42:40 +08:00
|
|
|
}
|
|
|
|
|
2016-01-26 21:40:22 +08:00
|
|
|
static void sdhci_adma_table_pre(struct sdhci_host *host,
|
|
|
|
struct mmc_data *data, int sg_count)
|
2008-06-29 00:28:51 +08:00
|
|
|
{
|
|
|
|
struct scatterlist *sg;
|
|
|
|
unsigned long flags;
|
2016-01-26 21:40:00 +08:00
|
|
|
dma_addr_t addr, align_addr;
|
|
|
|
void *desc, *align;
|
|
|
|
char *buffer;
|
|
|
|
int len, offset, i;
|
2008-06-29 00:28:51 +08:00
|
|
|
|
|
|
|
/*
|
|
|
|
* The spec does not specify endianness of descriptor table.
|
|
|
|
* We currently guess that it is LE.
|
|
|
|
*/
|
|
|
|
|
2016-01-26 21:40:22 +08:00
|
|
|
host->sg_count = sg_count;
|
2008-06-29 00:28:51 +08:00
|
|
|
|
2014-11-04 18:42:39 +08:00
|
|
|
desc = host->adma_table;
|
2008-06-29 00:28:51 +08:00
|
|
|
align = host->align_buffer;
|
|
|
|
|
|
|
|
align_addr = host->align_addr;
|
|
|
|
|
|
|
|
for_each_sg(data->sg, sg, host->sg_count, i) {
|
|
|
|
addr = sg_dma_address(sg);
|
|
|
|
len = sg_dma_len(sg);
|
|
|
|
|
|
|
|
/*
|
2016-01-26 21:40:00 +08:00
|
|
|
* The SDHCI specification states that ADMA addresses must
|
|
|
|
* be 32-bit aligned. If they aren't, then we use a bounce
|
|
|
|
* buffer for the (up to three) bytes that screw up the
|
2008-06-29 00:28:51 +08:00
|
|
|
* alignment.
|
|
|
|
*/
|
2015-11-26 20:00:49 +08:00
|
|
|
offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) &
|
|
|
|
SDHCI_ADMA2_MASK;
|
2008-06-29 00:28:51 +08:00
|
|
|
if (offset) {
|
|
|
|
if (data->flags & MMC_DATA_WRITE) {
|
|
|
|
buffer = sdhci_kmap_atomic(sg, &flags);
|
|
|
|
memcpy(align, buffer, offset);
|
|
|
|
sdhci_kunmap_atomic(buffer, &flags);
|
|
|
|
}
|
|
|
|
|
2010-03-06 05:43:26 +08:00
|
|
|
/* tran, valid */
|
2018-08-28 17:47:23 +08:00
|
|
|
__sdhci_adma_write_desc(host, &desc, align_addr,
|
|
|
|
offset, ADMA2_TRAN_VALID);
|
2008-06-29 00:28:51 +08:00
|
|
|
|
|
|
|
BUG_ON(offset > 65536);
|
|
|
|
|
2015-11-26 20:00:49 +08:00
|
|
|
align += SDHCI_ADMA2_ALIGN;
|
|
|
|
align_addr += SDHCI_ADMA2_ALIGN;
|
2008-06-29 00:28:51 +08:00
|
|
|
|
|
|
|
addr += offset;
|
|
|
|
len -= offset;
|
|
|
|
}
|
|
|
|
|
|
|
|
BUG_ON(len > 65536);
|
|
|
|
|
2018-08-28 17:47:23 +08:00
|
|
|
/* tran, valid */
|
|
|
|
if (len)
|
|
|
|
__sdhci_adma_write_desc(host, &desc, addr, len,
|
|
|
|
ADMA2_TRAN_VALID);
|
2008-06-29 00:28:51 +08:00
|
|
|
|
|
|
|
/*
|
|
|
|
* If this triggers then we have a calculation bug
|
|
|
|
* somewhere. :/
|
|
|
|
*/
|
2014-11-04 18:42:42 +08:00
|
|
|
WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
|
2008-06-29 00:28:51 +08:00
|
|
|
}
|
|
|
|
|
2010-05-27 05:42:04 +08:00
|
|
|
if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
|
2016-01-26 21:40:00 +08:00
|
|
|
/* Mark the last descriptor as the terminating descriptor */
|
2014-11-04 18:42:39 +08:00
|
|
|
if (desc != host->adma_table) {
|
2014-11-04 18:42:42 +08:00
|
|
|
desc -= host->desc_sz;
|
2014-11-04 18:42:40 +08:00
|
|
|
sdhci_adma_mark_end(desc);
|
2010-05-27 05:42:04 +08:00
|
|
|
}
|
|
|
|
} else {
|
2016-01-26 21:40:00 +08:00
|
|
|
/* Add a terminating entry - nop, end, valid */
|
2018-08-28 17:47:23 +08:00
|
|
|
__sdhci_adma_write_desc(host, &desc, 0, 0, ADMA2_NOP_END_VALID);
|
2010-05-27 05:42:04 +08:00
|
|
|
}
|
2008-06-29 00:28:51 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static void sdhci_adma_table_post(struct sdhci_host *host,
|
|
|
|
struct mmc_data *data)
|
|
|
|
{
|
|
|
|
struct scatterlist *sg;
|
|
|
|
int i, size;
|
2014-11-04 18:42:41 +08:00
|
|
|
void *align;
|
2008-06-29 00:28:51 +08:00
|
|
|
char *buffer;
|
|
|
|
unsigned long flags;
|
|
|
|
|
2016-01-26 21:40:06 +08:00
|
|
|
if (data->flags & MMC_DATA_READ) {
|
|
|
|
bool has_unaligned = false;
|
2014-04-25 19:58:29 +08:00
|
|
|
|
2016-01-26 21:40:06 +08:00
|
|
|
/* Do a quick scan of the SG list for any unaligned mappings */
|
|
|
|
for_each_sg(data->sg, sg, host->sg_count, i)
|
|
|
|
if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
|
|
|
|
has_unaligned = true;
|
|
|
|
break;
|
|
|
|
}
|
2008-06-29 00:28:51 +08:00
|
|
|
|
2016-01-26 21:40:06 +08:00
|
|
|
if (has_unaligned) {
|
|
|
|
dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
|
2016-01-26 21:40:11 +08:00
|
|
|
data->sg_len, DMA_FROM_DEVICE);
|
2008-06-29 00:28:51 +08:00
|
|
|
|
2016-01-26 21:40:06 +08:00
|
|
|
align = host->align_buffer;
|
2008-06-29 00:28:51 +08:00
|
|
|
|
2016-01-26 21:40:06 +08:00
|
|
|
for_each_sg(data->sg, sg, host->sg_count, i) {
|
|
|
|
if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
|
|
|
|
size = SDHCI_ADMA2_ALIGN -
|
|
|
|
(sg_dma_address(sg) & SDHCI_ADMA2_MASK);
|
|
|
|
|
|
|
|
buffer = sdhci_kmap_atomic(sg, &flags);
|
|
|
|
memcpy(buffer, align, size);
|
|
|
|
sdhci_kunmap_atomic(buffer, &flags);
|
2008-06-29 00:28:51 +08:00
|
|
|
|
2016-01-26 21:40:06 +08:00
|
|
|
align += SDHCI_ADMA2_ALIGN;
|
|
|
|
}
|
2008-06-29 00:28:51 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-08-29 19:22:06 +08:00
|
|
|
static void sdhci_set_adma_addr(struct sdhci_host *host, dma_addr_t addr)
|
|
|
|
{
|
|
|
|
sdhci_writel(host, lower_32_bits(addr), SDHCI_ADMA_ADDRESS);
|
|
|
|
if (host->flags & SDHCI_USE_64_BIT_DMA)
|
|
|
|
sdhci_writel(host, upper_32_bits(addr), SDHCI_ADMA_ADDRESS_HI);
|
|
|
|
}
|
|
|
|
|
2018-08-30 16:21:39 +08:00
|
|
|
static dma_addr_t sdhci_sdma_address(struct sdhci_host *host)
|
2018-01-29 07:44:53 +08:00
|
|
|
{
|
|
|
|
if (host->bounce_buffer)
|
|
|
|
return host->bounce_addr;
|
|
|
|
else
|
|
|
|
return sg_dma_address(host->data->sg);
|
|
|
|
}
|
|
|
|
|
2018-08-30 16:21:39 +08:00
|
|
|
static void sdhci_set_sdma_addr(struct sdhci_host *host, dma_addr_t addr)
|
|
|
|
{
|
2019-08-29 19:22:06 +08:00
|
|
|
if (host->v4_mode)
|
|
|
|
sdhci_set_adma_addr(host, addr);
|
|
|
|
else
|
2018-08-30 16:21:39 +08:00
|
|
|
sdhci_writel(host, addr, SDHCI_DMA_ADDRESS);
|
|
|
|
}
|
|
|
|
|
2018-04-27 19:47:16 +08:00
|
|
|
static unsigned int sdhci_target_timeout(struct sdhci_host *host,
|
|
|
|
struct mmc_command *cmd,
|
|
|
|
struct mmc_data *data)
|
|
|
|
{
|
|
|
|
unsigned int target_timeout;
|
|
|
|
|
|
|
|
/* timeout in us */
|
|
|
|
if (!data) {
|
|
|
|
target_timeout = cmd->busy_timeout * 1000;
|
|
|
|
} else {
|
|
|
|
target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000);
|
|
|
|
if (host->clock && data->timeout_clks) {
|
|
|
|
unsigned long long val;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* data->timeout_clks is in units of clock cycles.
|
|
|
|
* host->clock is in Hz. target_timeout is in us.
|
|
|
|
* Hence, us = 1000000 * cycles / Hz. Round up.
|
|
|
|
*/
|
|
|
|
val = 1000000ULL * data->timeout_clks;
|
|
|
|
if (do_div(val, host->clock))
|
|
|
|
target_timeout++;
|
|
|
|
target_timeout += val;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return target_timeout;
|
|
|
|
}
|
|
|
|
|
2018-04-27 19:47:17 +08:00
|
|
|
static void sdhci_calc_sw_timeout(struct sdhci_host *host,
|
|
|
|
struct mmc_command *cmd)
|
|
|
|
{
|
|
|
|
struct mmc_data *data = cmd->data;
|
|
|
|
struct mmc_host *mmc = host->mmc;
|
|
|
|
struct mmc_ios *ios = &mmc->ios;
|
|
|
|
unsigned char bus_width = 1 << ios->bus_width;
|
|
|
|
unsigned int blksz;
|
|
|
|
unsigned int freq;
|
|
|
|
u64 target_timeout;
|
|
|
|
u64 transfer_time;
|
|
|
|
|
|
|
|
target_timeout = sdhci_target_timeout(host, cmd, data);
|
|
|
|
target_timeout *= NSEC_PER_USEC;
|
|
|
|
|
|
|
|
if (data) {
|
|
|
|
blksz = data->blksz;
|
|
|
|
freq = host->mmc->actual_clock ? : host->clock;
|
|
|
|
transfer_time = (u64)blksz * NSEC_PER_SEC * (8 / bus_width);
|
|
|
|
do_div(transfer_time, freq);
|
|
|
|
/* multiply by '2' to account for any unknowns */
|
|
|
|
transfer_time = transfer_time * 2;
|
|
|
|
/* calculate timeout for the entire data */
|
|
|
|
host->data_timeout = data->blocks * target_timeout +
|
|
|
|
transfer_time;
|
|
|
|
} else {
|
|
|
|
host->data_timeout = target_timeout;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (host->data_timeout)
|
|
|
|
host->data_timeout += MMC_CMD_TRANSFER_TIME;
|
|
|
|
}
|
|
|
|
|
2018-04-27 19:47:15 +08:00
|
|
|
static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd,
|
|
|
|
bool *too_big)
|
2006-03-24 19:18:17 +08:00
|
|
|
{
|
2006-06-30 17:22:25 +08:00
|
|
|
u8 count;
|
2019-01-07 18:11:36 +08:00
|
|
|
struct mmc_data *data;
|
2006-06-30 17:22:25 +08:00
|
|
|
unsigned target_timeout, current_timeout;
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2018-04-27 19:47:15 +08:00
|
|
|
*too_big = true;
|
|
|
|
|
2008-07-05 06:25:15 +08:00
|
|
|
/*
|
|
|
|
* If the host controller provides us with an incorrect timeout
|
|
|
|
* value, just skip the check and use 0xE. The hardware may take
|
|
|
|
* longer to time out, but that's much better than having a too-short
|
|
|
|
* timeout value.
|
|
|
|
*/
|
2009-06-22 02:59:33 +08:00
|
|
|
if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
|
2008-07-05 06:25:15 +08:00
|
|
|
return 0xE;
|
2007-08-12 22:46:32 +08:00
|
|
|
|
2019-01-07 18:11:36 +08:00
|
|
|
/* Unspecified command, asume max */
|
|
|
|
if (cmd == NULL)
|
|
|
|
return 0xE;
|
|
|
|
|
|
|
|
data = cmd->data;
|
2011-04-12 05:13:42 +08:00
|
|
|
/* Unspecified timeout, assume max */
|
2014-01-08 22:06:08 +08:00
|
|
|
if (!data && !cmd->busy_timeout)
|
2011-04-12 05:13:42 +08:00
|
|
|
return 0xE;
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2011-04-12 05:13:42 +08:00
|
|
|
/* timeout in us */
|
2018-04-27 19:47:16 +08:00
|
|
|
target_timeout = sdhci_target_timeout(host, cmd, data);
|
2009-09-23 07:45:13 +08:00
|
|
|
|
2006-06-30 17:22:25 +08:00
|
|
|
/*
|
|
|
|
* Figure out needed cycles.
|
|
|
|
* We do this in steps in order to fit inside a 32 bit int.
|
|
|
|
* The first step is the minimum timeout, which will have a
|
|
|
|
* minimum resolution of 6 bits:
|
|
|
|
* (1) 2^13*1000 > 2^22,
|
|
|
|
* (2) host->timeout_clk < 2^16
|
|
|
|
* =>
|
|
|
|
* (1) / (2) > 2^6
|
|
|
|
*/
|
|
|
|
count = 0;
|
|
|
|
current_timeout = (1 << 13) * 1000 / host->timeout_clk;
|
|
|
|
while (current_timeout < target_timeout) {
|
|
|
|
count++;
|
|
|
|
current_timeout <<= 1;
|
|
|
|
if (count >= 0xF)
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (count >= 0xF) {
|
2018-04-27 19:47:15 +08:00
|
|
|
if (!(host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT))
|
|
|
|
DBG("Too large timeout 0x%x requested for CMD%d!\n",
|
|
|
|
count, cmd->opcode);
|
2006-06-30 17:22:25 +08:00
|
|
|
count = 0xE;
|
2018-04-27 19:47:15 +08:00
|
|
|
} else {
|
|
|
|
*too_big = false;
|
2006-06-30 17:22:25 +08:00
|
|
|
}
|
|
|
|
|
2008-07-05 06:25:15 +08:00
|
|
|
return count;
|
|
|
|
}
|
|
|
|
|
2009-03-17 05:13:50 +08:00
|
|
|
static void sdhci_set_transfer_irqs(struct sdhci_host *host)
|
|
|
|
{
|
|
|
|
u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
|
|
|
|
u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
|
|
|
|
|
|
|
|
if (host->flags & SDHCI_REQ_USE_DMA)
|
2014-04-25 19:56:01 +08:00
|
|
|
host->ier = (host->ier & ~pio_irqs) | dma_irqs;
|
2009-03-17 05:13:50 +08:00
|
|
|
else
|
2014-04-25 19:56:01 +08:00
|
|
|
host->ier = (host->ier & ~dma_irqs) | pio_irqs;
|
|
|
|
|
2018-11-15 21:53:43 +08:00
|
|
|
if (host->flags & (SDHCI_AUTO_CMD23 | SDHCI_AUTO_CMD12))
|
|
|
|
host->ier |= SDHCI_INT_AUTO_CMD_ERR;
|
|
|
|
else
|
|
|
|
host->ier &= ~SDHCI_INT_AUTO_CMD_ERR;
|
|
|
|
|
2014-04-25 19:56:01 +08:00
|
|
|
sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
|
|
|
|
sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
|
2009-03-17 05:13:50 +08:00
|
|
|
}
|
|
|
|
|
2020-01-16 18:51:49 +08:00
|
|
|
void sdhci_set_data_timeout_irq(struct sdhci_host *host, bool enable)
|
2018-04-27 19:47:15 +08:00
|
|
|
{
|
|
|
|
if (enable)
|
|
|
|
host->ier |= SDHCI_INT_DATA_TIMEOUT;
|
|
|
|
else
|
|
|
|
host->ier &= ~SDHCI_INT_DATA_TIMEOUT;
|
|
|
|
sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
|
|
|
|
sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
|
|
|
|
}
|
2020-01-16 18:51:49 +08:00
|
|
|
EXPORT_SYMBOL_GPL(sdhci_set_data_timeout_irq);
|
2018-04-27 19:47:15 +08:00
|
|
|
|
2020-01-16 18:51:50 +08:00
|
|
|
void __sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
|
2008-07-05 06:25:15 +08:00
|
|
|
{
|
2020-01-16 18:51:50 +08:00
|
|
|
bool too_big = false;
|
|
|
|
u8 count = sdhci_calc_timeout(host, cmd, &too_big);
|
|
|
|
|
|
|
|
if (too_big &&
|
|
|
|
host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT) {
|
|
|
|
sdhci_calc_sw_timeout(host, cmd);
|
|
|
|
sdhci_set_data_timeout_irq(host, false);
|
|
|
|
} else if (!(host->ier & SDHCI_INT_DATA_TIMEOUT)) {
|
|
|
|
sdhci_set_data_timeout_irq(host, true);
|
|
|
|
}
|
2018-04-27 19:47:15 +08:00
|
|
|
|
2020-01-16 18:51:50 +08:00
|
|
|
sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(__sdhci_set_timeout);
|
2018-04-27 19:47:15 +08:00
|
|
|
|
2020-01-16 18:51:50 +08:00
|
|
|
static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
|
|
|
|
{
|
|
|
|
if (host->ops->set_timeout)
|
|
|
|
host->ops->set_timeout(host, cmd);
|
|
|
|
else
|
|
|
|
__sdhci_set_timeout(host, cmd);
|
2014-08-27 15:26:29 +08:00
|
|
|
}
|
|
|
|
|
2020-01-16 18:51:46 +08:00
|
|
|
static void sdhci_initialize_data(struct sdhci_host *host,
|
|
|
|
struct mmc_data *data)
|
2014-08-27 15:26:29 +08:00
|
|
|
{
|
2016-06-29 21:24:26 +08:00
|
|
|
WARN_ON(host->data);
|
|
|
|
|
2008-07-05 06:25:15 +08:00
|
|
|
/* Sanity checks */
|
|
|
|
BUG_ON(data->blksz * data->blocks > 524288);
|
|
|
|
BUG_ON(data->blksz > host->mmc->max_blk_size);
|
|
|
|
BUG_ON(data->blocks > 65535);
|
|
|
|
|
|
|
|
host->data = data;
|
|
|
|
host->data_early = 0;
|
2011-04-12 21:36:18 +08:00
|
|
|
host->data->bytes_xfered = 0;
|
2020-01-16 18:51:46 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline void sdhci_set_block_info(struct sdhci_host *host,
|
|
|
|
struct mmc_data *data)
|
|
|
|
{
|
|
|
|
/* Set the DMA boundary value and block size */
|
|
|
|
sdhci_writew(host,
|
|
|
|
SDHCI_MAKE_BLKSZ(host->sdma_boundary, data->blksz),
|
|
|
|
SDHCI_BLOCK_SIZE);
|
|
|
|
/*
|
|
|
|
* For Version 4.10 onwards, if v4 mode is enabled, 32-bit Block Count
|
|
|
|
* can be supported, in that case 16-bit block count register must be 0.
|
|
|
|
*/
|
|
|
|
if (host->version >= SDHCI_SPEC_410 && host->v4_mode &&
|
|
|
|
(host->quirks2 & SDHCI_QUIRK2_USE_32BIT_BLK_CNT)) {
|
|
|
|
if (sdhci_readw(host, SDHCI_BLOCK_COUNT))
|
|
|
|
sdhci_writew(host, 0, SDHCI_BLOCK_COUNT);
|
|
|
|
sdhci_writew(host, data->blocks, SDHCI_32BIT_BLK_CNT);
|
|
|
|
} else {
|
|
|
|
sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
|
|
|
|
{
|
|
|
|
struct mmc_data *data = cmd->data;
|
|
|
|
|
|
|
|
sdhci_initialize_data(host, data);
|
2008-07-05 06:25:15 +08:00
|
|
|
|
2016-01-26 21:41:20 +08:00
|
|
|
if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
|
2008-06-29 00:28:51 +08:00
|
|
|
struct scatterlist *sg;
|
2016-01-26 21:41:14 +08:00
|
|
|
unsigned int length_mask, offset_mask;
|
2016-01-26 21:41:09 +08:00
|
|
|
int i;
|
2008-06-29 00:28:51 +08:00
|
|
|
|
2016-01-26 21:41:20 +08:00
|
|
|
host->flags |= SDHCI_REQ_USE_DMA;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* FIXME: This doesn't account for merging when mapping the
|
|
|
|
* scatterlist.
|
|
|
|
*
|
|
|
|
* The assumption here being that alignment and lengths are
|
|
|
|
* the same after DMA mapping to device address space.
|
|
|
|
*/
|
2016-01-26 21:41:09 +08:00
|
|
|
length_mask = 0;
|
2016-01-26 21:41:14 +08:00
|
|
|
offset_mask = 0;
|
2008-06-29 00:28:51 +08:00
|
|
|
if (host->flags & SDHCI_USE_ADMA) {
|
2016-01-26 21:41:14 +08:00
|
|
|
if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) {
|
2016-01-26 21:41:09 +08:00
|
|
|
length_mask = 3;
|
2016-01-26 21:41:14 +08:00
|
|
|
/*
|
|
|
|
* As we use up to 3 byte chunks to work
|
|
|
|
* around alignment problems, we need to
|
|
|
|
* check the offset as well.
|
|
|
|
*/
|
|
|
|
offset_mask = 3;
|
|
|
|
}
|
2008-06-29 00:28:51 +08:00
|
|
|
} else {
|
|
|
|
if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
|
2016-01-26 21:41:09 +08:00
|
|
|
length_mask = 3;
|
2016-01-26 21:41:14 +08:00
|
|
|
if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
|
|
|
|
offset_mask = 3;
|
2008-06-29 00:28:51 +08:00
|
|
|
}
|
|
|
|
|
2016-01-26 21:41:14 +08:00
|
|
|
if (unlikely(length_mask | offset_mask)) {
|
2008-06-29 00:28:51 +08:00
|
|
|
for_each_sg(data->sg, sg, data->sg_len, i) {
|
2016-01-26 21:41:09 +08:00
|
|
|
if (sg->length & length_mask) {
|
2015-11-18 17:47:02 +08:00
|
|
|
DBG("Reverting to PIO because of transfer size (%d)\n",
|
2016-01-26 21:41:09 +08:00
|
|
|
sg->length);
|
2008-06-29 00:28:51 +08:00
|
|
|
host->flags &= ~SDHCI_REQ_USE_DMA;
|
|
|
|
break;
|
|
|
|
}
|
2016-01-26 21:41:09 +08:00
|
|
|
if (sg->offset & offset_mask) {
|
2015-11-18 17:47:02 +08:00
|
|
|
DBG("Reverting to PIO because of bad alignment\n");
|
2008-06-29 00:28:51 +08:00
|
|
|
host->flags &= ~SDHCI_REQ_USE_DMA;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2008-07-01 03:15:49 +08:00
|
|
|
if (host->flags & SDHCI_REQ_USE_DMA) {
|
2016-01-26 21:40:27 +08:00
|
|
|
int sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
|
2016-01-26 21:40:22 +08:00
|
|
|
|
|
|
|
if (sg_cnt <= 0) {
|
|
|
|
/*
|
|
|
|
* This only happens when someone fed
|
|
|
|
* us an invalid request.
|
|
|
|
*/
|
|
|
|
WARN_ON(1);
|
|
|
|
host->flags &= ~SDHCI_REQ_USE_DMA;
|
|
|
|
} else if (host->flags & SDHCI_USE_ADMA) {
|
|
|
|
sdhci_adma_table_pre(host, data, sg_cnt);
|
2019-08-29 19:22:06 +08:00
|
|
|
sdhci_set_adma_addr(host, host->adma_addr);
|
2008-07-01 03:15:49 +08:00
|
|
|
} else {
|
2016-01-26 21:40:22 +08:00
|
|
|
WARN_ON(sg_cnt != 1);
|
2018-08-30 16:21:39 +08:00
|
|
|
sdhci_set_sdma_addr(host, sdhci_sdma_address(host));
|
2008-07-01 03:15:49 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-08-30 16:21:40 +08:00
|
|
|
sdhci_config_dma(host);
|
2007-12-03 02:52:11 +08:00
|
|
|
|
2008-07-01 03:15:49 +08:00
|
|
|
if (!(host->flags & SDHCI_REQ_USE_DMA)) {
|
2009-06-18 15:33:32 +08:00
|
|
|
int flags;
|
|
|
|
|
|
|
|
flags = SG_MITER_ATOMIC;
|
|
|
|
if (host->data->flags & MMC_DATA_READ)
|
|
|
|
flags |= SG_MITER_TO_SG;
|
|
|
|
else
|
|
|
|
flags |= SG_MITER_FROM_SG;
|
|
|
|
sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
|
2008-07-21 06:32:11 +08:00
|
|
|
host->blocks = data->blocks;
|
2006-03-24 19:18:17 +08:00
|
|
|
}
|
2006-06-30 17:22:25 +08:00
|
|
|
|
2009-03-17 05:13:50 +08:00
|
|
|
sdhci_set_transfer_irqs(host);
|
|
|
|
|
2020-01-16 18:51:46 +08:00
|
|
|
sdhci_set_block_info(host, data);
|
2006-06-30 17:22:25 +08:00
|
|
|
}
|
|
|
|
|
2020-01-16 18:51:47 +08:00
|
|
|
#if IS_ENABLED(CONFIG_MMC_SDHCI_EXTERNAL_DMA)
|
|
|
|
|
|
|
|
static int sdhci_external_dma_init(struct sdhci_host *host)
|
|
|
|
{
|
|
|
|
int ret = 0;
|
|
|
|
struct mmc_host *mmc = host->mmc;
|
|
|
|
|
|
|
|
host->tx_chan = dma_request_chan(mmc->parent, "tx");
|
|
|
|
if (IS_ERR(host->tx_chan)) {
|
|
|
|
ret = PTR_ERR(host->tx_chan);
|
|
|
|
if (ret != -EPROBE_DEFER)
|
|
|
|
pr_warn("Failed to request TX DMA channel.\n");
|
|
|
|
host->tx_chan = NULL;
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
host->rx_chan = dma_request_chan(mmc->parent, "rx");
|
|
|
|
if (IS_ERR(host->rx_chan)) {
|
|
|
|
if (host->tx_chan) {
|
|
|
|
dma_release_channel(host->tx_chan);
|
|
|
|
host->tx_chan = NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = PTR_ERR(host->rx_chan);
|
|
|
|
if (ret != -EPROBE_DEFER)
|
|
|
|
pr_warn("Failed to request RX DMA channel.\n");
|
|
|
|
host->rx_chan = NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct dma_chan *sdhci_external_dma_channel(struct sdhci_host *host,
|
|
|
|
struct mmc_data *data)
|
|
|
|
{
|
|
|
|
return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int sdhci_external_dma_setup(struct sdhci_host *host,
|
|
|
|
struct mmc_command *cmd)
|
|
|
|
{
|
|
|
|
int ret, i;
|
2020-01-20 11:32:23 +08:00
|
|
|
enum dma_transfer_direction dir;
|
2020-01-16 18:51:47 +08:00
|
|
|
struct dma_async_tx_descriptor *desc;
|
|
|
|
struct mmc_data *data = cmd->data;
|
|
|
|
struct dma_chan *chan;
|
|
|
|
struct dma_slave_config cfg;
|
|
|
|
dma_cookie_t cookie;
|
|
|
|
int sg_cnt;
|
|
|
|
|
|
|
|
if (!host->mapbase)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
cfg.src_addr = host->mapbase + SDHCI_BUFFER;
|
|
|
|
cfg.dst_addr = host->mapbase + SDHCI_BUFFER;
|
|
|
|
cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
|
|
|
|
cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
|
|
|
|
cfg.src_maxburst = data->blksz / 4;
|
|
|
|
cfg.dst_maxburst = data->blksz / 4;
|
|
|
|
|
|
|
|
/* Sanity check: all the SG entries must be aligned by block size. */
|
|
|
|
for (i = 0; i < data->sg_len; i++) {
|
|
|
|
if ((data->sg + i)->length % data->blksz)
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
chan = sdhci_external_dma_channel(host, data);
|
|
|
|
|
|
|
|
ret = dmaengine_slave_config(chan, &cfg);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
|
|
|
|
if (sg_cnt <= 0)
|
|
|
|
return -EINVAL;
|
|
|
|
|
2020-01-20 11:32:23 +08:00
|
|
|
dir = data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
|
|
|
|
desc = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len, dir,
|
2020-01-16 18:51:47 +08:00
|
|
|
DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
|
|
|
|
if (!desc)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
desc->callback = NULL;
|
|
|
|
desc->callback_param = NULL;
|
|
|
|
|
|
|
|
cookie = dmaengine_submit(desc);
|
|
|
|
if (dma_submit_error(cookie))
|
|
|
|
ret = cookie;
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void sdhci_external_dma_release(struct sdhci_host *host)
|
|
|
|
{
|
|
|
|
if (host->tx_chan) {
|
|
|
|
dma_release_channel(host->tx_chan);
|
|
|
|
host->tx_chan = NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (host->rx_chan) {
|
|
|
|
dma_release_channel(host->rx_chan);
|
|
|
|
host->rx_chan = NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
sdhci_switch_external_dma(host, false);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void __sdhci_external_dma_prepare_data(struct sdhci_host *host,
|
|
|
|
struct mmc_command *cmd)
|
|
|
|
{
|
|
|
|
struct mmc_data *data = cmd->data;
|
|
|
|
|
|
|
|
sdhci_initialize_data(host, data);
|
|
|
|
|
|
|
|
host->flags |= SDHCI_REQ_USE_DMA;
|
|
|
|
sdhci_set_transfer_irqs(host);
|
|
|
|
|
|
|
|
sdhci_set_block_info(host, data);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void sdhci_external_dma_prepare_data(struct sdhci_host *host,
|
|
|
|
struct mmc_command *cmd)
|
|
|
|
{
|
|
|
|
if (!sdhci_external_dma_setup(host, cmd)) {
|
|
|
|
__sdhci_external_dma_prepare_data(host, cmd);
|
|
|
|
} else {
|
|
|
|
sdhci_external_dma_release(host);
|
|
|
|
pr_err("%s: Cannot use external DMA, switch to the DMA/PIO which standard SDHCI provides.\n",
|
|
|
|
mmc_hostname(host->mmc));
|
|
|
|
sdhci_prepare_data(host, cmd);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void sdhci_external_dma_pre_transfer(struct sdhci_host *host,
|
|
|
|
struct mmc_command *cmd)
|
|
|
|
{
|
|
|
|
struct dma_chan *chan;
|
|
|
|
|
|
|
|
if (!cmd->data)
|
|
|
|
return;
|
|
|
|
|
|
|
|
chan = sdhci_external_dma_channel(host, cmd->data);
|
|
|
|
if (chan)
|
|
|
|
dma_async_issue_pending(chan);
|
|
|
|
}
|
|
|
|
|
|
|
|
#else
|
|
|
|
|
|
|
|
static inline int sdhci_external_dma_init(struct sdhci_host *host)
|
|
|
|
{
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void sdhci_external_dma_release(struct sdhci_host *host)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void sdhci_external_dma_prepare_data(struct sdhci_host *host,
|
|
|
|
struct mmc_command *cmd)
|
|
|
|
{
|
|
|
|
/* This should never happen */
|
|
|
|
WARN_ON_ONCE(1);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void sdhci_external_dma_pre_transfer(struct sdhci_host *host,
|
|
|
|
struct mmc_command *cmd)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline struct dma_chan *sdhci_external_dma_channel(struct sdhci_host *host,
|
|
|
|
struct mmc_data *data)
|
|
|
|
{
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
void sdhci_switch_external_dma(struct sdhci_host *host, bool en)
|
|
|
|
{
|
|
|
|
host->use_external_dma = en;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(sdhci_switch_external_dma);
|
|
|
|
|
2016-06-29 21:24:35 +08:00
|
|
|
static inline bool sdhci_auto_cmd12(struct sdhci_host *host,
|
|
|
|
struct mmc_request *mrq)
|
|
|
|
{
|
2016-08-16 18:44:13 +08:00
|
|
|
return !mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
|
|
|
|
!mrq->cap_cmd_during_tfr;
|
2016-06-29 21:24:35 +08:00
|
|
|
}
|
|
|
|
|
2020-04-12 17:03:45 +08:00
|
|
|
static inline bool sdhci_auto_cmd23(struct sdhci_host *host,
|
|
|
|
struct mmc_request *mrq)
|
|
|
|
{
|
|
|
|
return mrq->sbc && (host->flags & SDHCI_AUTO_CMD23);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline bool sdhci_manual_cmd23(struct sdhci_host *host,
|
|
|
|
struct mmc_request *mrq)
|
|
|
|
{
|
|
|
|
return mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23);
|
|
|
|
}
|
|
|
|
|
2018-08-30 16:21:42 +08:00
|
|
|
static inline void sdhci_auto_cmd_select(struct sdhci_host *host,
|
|
|
|
struct mmc_command *cmd,
|
|
|
|
u16 *mode)
|
|
|
|
{
|
|
|
|
bool use_cmd12 = sdhci_auto_cmd12(host, cmd->mrq) &&
|
|
|
|
(cmd->opcode != SD_IO_RW_EXTENDED);
|
2020-04-12 17:03:45 +08:00
|
|
|
bool use_cmd23 = sdhci_auto_cmd23(host, cmd->mrq);
|
2018-08-30 16:21:42 +08:00
|
|
|
u16 ctrl2;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* In case of Version 4.10 or later, use of 'Auto CMD Auto
|
|
|
|
* Select' is recommended rather than use of 'Auto CMD12
|
|
|
|
* Enable' or 'Auto CMD23 Enable'.
|
|
|
|
*/
|
|
|
|
if (host->version >= SDHCI_SPEC_410 && (use_cmd12 || use_cmd23)) {
|
|
|
|
*mode |= SDHCI_TRNS_AUTO_SEL;
|
|
|
|
|
|
|
|
ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
|
|
|
|
if (use_cmd23)
|
|
|
|
ctrl2 |= SDHCI_CMD23_ENABLE;
|
|
|
|
else
|
|
|
|
ctrl2 &= ~SDHCI_CMD23_ENABLE;
|
|
|
|
sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
|
|
|
|
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* If we are sending CMD23, CMD12 never gets sent
|
|
|
|
* on successful completion (so no Auto-CMD12).
|
|
|
|
*/
|
|
|
|
if (use_cmd12)
|
|
|
|
*mode |= SDHCI_TRNS_AUTO_CMD12;
|
|
|
|
else if (use_cmd23)
|
|
|
|
*mode |= SDHCI_TRNS_AUTO_CMD23;
|
|
|
|
}
|
|
|
|
|
2006-06-30 17:22:25 +08:00
|
|
|
static void sdhci_set_transfer_mode(struct sdhci_host *host,
|
2011-05-24 04:06:37 +08:00
|
|
|
struct mmc_command *cmd)
|
2006-06-30 17:22:25 +08:00
|
|
|
{
|
2015-01-20 16:05:17 +08:00
|
|
|
u16 mode = 0;
|
2011-05-24 04:06:37 +08:00
|
|
|
struct mmc_data *data = cmd->data;
|
2006-06-30 17:22:25 +08:00
|
|
|
|
2013-10-30 22:09:48 +08:00
|
|
|
if (data == NULL) {
|
2014-11-05 14:09:00 +08:00
|
|
|
if (host->quirks2 &
|
|
|
|
SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
|
2018-07-16 14:26:54 +08:00
|
|
|
/* must not clear SDHCI_TRANSFER_MODE when tuning */
|
|
|
|
if (cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200)
|
|
|
|
sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
|
2014-11-05 14:09:00 +08:00
|
|
|
} else {
|
2013-10-30 22:09:48 +08:00
|
|
|
/* clear Auto CMD settings for no data CMDs */
|
2014-11-05 14:09:00 +08:00
|
|
|
mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
|
|
|
|
sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
|
2013-10-30 22:09:48 +08:00
|
|
|
SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
|
2014-11-05 14:09:00 +08:00
|
|
|
}
|
2006-06-30 17:22:25 +08:00
|
|
|
return;
|
2013-10-30 22:09:48 +08:00
|
|
|
}
|
2006-06-30 17:22:25 +08:00
|
|
|
|
2007-08-12 22:46:32 +08:00
|
|
|
WARN_ON(!host->data);
|
|
|
|
|
2015-01-20 16:05:17 +08:00
|
|
|
if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
|
|
|
|
mode = SDHCI_TRNS_BLK_CNT_EN;
|
|
|
|
|
2011-05-24 04:06:37 +08:00
|
|
|
if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
|
2015-01-20 16:05:17 +08:00
|
|
|
mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
|
2018-08-30 16:21:42 +08:00
|
|
|
sdhci_auto_cmd_select(host, cmd, &mode);
|
2020-04-12 17:03:45 +08:00
|
|
|
if (sdhci_auto_cmd23(host, cmd->mrq))
|
2016-06-29 21:24:25 +08:00
|
|
|
sdhci_writel(host, cmd->mrq->sbc->arg, SDHCI_ARGUMENT2);
|
2010-08-11 09:01:59 +08:00
|
|
|
}
|
2011-05-24 04:06:39 +08:00
|
|
|
|
2006-06-30 17:22:25 +08:00
|
|
|
if (data->flags & MMC_DATA_READ)
|
|
|
|
mode |= SDHCI_TRNS_READ;
|
2007-12-03 02:52:11 +08:00
|
|
|
if (host->flags & SDHCI_REQ_USE_DMA)
|
2006-06-30 17:22:25 +08:00
|
|
|
mode |= SDHCI_TRNS_DMA;
|
|
|
|
|
2009-03-17 05:13:46 +08:00
|
|
|
sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
|
2006-03-24 19:18:17 +08:00
|
|
|
}
|
|
|
|
|
2016-06-29 21:24:28 +08:00
|
|
|
static bool sdhci_needs_reset(struct sdhci_host *host, struct mmc_request *mrq)
|
|
|
|
{
|
|
|
|
return (!(host->flags & SDHCI_DEVICE_DEAD) &&
|
|
|
|
((mrq->cmd && mrq->cmd->error) ||
|
|
|
|
(mrq->sbc && mrq->sbc->error) ||
|
2018-11-15 21:53:41 +08:00
|
|
|
(mrq->data && mrq->data->stop && mrq->data->stop->error) ||
|
2016-06-29 21:24:28 +08:00
|
|
|
(host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)));
|
|
|
|
}
|
|
|
|
|
2020-01-16 18:51:46 +08:00
|
|
|
static void sdhci_set_mrq_done(struct sdhci_host *host, struct mmc_request *mrq)
|
2016-06-29 21:24:34 +08:00
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < SDHCI_MAX_MRQS; i++) {
|
|
|
|
if (host->mrqs_done[i] == mrq) {
|
|
|
|
WARN_ON(1);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0; i < SDHCI_MAX_MRQS; i++) {
|
|
|
|
if (!host->mrqs_done[i]) {
|
|
|
|
host->mrqs_done[i] = mrq;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
WARN_ON(i >= SDHCI_MAX_MRQS);
|
2020-01-16 18:51:46 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static void __sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
|
|
|
|
{
|
|
|
|
if (host->cmd && host->cmd->mrq == mrq)
|
|
|
|
host->cmd = NULL;
|
|
|
|
|
|
|
|
if (host->data_cmd && host->data_cmd->mrq == mrq)
|
|
|
|
host->data_cmd = NULL;
|
|
|
|
|
2020-04-12 17:03:49 +08:00
|
|
|
if (host->deferred_cmd && host->deferred_cmd->mrq == mrq)
|
|
|
|
host->deferred_cmd = NULL;
|
|
|
|
|
2020-01-16 18:51:46 +08:00
|
|
|
if (host->data && host->data->mrq == mrq)
|
|
|
|
host->data = NULL;
|
|
|
|
|
|
|
|
if (sdhci_needs_reset(host, mrq))
|
|
|
|
host->pending_reset = true;
|
|
|
|
|
|
|
|
sdhci_set_mrq_done(host, mrq);
|
2016-06-29 21:24:34 +08:00
|
|
|
|
2019-04-05 20:40:18 +08:00
|
|
|
sdhci_del_timer(host, mrq);
|
|
|
|
|
|
|
|
if (!sdhci_has_requests(host))
|
|
|
|
sdhci_led_deactivate(host);
|
2016-06-29 21:24:34 +08:00
|
|
|
}
|
|
|
|
|
2016-06-29 21:24:27 +08:00
|
|
|
static void sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
|
|
|
|
{
|
2016-06-29 21:24:34 +08:00
|
|
|
__sdhci_finish_mrq(host, mrq);
|
2019-04-05 20:40:16 +08:00
|
|
|
|
2019-04-05 20:40:20 +08:00
|
|
|
queue_work(host->complete_wq, &host->complete_work);
|
2016-06-29 21:24:27 +08:00
|
|
|
}
|
|
|
|
|
2020-04-12 17:03:49 +08:00
|
|
|
static void __sdhci_finish_data(struct sdhci_host *host, bool sw_data_timeout)
|
2006-03-24 19:18:17 +08:00
|
|
|
{
|
2016-06-29 21:24:36 +08:00
|
|
|
struct mmc_command *data_cmd = host->data_cmd;
|
|
|
|
struct mmc_data *data = host->data;
|
2006-03-24 19:18:17 +08:00
|
|
|
|
|
|
|
host->data = NULL;
|
2016-06-29 21:24:23 +08:00
|
|
|
host->data_cmd = NULL;
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2018-11-15 21:53:41 +08:00
|
|
|
/*
|
|
|
|
* The controller needs a reset of internal state machines upon error
|
|
|
|
* conditions.
|
|
|
|
*/
|
|
|
|
if (data->error) {
|
|
|
|
if (!host->cmd || host->cmd == data_cmd)
|
|
|
|
sdhci_do_reset(host, SDHCI_RESET_CMD);
|
|
|
|
sdhci_do_reset(host, SDHCI_RESET_DATA);
|
|
|
|
}
|
|
|
|
|
2016-01-26 21:40:42 +08:00
|
|
|
if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) ==
|
|
|
|
(SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA))
|
|
|
|
sdhci_adma_table_post(host, data);
|
2006-03-24 19:18:17 +08:00
|
|
|
|
|
|
|
/*
|
2008-04-19 02:41:49 +08:00
|
|
|
* The specification states that the block count register must
|
|
|
|
* be updated, but it does not specify at what point in the
|
|
|
|
* data flow. That makes the register entirely useless to read
|
|
|
|
* back so we have to assume that nothing made it to the card
|
|
|
|
* in the event of an error.
|
2006-03-24 19:18:17 +08:00
|
|
|
*/
|
2008-04-19 02:41:49 +08:00
|
|
|
if (data->error)
|
|
|
|
data->bytes_xfered = 0;
|
2006-03-24 19:18:17 +08:00
|
|
|
else
|
2008-04-19 02:41:49 +08:00
|
|
|
data->bytes_xfered = data->blksz * data->blocks;
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2011-05-24 04:06:37 +08:00
|
|
|
/*
|
|
|
|
* Need to send CMD12 if -
|
2019-11-14 19:18:14 +08:00
|
|
|
* a) open-ended multiblock transfer not using auto CMD12 (no CMD23)
|
2011-05-24 04:06:37 +08:00
|
|
|
* b) error in multiblock transfer
|
|
|
|
*/
|
|
|
|
if (data->stop &&
|
2019-11-14 19:18:14 +08:00
|
|
|
((!data->mrq->sbc && !sdhci_auto_cmd12(host, data->mrq)) ||
|
|
|
|
data->error)) {
|
2016-08-16 18:44:13 +08:00
|
|
|
/*
|
|
|
|
* 'cap_cmd_during_tfr' request must not use the command line
|
|
|
|
* after mmc_command_done() has been called. It is upper layer's
|
|
|
|
* responsibility to send the stop command if required.
|
|
|
|
*/
|
|
|
|
if (data->mrq->cap_cmd_during_tfr) {
|
2019-04-05 20:40:19 +08:00
|
|
|
__sdhci_finish_mrq(host, data->mrq);
|
2016-08-16 18:44:13 +08:00
|
|
|
} else {
|
|
|
|
/* Avoid triggering warning in sdhci_send_command() */
|
|
|
|
host->cmd = NULL;
|
2020-04-12 17:03:49 +08:00
|
|
|
if (!sdhci_send_command(host, data->stop)) {
|
|
|
|
if (sw_data_timeout) {
|
|
|
|
/*
|
|
|
|
* This is anyway a sw data timeout, so
|
|
|
|
* give up now.
|
|
|
|
*/
|
|
|
|
data->stop->error = -EIO;
|
|
|
|
__sdhci_finish_mrq(host, data->mrq);
|
|
|
|
} else {
|
|
|
|
WARN_ON(host->deferred_cmd);
|
|
|
|
host->deferred_cmd = data->stop;
|
|
|
|
}
|
|
|
|
}
|
2016-08-16 18:44:13 +08:00
|
|
|
}
|
2016-06-29 21:24:27 +08:00
|
|
|
} else {
|
2019-04-05 20:40:19 +08:00
|
|
|
__sdhci_finish_mrq(host, data->mrq);
|
2016-06-29 21:24:27 +08:00
|
|
|
}
|
2006-03-24 19:18:17 +08:00
|
|
|
}
|
|
|
|
|
2020-04-12 17:03:49 +08:00
|
|
|
static void sdhci_finish_data(struct sdhci_host *host)
|
|
|
|
{
|
|
|
|
__sdhci_finish_data(host, false);
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
|
2006-03-24 19:18:17 +08:00
|
|
|
{
|
|
|
|
int flags;
|
2006-06-30 17:22:28 +08:00
|
|
|
u32 mask;
|
2006-06-30 17:22:23 +08:00
|
|
|
unsigned long timeout;
|
2006-03-24 19:18:17 +08:00
|
|
|
|
|
|
|
WARN_ON(host->cmd);
|
|
|
|
|
2016-01-26 21:39:34 +08:00
|
|
|
/* Initially, a command has no error */
|
|
|
|
cmd->error = 0;
|
|
|
|
|
2016-10-05 17:11:21 +08:00
|
|
|
if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
|
|
|
|
cmd->opcode == MMC_STOP_TRANSMISSION)
|
|
|
|
cmd->flags |= MMC_RSP_BUSY;
|
|
|
|
|
2006-06-30 17:22:28 +08:00
|
|
|
mask = SDHCI_CMD_INHIBIT;
|
2016-06-29 21:24:32 +08:00
|
|
|
if (sdhci_data_line_cmd(cmd))
|
2006-06-30 17:22:28 +08:00
|
|
|
mask |= SDHCI_DATA_INHIBIT;
|
|
|
|
|
|
|
|
/* We shouldn't wait for data inihibit for stop commands, even
|
|
|
|
though they might use busy signaling */
|
2016-06-29 21:24:25 +08:00
|
|
|
if (cmd->mrq->data && (cmd == cmd->mrq->data->stop))
|
2006-06-30 17:22:28 +08:00
|
|
|
mask &= ~SDHCI_DATA_INHIBIT;
|
|
|
|
|
2020-04-12 17:03:49 +08:00
|
|
|
if (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask)
|
|
|
|
return false;
|
2006-03-24 19:18:17 +08:00
|
|
|
|
|
|
|
host->cmd = cmd;
|
2020-01-16 18:51:46 +08:00
|
|
|
host->data_timeout = 0;
|
2016-06-29 21:24:32 +08:00
|
|
|
if (sdhci_data_line_cmd(cmd)) {
|
2016-06-29 21:24:23 +08:00
|
|
|
WARN_ON(host->data_cmd);
|
|
|
|
host->data_cmd = cmd;
|
2020-01-16 18:51:46 +08:00
|
|
|
sdhci_set_timeout(host, cmd);
|
2016-06-29 21:24:23 +08:00
|
|
|
}
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2020-01-16 18:51:47 +08:00
|
|
|
if (cmd->data) {
|
|
|
|
if (host->use_external_dma)
|
|
|
|
sdhci_external_dma_prepare_data(host, cmd);
|
|
|
|
else
|
|
|
|
sdhci_prepare_data(host, cmd);
|
|
|
|
}
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2009-03-17 05:13:46 +08:00
|
|
|
sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2011-05-24 04:06:37 +08:00
|
|
|
sdhci_set_transfer_mode(host, cmd);
|
2006-06-30 17:22:25 +08:00
|
|
|
|
2006-03-24 19:18:17 +08:00
|
|
|
if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
|
2020-04-12 17:03:49 +08:00
|
|
|
WARN_ONCE(1, "Unsupported response type!\n");
|
|
|
|
/*
|
|
|
|
* This does not happen in practice because 136-bit response
|
|
|
|
* commands never have busy waiting, so rather than complicate
|
|
|
|
* the error path, just remove busy waiting and continue.
|
|
|
|
*/
|
|
|
|
cmd->flags &= ~MMC_RSP_BUSY;
|
2006-03-24 19:18:17 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
if (!(cmd->flags & MMC_RSP_PRESENT))
|
|
|
|
flags = SDHCI_CMD_RESP_NONE;
|
|
|
|
else if (cmd->flags & MMC_RSP_136)
|
|
|
|
flags = SDHCI_CMD_RESP_LONG;
|
|
|
|
else if (cmd->flags & MMC_RSP_BUSY)
|
|
|
|
flags = SDHCI_CMD_RESP_SHORT_BUSY;
|
|
|
|
else
|
|
|
|
flags = SDHCI_CMD_RESP_SHORT;
|
|
|
|
|
|
|
|
if (cmd->flags & MMC_RSP_CRC)
|
|
|
|
flags |= SDHCI_CMD_CRC;
|
|
|
|
if (cmd->flags & MMC_RSP_OPCODE)
|
|
|
|
flags |= SDHCI_CMD_INDEX;
|
2011-05-05 14:49:04 +08:00
|
|
|
|
|
|
|
/* CMD19 is special in that the Data Present Select should be set */
|
2012-01-06 12:26:39 +08:00
|
|
|
if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
|
|
|
|
cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
|
2006-03-24 19:18:17 +08:00
|
|
|
flags |= SDHCI_CMD_DATA;
|
|
|
|
|
2018-04-27 19:47:17 +08:00
|
|
|
timeout = jiffies;
|
|
|
|
if (host->data_timeout)
|
|
|
|
timeout += nsecs_to_jiffies(host->data_timeout);
|
|
|
|
else if (!cmd->data && cmd->busy_timeout > 9000)
|
|
|
|
timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
|
|
|
|
else
|
|
|
|
timeout += 10 * HZ;
|
|
|
|
sdhci_mod_timer(host, cmd->mrq, timeout);
|
|
|
|
|
2020-01-16 18:51:47 +08:00
|
|
|
if (host->use_external_dma)
|
|
|
|
sdhci_external_dma_pre_transfer(host, cmd);
|
|
|
|
|
2009-03-17 05:13:46 +08:00
|
|
|
sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
|
2020-04-12 17:03:49 +08:00
|
|
|
|
|
|
|
return true;
|
2006-03-24 19:18:17 +08:00
|
|
|
}
|
|
|
|
|
2020-04-12 17:03:48 +08:00
|
|
|
static bool sdhci_present_error(struct sdhci_host *host,
|
|
|
|
struct mmc_command *cmd, bool present)
|
|
|
|
{
|
|
|
|
if (!present || host->flags & SDHCI_DEVICE_DEAD) {
|
|
|
|
cmd->error = -ENOMEDIUM;
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2020-04-12 17:03:49 +08:00
|
|
|
static bool sdhci_send_command_retry(struct sdhci_host *host,
|
|
|
|
struct mmc_command *cmd,
|
|
|
|
unsigned long flags)
|
|
|
|
__releases(host->lock)
|
|
|
|
__acquires(host->lock)
|
|
|
|
{
|
|
|
|
struct mmc_command *deferred_cmd = host->deferred_cmd;
|
|
|
|
int timeout = 10; /* Approx. 10 ms */
|
|
|
|
bool present;
|
|
|
|
|
|
|
|
while (!sdhci_send_command(host, cmd)) {
|
|
|
|
if (!timeout--) {
|
|
|
|
pr_err("%s: Controller never released inhibit bit(s).\n",
|
|
|
|
mmc_hostname(host->mmc));
|
|
|
|
sdhci_dumpregs(host);
|
|
|
|
cmd->error = -EIO;
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&host->lock, flags);
|
|
|
|
|
|
|
|
usleep_range(1000, 1250);
|
|
|
|
|
|
|
|
present = host->mmc->ops->get_cd(host->mmc);
|
|
|
|
|
|
|
|
spin_lock_irqsave(&host->lock, flags);
|
|
|
|
|
|
|
|
/* A deferred command might disappear, handle that */
|
|
|
|
if (cmd == deferred_cmd && cmd != host->deferred_cmd)
|
|
|
|
return true;
|
|
|
|
|
|
|
|
if (sdhci_present_error(host, cmd, present))
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (cmd == host->deferred_cmd)
|
|
|
|
host->deferred_cmd = NULL;
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2017-08-21 15:41:28 +08:00
|
|
|
static void sdhci_read_rsp_136(struct sdhci_host *host, struct mmc_command *cmd)
|
|
|
|
{
|
|
|
|
int i, reg;
|
|
|
|
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
|
|
reg = SDHCI_RESPONSE + (3 - i) * 4;
|
|
|
|
cmd->resp[i] = sdhci_readl(host, reg);
|
|
|
|
}
|
|
|
|
|
2017-08-21 15:41:29 +08:00
|
|
|
if (host->quirks2 & SDHCI_QUIRK2_RSP_136_HAS_CRC)
|
|
|
|
return;
|
|
|
|
|
2017-08-21 15:41:28 +08:00
|
|
|
/* CRC is stripped so we need to do some shifting */
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
|
|
cmd->resp[i] <<= 8;
|
|
|
|
if (i != 3)
|
|
|
|
cmd->resp[i] |= cmd->resp[i + 1] >> 24;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2006-03-24 19:18:17 +08:00
|
|
|
static void sdhci_finish_command(struct sdhci_host *host)
|
|
|
|
{
|
2016-06-29 21:24:22 +08:00
|
|
|
struct mmc_command *cmd = host->cmd;
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2016-06-29 21:24:22 +08:00
|
|
|
host->cmd = NULL;
|
|
|
|
|
|
|
|
if (cmd->flags & MMC_RSP_PRESENT) {
|
|
|
|
if (cmd->flags & MMC_RSP_136) {
|
2017-08-21 15:41:28 +08:00
|
|
|
sdhci_read_rsp_136(host, cmd);
|
2006-03-24 19:18:17 +08:00
|
|
|
} else {
|
2016-06-29 21:24:22 +08:00
|
|
|
cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
|
2006-03-24 19:18:17 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-08-16 18:44:13 +08:00
|
|
|
if (cmd->mrq->cap_cmd_during_tfr && cmd == cmd->mrq->cmd)
|
|
|
|
mmc_command_done(host->mmc, cmd->mrq);
|
|
|
|
|
2016-06-29 21:24:20 +08:00
|
|
|
/*
|
|
|
|
* The host can send and interrupt when the busy state has
|
|
|
|
* ended, allowing us to wait without wasting CPU cycles.
|
|
|
|
* The busy signal uses DAT0 so this is similar to waiting
|
|
|
|
* for data to complete.
|
|
|
|
*
|
|
|
|
* Note: The 1.0 specification is a bit ambiguous about this
|
|
|
|
* feature so there might be some problems with older
|
|
|
|
* controllers.
|
|
|
|
*/
|
2016-06-29 21:24:22 +08:00
|
|
|
if (cmd->flags & MMC_RSP_BUSY) {
|
|
|
|
if (cmd->data) {
|
2016-06-29 21:24:20 +08:00
|
|
|
DBG("Cannot wait for busy signal when also doing a data transfer");
|
|
|
|
} else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) &&
|
2016-06-29 21:24:24 +08:00
|
|
|
cmd == host->data_cmd) {
|
|
|
|
/* Command complete before busy is ended */
|
2016-06-29 21:24:20 +08:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-05-24 04:06:37 +08:00
|
|
|
/* Finished CMD23, now send actual command. */
|
2016-06-29 21:24:25 +08:00
|
|
|
if (cmd == cmd->mrq->sbc) {
|
2020-04-12 17:03:49 +08:00
|
|
|
if (!sdhci_send_command(host, cmd->mrq->cmd)) {
|
|
|
|
WARN_ON(host->deferred_cmd);
|
|
|
|
host->deferred_cmd = cmd->mrq->cmd;
|
|
|
|
}
|
2011-05-24 04:06:37 +08:00
|
|
|
} else {
|
2007-08-12 22:46:32 +08:00
|
|
|
|
2011-05-24 04:06:37 +08:00
|
|
|
/* Processed actual command. */
|
|
|
|
if (host->data && host->data_early)
|
|
|
|
sdhci_finish_data(host);
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2016-06-29 21:24:22 +08:00
|
|
|
if (!cmd->data)
|
2019-04-05 20:40:19 +08:00
|
|
|
__sdhci_finish_mrq(host, cmd->mrq);
|
2011-05-24 04:06:37 +08:00
|
|
|
}
|
2006-03-24 19:18:17 +08:00
|
|
|
}
|
|
|
|
|
2013-01-31 11:31:37 +08:00
|
|
|
static u16 sdhci_get_preset_value(struct sdhci_host *host)
|
|
|
|
{
|
2014-04-25 19:59:31 +08:00
|
|
|
u16 preset = 0;
|
2013-01-31 11:31:37 +08:00
|
|
|
|
2014-04-25 19:59:31 +08:00
|
|
|
switch (host->timing) {
|
|
|
|
case MMC_TIMING_UHS_SDR12:
|
2013-01-31 11:31:37 +08:00
|
|
|
preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
|
|
|
|
break;
|
2014-04-25 19:59:31 +08:00
|
|
|
case MMC_TIMING_UHS_SDR25:
|
2013-01-31 11:31:37 +08:00
|
|
|
preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
|
|
|
|
break;
|
2014-04-25 19:59:31 +08:00
|
|
|
case MMC_TIMING_UHS_SDR50:
|
2013-01-31 11:31:37 +08:00
|
|
|
preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
|
|
|
|
break;
|
2014-04-25 19:59:31 +08:00
|
|
|
case MMC_TIMING_UHS_SDR104:
|
|
|
|
case MMC_TIMING_MMC_HS200:
|
2013-01-31 11:31:37 +08:00
|
|
|
preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
|
|
|
|
break;
|
2014-04-25 19:59:31 +08:00
|
|
|
case MMC_TIMING_UHS_DDR50:
|
mmc: sdhci: also get preset value and driver type for MMC_DDR52
commit bb8175a8aa42 ("mmc: sdhci: clarify DDR timing mode between
SD-UHS and eMMC") added MMC_DDR52 as eMMC's DDR mode to be
distinguished from SD-UHS, but it missed setting driver type for
MMC_DDR52 timing mode.
So sometimes we get the following error on Marvell BG2Q DMP board:
[ 1.559598] mmcblk0: error -84 transferring data, sector 0, nr 8, cmd
response 0x900, card status 0xb00
[ 1.569314] mmcblk0: retrying using single block read
[ 1.575676] mmcblk0: error -84 transferring data, sector 2, nr 6, cmd
response 0x900, card status 0x0
[ 1.585202] blk_update_request: I/O error, dev mmcblk0, sector 2
[ 1.591818] mmcblk0: error -84 transferring data, sector 3, nr 5, cmd
response 0x900, card status 0x0
[ 1.601341] blk_update_request: I/O error, dev mmcblk0, sector 3
This patches fixes this by adding the missing driver type setting.
Fixes: bb8175a8aa42 ("mmc: sdhci: clarify DDR timing mode ...")
Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-08-18 16:21:39 +08:00
|
|
|
case MMC_TIMING_MMC_DDR52:
|
2013-01-31 11:31:37 +08:00
|
|
|
preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
|
|
|
|
break;
|
2014-11-06 21:19:06 +08:00
|
|
|
case MMC_TIMING_MMC_HS400:
|
|
|
|
preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
|
|
|
|
break;
|
2013-01-31 11:31:37 +08:00
|
|
|
default:
|
|
|
|
pr_warn("%s: Invalid UHS-I mode selected\n",
|
|
|
|
mmc_hostname(host->mmc));
|
|
|
|
preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
return preset;
|
|
|
|
}
|
|
|
|
|
2016-04-07 17:13:08 +08:00
|
|
|
u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
|
|
|
|
unsigned int *actual_clock)
|
2006-03-24 19:18:17 +08:00
|
|
|
{
|
2011-05-05 14:49:06 +08:00
|
|
|
int div = 0; /* Initialized for compiler warning */
|
2011-11-04 20:53:19 +08:00
|
|
|
int real_div = div, clk_mul = 1;
|
2011-05-05 14:49:06 +08:00
|
|
|
u16 clk = 0;
|
2015-07-29 22:22:46 +08:00
|
|
|
bool switch_base_clk = false;
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2010-08-06 07:10:01 +08:00
|
|
|
if (host->version >= SDHCI_SPEC_300) {
|
2014-04-25 20:00:12 +08:00
|
|
|
if (host->preset_enabled) {
|
2013-01-31 11:31:37 +08:00
|
|
|
u16 pre_val;
|
|
|
|
|
|
|
|
clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
|
|
|
|
pre_val = sdhci_get_preset_value(host);
|
2020-03-12 19:00:50 +08:00
|
|
|
div = FIELD_GET(SDHCI_PRESET_SDCLK_FREQ_MASK, pre_val);
|
2013-01-31 11:31:37 +08:00
|
|
|
if (host->clk_mul &&
|
2020-03-12 19:00:50 +08:00
|
|
|
(pre_val & SDHCI_PRESET_CLKGEN_SEL)) {
|
2013-01-31 11:31:37 +08:00
|
|
|
clk = SDHCI_PROG_CLOCK_MODE;
|
|
|
|
real_div = div + 1;
|
|
|
|
clk_mul = host->clk_mul;
|
|
|
|
} else {
|
|
|
|
real_div = max_t(int, 1, div << 1);
|
|
|
|
}
|
|
|
|
goto clock_set;
|
|
|
|
}
|
|
|
|
|
2011-05-05 14:49:06 +08:00
|
|
|
/*
|
|
|
|
* Check if the Host Controller supports Programmable Clock
|
|
|
|
* Mode.
|
|
|
|
*/
|
|
|
|
if (host->clk_mul) {
|
2013-01-31 11:31:37 +08:00
|
|
|
for (div = 1; div <= 1024; div++) {
|
|
|
|
if ((host->max_clk * host->clk_mul / div)
|
|
|
|
<= clock)
|
|
|
|
break;
|
|
|
|
}
|
2015-07-29 22:22:46 +08:00
|
|
|
if ((host->max_clk * host->clk_mul / div) <= clock) {
|
|
|
|
/*
|
|
|
|
* Set Programmable Clock Mode in the Clock
|
|
|
|
* Control register.
|
|
|
|
*/
|
|
|
|
clk = SDHCI_PROG_CLOCK_MODE;
|
|
|
|
real_div = div;
|
|
|
|
clk_mul = host->clk_mul;
|
|
|
|
div--;
|
|
|
|
} else {
|
|
|
|
/*
|
|
|
|
* Divisor can be too small to reach clock
|
|
|
|
* speed requirement. Then use the base clock.
|
|
|
|
*/
|
|
|
|
switch_base_clk = true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!host->clk_mul || switch_base_clk) {
|
2011-05-05 14:49:06 +08:00
|
|
|
/* Version 3.00 divisors must be a multiple of 2. */
|
|
|
|
if (host->max_clk <= clock)
|
|
|
|
div = 1;
|
|
|
|
else {
|
|
|
|
for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
|
|
|
|
div += 2) {
|
|
|
|
if ((host->max_clk / div) <= clock)
|
|
|
|
break;
|
|
|
|
}
|
2010-08-06 07:10:01 +08:00
|
|
|
}
|
2011-11-04 20:53:19 +08:00
|
|
|
real_div = div;
|
2011-05-05 14:49:06 +08:00
|
|
|
div >>= 1;
|
2015-06-09 15:31:50 +08:00
|
|
|
if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
|
|
|
|
&& !div && host->max_clk <= 25000000)
|
|
|
|
div = 1;
|
2010-08-06 07:10:01 +08:00
|
|
|
}
|
|
|
|
} else {
|
|
|
|
/* Version 2.00 divisors must be a power of 2. */
|
2010-09-21 03:15:18 +08:00
|
|
|
for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
|
2010-08-06 07:10:01 +08:00
|
|
|
if ((host->max_clk / div) <= clock)
|
|
|
|
break;
|
|
|
|
}
|
2011-11-04 20:53:19 +08:00
|
|
|
real_div = div;
|
2011-05-05 14:49:06 +08:00
|
|
|
div >>= 1;
|
2006-03-24 19:18:17 +08:00
|
|
|
}
|
|
|
|
|
2013-01-31 11:31:37 +08:00
|
|
|
clock_set:
|
2014-08-27 15:26:32 +08:00
|
|
|
if (real_div)
|
2016-04-07 17:13:08 +08:00
|
|
|
*actual_clock = (host->max_clk * clk_mul) / real_div;
|
2011-05-05 14:49:06 +08:00
|
|
|
clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
|
2010-08-06 07:10:01 +08:00
|
|
|
clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
|
|
|
|
<< SDHCI_DIVIDER_HI_SHIFT;
|
2016-04-07 17:13:08 +08:00
|
|
|
|
|
|
|
return clk;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(sdhci_calc_clk);
|
|
|
|
|
2016-11-21 14:37:19 +08:00
|
|
|
void sdhci_enable_clk(struct sdhci_host *host, u16 clk)
|
2016-04-07 17:13:08 +08:00
|
|
|
{
|
2017-03-21 01:50:31 +08:00
|
|
|
ktime_t timeout;
|
2016-04-07 17:13:08 +08:00
|
|
|
|
2006-03-24 19:18:17 +08:00
|
|
|
clk |= SDHCI_CLOCK_INT_EN;
|
2009-03-17 05:13:46 +08:00
|
|
|
sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2019-08-27 08:32:42 +08:00
|
|
|
/* Wait max 150 ms */
|
|
|
|
timeout = ktime_add_ms(ktime_get(), 150);
|
2018-12-06 17:24:59 +08:00
|
|
|
while (1) {
|
|
|
|
bool timedout = ktime_after(ktime_get(), timeout);
|
|
|
|
|
|
|
|
clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
|
|
|
|
if (clk & SDHCI_CLOCK_INT_STABLE)
|
|
|
|
break;
|
|
|
|
if (timedout) {
|
2015-11-18 17:47:02 +08:00
|
|
|
pr_err("%s: Internal clock never stabilised.\n",
|
|
|
|
mmc_hostname(host->mmc));
|
2006-03-24 19:18:17 +08:00
|
|
|
sdhci_dumpregs(host);
|
|
|
|
return;
|
|
|
|
}
|
2017-03-21 01:50:31 +08:00
|
|
|
udelay(10);
|
2006-06-30 17:22:23 +08:00
|
|
|
}
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2019-08-27 08:32:55 +08:00
|
|
|
if (host->version >= SDHCI_SPEC_410 && host->v4_mode) {
|
|
|
|
clk |= SDHCI_CLOCK_PLL_EN;
|
|
|
|
clk &= ~SDHCI_CLOCK_INT_STABLE;
|
|
|
|
sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
|
|
|
|
|
|
|
|
/* Wait max 150 ms */
|
|
|
|
timeout = ktime_add_ms(ktime_get(), 150);
|
|
|
|
while (1) {
|
|
|
|
bool timedout = ktime_after(ktime_get(), timeout);
|
|
|
|
|
|
|
|
clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
|
|
|
|
if (clk & SDHCI_CLOCK_INT_STABLE)
|
|
|
|
break;
|
|
|
|
if (timedout) {
|
|
|
|
pr_err("%s: PLL clock never stabilised.\n",
|
|
|
|
mmc_hostname(host->mmc));
|
|
|
|
sdhci_dumpregs(host);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
udelay(10);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2006-03-24 19:18:17 +08:00
|
|
|
clk |= SDHCI_CLOCK_CARD_EN;
|
2009-03-17 05:13:46 +08:00
|
|
|
sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
|
2006-03-24 19:18:17 +08:00
|
|
|
}
|
2016-11-21 14:37:19 +08:00
|
|
|
EXPORT_SYMBOL_GPL(sdhci_enable_clk);
|
|
|
|
|
|
|
|
void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
|
|
|
|
{
|
|
|
|
u16 clk;
|
|
|
|
|
|
|
|
host->mmc->actual_clock = 0;
|
|
|
|
|
|
|
|
sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
|
|
|
|
|
|
|
|
if (clock == 0)
|
|
|
|
return;
|
|
|
|
|
|
|
|
clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
|
|
|
|
sdhci_enable_clk(host, clk);
|
|
|
|
}
|
2014-04-25 19:58:55 +08:00
|
|
|
EXPORT_SYMBOL_GPL(sdhci_set_clock);
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2016-03-29 17:45:43 +08:00
|
|
|
static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode,
|
|
|
|
unsigned short vdd)
|
2006-06-30 17:22:23 +08:00
|
|
|
{
|
2014-06-14 01:13:56 +08:00
|
|
|
struct mmc_host *mmc = host->mmc;
|
2016-03-29 17:45:43 +08:00
|
|
|
|
|
|
|
mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
|
|
|
|
|
|
|
|
if (mode != MMC_POWER_OFF)
|
|
|
|
sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
|
|
|
|
else
|
|
|
|
sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
|
|
|
|
}
|
|
|
|
|
2016-10-05 17:11:22 +08:00
|
|
|
void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode,
|
|
|
|
unsigned short vdd)
|
2016-03-29 17:45:43 +08:00
|
|
|
{
|
2010-09-28 16:41:28 +08:00
|
|
|
u8 pwr = 0;
|
2006-06-30 17:22:23 +08:00
|
|
|
|
2014-04-25 20:00:06 +08:00
|
|
|
if (mode != MMC_POWER_OFF) {
|
|
|
|
switch (1 << vdd) {
|
2009-05-04 02:45:03 +08:00
|
|
|
case MMC_VDD_165_195:
|
2018-01-11 21:51:58 +08:00
|
|
|
/*
|
|
|
|
* Without a regulator, SDHCI does not support 2.0v
|
|
|
|
* so we only get here if the driver deliberately
|
|
|
|
* added the 2.0v range to ocr_avail. Map it to 1.8v
|
|
|
|
* for the purpose of turning on the power.
|
|
|
|
*/
|
|
|
|
case MMC_VDD_20_21:
|
2009-05-04 02:45:03 +08:00
|
|
|
pwr = SDHCI_POWER_180;
|
|
|
|
break;
|
|
|
|
case MMC_VDD_29_30:
|
|
|
|
case MMC_VDD_30_31:
|
|
|
|
pwr = SDHCI_POWER_300;
|
|
|
|
break;
|
|
|
|
case MMC_VDD_32_33:
|
|
|
|
case MMC_VDD_33_34:
|
|
|
|
pwr = SDHCI_POWER_330;
|
|
|
|
break;
|
|
|
|
default:
|
2015-11-26 20:00:46 +08:00
|
|
|
WARN(1, "%s: Invalid vdd %#x\n",
|
|
|
|
mmc_hostname(host->mmc), vdd);
|
|
|
|
break;
|
2009-05-04 02:45:03 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (host->pwr == pwr)
|
2014-04-25 20:00:01 +08:00
|
|
|
return;
|
2006-06-30 17:22:23 +08:00
|
|
|
|
2009-05-04 02:45:03 +08:00
|
|
|
host->pwr = pwr;
|
|
|
|
|
|
|
|
if (pwr == 0) {
|
2009-03-17 05:13:46 +08:00
|
|
|
sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
|
2013-05-06 17:17:32 +08:00
|
|
|
if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
|
|
|
|
sdhci_runtime_pm_bus_off(host);
|
2014-04-25 20:00:01 +08:00
|
|
|
} else {
|
|
|
|
/*
|
|
|
|
* Spec says that we should clear the power reg before setting
|
|
|
|
* a new value. Some controllers don't seem to like this though.
|
|
|
|
*/
|
|
|
|
if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
|
|
|
|
sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
|
2006-06-30 17:22:23 +08:00
|
|
|
|
2014-04-25 20:00:01 +08:00
|
|
|
/*
|
|
|
|
* At least the Marvell CaFe chip gets confused if we set the
|
|
|
|
* voltage and set turn on power at the same time, so set the
|
|
|
|
* voltage first.
|
|
|
|
*/
|
|
|
|
if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
|
|
|
|
sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
|
2008-07-05 01:00:03 +08:00
|
|
|
|
2014-04-25 20:00:01 +08:00
|
|
|
pwr |= SDHCI_POWER_ON;
|
2006-06-30 17:22:23 +08:00
|
|
|
|
2014-04-25 20:00:01 +08:00
|
|
|
sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
|
2009-06-18 22:53:38 +08:00
|
|
|
|
2014-04-25 20:00:01 +08:00
|
|
|
if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
|
|
|
|
sdhci_runtime_pm_bus_on(host);
|
2013-05-06 17:17:32 +08:00
|
|
|
|
2014-04-25 20:00:01 +08:00
|
|
|
/*
|
|
|
|
* Some controllers need an extra 10ms delay of 10ms before
|
|
|
|
* they can apply clock after applying power
|
|
|
|
*/
|
|
|
|
if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
|
|
|
|
mdelay(10);
|
|
|
|
}
|
2016-03-29 17:45:43 +08:00
|
|
|
}
|
2016-10-05 17:11:22 +08:00
|
|
|
EXPORT_SYMBOL_GPL(sdhci_set_power_noreg);
|
2015-12-11 21:36:29 +08:00
|
|
|
|
2016-10-05 17:11:22 +08:00
|
|
|
void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
|
|
|
|
unsigned short vdd)
|
2016-03-29 17:45:43 +08:00
|
|
|
{
|
2016-10-05 17:11:22 +08:00
|
|
|
if (IS_ERR(host->mmc->supply.vmmc))
|
|
|
|
sdhci_set_power_noreg(host, mode, vdd);
|
2016-03-29 17:45:43 +08:00
|
|
|
else
|
2016-10-05 17:11:22 +08:00
|
|
|
sdhci_set_power_reg(host, mode, vdd);
|
2006-06-30 17:22:23 +08:00
|
|
|
}
|
2016-10-05 17:11:22 +08:00
|
|
|
EXPORT_SYMBOL_GPL(sdhci_set_power);
|
2006-06-30 17:22:23 +08:00
|
|
|
|
2020-03-07 01:44:03 +08:00
|
|
|
/*
|
|
|
|
* Some controllers need to configure a valid bus voltage on their power
|
|
|
|
* register regardless of whether an external regulator is taking care of power
|
|
|
|
* supply. This helper function takes care of it if set as the controller's
|
|
|
|
* sdhci_ops.set_power callback.
|
|
|
|
*/
|
|
|
|
void sdhci_set_power_and_bus_voltage(struct sdhci_host *host,
|
|
|
|
unsigned char mode,
|
|
|
|
unsigned short vdd)
|
|
|
|
{
|
|
|
|
if (!IS_ERR(host->mmc->supply.vmmc)) {
|
|
|
|
struct mmc_host *mmc = host->mmc;
|
|
|
|
|
|
|
|
mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
|
|
|
|
}
|
|
|
|
sdhci_set_power_noreg(host, mode, vdd);
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(sdhci_set_power_and_bus_voltage);
|
|
|
|
|
2006-03-24 19:18:17 +08:00
|
|
|
/*****************************************************************************\
|
|
|
|
* *
|
|
|
|
* MMC callbacks *
|
|
|
|
* *
|
|
|
|
\*****************************************************************************/
|
|
|
|
|
2018-08-20 17:23:32 +08:00
|
|
|
void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
|
2006-03-24 19:18:17 +08:00
|
|
|
{
|
2020-04-12 17:03:48 +08:00
|
|
|
struct sdhci_host *host = mmc_priv(mmc);
|
|
|
|
struct mmc_command *cmd;
|
2006-03-24 19:18:17 +08:00
|
|
|
unsigned long flags;
|
2020-04-12 17:03:48 +08:00
|
|
|
bool present;
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2015-03-11 02:35:10 +08:00
|
|
|
/* Firstly check card presence */
|
2016-02-09 22:12:36 +08:00
|
|
|
present = mmc->ops->get_cd(mmc);
|
2015-01-05 17:50:15 +08:00
|
|
|
|
2006-03-24 19:18:17 +08:00
|
|
|
spin_lock_irqsave(&host->lock, flags);
|
|
|
|
|
2016-04-12 19:25:09 +08:00
|
|
|
sdhci_led_activate(host);
|
2011-05-24 04:06:37 +08:00
|
|
|
|
2020-04-12 17:03:48 +08:00
|
|
|
if (sdhci_present_error(host, mrq->cmd, present))
|
|
|
|
goto out_finish;
|
|
|
|
|
|
|
|
cmd = sdhci_manual_cmd23(host, mrq) ? mrq->sbc : mrq->cmd;
|
|
|
|
|
2020-04-12 17:03:49 +08:00
|
|
|
if (!sdhci_send_command_retry(host, cmd, flags))
|
|
|
|
goto out_finish;
|
2020-04-12 17:03:48 +08:00
|
|
|
|
|
|
|
spin_unlock_irqrestore(&host->lock, flags);
|
|
|
|
|
|
|
|
return;
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2020-04-12 17:03:48 +08:00
|
|
|
out_finish:
|
|
|
|
sdhci_finish_mrq(host, mrq);
|
2006-03-24 19:18:17 +08:00
|
|
|
spin_unlock_irqrestore(&host->lock, flags);
|
|
|
|
}
|
2018-08-20 17:23:32 +08:00
|
|
|
EXPORT_SYMBOL_GPL(sdhci_request);
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2020-04-13 10:46:04 +08:00
|
|
|
int sdhci_request_atomic(struct mmc_host *mmc, struct mmc_request *mrq)
|
|
|
|
{
|
|
|
|
struct sdhci_host *host = mmc_priv(mmc);
|
|
|
|
struct mmc_command *cmd;
|
|
|
|
unsigned long flags;
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&host->lock, flags);
|
|
|
|
|
|
|
|
if (sdhci_present_error(host, mrq->cmd, true)) {
|
|
|
|
sdhci_finish_mrq(host, mrq);
|
|
|
|
goto out_finish;
|
|
|
|
}
|
|
|
|
|
|
|
|
cmd = sdhci_manual_cmd23(host, mrq) ? mrq->sbc : mrq->cmd;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The HSQ may send a command in interrupt context without polling
|
|
|
|
* the busy signaling, which means we should return BUSY if controller
|
|
|
|
* has not released inhibit bits to allow HSQ trying to send request
|
|
|
|
* again in non-atomic context. So we should not finish this request
|
|
|
|
* here.
|
|
|
|
*/
|
|
|
|
if (!sdhci_send_command(host, cmd))
|
|
|
|
ret = -EBUSY;
|
|
|
|
else
|
|
|
|
sdhci_led_activate(host);
|
|
|
|
|
|
|
|
out_finish:
|
|
|
|
spin_unlock_irqrestore(&host->lock, flags);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(sdhci_request_atomic);
|
|
|
|
|
2014-04-25 19:57:07 +08:00
|
|
|
void sdhci_set_bus_width(struct sdhci_host *host, int width)
|
|
|
|
{
|
|
|
|
u8 ctrl;
|
|
|
|
|
|
|
|
ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
|
|
|
|
if (width == MMC_BUS_WIDTH_8) {
|
|
|
|
ctrl &= ~SDHCI_CTRL_4BITBUS;
|
2017-08-15 04:00:24 +08:00
|
|
|
ctrl |= SDHCI_CTRL_8BITBUS;
|
2014-04-25 19:57:07 +08:00
|
|
|
} else {
|
2017-08-15 04:00:24 +08:00
|
|
|
if (host->mmc->caps & MMC_CAP_8_BIT_DATA)
|
2014-04-25 19:57:07 +08:00
|
|
|
ctrl &= ~SDHCI_CTRL_8BITBUS;
|
|
|
|
if (width == MMC_BUS_WIDTH_4)
|
|
|
|
ctrl |= SDHCI_CTRL_4BITBUS;
|
|
|
|
else
|
|
|
|
ctrl &= ~SDHCI_CTRL_4BITBUS;
|
|
|
|
}
|
|
|
|
sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
|
|
|
|
|
2014-04-25 19:59:26 +08:00
|
|
|
void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
|
|
|
|
{
|
|
|
|
u16 ctrl_2;
|
|
|
|
|
|
|
|
ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
|
|
|
|
/* Select Bus Speed Mode for host */
|
|
|
|
ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
|
|
|
|
if ((timing == MMC_TIMING_MMC_HS200) ||
|
|
|
|
(timing == MMC_TIMING_UHS_SDR104))
|
|
|
|
ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
|
|
|
|
else if (timing == MMC_TIMING_UHS_SDR12)
|
|
|
|
ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
|
2019-11-28 19:04:22 +08:00
|
|
|
else if (timing == MMC_TIMING_UHS_SDR25)
|
2014-04-25 19:59:26 +08:00
|
|
|
ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
|
|
|
|
else if (timing == MMC_TIMING_UHS_SDR50)
|
|
|
|
ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
|
|
|
|
else if ((timing == MMC_TIMING_UHS_DDR50) ||
|
|
|
|
(timing == MMC_TIMING_MMC_DDR52))
|
|
|
|
ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
|
2014-11-06 21:19:06 +08:00
|
|
|
else if (timing == MMC_TIMING_MMC_HS400)
|
|
|
|
ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
|
2014-04-25 19:59:26 +08:00
|
|
|
sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
|
|
|
|
|
2017-03-30 23:22:55 +08:00
|
|
|
void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
|
2006-03-24 19:18:17 +08:00
|
|
|
{
|
2016-04-16 01:29:25 +08:00
|
|
|
struct sdhci_host *host = mmc_priv(mmc);
|
2006-03-24 19:18:17 +08:00
|
|
|
u8 ctrl;
|
|
|
|
|
2016-12-19 21:33:11 +08:00
|
|
|
if (ios->power_mode == MMC_POWER_UNDEFINED)
|
|
|
|
return;
|
|
|
|
|
2011-12-27 21:48:41 +08:00
|
|
|
if (host->flags & SDHCI_DEVICE_DEAD) {
|
2014-06-14 01:13:56 +08:00
|
|
|
if (!IS_ERR(mmc->supply.vmmc) &&
|
|
|
|
ios->power_mode == MMC_POWER_OFF)
|
2014-07-04 04:27:42 +08:00
|
|
|
mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
|
2011-12-27 21:48:41 +08:00
|
|
|
return;
|
|
|
|
}
|
2008-04-17 01:13:13 +08:00
|
|
|
|
2006-03-24 19:18:17 +08:00
|
|
|
/*
|
|
|
|
* Reset the chip on each power off.
|
|
|
|
* Should clear out any weird states.
|
|
|
|
*/
|
|
|
|
if (ios->power_mode == MMC_POWER_OFF) {
|
2009-03-17 05:13:46 +08:00
|
|
|
sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
|
2009-03-17 05:13:48 +08:00
|
|
|
sdhci_reinit(host);
|
2006-03-24 19:18:17 +08:00
|
|
|
}
|
|
|
|
|
2013-01-31 11:31:37 +08:00
|
|
|
if (host->version >= SDHCI_SPEC_300 &&
|
2013-10-18 19:48:50 +08:00
|
|
|
(ios->power_mode == MMC_POWER_UP) &&
|
|
|
|
!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
|
2013-01-31 11:31:37 +08:00
|
|
|
sdhci_enable_preset_value(host, false);
|
|
|
|
|
2014-04-25 19:58:45 +08:00
|
|
|
if (!ios->clock || ios->clock != host->clock) {
|
2014-04-25 19:58:55 +08:00
|
|
|
host->ops->set_clock(host, ios->clock);
|
2014-04-25 19:58:45 +08:00
|
|
|
host->clock = ios->clock;
|
2014-08-27 15:26:32 +08:00
|
|
|
|
|
|
|
if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
|
|
|
|
host->clock) {
|
|
|
|
host->timeout_clk = host->mmc->actual_clock ?
|
|
|
|
host->mmc->actual_clock / 1000 :
|
|
|
|
host->clock / 1000;
|
|
|
|
host->mmc->max_busy_timeout =
|
|
|
|
host->ops->get_max_timeout_count ?
|
|
|
|
host->ops->get_max_timeout_count(host) :
|
|
|
|
1 << 27;
|
|
|
|
host->mmc->max_busy_timeout /= host->timeout_clk;
|
|
|
|
}
|
2014-04-25 19:58:45 +08:00
|
|
|
}
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2016-10-05 17:11:22 +08:00
|
|
|
if (host->ops->set_power)
|
|
|
|
host->ops->set_power(host, ios->power_mode, ios->vdd);
|
|
|
|
else
|
|
|
|
sdhci_set_power(host, ios->power_mode, ios->vdd);
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2010-09-23 23:24:32 +08:00
|
|
|
if (host->ops->platform_send_init_74_clocks)
|
|
|
|
host->ops->platform_send_init_74_clocks(host, ios->power_mode);
|
|
|
|
|
2014-04-25 19:57:07 +08:00
|
|
|
host->ops->set_bus_width(host, ios->bus_width);
|
2010-08-11 09:01:43 +08:00
|
|
|
|
2010-11-20 05:48:39 +08:00
|
|
|
ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
|
2007-02-18 19:07:47 +08:00
|
|
|
|
2017-08-15 10:16:47 +08:00
|
|
|
if (!(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) {
|
|
|
|
if (ios->timing == MMC_TIMING_SD_HS ||
|
|
|
|
ios->timing == MMC_TIMING_MMC_HS ||
|
|
|
|
ios->timing == MMC_TIMING_MMC_HS400 ||
|
|
|
|
ios->timing == MMC_TIMING_MMC_HS200 ||
|
|
|
|
ios->timing == MMC_TIMING_MMC_DDR52 ||
|
|
|
|
ios->timing == MMC_TIMING_UHS_SDR50 ||
|
|
|
|
ios->timing == MMC_TIMING_UHS_SDR104 ||
|
|
|
|
ios->timing == MMC_TIMING_UHS_DDR50 ||
|
|
|
|
ios->timing == MMC_TIMING_UHS_SDR25)
|
|
|
|
ctrl |= SDHCI_CTRL_HISPD;
|
|
|
|
else
|
|
|
|
ctrl &= ~SDHCI_CTRL_HISPD;
|
|
|
|
}
|
2007-02-18 19:07:47 +08:00
|
|
|
|
2011-05-05 14:48:59 +08:00
|
|
|
if (host->version >= SDHCI_SPEC_300) {
|
2011-05-05 14:49:01 +08:00
|
|
|
u16 clk, ctrl_2;
|
|
|
|
|
2014-04-25 20:00:12 +08:00
|
|
|
if (!host->preset_enabled) {
|
2011-05-05 14:49:00 +08:00
|
|
|
sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
|
2011-05-05 14:48:59 +08:00
|
|
|
/*
|
|
|
|
* We only need to set Driver Strength if the
|
|
|
|
* preset value enable is not set.
|
|
|
|
*/
|
2014-04-25 20:00:12 +08:00
|
|
|
ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
|
2011-05-05 14:48:59 +08:00
|
|
|
ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
|
|
|
|
if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
|
|
|
|
ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
|
2015-05-21 05:35:00 +08:00
|
|
|
else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
|
|
|
|
ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
|
2011-05-05 14:48:59 +08:00
|
|
|
else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
|
|
|
|
ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
|
2015-05-21 05:35:00 +08:00
|
|
|
else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
|
|
|
|
ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
|
|
|
|
else {
|
2015-11-18 17:47:02 +08:00
|
|
|
pr_warn("%s: invalid driver type, default to driver type B\n",
|
|
|
|
mmc_hostname(mmc));
|
2015-05-21 05:35:00 +08:00
|
|
|
ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
|
|
|
|
}
|
2011-05-05 14:48:59 +08:00
|
|
|
|
|
|
|
sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
|
2011-05-05 14:49:00 +08:00
|
|
|
} else {
|
|
|
|
/*
|
|
|
|
* According to SDHC Spec v3.00, if the Preset Value
|
|
|
|
* Enable in the Host Control 2 register is set, we
|
|
|
|
* need to reset SD Clock Enable before changing High
|
|
|
|
* Speed Enable to avoid generating clock gliches.
|
|
|
|
*/
|
|
|
|
|
|
|
|
/* Reset SD Clock Enable */
|
|
|
|
clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
|
|
|
|
clk &= ~SDHCI_CLOCK_CARD_EN;
|
|
|
|
sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
|
|
|
|
|
|
|
|
sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
|
|
|
|
|
|
|
|
/* Re-enable SD Clock */
|
2014-04-25 19:58:55 +08:00
|
|
|
host->ops->set_clock(host, host->clock);
|
2011-05-05 14:48:59 +08:00
|
|
|
}
|
2011-05-05 14:49:01 +08:00
|
|
|
|
|
|
|
/* Reset SD Clock Enable */
|
|
|
|
clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
|
|
|
|
clk &= ~SDHCI_CLOCK_CARD_EN;
|
|
|
|
sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
|
|
|
|
|
2014-04-25 19:59:26 +08:00
|
|
|
host->ops->set_uhs_signaling(host, ios->timing);
|
2014-04-25 19:59:31 +08:00
|
|
|
host->timing = ios->timing;
|
2011-05-05 14:49:01 +08:00
|
|
|
|
2013-01-31 11:31:37 +08:00
|
|
|
if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
|
|
|
|
((ios->timing == MMC_TIMING_UHS_SDR12) ||
|
|
|
|
(ios->timing == MMC_TIMING_UHS_SDR25) ||
|
|
|
|
(ios->timing == MMC_TIMING_UHS_SDR50) ||
|
|
|
|
(ios->timing == MMC_TIMING_UHS_SDR104) ||
|
mmc: sdhci: also get preset value and driver type for MMC_DDR52
commit bb8175a8aa42 ("mmc: sdhci: clarify DDR timing mode between
SD-UHS and eMMC") added MMC_DDR52 as eMMC's DDR mode to be
distinguished from SD-UHS, but it missed setting driver type for
MMC_DDR52 timing mode.
So sometimes we get the following error on Marvell BG2Q DMP board:
[ 1.559598] mmcblk0: error -84 transferring data, sector 0, nr 8, cmd
response 0x900, card status 0xb00
[ 1.569314] mmcblk0: retrying using single block read
[ 1.575676] mmcblk0: error -84 transferring data, sector 2, nr 6, cmd
response 0x900, card status 0x0
[ 1.585202] blk_update_request: I/O error, dev mmcblk0, sector 2
[ 1.591818] mmcblk0: error -84 transferring data, sector 3, nr 5, cmd
response 0x900, card status 0x0
[ 1.601341] blk_update_request: I/O error, dev mmcblk0, sector 3
This patches fixes this by adding the missing driver type setting.
Fixes: bb8175a8aa42 ("mmc: sdhci: clarify DDR timing mode ...")
Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-08-18 16:21:39 +08:00
|
|
|
(ios->timing == MMC_TIMING_UHS_DDR50) ||
|
|
|
|
(ios->timing == MMC_TIMING_MMC_DDR52))) {
|
2013-01-31 11:31:37 +08:00
|
|
|
u16 preset;
|
|
|
|
|
|
|
|
sdhci_enable_preset_value(host, true);
|
|
|
|
preset = sdhci_get_preset_value(host);
|
2020-03-12 19:00:50 +08:00
|
|
|
ios->drv_type = FIELD_GET(SDHCI_PRESET_DRV_MASK,
|
|
|
|
preset);
|
2013-01-31 11:31:37 +08:00
|
|
|
}
|
|
|
|
|
2011-05-05 14:49:01 +08:00
|
|
|
/* Re-enable SD Clock */
|
2014-04-25 19:58:55 +08:00
|
|
|
host->ops->set_clock(host, host->clock);
|
2011-05-05 14:49:00 +08:00
|
|
|
} else
|
|
|
|
sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
|
2011-05-05 14:48:59 +08:00
|
|
|
|
2007-07-26 05:47:04 +08:00
|
|
|
/*
|
|
|
|
* Some (ENE) controllers go apeshit on some ios operation,
|
|
|
|
* signalling timeout and CRC errors even on CMD0. Resetting
|
|
|
|
* it on each ios seems to solve the problem.
|
|
|
|
*/
|
2015-01-13 23:17:24 +08:00
|
|
|
if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
|
2014-04-25 19:57:12 +08:00
|
|
|
sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
|
2006-03-24 19:18:17 +08:00
|
|
|
}
|
2017-03-30 23:22:55 +08:00
|
|
|
EXPORT_SYMBOL_GPL(sdhci_set_ios);
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2016-04-16 01:29:25 +08:00
|
|
|
static int sdhci_get_cd(struct mmc_host *mmc)
|
2011-10-03 20:33:34 +08:00
|
|
|
{
|
|
|
|
struct sdhci_host *host = mmc_priv(mmc);
|
2016-04-16 01:29:25 +08:00
|
|
|
int gpio_cd = mmc_gpio_get_cd(mmc);
|
2013-02-28 17:35:53 +08:00
|
|
|
|
|
|
|
if (host->flags & SDHCI_DEVICE_DEAD)
|
|
|
|
return 0;
|
|
|
|
|
2015-07-06 20:16:19 +08:00
|
|
|
/* If nonremovable, assume that the card is always present. */
|
2016-06-21 09:13:26 +08:00
|
|
|
if (!mmc_card_is_removable(host->mmc))
|
2013-02-28 17:35:53 +08:00
|
|
|
return 1;
|
|
|
|
|
2015-07-06 20:16:19 +08:00
|
|
|
/*
|
|
|
|
* Try slot gpio detect, if defined it take precedence
|
|
|
|
* over build in controller functionality
|
|
|
|
*/
|
remove lots of IS_ERR_VALUE abuses
Most users of IS_ERR_VALUE() in the kernel are wrong, as they
pass an 'int' into a function that takes an 'unsigned long'
argument. This happens to work because the type is sign-extended
on 64-bit architectures before it gets converted into an
unsigned type.
However, anything that passes an 'unsigned short' or 'unsigned int'
argument into IS_ERR_VALUE() is guaranteed to be broken, as are
8-bit integers and types that are wider than 'unsigned long'.
Andrzej Hajda has already fixed a lot of the worst abusers that
were causing actual bugs, but it would be nice to prevent any
users that are not passing 'unsigned long' arguments.
This patch changes all users of IS_ERR_VALUE() that I could find
on 32-bit ARM randconfig builds and x86 allmodconfig. For the
moment, this doesn't change the definition of IS_ERR_VALUE()
because there are probably still architecture specific users
elsewhere.
Almost all the warnings I got are for files that are better off
using 'if (err)' or 'if (err < 0)'.
The only legitimate user I could find that we get a warning for
is the (32-bit only) freescale fman driver, so I did not remove
the IS_ERR_VALUE() there but changed the type to 'unsigned long'.
For 9pfs, I just worked around one user whose calling conventions
are so obscure that I did not dare change the behavior.
I was using this definition for testing:
#define IS_ERR_VALUE(x) ((unsigned long*)NULL == (typeof (x)*)NULL && \
unlikely((unsigned long long)(x) >= (unsigned long long)(typeof(x))-MAX_ERRNO))
which ends up making all 16-bit or wider types work correctly with
the most plausible interpretation of what IS_ERR_VALUE() was supposed
to return according to its users, but also causes a compile-time
warning for any users that do not pass an 'unsigned long' argument.
I suggested this approach earlier this year, but back then we ended
up deciding to just fix the users that are obviously broken. After
the initial warning that caused me to get involved in the discussion
(fs/gfs2/dir.c) showed up again in the mainline kernel, Linus
asked me to send the whole thing again.
[ Updated the 9p parts as per Al Viro - Linus ]
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Cc: Andrzej Hajda <a.hajda@samsung.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Link: https://lkml.org/lkml/2016/1/7/363
Link: https://lkml.org/lkml/2016/5/27/486
Acked-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> # For nvmem part
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2016-05-28 05:23:25 +08:00
|
|
|
if (gpio_cd >= 0)
|
2013-02-28 17:35:53 +08:00
|
|
|
return !!gpio_cd;
|
|
|
|
|
2015-07-06 20:16:19 +08:00
|
|
|
/* If polling, assume that the card is always present. */
|
|
|
|
if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
|
|
|
|
return 1;
|
|
|
|
|
2013-02-28 17:35:53 +08:00
|
|
|
/* Host native card detect */
|
|
|
|
return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
|
|
|
|
}
|
|
|
|
|
2011-10-03 20:33:34 +08:00
|
|
|
static int sdhci_check_ro(struct sdhci_host *host)
|
2006-03-24 19:18:17 +08:00
|
|
|
{
|
|
|
|
unsigned long flags;
|
2010-10-15 18:21:01 +08:00
|
|
|
int is_readonly;
|
2006-03-24 19:18:17 +08:00
|
|
|
|
|
|
|
spin_lock_irqsave(&host->lock, flags);
|
|
|
|
|
2008-04-17 01:13:13 +08:00
|
|
|
if (host->flags & SDHCI_DEVICE_DEAD)
|
2010-10-15 18:21:01 +08:00
|
|
|
is_readonly = 0;
|
|
|
|
else if (host->ops->get_ro)
|
|
|
|
is_readonly = host->ops->get_ro(host);
|
2019-02-12 22:07:35 +08:00
|
|
|
else if (mmc_can_gpio_ro(host->mmc))
|
|
|
|
is_readonly = mmc_gpio_get_ro(host->mmc);
|
2008-04-17 01:13:13 +08:00
|
|
|
else
|
2010-10-15 18:21:01 +08:00
|
|
|
is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
|
|
|
|
& SDHCI_WRITE_PROTECT);
|
2006-03-24 19:18:17 +08:00
|
|
|
|
|
|
|
spin_unlock_irqrestore(&host->lock, flags);
|
|
|
|
|
2010-10-15 18:21:01 +08:00
|
|
|
/* This quirk needs to be replaced by a callback-function later */
|
|
|
|
return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
|
|
|
|
!is_readonly : is_readonly;
|
2006-03-24 19:18:17 +08:00
|
|
|
}
|
|
|
|
|
2011-04-22 02:26:38 +08:00
|
|
|
#define SAMPLE_COUNT 5
|
|
|
|
|
2016-04-16 01:29:25 +08:00
|
|
|
static int sdhci_get_ro(struct mmc_host *mmc)
|
2011-04-22 02:26:38 +08:00
|
|
|
{
|
2016-04-16 01:29:25 +08:00
|
|
|
struct sdhci_host *host = mmc_priv(mmc);
|
2011-04-22 02:26:38 +08:00
|
|
|
int i, ro_count;
|
|
|
|
|
|
|
|
if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
|
2011-10-03 20:33:34 +08:00
|
|
|
return sdhci_check_ro(host);
|
2011-04-22 02:26:38 +08:00
|
|
|
|
|
|
|
ro_count = 0;
|
|
|
|
for (i = 0; i < SAMPLE_COUNT; i++) {
|
2011-10-03 20:33:34 +08:00
|
|
|
if (sdhci_check_ro(host)) {
|
2011-04-22 02:26:38 +08:00
|
|
|
if (++ro_count > SAMPLE_COUNT / 2)
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
msleep(30);
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-08-29 21:42:12 +08:00
|
|
|
static void sdhci_hw_reset(struct mmc_host *mmc)
|
|
|
|
{
|
|
|
|
struct sdhci_host *host = mmc_priv(mmc);
|
|
|
|
|
|
|
|
if (host->ops && host->ops->hw_reset)
|
|
|
|
host->ops->hw_reset(host);
|
|
|
|
}
|
|
|
|
|
2011-10-03 20:33:34 +08:00
|
|
|
static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
|
|
|
|
{
|
2014-04-25 19:55:56 +08:00
|
|
|
if (!(host->flags & SDHCI_DEVICE_DEAD)) {
|
2014-04-25 19:55:41 +08:00
|
|
|
if (enable)
|
2014-04-25 19:56:01 +08:00
|
|
|
host->ier |= SDHCI_INT_CARD_INT;
|
2014-04-25 19:55:41 +08:00
|
|
|
else
|
2014-04-25 19:56:01 +08:00
|
|
|
host->ier &= ~SDHCI_INT_CARD_INT;
|
|
|
|
|
|
|
|
sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
|
|
|
|
sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
|
2014-04-25 19:55:41 +08:00
|
|
|
}
|
2011-10-03 20:33:34 +08:00
|
|
|
}
|
|
|
|
|
2017-03-30 23:22:57 +08:00
|
|
|
void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
|
2011-10-03 20:33:34 +08:00
|
|
|
{
|
|
|
|
struct sdhci_host *host = mmc_priv(mmc);
|
|
|
|
unsigned long flags;
|
2007-09-04 13:59:18 +08:00
|
|
|
|
2017-03-26 19:14:45 +08:00
|
|
|
if (enable)
|
|
|
|
pm_runtime_get_noresume(host->mmc->parent);
|
|
|
|
|
2011-10-03 20:33:34 +08:00
|
|
|
spin_lock_irqsave(&host->lock, flags);
|
|
|
|
sdhci_enable_sdio_irq_nolock(host, enable);
|
2007-09-04 13:59:18 +08:00
|
|
|
spin_unlock_irqrestore(&host->lock, flags);
|
2017-03-26 19:14:45 +08:00
|
|
|
|
|
|
|
if (!enable)
|
|
|
|
pm_runtime_put_noidle(host->mmc->parent);
|
2007-09-04 13:59:18 +08:00
|
|
|
}
|
2017-03-30 23:22:57 +08:00
|
|
|
EXPORT_SYMBOL_GPL(sdhci_enable_sdio_irq);
|
2007-09-04 13:59:18 +08:00
|
|
|
|
2019-05-27 19:45:55 +08:00
|
|
|
static void sdhci_ack_sdio_irq(struct mmc_host *mmc)
|
|
|
|
{
|
|
|
|
struct sdhci_host *host = mmc_priv(mmc);
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&host->lock, flags);
|
2019-09-08 18:12:34 +08:00
|
|
|
sdhci_enable_sdio_irq_nolock(host, true);
|
2019-05-27 19:45:55 +08:00
|
|
|
spin_unlock_irqrestore(&host->lock, flags);
|
|
|
|
}
|
|
|
|
|
2017-03-30 23:22:56 +08:00
|
|
|
int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
|
|
|
|
struct mmc_ios *ios)
|
mmc: sd: add support for signal voltage switch procedure
Host Controller v3.00 adds another Capabilities register. Apart
from other things, this new register indicates whether the Host
Controller supports SDR50, SDR104, and DDR50 UHS-I modes. The spec
doesn't mention about explicit support for SDR12 and SDR25 UHS-I
modes, so the Host Controller v3.00 should support them by default.
Also if the controller supports SDR104 mode, it will also support
SDR50 mode as well. So depending on the host support, we set the
corresponding MMC_CAP_* flags. One more new register. Host Control2
is added in v3.00, which is used during Signal Voltage Switch
procedure described below.
Since as per v3.00 spec, UHS-I supported hosts should set S18R
to 1, we set S18R (bit 24) of OCR before sending ACMD41. We also
need to set XPC (bit 28) of OCR in case the host can supply >150mA.
This support is indicated by the Maximum Current Capabilities
register of the Host Controller.
If the response of ACMD41 has both CCS and S18A set, we start the
signal voltage switch procedure, which if successfull, will switch
the card from 3.3V signalling to 1.8V signalling. Signal voltage
switch procedure adds support for a new command CMD11 in the
Physical Layer Spec v3.01. As part of this procedure, we need to
set 1.8V Signalling Enable (bit 3) of Host Control2 register, which
if remains set after 5ms, means the switch to 1.8V signalling is
successfull. Otherwise, we clear bit 24 of OCR and retry the
initialization sequence. When we remove the card, and insert the
same or another card, we need to make sure that we start with 3.3V
signalling voltage. So we call mmc_set_signal_voltage() with
MMC_SIGNAL_VOLTAGE_330 set so that we are back to 3.3V signalling
voltage before we actually start initializing the card.
Tested by Zhangfei Gao with a Toshiba uhs card and general hs card,
on mmp2 in SDMA mode.
Signed-off-by: Arindam Nath <arindam.nath@amd.com>
Reviewed-by: Philip Rakity <prakity@marvell.com>
Tested-by: Philip Rakity <prakity@marvell.com>
Acked-by: Zhangfei Gao <zhangfei.gao@marvell.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
2011-05-05 14:48:57 +08:00
|
|
|
{
|
2016-04-16 01:29:25 +08:00
|
|
|
struct sdhci_host *host = mmc_priv(mmc);
|
2012-12-17 19:29:26 +08:00
|
|
|
u16 ctrl;
|
2012-07-24 06:56:23 +08:00
|
|
|
int ret;
|
mmc: sd: add support for signal voltage switch procedure
Host Controller v3.00 adds another Capabilities register. Apart
from other things, this new register indicates whether the Host
Controller supports SDR50, SDR104, and DDR50 UHS-I modes. The spec
doesn't mention about explicit support for SDR12 and SDR25 UHS-I
modes, so the Host Controller v3.00 should support them by default.
Also if the controller supports SDR104 mode, it will also support
SDR50 mode as well. So depending on the host support, we set the
corresponding MMC_CAP_* flags. One more new register. Host Control2
is added in v3.00, which is used during Signal Voltage Switch
procedure described below.
Since as per v3.00 spec, UHS-I supported hosts should set S18R
to 1, we set S18R (bit 24) of OCR before sending ACMD41. We also
need to set XPC (bit 28) of OCR in case the host can supply >150mA.
This support is indicated by the Maximum Current Capabilities
register of the Host Controller.
If the response of ACMD41 has both CCS and S18A set, we start the
signal voltage switch procedure, which if successfull, will switch
the card from 3.3V signalling to 1.8V signalling. Signal voltage
switch procedure adds support for a new command CMD11 in the
Physical Layer Spec v3.01. As part of this procedure, we need to
set 1.8V Signalling Enable (bit 3) of Host Control2 register, which
if remains set after 5ms, means the switch to 1.8V signalling is
successfull. Otherwise, we clear bit 24 of OCR and retry the
initialization sequence. When we remove the card, and insert the
same or another card, we need to make sure that we start with 3.3V
signalling voltage. So we call mmc_set_signal_voltage() with
MMC_SIGNAL_VOLTAGE_330 set so that we are back to 3.3V signalling
voltage before we actually start initializing the card.
Tested by Zhangfei Gao with a Toshiba uhs card and general hs card,
on mmp2 in SDMA mode.
Signed-off-by: Arindam Nath <arindam.nath@amd.com>
Reviewed-by: Philip Rakity <prakity@marvell.com>
Tested-by: Philip Rakity <prakity@marvell.com>
Acked-by: Zhangfei Gao <zhangfei.gao@marvell.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
2011-05-05 14:48:57 +08:00
|
|
|
|
2012-12-17 19:29:26 +08:00
|
|
|
/*
|
|
|
|
* Signal Voltage Switching is only applicable for Host Controllers
|
|
|
|
* v3.00 and above.
|
|
|
|
*/
|
|
|
|
if (host->version < SDHCI_SPEC_300)
|
|
|
|
return 0;
|
2012-07-24 06:56:23 +08:00
|
|
|
|
mmc: sd: add support for signal voltage switch procedure
Host Controller v3.00 adds another Capabilities register. Apart
from other things, this new register indicates whether the Host
Controller supports SDR50, SDR104, and DDR50 UHS-I modes. The spec
doesn't mention about explicit support for SDR12 and SDR25 UHS-I
modes, so the Host Controller v3.00 should support them by default.
Also if the controller supports SDR104 mode, it will also support
SDR50 mode as well. So depending on the host support, we set the
corresponding MMC_CAP_* flags. One more new register. Host Control2
is added in v3.00, which is used during Signal Voltage Switch
procedure described below.
Since as per v3.00 spec, UHS-I supported hosts should set S18R
to 1, we set S18R (bit 24) of OCR before sending ACMD41. We also
need to set XPC (bit 28) of OCR in case the host can supply >150mA.
This support is indicated by the Maximum Current Capabilities
register of the Host Controller.
If the response of ACMD41 has both CCS and S18A set, we start the
signal voltage switch procedure, which if successfull, will switch
the card from 3.3V signalling to 1.8V signalling. Signal voltage
switch procedure adds support for a new command CMD11 in the
Physical Layer Spec v3.01. As part of this procedure, we need to
set 1.8V Signalling Enable (bit 3) of Host Control2 register, which
if remains set after 5ms, means the switch to 1.8V signalling is
successfull. Otherwise, we clear bit 24 of OCR and retry the
initialization sequence. When we remove the card, and insert the
same or another card, we need to make sure that we start with 3.3V
signalling voltage. So we call mmc_set_signal_voltage() with
MMC_SIGNAL_VOLTAGE_330 set so that we are back to 3.3V signalling
voltage before we actually start initializing the card.
Tested by Zhangfei Gao with a Toshiba uhs card and general hs card,
on mmp2 in SDMA mode.
Signed-off-by: Arindam Nath <arindam.nath@amd.com>
Reviewed-by: Philip Rakity <prakity@marvell.com>
Tested-by: Philip Rakity <prakity@marvell.com>
Acked-by: Zhangfei Gao <zhangfei.gao@marvell.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
2011-05-05 14:48:57 +08:00
|
|
|
ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
|
|
|
|
|
2013-02-14 20:35:03 +08:00
|
|
|
switch (ios->signal_voltage) {
|
2012-12-17 19:29:26 +08:00
|
|
|
case MMC_SIGNAL_VOLTAGE_330:
|
2016-06-29 21:24:16 +08:00
|
|
|
if (!(host->flags & SDHCI_SIGNALING_330))
|
|
|
|
return -EINVAL;
|
2012-12-17 19:29:26 +08:00
|
|
|
/* Set 1.8V Signal Enable in the Host Control2 register to 0 */
|
|
|
|
ctrl &= ~SDHCI_CTRL_VDD_180;
|
|
|
|
sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
|
mmc: sd: add support for signal voltage switch procedure
Host Controller v3.00 adds another Capabilities register. Apart
from other things, this new register indicates whether the Host
Controller supports SDR50, SDR104, and DDR50 UHS-I modes. The spec
doesn't mention about explicit support for SDR12 and SDR25 UHS-I
modes, so the Host Controller v3.00 should support them by default.
Also if the controller supports SDR104 mode, it will also support
SDR50 mode as well. So depending on the host support, we set the
corresponding MMC_CAP_* flags. One more new register. Host Control2
is added in v3.00, which is used during Signal Voltage Switch
procedure described below.
Since as per v3.00 spec, UHS-I supported hosts should set S18R
to 1, we set S18R (bit 24) of OCR before sending ACMD41. We also
need to set XPC (bit 28) of OCR in case the host can supply >150mA.
This support is indicated by the Maximum Current Capabilities
register of the Host Controller.
If the response of ACMD41 has both CCS and S18A set, we start the
signal voltage switch procedure, which if successfull, will switch
the card from 3.3V signalling to 1.8V signalling. Signal voltage
switch procedure adds support for a new command CMD11 in the
Physical Layer Spec v3.01. As part of this procedure, we need to
set 1.8V Signalling Enable (bit 3) of Host Control2 register, which
if remains set after 5ms, means the switch to 1.8V signalling is
successfull. Otherwise, we clear bit 24 of OCR and retry the
initialization sequence. When we remove the card, and insert the
same or another card, we need to make sure that we start with 3.3V
signalling voltage. So we call mmc_set_signal_voltage() with
MMC_SIGNAL_VOLTAGE_330 set so that we are back to 3.3V signalling
voltage before we actually start initializing the card.
Tested by Zhangfei Gao with a Toshiba uhs card and general hs card,
on mmp2 in SDMA mode.
Signed-off-by: Arindam Nath <arindam.nath@amd.com>
Reviewed-by: Philip Rakity <prakity@marvell.com>
Tested-by: Philip Rakity <prakity@marvell.com>
Acked-by: Zhangfei Gao <zhangfei.gao@marvell.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
2011-05-05 14:48:57 +08:00
|
|
|
|
2014-06-14 01:13:56 +08:00
|
|
|
if (!IS_ERR(mmc->supply.vqmmc)) {
|
2016-07-12 15:46:10 +08:00
|
|
|
ret = mmc_regulator_set_vqmmc(mmc, ios);
|
2020-04-17 00:36:47 +08:00
|
|
|
if (ret < 0) {
|
2014-09-13 05:56:56 +08:00
|
|
|
pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
|
|
|
|
mmc_hostname(mmc));
|
2012-12-17 19:29:26 +08:00
|
|
|
return -EIO;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
/* Wait for 5ms */
|
|
|
|
usleep_range(5000, 5500);
|
mmc: sd: add support for signal voltage switch procedure
Host Controller v3.00 adds another Capabilities register. Apart
from other things, this new register indicates whether the Host
Controller supports SDR50, SDR104, and DDR50 UHS-I modes. The spec
doesn't mention about explicit support for SDR12 and SDR25 UHS-I
modes, so the Host Controller v3.00 should support them by default.
Also if the controller supports SDR104 mode, it will also support
SDR50 mode as well. So depending on the host support, we set the
corresponding MMC_CAP_* flags. One more new register. Host Control2
is added in v3.00, which is used during Signal Voltage Switch
procedure described below.
Since as per v3.00 spec, UHS-I supported hosts should set S18R
to 1, we set S18R (bit 24) of OCR before sending ACMD41. We also
need to set XPC (bit 28) of OCR in case the host can supply >150mA.
This support is indicated by the Maximum Current Capabilities
register of the Host Controller.
If the response of ACMD41 has both CCS and S18A set, we start the
signal voltage switch procedure, which if successfull, will switch
the card from 3.3V signalling to 1.8V signalling. Signal voltage
switch procedure adds support for a new command CMD11 in the
Physical Layer Spec v3.01. As part of this procedure, we need to
set 1.8V Signalling Enable (bit 3) of Host Control2 register, which
if remains set after 5ms, means the switch to 1.8V signalling is
successfull. Otherwise, we clear bit 24 of OCR and retry the
initialization sequence. When we remove the card, and insert the
same or another card, we need to make sure that we start with 3.3V
signalling voltage. So we call mmc_set_signal_voltage() with
MMC_SIGNAL_VOLTAGE_330 set so that we are back to 3.3V signalling
voltage before we actually start initializing the card.
Tested by Zhangfei Gao with a Toshiba uhs card and general hs card,
on mmp2 in SDMA mode.
Signed-off-by: Arindam Nath <arindam.nath@amd.com>
Reviewed-by: Philip Rakity <prakity@marvell.com>
Tested-by: Philip Rakity <prakity@marvell.com>
Acked-by: Zhangfei Gao <zhangfei.gao@marvell.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
2011-05-05 14:48:57 +08:00
|
|
|
|
2012-12-17 19:29:26 +08:00
|
|
|
/* 3.3V regulator output should be stable within 5 ms */
|
|
|
|
ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
|
|
|
|
if (!(ctrl & SDHCI_CTRL_VDD_180))
|
|
|
|
return 0;
|
2012-07-24 06:56:23 +08:00
|
|
|
|
2019-11-19 23:55:03 +08:00
|
|
|
pr_warn("%s: 3.3V regulator output did not become stable\n",
|
2014-09-13 05:56:56 +08:00
|
|
|
mmc_hostname(mmc));
|
2012-12-17 19:29:26 +08:00
|
|
|
|
|
|
|
return -EAGAIN;
|
|
|
|
case MMC_SIGNAL_VOLTAGE_180:
|
2016-06-29 21:24:16 +08:00
|
|
|
if (!(host->flags & SDHCI_SIGNALING_180))
|
|
|
|
return -EINVAL;
|
2014-06-14 01:13:56 +08:00
|
|
|
if (!IS_ERR(mmc->supply.vqmmc)) {
|
2016-07-12 15:46:10 +08:00
|
|
|
ret = mmc_regulator_set_vqmmc(mmc, ios);
|
2020-04-17 00:36:47 +08:00
|
|
|
if (ret < 0) {
|
2014-09-13 05:56:56 +08:00
|
|
|
pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
|
|
|
|
mmc_hostname(mmc));
|
2012-12-17 19:29:26 +08:00
|
|
|
return -EIO;
|
|
|
|
}
|
|
|
|
}
|
2012-07-24 06:56:23 +08:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Enable 1.8V Signal Enable in the Host Control2
|
|
|
|
* register
|
|
|
|
*/
|
2012-12-17 19:29:26 +08:00
|
|
|
ctrl |= SDHCI_CTRL_VDD_180;
|
|
|
|
sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
|
2012-07-24 06:56:23 +08:00
|
|
|
|
2015-01-20 16:05:15 +08:00
|
|
|
/* Some controller need to do more when switching */
|
|
|
|
if (host->ops->voltage_switch)
|
|
|
|
host->ops->voltage_switch(host);
|
|
|
|
|
2012-12-17 19:29:26 +08:00
|
|
|
/* 1.8V regulator output should be stable within 5 ms */
|
|
|
|
ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
|
|
|
|
if (ctrl & SDHCI_CTRL_VDD_180)
|
|
|
|
return 0;
|
mmc: sd: add support for signal voltage switch procedure
Host Controller v3.00 adds another Capabilities register. Apart
from other things, this new register indicates whether the Host
Controller supports SDR50, SDR104, and DDR50 UHS-I modes. The spec
doesn't mention about explicit support for SDR12 and SDR25 UHS-I
modes, so the Host Controller v3.00 should support them by default.
Also if the controller supports SDR104 mode, it will also support
SDR50 mode as well. So depending on the host support, we set the
corresponding MMC_CAP_* flags. One more new register. Host Control2
is added in v3.00, which is used during Signal Voltage Switch
procedure described below.
Since as per v3.00 spec, UHS-I supported hosts should set S18R
to 1, we set S18R (bit 24) of OCR before sending ACMD41. We also
need to set XPC (bit 28) of OCR in case the host can supply >150mA.
This support is indicated by the Maximum Current Capabilities
register of the Host Controller.
If the response of ACMD41 has both CCS and S18A set, we start the
signal voltage switch procedure, which if successfull, will switch
the card from 3.3V signalling to 1.8V signalling. Signal voltage
switch procedure adds support for a new command CMD11 in the
Physical Layer Spec v3.01. As part of this procedure, we need to
set 1.8V Signalling Enable (bit 3) of Host Control2 register, which
if remains set after 5ms, means the switch to 1.8V signalling is
successfull. Otherwise, we clear bit 24 of OCR and retry the
initialization sequence. When we remove the card, and insert the
same or another card, we need to make sure that we start with 3.3V
signalling voltage. So we call mmc_set_signal_voltage() with
MMC_SIGNAL_VOLTAGE_330 set so that we are back to 3.3V signalling
voltage before we actually start initializing the card.
Tested by Zhangfei Gao with a Toshiba uhs card and general hs card,
on mmp2 in SDMA mode.
Signed-off-by: Arindam Nath <arindam.nath@amd.com>
Reviewed-by: Philip Rakity <prakity@marvell.com>
Tested-by: Philip Rakity <prakity@marvell.com>
Acked-by: Zhangfei Gao <zhangfei.gao@marvell.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
2011-05-05 14:48:57 +08:00
|
|
|
|
2019-11-19 23:55:03 +08:00
|
|
|
pr_warn("%s: 1.8V regulator output did not become stable\n",
|
2014-09-13 05:56:56 +08:00
|
|
|
mmc_hostname(mmc));
|
mmc: sd: add support for signal voltage switch procedure
Host Controller v3.00 adds another Capabilities register. Apart
from other things, this new register indicates whether the Host
Controller supports SDR50, SDR104, and DDR50 UHS-I modes. The spec
doesn't mention about explicit support for SDR12 and SDR25 UHS-I
modes, so the Host Controller v3.00 should support them by default.
Also if the controller supports SDR104 mode, it will also support
SDR50 mode as well. So depending on the host support, we set the
corresponding MMC_CAP_* flags. One more new register. Host Control2
is added in v3.00, which is used during Signal Voltage Switch
procedure described below.
Since as per v3.00 spec, UHS-I supported hosts should set S18R
to 1, we set S18R (bit 24) of OCR before sending ACMD41. We also
need to set XPC (bit 28) of OCR in case the host can supply >150mA.
This support is indicated by the Maximum Current Capabilities
register of the Host Controller.
If the response of ACMD41 has both CCS and S18A set, we start the
signal voltage switch procedure, which if successfull, will switch
the card from 3.3V signalling to 1.8V signalling. Signal voltage
switch procedure adds support for a new command CMD11 in the
Physical Layer Spec v3.01. As part of this procedure, we need to
set 1.8V Signalling Enable (bit 3) of Host Control2 register, which
if remains set after 5ms, means the switch to 1.8V signalling is
successfull. Otherwise, we clear bit 24 of OCR and retry the
initialization sequence. When we remove the card, and insert the
same or another card, we need to make sure that we start with 3.3V
signalling voltage. So we call mmc_set_signal_voltage() with
MMC_SIGNAL_VOLTAGE_330 set so that we are back to 3.3V signalling
voltage before we actually start initializing the card.
Tested by Zhangfei Gao with a Toshiba uhs card and general hs card,
on mmp2 in SDMA mode.
Signed-off-by: Arindam Nath <arindam.nath@amd.com>
Reviewed-by: Philip Rakity <prakity@marvell.com>
Tested-by: Philip Rakity <prakity@marvell.com>
Acked-by: Zhangfei Gao <zhangfei.gao@marvell.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
2011-05-05 14:48:57 +08:00
|
|
|
|
2012-12-17 19:29:26 +08:00
|
|
|
return -EAGAIN;
|
|
|
|
case MMC_SIGNAL_VOLTAGE_120:
|
2016-06-29 21:24:16 +08:00
|
|
|
if (!(host->flags & SDHCI_SIGNALING_120))
|
|
|
|
return -EINVAL;
|
2014-06-14 01:13:56 +08:00
|
|
|
if (!IS_ERR(mmc->supply.vqmmc)) {
|
2016-07-12 15:46:10 +08:00
|
|
|
ret = mmc_regulator_set_vqmmc(mmc, ios);
|
2020-04-17 00:36:47 +08:00
|
|
|
if (ret < 0) {
|
2014-09-13 05:56:56 +08:00
|
|
|
pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
|
|
|
|
mmc_hostname(mmc));
|
2012-12-17 19:29:26 +08:00
|
|
|
return -EIO;
|
mmc: sd: add support for signal voltage switch procedure
Host Controller v3.00 adds another Capabilities register. Apart
from other things, this new register indicates whether the Host
Controller supports SDR50, SDR104, and DDR50 UHS-I modes. The spec
doesn't mention about explicit support for SDR12 and SDR25 UHS-I
modes, so the Host Controller v3.00 should support them by default.
Also if the controller supports SDR104 mode, it will also support
SDR50 mode as well. So depending on the host support, we set the
corresponding MMC_CAP_* flags. One more new register. Host Control2
is added in v3.00, which is used during Signal Voltage Switch
procedure described below.
Since as per v3.00 spec, UHS-I supported hosts should set S18R
to 1, we set S18R (bit 24) of OCR before sending ACMD41. We also
need to set XPC (bit 28) of OCR in case the host can supply >150mA.
This support is indicated by the Maximum Current Capabilities
register of the Host Controller.
If the response of ACMD41 has both CCS and S18A set, we start the
signal voltage switch procedure, which if successfull, will switch
the card from 3.3V signalling to 1.8V signalling. Signal voltage
switch procedure adds support for a new command CMD11 in the
Physical Layer Spec v3.01. As part of this procedure, we need to
set 1.8V Signalling Enable (bit 3) of Host Control2 register, which
if remains set after 5ms, means the switch to 1.8V signalling is
successfull. Otherwise, we clear bit 24 of OCR and retry the
initialization sequence. When we remove the card, and insert the
same or another card, we need to make sure that we start with 3.3V
signalling voltage. So we call mmc_set_signal_voltage() with
MMC_SIGNAL_VOLTAGE_330 set so that we are back to 3.3V signalling
voltage before we actually start initializing the card.
Tested by Zhangfei Gao with a Toshiba uhs card and general hs card,
on mmp2 in SDMA mode.
Signed-off-by: Arindam Nath <arindam.nath@amd.com>
Reviewed-by: Philip Rakity <prakity@marvell.com>
Tested-by: Philip Rakity <prakity@marvell.com>
Acked-by: Zhangfei Gao <zhangfei.gao@marvell.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
2011-05-05 14:48:57 +08:00
|
|
|
}
|
|
|
|
}
|
2012-07-24 06:56:23 +08:00
|
|
|
return 0;
|
2012-12-17 19:29:26 +08:00
|
|
|
default:
|
mmc: sd: add support for signal voltage switch procedure
Host Controller v3.00 adds another Capabilities register. Apart
from other things, this new register indicates whether the Host
Controller supports SDR50, SDR104, and DDR50 UHS-I modes. The spec
doesn't mention about explicit support for SDR12 and SDR25 UHS-I
modes, so the Host Controller v3.00 should support them by default.
Also if the controller supports SDR104 mode, it will also support
SDR50 mode as well. So depending on the host support, we set the
corresponding MMC_CAP_* flags. One more new register. Host Control2
is added in v3.00, which is used during Signal Voltage Switch
procedure described below.
Since as per v3.00 spec, UHS-I supported hosts should set S18R
to 1, we set S18R (bit 24) of OCR before sending ACMD41. We also
need to set XPC (bit 28) of OCR in case the host can supply >150mA.
This support is indicated by the Maximum Current Capabilities
register of the Host Controller.
If the response of ACMD41 has both CCS and S18A set, we start the
signal voltage switch procedure, which if successfull, will switch
the card from 3.3V signalling to 1.8V signalling. Signal voltage
switch procedure adds support for a new command CMD11 in the
Physical Layer Spec v3.01. As part of this procedure, we need to
set 1.8V Signalling Enable (bit 3) of Host Control2 register, which
if remains set after 5ms, means the switch to 1.8V signalling is
successfull. Otherwise, we clear bit 24 of OCR and retry the
initialization sequence. When we remove the card, and insert the
same or another card, we need to make sure that we start with 3.3V
signalling voltage. So we call mmc_set_signal_voltage() with
MMC_SIGNAL_VOLTAGE_330 set so that we are back to 3.3V signalling
voltage before we actually start initializing the card.
Tested by Zhangfei Gao with a Toshiba uhs card and general hs card,
on mmp2 in SDMA mode.
Signed-off-by: Arindam Nath <arindam.nath@amd.com>
Reviewed-by: Philip Rakity <prakity@marvell.com>
Tested-by: Philip Rakity <prakity@marvell.com>
Acked-by: Zhangfei Gao <zhangfei.gao@marvell.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
2011-05-05 14:48:57 +08:00
|
|
|
/* No signal voltage switch required */
|
|
|
|
return 0;
|
2012-12-17 19:29:26 +08:00
|
|
|
}
|
mmc: sd: add support for signal voltage switch procedure
Host Controller v3.00 adds another Capabilities register. Apart
from other things, this new register indicates whether the Host
Controller supports SDR50, SDR104, and DDR50 UHS-I modes. The spec
doesn't mention about explicit support for SDR12 and SDR25 UHS-I
modes, so the Host Controller v3.00 should support them by default.
Also if the controller supports SDR104 mode, it will also support
SDR50 mode as well. So depending on the host support, we set the
corresponding MMC_CAP_* flags. One more new register. Host Control2
is added in v3.00, which is used during Signal Voltage Switch
procedure described below.
Since as per v3.00 spec, UHS-I supported hosts should set S18R
to 1, we set S18R (bit 24) of OCR before sending ACMD41. We also
need to set XPC (bit 28) of OCR in case the host can supply >150mA.
This support is indicated by the Maximum Current Capabilities
register of the Host Controller.
If the response of ACMD41 has both CCS and S18A set, we start the
signal voltage switch procedure, which if successfull, will switch
the card from 3.3V signalling to 1.8V signalling. Signal voltage
switch procedure adds support for a new command CMD11 in the
Physical Layer Spec v3.01. As part of this procedure, we need to
set 1.8V Signalling Enable (bit 3) of Host Control2 register, which
if remains set after 5ms, means the switch to 1.8V signalling is
successfull. Otherwise, we clear bit 24 of OCR and retry the
initialization sequence. When we remove the card, and insert the
same or another card, we need to make sure that we start with 3.3V
signalling voltage. So we call mmc_set_signal_voltage() with
MMC_SIGNAL_VOLTAGE_330 set so that we are back to 3.3V signalling
voltage before we actually start initializing the card.
Tested by Zhangfei Gao with a Toshiba uhs card and general hs card,
on mmp2 in SDMA mode.
Signed-off-by: Arindam Nath <arindam.nath@amd.com>
Reviewed-by: Philip Rakity <prakity@marvell.com>
Tested-by: Philip Rakity <prakity@marvell.com>
Acked-by: Zhangfei Gao <zhangfei.gao@marvell.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
2011-05-05 14:48:57 +08:00
|
|
|
}
|
2017-03-30 23:22:56 +08:00
|
|
|
EXPORT_SYMBOL_GPL(sdhci_start_signal_voltage_switch);
|
mmc: sd: add support for signal voltage switch procedure
Host Controller v3.00 adds another Capabilities register. Apart
from other things, this new register indicates whether the Host
Controller supports SDR50, SDR104, and DDR50 UHS-I modes. The spec
doesn't mention about explicit support for SDR12 and SDR25 UHS-I
modes, so the Host Controller v3.00 should support them by default.
Also if the controller supports SDR104 mode, it will also support
SDR50 mode as well. So depending on the host support, we set the
corresponding MMC_CAP_* flags. One more new register. Host Control2
is added in v3.00, which is used during Signal Voltage Switch
procedure described below.
Since as per v3.00 spec, UHS-I supported hosts should set S18R
to 1, we set S18R (bit 24) of OCR before sending ACMD41. We also
need to set XPC (bit 28) of OCR in case the host can supply >150mA.
This support is indicated by the Maximum Current Capabilities
register of the Host Controller.
If the response of ACMD41 has both CCS and S18A set, we start the
signal voltage switch procedure, which if successfull, will switch
the card from 3.3V signalling to 1.8V signalling. Signal voltage
switch procedure adds support for a new command CMD11 in the
Physical Layer Spec v3.01. As part of this procedure, we need to
set 1.8V Signalling Enable (bit 3) of Host Control2 register, which
if remains set after 5ms, means the switch to 1.8V signalling is
successfull. Otherwise, we clear bit 24 of OCR and retry the
initialization sequence. When we remove the card, and insert the
same or another card, we need to make sure that we start with 3.3V
signalling voltage. So we call mmc_set_signal_voltage() with
MMC_SIGNAL_VOLTAGE_330 set so that we are back to 3.3V signalling
voltage before we actually start initializing the card.
Tested by Zhangfei Gao with a Toshiba uhs card and general hs card,
on mmp2 in SDMA mode.
Signed-off-by: Arindam Nath <arindam.nath@amd.com>
Reviewed-by: Philip Rakity <prakity@marvell.com>
Tested-by: Philip Rakity <prakity@marvell.com>
Acked-by: Zhangfei Gao <zhangfei.gao@marvell.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
2011-05-05 14:48:57 +08:00
|
|
|
|
2012-12-17 19:29:26 +08:00
|
|
|
static int sdhci_card_busy(struct mmc_host *mmc)
|
|
|
|
{
|
|
|
|
struct sdhci_host *host = mmc_priv(mmc);
|
|
|
|
u32 present_state;
|
|
|
|
|
2016-06-23 19:00:58 +08:00
|
|
|
/* Check whether DAT[0] is 0 */
|
2012-12-17 19:29:26 +08:00
|
|
|
present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
|
|
|
|
|
2016-06-23 19:00:58 +08:00
|
|
|
return !(present_state & SDHCI_DATA_0_LVL_MASK);
|
2012-12-17 19:29:26 +08:00
|
|
|
}
|
|
|
|
|
2014-12-06 01:25:31 +08:00
|
|
|
static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
|
|
|
|
{
|
|
|
|
struct sdhci_host *host = mmc_priv(mmc);
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&host->lock, flags);
|
|
|
|
host->flags |= SDHCI_HS400_TUNING;
|
|
|
|
spin_unlock_irqrestore(&host->lock, flags);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2018-07-16 14:26:53 +08:00
|
|
|
void sdhci_start_tuning(struct sdhci_host *host)
|
2016-12-02 21:59:23 +08:00
|
|
|
{
|
|
|
|
u16 ctrl;
|
|
|
|
|
|
|
|
ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
|
|
|
|
ctrl |= SDHCI_CTRL_EXEC_TUNING;
|
|
|
|
if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
|
|
|
|
ctrl |= SDHCI_CTRL_TUNED_CLK;
|
|
|
|
sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* As per the Host Controller spec v3.00, tuning command
|
|
|
|
* generates Buffer Read Ready interrupt, so enable that.
|
|
|
|
*
|
|
|
|
* Note: The spec clearly says that when tuning sequence
|
|
|
|
* is being performed, the controller does not generate
|
|
|
|
* interrupts other than Buffer Read Ready interrupt. But
|
|
|
|
* to make sure we don't hit a controller bug, we _only_
|
|
|
|
* enable Buffer Read Ready interrupt here.
|
|
|
|
*/
|
|
|
|
sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
|
|
|
|
sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
|
|
|
|
}
|
2018-07-16 14:26:53 +08:00
|
|
|
EXPORT_SYMBOL_GPL(sdhci_start_tuning);
|
2016-12-02 21:59:23 +08:00
|
|
|
|
2018-07-16 14:26:53 +08:00
|
|
|
void sdhci_end_tuning(struct sdhci_host *host)
|
2016-12-02 21:59:23 +08:00
|
|
|
{
|
|
|
|
sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
|
|
|
|
sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
|
|
|
|
}
|
2018-07-16 14:26:53 +08:00
|
|
|
EXPORT_SYMBOL_GPL(sdhci_end_tuning);
|
2016-12-02 21:59:23 +08:00
|
|
|
|
2018-07-16 14:26:53 +08:00
|
|
|
void sdhci_reset_tuning(struct sdhci_host *host)
|
2016-12-02 21:59:23 +08:00
|
|
|
{
|
|
|
|
u16 ctrl;
|
|
|
|
|
|
|
|
ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
|
|
|
|
ctrl &= ~SDHCI_CTRL_TUNED_CLK;
|
|
|
|
ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
|
|
|
|
sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
|
|
|
|
}
|
2018-07-16 14:26:53 +08:00
|
|
|
EXPORT_SYMBOL_GPL(sdhci_reset_tuning);
|
2016-12-02 21:59:23 +08:00
|
|
|
|
2019-08-27 08:33:22 +08:00
|
|
|
void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode)
|
2016-12-02 21:59:23 +08:00
|
|
|
{
|
|
|
|
sdhci_reset_tuning(host);
|
|
|
|
|
|
|
|
sdhci_do_reset(host, SDHCI_RESET_CMD);
|
|
|
|
sdhci_do_reset(host, SDHCI_RESET_DATA);
|
|
|
|
|
|
|
|
sdhci_end_tuning(host);
|
|
|
|
|
|
|
|
mmc_abort_tuning(host->mmc, opcode);
|
|
|
|
}
|
2019-08-27 08:33:22 +08:00
|
|
|
EXPORT_SYMBOL_GPL(sdhci_abort_tuning);
|
2016-12-02 21:59:23 +08:00
|
|
|
|
|
|
|
/*
|
|
|
|
* We use sdhci_send_tuning() because mmc_send_tuning() is not a good fit. SDHCI
|
|
|
|
* tuning command does not have a data payload (or rather the hardware does it
|
|
|
|
* automatically) so mmc_send_tuning() will return -EIO. Also the tuning command
|
|
|
|
* interrupt setup is different to other commands and there is no timeout
|
|
|
|
* interrupt so special handling is needed.
|
|
|
|
*/
|
2018-07-16 14:26:53 +08:00
|
|
|
void sdhci_send_tuning(struct sdhci_host *host, u32 opcode)
|
2016-12-02 21:59:23 +08:00
|
|
|
{
|
|
|
|
struct mmc_host *mmc = host->mmc;
|
2016-12-19 19:51:18 +08:00
|
|
|
struct mmc_command cmd = {};
|
|
|
|
struct mmc_request mrq = {};
|
2017-03-21 01:50:38 +08:00
|
|
|
unsigned long flags;
|
2017-08-03 20:46:13 +08:00
|
|
|
u32 b = host->sdma_boundary;
|
2017-03-21 01:50:38 +08:00
|
|
|
|
|
|
|
spin_lock_irqsave(&host->lock, flags);
|
2016-12-02 21:59:23 +08:00
|
|
|
|
|
|
|
cmd.opcode = opcode;
|
|
|
|
cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
|
|
|
|
cmd.mrq = &mrq;
|
|
|
|
|
|
|
|
mrq.cmd = &cmd;
|
|
|
|
/*
|
|
|
|
* In response to CMD19, the card sends 64 bytes of tuning
|
|
|
|
* block to the Host Controller. So we set the block size
|
|
|
|
* to 64 here.
|
|
|
|
*/
|
2016-12-02 21:14:26 +08:00
|
|
|
if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200 &&
|
|
|
|
mmc->ios.bus_width == MMC_BUS_WIDTH_8)
|
2017-08-03 20:46:13 +08:00
|
|
|
sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 128), SDHCI_BLOCK_SIZE);
|
2016-12-02 21:14:26 +08:00
|
|
|
else
|
2017-08-03 20:46:13 +08:00
|
|
|
sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 64), SDHCI_BLOCK_SIZE);
|
2016-12-02 21:59:23 +08:00
|
|
|
|
|
|
|
/*
|
|
|
|
* The tuning block is sent by the card to the host controller.
|
|
|
|
* So we set the TRNS_READ bit in the Transfer Mode register.
|
|
|
|
* This also takes care of setting DMA Enable and Multi Block
|
|
|
|
* Select in the same register to 0.
|
|
|
|
*/
|
|
|
|
sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
|
|
|
|
|
2020-04-12 17:03:49 +08:00
|
|
|
if (!sdhci_send_command_retry(host, &cmd, flags)) {
|
|
|
|
spin_unlock_irqrestore(&host->lock, flags);
|
|
|
|
host->tuning_done = 0;
|
|
|
|
return;
|
|
|
|
}
|
2016-12-02 21:59:23 +08:00
|
|
|
|
|
|
|
host->cmd = NULL;
|
|
|
|
|
|
|
|
sdhci_del_timer(host, &mrq);
|
|
|
|
|
|
|
|
host->tuning_done = 0;
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&host->lock, flags);
|
|
|
|
|
|
|
|
/* Wait for Buffer Read Ready interrupt */
|
|
|
|
wait_event_timeout(host->buf_ready_int, (host->tuning_done == 1),
|
|
|
|
msecs_to_jiffies(50));
|
|
|
|
|
|
|
|
}
|
2018-07-16 14:26:53 +08:00
|
|
|
EXPORT_SYMBOL_GPL(sdhci_send_tuning);
|
2016-12-02 21:59:23 +08:00
|
|
|
|
2018-08-23 16:48:31 +08:00
|
|
|
static int __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
|
2016-12-02 21:14:27 +08:00
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Issue opcode repeatedly till Execute Tuning is set to 0 or the number
|
2019-03-24 12:45:19 +08:00
|
|
|
* of loops reaches tuning loop count.
|
2016-12-02 21:14:27 +08:00
|
|
|
*/
|
2019-03-24 12:45:19 +08:00
|
|
|
for (i = 0; i < host->tuning_loop_count; i++) {
|
2016-12-02 21:14:27 +08:00
|
|
|
u16 ctrl;
|
|
|
|
|
2017-03-21 01:50:38 +08:00
|
|
|
sdhci_send_tuning(host, opcode);
|
2016-12-02 21:14:27 +08:00
|
|
|
|
|
|
|
if (!host->tuning_done) {
|
2019-12-06 19:43:26 +08:00
|
|
|
pr_debug("%s: Tuning timeout, falling back to fixed sampling clock\n",
|
|
|
|
mmc_hostname(host->mmc));
|
2017-03-21 01:50:38 +08:00
|
|
|
sdhci_abort_tuning(host, opcode);
|
2018-08-23 16:48:31 +08:00
|
|
|
return -ETIMEDOUT;
|
2016-12-02 21:14:27 +08:00
|
|
|
}
|
|
|
|
|
2018-12-28 16:35:49 +08:00
|
|
|
/* Spec does not require a delay between tuning cycles */
|
|
|
|
if (host->tuning_delay > 0)
|
|
|
|
mdelay(host->tuning_delay);
|
|
|
|
|
2016-12-02 21:14:27 +08:00
|
|
|
ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
|
|
|
|
if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
|
|
|
|
if (ctrl & SDHCI_CTRL_TUNED_CLK)
|
2018-08-23 16:48:31 +08:00
|
|
|
return 0; /* Success! */
|
2016-12-02 21:14:27 +08:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
|
|
|
|
mmc_hostname(host->mmc));
|
|
|
|
sdhci_reset_tuning(host);
|
2018-08-23 16:48:31 +08:00
|
|
|
return -EAGAIN;
|
2016-12-02 21:14:27 +08:00
|
|
|
}
|
|
|
|
|
2016-12-08 20:50:54 +08:00
|
|
|
int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
|
2011-05-05 14:49:04 +08:00
|
|
|
{
|
2014-04-25 19:59:36 +08:00
|
|
|
struct sdhci_host *host = mmc_priv(mmc);
|
2011-05-05 14:49:04 +08:00
|
|
|
int err = 0;
|
2014-12-06 01:25:30 +08:00
|
|
|
unsigned int tuning_count = 0;
|
2014-12-06 01:25:31 +08:00
|
|
|
bool hs400_tuning;
|
2011-05-05 14:49:04 +08:00
|
|
|
|
2014-12-06 01:25:31 +08:00
|
|
|
hs400_tuning = host->flags & SDHCI_HS400_TUNING;
|
|
|
|
|
2014-12-06 01:25:30 +08:00
|
|
|
if (host->tuning_mode == SDHCI_TUNING_MODE_1)
|
|
|
|
tuning_count = host->tuning_count;
|
|
|
|
|
2011-05-05 14:49:04 +08:00
|
|
|
/*
|
2015-10-04 20:04:12 +08:00
|
|
|
* The Host Controller needs tuning in case of SDR104 and DDR50
|
|
|
|
* mode, and for SDR50 mode when Use Tuning for SDR50 is set in
|
|
|
|
* the Capabilities register.
|
2012-01-06 12:26:39 +08:00
|
|
|
* If the Host Controller supports the HS200 mode then the
|
|
|
|
* tuning function has to be executed.
|
2011-05-05 14:49:04 +08:00
|
|
|
*/
|
2014-04-25 19:59:36 +08:00
|
|
|
switch (host->timing) {
|
2014-12-06 01:25:31 +08:00
|
|
|
/* HS400 tuning is done in HS200 mode */
|
2014-11-06 21:19:06 +08:00
|
|
|
case MMC_TIMING_MMC_HS400:
|
2014-12-06 01:25:31 +08:00
|
|
|
err = -EINVAL;
|
2017-03-21 01:50:38 +08:00
|
|
|
goto out;
|
2014-12-06 01:25:31 +08:00
|
|
|
|
2014-04-25 19:59:36 +08:00
|
|
|
case MMC_TIMING_MMC_HS200:
|
2014-12-06 01:25:31 +08:00
|
|
|
/*
|
|
|
|
* Periodic re-tuning for HS400 is not expected to be needed, so
|
|
|
|
* disable it here.
|
|
|
|
*/
|
|
|
|
if (hs400_tuning)
|
|
|
|
tuning_count = 0;
|
|
|
|
break;
|
|
|
|
|
2014-04-25 19:59:36 +08:00
|
|
|
case MMC_TIMING_UHS_SDR104:
|
2015-10-04 20:04:12 +08:00
|
|
|
case MMC_TIMING_UHS_DDR50:
|
2014-04-25 19:59:36 +08:00
|
|
|
break;
|
|
|
|
|
|
|
|
case MMC_TIMING_UHS_SDR50:
|
2016-04-20 14:24:03 +08:00
|
|
|
if (host->flags & SDHCI_SDR50_NEEDS_TUNING)
|
2014-04-25 19:59:36 +08:00
|
|
|
break;
|
|
|
|
/* FALLTHROUGH */
|
|
|
|
|
|
|
|
default:
|
2017-03-21 01:50:38 +08:00
|
|
|
goto out;
|
2011-05-05 14:49:04 +08:00
|
|
|
}
|
|
|
|
|
2013-09-13 19:11:30 +08:00
|
|
|
if (host->ops->platform_execute_tuning) {
|
2017-01-10 15:00:50 +08:00
|
|
|
err = host->ops->platform_execute_tuning(host, opcode);
|
2017-03-21 01:50:38 +08:00
|
|
|
goto out;
|
2013-09-13 19:11:30 +08:00
|
|
|
}
|
|
|
|
|
2016-12-02 21:14:27 +08:00
|
|
|
host->mmc->retune_period = tuning_count;
|
2011-05-05 14:49:04 +08:00
|
|
|
|
2017-04-20 16:14:43 +08:00
|
|
|
if (host->tuning_delay < 0)
|
|
|
|
host->tuning_delay = opcode == MMC_SEND_TUNING_BLOCK;
|
|
|
|
|
2016-12-02 21:14:27 +08:00
|
|
|
sdhci_start_tuning(host);
|
2016-12-02 21:59:23 +08:00
|
|
|
|
2018-08-23 16:48:31 +08:00
|
|
|
host->tuning_err = __sdhci_execute_tuning(host, opcode);
|
2011-05-05 14:49:07 +08:00
|
|
|
|
2016-12-02 21:59:23 +08:00
|
|
|
sdhci_end_tuning(host);
|
2017-03-21 01:50:38 +08:00
|
|
|
out:
|
2017-01-10 15:00:50 +08:00
|
|
|
host->flags &= ~SDHCI_HS400_TUNING;
|
2016-12-02 21:14:27 +08:00
|
|
|
|
2011-05-05 14:49:04 +08:00
|
|
|
return err;
|
|
|
|
}
|
2016-12-08 20:50:54 +08:00
|
|
|
EXPORT_SYMBOL_GPL(sdhci_execute_tuning);
|
2011-05-05 14:49:04 +08:00
|
|
|
|
2013-01-31 11:31:37 +08:00
|
|
|
static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
|
2011-05-05 14:49:05 +08:00
|
|
|
{
|
|
|
|
/* Host Controller v3.00 defines preset value registers */
|
|
|
|
if (host->version < SDHCI_SPEC_300)
|
|
|
|
return;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* We only enable or disable Preset Value if they are not already
|
|
|
|
* enabled or disabled respectively. Otherwise, we bail out.
|
|
|
|
*/
|
2014-04-25 20:00:12 +08:00
|
|
|
if (host->preset_enabled != enable) {
|
|
|
|
u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
|
|
|
|
|
|
|
|
if (enable)
|
|
|
|
ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
|
|
|
|
else
|
|
|
|
ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
|
|
|
|
|
2011-05-05 14:49:05 +08:00
|
|
|
sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
|
2014-04-25 20:00:12 +08:00
|
|
|
|
|
|
|
if (enable)
|
|
|
|
host->flags |= SDHCI_PV_ENABLED;
|
|
|
|
else
|
|
|
|
host->flags &= ~SDHCI_PV_ENABLED;
|
|
|
|
|
|
|
|
host->preset_enabled = enable;
|
2011-05-05 14:49:05 +08:00
|
|
|
}
|
2011-10-03 20:33:34 +08:00
|
|
|
}
|
|
|
|
|
mmc: sdhci: use pipeline mmc requests to improve performance
This patch is based on the patches by Per Forlin, Tony Lin and Ryan QIAN.
This patch complete the API 'post_req' and 'pre_req' in sdhci host side,
Test Env:
1. i.MX6Q-SABREAUTO board, CPU @ 996MHz, use ADMA in uSDHC controller.
2. Test command:
$ echo 1 > /proc/sys/vm/drop_caches
write to sd card:
$ dd if=/dev/zero of=/dev/mmcblk0 bs=1M count=2000 conv=fsync
read the sd card:
$ dd if=/dev/mmcblk0 of=/dev/null bs=1M count=2000
3. TOSHIBA 16GB SD3.0 card, running at 4 bit, SDR104 @ 198MHZ
Performance with and without this patch:
-------------------------------------------------
| | read speed | write speed |
|------------------------------------------------
| with this patch | ~76.7 MB/s | ~23.3 MB/s |
|------------------------------------------------
|without this patch | ~60.5 MB/s | ~22.5 MB/s |
-------------------------------------------------
4. SanDisk 8GB SD3.0 card, running at 4 bit, DDR50 @ 50MHZ
Performance with and without this patch:
-------------------------------------------------
| | read speed | write speed |
|------------------------------------------------
| with this patch | ~40.5 MB/s | ~15.6 MB/s |
|------------------------------------------------
|without this patch | ~36.1 MB/s | ~14.1 MB/s |
-------------------------------------------------
5. Kingston 8GB SD2.0 card, running at 4 bit, High-speed @ 50MHZ
Performance with and without this patch:
-------------------------------------------------
| | read speed | write speed |
|------------------------------------------------
| with this patch | ~22.7 MB/s | ~8.2 MB/s |
|------------------------------------------------
|without this patch | ~21.3 MB/s | ~8.0 MB/s |
-------------------------------------------------
6. About eMMC, Sandisk 8GB eMMC on i.MX6DL-sabresd board, CPU @ 792MHZ,
eMMC running at 8 bit, DDR52 @ 52MHZ.
Performance with and without this patch:
-------------------------------------------------
| | read speed | write speed |
|------------------------------------------------
| with this patch | ~37.3 MB/s | ~10.5 MB/s |
|------------------------------------------------
|without this patch | ~33.4 MB/s | ~10.5 MB/s |
-------------------------------------------------
Signed-off-by: Haibo Chen <haibo.chen@freescale.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2014-12-09 17:04:05 +08:00
|
|
|
static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
|
|
|
|
int err)
|
|
|
|
{
|
|
|
|
struct sdhci_host *host = mmc_priv(mmc);
|
|
|
|
struct mmc_data *data = mrq->data;
|
|
|
|
|
2016-01-26 21:40:32 +08:00
|
|
|
if (data->host_cookie != COOKIE_UNMAPPED)
|
2016-01-26 21:40:53 +08:00
|
|
|
dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
|
2017-03-27 02:45:56 +08:00
|
|
|
mmc_get_dma_dir(data));
|
2016-01-26 21:40:53 +08:00
|
|
|
|
|
|
|
data->host_cookie = COOKIE_UNMAPPED;
|
mmc: sdhci: use pipeline mmc requests to improve performance
This patch is based on the patches by Per Forlin, Tony Lin and Ryan QIAN.
This patch complete the API 'post_req' and 'pre_req' in sdhci host side,
Test Env:
1. i.MX6Q-SABREAUTO board, CPU @ 996MHz, use ADMA in uSDHC controller.
2. Test command:
$ echo 1 > /proc/sys/vm/drop_caches
write to sd card:
$ dd if=/dev/zero of=/dev/mmcblk0 bs=1M count=2000 conv=fsync
read the sd card:
$ dd if=/dev/mmcblk0 of=/dev/null bs=1M count=2000
3. TOSHIBA 16GB SD3.0 card, running at 4 bit, SDR104 @ 198MHZ
Performance with and without this patch:
-------------------------------------------------
| | read speed | write speed |
|------------------------------------------------
| with this patch | ~76.7 MB/s | ~23.3 MB/s |
|------------------------------------------------
|without this patch | ~60.5 MB/s | ~22.5 MB/s |
-------------------------------------------------
4. SanDisk 8GB SD3.0 card, running at 4 bit, DDR50 @ 50MHZ
Performance with and without this patch:
-------------------------------------------------
| | read speed | write speed |
|------------------------------------------------
| with this patch | ~40.5 MB/s | ~15.6 MB/s |
|------------------------------------------------
|without this patch | ~36.1 MB/s | ~14.1 MB/s |
-------------------------------------------------
5. Kingston 8GB SD2.0 card, running at 4 bit, High-speed @ 50MHZ
Performance with and without this patch:
-------------------------------------------------
| | read speed | write speed |
|------------------------------------------------
| with this patch | ~22.7 MB/s | ~8.2 MB/s |
|------------------------------------------------
|without this patch | ~21.3 MB/s | ~8.0 MB/s |
-------------------------------------------------
6. About eMMC, Sandisk 8GB eMMC on i.MX6DL-sabresd board, CPU @ 792MHZ,
eMMC running at 8 bit, DDR52 @ 52MHZ.
Performance with and without this patch:
-------------------------------------------------
| | read speed | write speed |
|------------------------------------------------
| with this patch | ~37.3 MB/s | ~10.5 MB/s |
|------------------------------------------------
|without this patch | ~33.4 MB/s | ~10.5 MB/s |
-------------------------------------------------
Signed-off-by: Haibo Chen <haibo.chen@freescale.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2014-12-09 17:04:05 +08:00
|
|
|
}
|
|
|
|
|
2016-11-23 18:02:24 +08:00
|
|
|
static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
|
mmc: sdhci: use pipeline mmc requests to improve performance
This patch is based on the patches by Per Forlin, Tony Lin and Ryan QIAN.
This patch complete the API 'post_req' and 'pre_req' in sdhci host side,
Test Env:
1. i.MX6Q-SABREAUTO board, CPU @ 996MHz, use ADMA in uSDHC controller.
2. Test command:
$ echo 1 > /proc/sys/vm/drop_caches
write to sd card:
$ dd if=/dev/zero of=/dev/mmcblk0 bs=1M count=2000 conv=fsync
read the sd card:
$ dd if=/dev/mmcblk0 of=/dev/null bs=1M count=2000
3. TOSHIBA 16GB SD3.0 card, running at 4 bit, SDR104 @ 198MHZ
Performance with and without this patch:
-------------------------------------------------
| | read speed | write speed |
|------------------------------------------------
| with this patch | ~76.7 MB/s | ~23.3 MB/s |
|------------------------------------------------
|without this patch | ~60.5 MB/s | ~22.5 MB/s |
-------------------------------------------------
4. SanDisk 8GB SD3.0 card, running at 4 bit, DDR50 @ 50MHZ
Performance with and without this patch:
-------------------------------------------------
| | read speed | write speed |
|------------------------------------------------
| with this patch | ~40.5 MB/s | ~15.6 MB/s |
|------------------------------------------------
|without this patch | ~36.1 MB/s | ~14.1 MB/s |
-------------------------------------------------
5. Kingston 8GB SD2.0 card, running at 4 bit, High-speed @ 50MHZ
Performance with and without this patch:
-------------------------------------------------
| | read speed | write speed |
|------------------------------------------------
| with this patch | ~22.7 MB/s | ~8.2 MB/s |
|------------------------------------------------
|without this patch | ~21.3 MB/s | ~8.0 MB/s |
-------------------------------------------------
6. About eMMC, Sandisk 8GB eMMC on i.MX6DL-sabresd board, CPU @ 792MHZ,
eMMC running at 8 bit, DDR52 @ 52MHZ.
Performance with and without this patch:
-------------------------------------------------
| | read speed | write speed |
|------------------------------------------------
| with this patch | ~37.3 MB/s | ~10.5 MB/s |
|------------------------------------------------
|without this patch | ~33.4 MB/s | ~10.5 MB/s |
-------------------------------------------------
Signed-off-by: Haibo Chen <haibo.chen@freescale.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2014-12-09 17:04:05 +08:00
|
|
|
{
|
|
|
|
struct sdhci_host *host = mmc_priv(mmc);
|
|
|
|
|
2015-08-25 10:02:11 +08:00
|
|
|
mrq->data->host_cookie = COOKIE_UNMAPPED;
|
mmc: sdhci: use pipeline mmc requests to improve performance
This patch is based on the patches by Per Forlin, Tony Lin and Ryan QIAN.
This patch complete the API 'post_req' and 'pre_req' in sdhci host side,
Test Env:
1. i.MX6Q-SABREAUTO board, CPU @ 996MHz, use ADMA in uSDHC controller.
2. Test command:
$ echo 1 > /proc/sys/vm/drop_caches
write to sd card:
$ dd if=/dev/zero of=/dev/mmcblk0 bs=1M count=2000 conv=fsync
read the sd card:
$ dd if=/dev/mmcblk0 of=/dev/null bs=1M count=2000
3. TOSHIBA 16GB SD3.0 card, running at 4 bit, SDR104 @ 198MHZ
Performance with and without this patch:
-------------------------------------------------
| | read speed | write speed |
|------------------------------------------------
| with this patch | ~76.7 MB/s | ~23.3 MB/s |
|------------------------------------------------
|without this patch | ~60.5 MB/s | ~22.5 MB/s |
-------------------------------------------------
4. SanDisk 8GB SD3.0 card, running at 4 bit, DDR50 @ 50MHZ
Performance with and without this patch:
-------------------------------------------------
| | read speed | write speed |
|------------------------------------------------
| with this patch | ~40.5 MB/s | ~15.6 MB/s |
|------------------------------------------------
|without this patch | ~36.1 MB/s | ~14.1 MB/s |
-------------------------------------------------
5. Kingston 8GB SD2.0 card, running at 4 bit, High-speed @ 50MHZ
Performance with and without this patch:
-------------------------------------------------
| | read speed | write speed |
|------------------------------------------------
| with this patch | ~22.7 MB/s | ~8.2 MB/s |
|------------------------------------------------
|without this patch | ~21.3 MB/s | ~8.0 MB/s |
-------------------------------------------------
6. About eMMC, Sandisk 8GB eMMC on i.MX6DL-sabresd board, CPU @ 792MHZ,
eMMC running at 8 bit, DDR52 @ 52MHZ.
Performance with and without this patch:
-------------------------------------------------
| | read speed | write speed |
|------------------------------------------------
| with this patch | ~37.3 MB/s | ~10.5 MB/s |
|------------------------------------------------
|without this patch | ~33.4 MB/s | ~10.5 MB/s |
-------------------------------------------------
Signed-off-by: Haibo Chen <haibo.chen@freescale.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2014-12-09 17:04:05 +08:00
|
|
|
|
2018-01-29 07:44:53 +08:00
|
|
|
/*
|
|
|
|
* No pre-mapping in the pre hook if we're using the bounce buffer,
|
|
|
|
* for that we would need two bounce buffers since one buffer is
|
|
|
|
* in flight when this is getting called.
|
|
|
|
*/
|
|
|
|
if (host->flags & SDHCI_REQ_USE_DMA && !host->bounce_buffer)
|
2016-01-26 21:40:37 +08:00
|
|
|
sdhci_pre_dma_transfer(host, mrq->data, COOKIE_PRE_MAPPED);
|
mmc: sdhci: use pipeline mmc requests to improve performance
This patch is based on the patches by Per Forlin, Tony Lin and Ryan QIAN.
This patch complete the API 'post_req' and 'pre_req' in sdhci host side,
Test Env:
1. i.MX6Q-SABREAUTO board, CPU @ 996MHz, use ADMA in uSDHC controller.
2. Test command:
$ echo 1 > /proc/sys/vm/drop_caches
write to sd card:
$ dd if=/dev/zero of=/dev/mmcblk0 bs=1M count=2000 conv=fsync
read the sd card:
$ dd if=/dev/mmcblk0 of=/dev/null bs=1M count=2000
3. TOSHIBA 16GB SD3.0 card, running at 4 bit, SDR104 @ 198MHZ
Performance with and without this patch:
-------------------------------------------------
| | read speed | write speed |
|------------------------------------------------
| with this patch | ~76.7 MB/s | ~23.3 MB/s |
|------------------------------------------------
|without this patch | ~60.5 MB/s | ~22.5 MB/s |
-------------------------------------------------
4. SanDisk 8GB SD3.0 card, running at 4 bit, DDR50 @ 50MHZ
Performance with and without this patch:
-------------------------------------------------
| | read speed | write speed |
|------------------------------------------------
| with this patch | ~40.5 MB/s | ~15.6 MB/s |
|------------------------------------------------
|without this patch | ~36.1 MB/s | ~14.1 MB/s |
-------------------------------------------------
5. Kingston 8GB SD2.0 card, running at 4 bit, High-speed @ 50MHZ
Performance with and without this patch:
-------------------------------------------------
| | read speed | write speed |
|------------------------------------------------
| with this patch | ~22.7 MB/s | ~8.2 MB/s |
|------------------------------------------------
|without this patch | ~21.3 MB/s | ~8.0 MB/s |
-------------------------------------------------
6. About eMMC, Sandisk 8GB eMMC on i.MX6DL-sabresd board, CPU @ 792MHZ,
eMMC running at 8 bit, DDR52 @ 52MHZ.
Performance with and without this patch:
-------------------------------------------------
| | read speed | write speed |
|------------------------------------------------
| with this patch | ~37.3 MB/s | ~10.5 MB/s |
|------------------------------------------------
|without this patch | ~33.4 MB/s | ~10.5 MB/s |
-------------------------------------------------
Signed-off-by: Haibo Chen <haibo.chen@freescale.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2014-12-09 17:04:05 +08:00
|
|
|
}
|
|
|
|
|
2016-06-29 21:24:31 +08:00
|
|
|
static void sdhci_error_out_mrqs(struct sdhci_host *host, int err)
|
|
|
|
{
|
|
|
|
if (host->data_cmd) {
|
|
|
|
host->data_cmd->error = err;
|
|
|
|
sdhci_finish_mrq(host, host->data_cmd->mrq);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (host->cmd) {
|
|
|
|
host->cmd->error = err;
|
|
|
|
sdhci_finish_mrq(host, host->cmd->mrq);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-12-04 23:51:40 +08:00
|
|
|
static void sdhci_card_event(struct mmc_host *mmc)
|
2006-03-24 19:18:17 +08:00
|
|
|
{
|
2012-12-04 23:51:40 +08:00
|
|
|
struct sdhci_host *host = mmc_priv(mmc);
|
2006-03-24 19:18:17 +08:00
|
|
|
unsigned long flags;
|
2015-01-05 17:50:15 +08:00
|
|
|
int present;
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2013-06-21 05:26:36 +08:00
|
|
|
/* First check if client has provided their own card event */
|
|
|
|
if (host->ops->card_event)
|
|
|
|
host->ops->card_event(host);
|
|
|
|
|
2016-06-29 21:24:14 +08:00
|
|
|
present = mmc->ops->get_cd(mmc);
|
2015-01-05 17:50:15 +08:00
|
|
|
|
2006-03-24 19:18:17 +08:00
|
|
|
spin_lock_irqsave(&host->lock, flags);
|
|
|
|
|
2016-06-29 21:24:31 +08:00
|
|
|
/* Check sdhci_has_requests() first in case we are runtime suspended */
|
|
|
|
if (sdhci_has_requests(host) && !present) {
|
2011-10-11 14:14:09 +08:00
|
|
|
pr_err("%s: Card removed during transfer!\n",
|
2011-10-03 20:33:34 +08:00
|
|
|
mmc_hostname(host->mmc));
|
2011-10-11 14:14:09 +08:00
|
|
|
pr_err("%s: Resetting controller.\n",
|
2011-10-03 20:33:34 +08:00
|
|
|
mmc_hostname(host->mmc));
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2014-04-25 19:57:12 +08:00
|
|
|
sdhci_do_reset(host, SDHCI_RESET_CMD);
|
|
|
|
sdhci_do_reset(host, SDHCI_RESET_DATA);
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2016-06-29 21:24:31 +08:00
|
|
|
sdhci_error_out_mrqs(host, -ENOMEDIUM);
|
2006-03-24 19:18:17 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&host->lock, flags);
|
2012-12-04 23:51:40 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static const struct mmc_host_ops sdhci_ops = {
|
|
|
|
.request = sdhci_request,
|
mmc: sdhci: use pipeline mmc requests to improve performance
This patch is based on the patches by Per Forlin, Tony Lin and Ryan QIAN.
This patch complete the API 'post_req' and 'pre_req' in sdhci host side,
Test Env:
1. i.MX6Q-SABREAUTO board, CPU @ 996MHz, use ADMA in uSDHC controller.
2. Test command:
$ echo 1 > /proc/sys/vm/drop_caches
write to sd card:
$ dd if=/dev/zero of=/dev/mmcblk0 bs=1M count=2000 conv=fsync
read the sd card:
$ dd if=/dev/mmcblk0 of=/dev/null bs=1M count=2000
3. TOSHIBA 16GB SD3.0 card, running at 4 bit, SDR104 @ 198MHZ
Performance with and without this patch:
-------------------------------------------------
| | read speed | write speed |
|------------------------------------------------
| with this patch | ~76.7 MB/s | ~23.3 MB/s |
|------------------------------------------------
|without this patch | ~60.5 MB/s | ~22.5 MB/s |
-------------------------------------------------
4. SanDisk 8GB SD3.0 card, running at 4 bit, DDR50 @ 50MHZ
Performance with and without this patch:
-------------------------------------------------
| | read speed | write speed |
|------------------------------------------------
| with this patch | ~40.5 MB/s | ~15.6 MB/s |
|------------------------------------------------
|without this patch | ~36.1 MB/s | ~14.1 MB/s |
-------------------------------------------------
5. Kingston 8GB SD2.0 card, running at 4 bit, High-speed @ 50MHZ
Performance with and without this patch:
-------------------------------------------------
| | read speed | write speed |
|------------------------------------------------
| with this patch | ~22.7 MB/s | ~8.2 MB/s |
|------------------------------------------------
|without this patch | ~21.3 MB/s | ~8.0 MB/s |
-------------------------------------------------
6. About eMMC, Sandisk 8GB eMMC on i.MX6DL-sabresd board, CPU @ 792MHZ,
eMMC running at 8 bit, DDR52 @ 52MHZ.
Performance with and without this patch:
-------------------------------------------------
| | read speed | write speed |
|------------------------------------------------
| with this patch | ~37.3 MB/s | ~10.5 MB/s |
|------------------------------------------------
|without this patch | ~33.4 MB/s | ~10.5 MB/s |
-------------------------------------------------
Signed-off-by: Haibo Chen <haibo.chen@freescale.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2014-12-09 17:04:05 +08:00
|
|
|
.post_req = sdhci_post_req,
|
|
|
|
.pre_req = sdhci_pre_req,
|
2012-12-04 23:51:40 +08:00
|
|
|
.set_ios = sdhci_set_ios,
|
2013-02-28 17:35:53 +08:00
|
|
|
.get_cd = sdhci_get_cd,
|
2012-12-04 23:51:40 +08:00
|
|
|
.get_ro = sdhci_get_ro,
|
|
|
|
.hw_reset = sdhci_hw_reset,
|
|
|
|
.enable_sdio_irq = sdhci_enable_sdio_irq,
|
2019-05-27 19:45:55 +08:00
|
|
|
.ack_sdio_irq = sdhci_ack_sdio_irq,
|
2012-12-04 23:51:40 +08:00
|
|
|
.start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
|
2014-12-06 01:25:31 +08:00
|
|
|
.prepare_hs400_tuning = sdhci_prepare_hs400_tuning,
|
2012-12-04 23:51:40 +08:00
|
|
|
.execute_tuning = sdhci_execute_tuning,
|
|
|
|
.card_event = sdhci_card_event,
|
2012-12-17 19:29:26 +08:00
|
|
|
.card_busy = sdhci_card_busy,
|
2012-12-04 23:51:40 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
/*****************************************************************************\
|
|
|
|
* *
|
2019-04-05 20:40:20 +08:00
|
|
|
* Request done *
|
2012-12-04 23:51:40 +08:00
|
|
|
* *
|
|
|
|
\*****************************************************************************/
|
|
|
|
|
2016-06-29 21:24:34 +08:00
|
|
|
static bool sdhci_request_done(struct sdhci_host *host)
|
2006-03-24 19:18:17 +08:00
|
|
|
{
|
|
|
|
unsigned long flags;
|
|
|
|
struct mmc_request *mrq;
|
2016-06-29 21:24:34 +08:00
|
|
|
int i;
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2011-10-03 20:33:34 +08:00
|
|
|
spin_lock_irqsave(&host->lock, flags);
|
|
|
|
|
2016-06-29 21:24:34 +08:00
|
|
|
for (i = 0; i < SDHCI_MAX_MRQS; i++) {
|
|
|
|
mrq = host->mrqs_done[i];
|
2016-11-02 21:49:08 +08:00
|
|
|
if (mrq)
|
2016-06-29 21:24:34 +08:00
|
|
|
break;
|
2011-10-03 20:33:34 +08:00
|
|
|
}
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2016-06-29 21:24:34 +08:00
|
|
|
if (!mrq) {
|
|
|
|
spin_unlock_irqrestore(&host->lock, flags);
|
|
|
|
return true;
|
|
|
|
}
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2016-01-26 21:40:42 +08:00
|
|
|
/*
|
|
|
|
* Always unmap the data buffers if they were mapped by
|
|
|
|
* sdhci_prepare_data() whenever we finish with a request.
|
|
|
|
* This avoids leaking DMA mappings on error.
|
|
|
|
*/
|
|
|
|
if (host->flags & SDHCI_REQ_USE_DMA) {
|
|
|
|
struct mmc_data *data = mrq->data;
|
|
|
|
|
2020-01-16 18:51:47 +08:00
|
|
|
if (host->use_external_dma && data &&
|
|
|
|
(mrq->cmd->error || data->error)) {
|
|
|
|
struct dma_chan *chan = sdhci_external_dma_channel(host, data);
|
|
|
|
|
|
|
|
host->mrqs_done[i] = NULL;
|
|
|
|
spin_unlock_irqrestore(&host->lock, flags);
|
|
|
|
dmaengine_terminate_sync(chan);
|
|
|
|
spin_lock_irqsave(&host->lock, flags);
|
|
|
|
sdhci_set_mrq_done(host, mrq);
|
|
|
|
}
|
|
|
|
|
2016-01-26 21:40:42 +08:00
|
|
|
if (data && data->host_cookie == COOKIE_MAPPED) {
|
2018-01-29 07:44:53 +08:00
|
|
|
if (host->bounce_buffer) {
|
|
|
|
/*
|
|
|
|
* On reads, copy the bounced data into the
|
|
|
|
* sglist
|
|
|
|
*/
|
|
|
|
if (mmc_get_dma_dir(data) == DMA_FROM_DEVICE) {
|
|
|
|
unsigned int length = data->bytes_xfered;
|
|
|
|
|
|
|
|
if (length > host->bounce_buffer_size) {
|
|
|
|
pr_err("%s: bounce buffer is %u bytes but DMA claims to have transferred %u bytes\n",
|
|
|
|
mmc_hostname(host->mmc),
|
|
|
|
host->bounce_buffer_size,
|
|
|
|
data->bytes_xfered);
|
|
|
|
/* Cap it down and continue */
|
|
|
|
length = host->bounce_buffer_size;
|
|
|
|
}
|
|
|
|
dma_sync_single_for_cpu(
|
|
|
|
host->mmc->parent,
|
|
|
|
host->bounce_addr,
|
|
|
|
host->bounce_buffer_size,
|
|
|
|
DMA_FROM_DEVICE);
|
|
|
|
sg_copy_from_buffer(data->sg,
|
|
|
|
data->sg_len,
|
|
|
|
host->bounce_buffer,
|
|
|
|
length);
|
|
|
|
} else {
|
|
|
|
/* No copying, just switch ownership */
|
|
|
|
dma_sync_single_for_cpu(
|
|
|
|
host->mmc->parent,
|
|
|
|
host->bounce_addr,
|
|
|
|
host->bounce_buffer_size,
|
|
|
|
mmc_get_dma_dir(data));
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
/* Unmap the raw data */
|
|
|
|
dma_unmap_sg(mmc_dev(host->mmc), data->sg,
|
|
|
|
data->sg_len,
|
|
|
|
mmc_get_dma_dir(data));
|
|
|
|
}
|
2016-01-26 21:40:42 +08:00
|
|
|
data->host_cookie = COOKIE_UNMAPPED;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2006-03-24 19:18:17 +08:00
|
|
|
/*
|
|
|
|
* The controller needs a reset of internal state machines
|
|
|
|
* upon error conditions.
|
|
|
|
*/
|
2016-06-29 21:24:28 +08:00
|
|
|
if (sdhci_needs_reset(host, mrq)) {
|
2016-11-02 21:49:08 +08:00
|
|
|
/*
|
|
|
|
* Do not finish until command and data lines are available for
|
|
|
|
* reset. Note there can only be one other mrq, so it cannot
|
|
|
|
* also be in mrqs_done, otherwise host->cmd and host->data_cmd
|
|
|
|
* would both be null.
|
|
|
|
*/
|
|
|
|
if (host->cmd || host->data_cmd) {
|
|
|
|
spin_unlock_irqrestore(&host->lock, flags);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2006-06-30 17:22:33 +08:00
|
|
|
/* Some controllers need this kick or reset won't work here */
|
2013-01-07 22:31:08 +08:00
|
|
|
if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
|
2006-06-30 17:22:33 +08:00
|
|
|
/* This is to force an update */
|
2014-04-25 19:58:55 +08:00
|
|
|
host->ops->set_clock(host, host->clock);
|
2006-06-30 17:22:33 +08:00
|
|
|
|
|
|
|
/* Spec says we should do both at the same time, but Ricoh
|
|
|
|
controllers do not like that. */
|
2016-11-02 21:49:08 +08:00
|
|
|
sdhci_do_reset(host, SDHCI_RESET_CMD);
|
|
|
|
sdhci_do_reset(host, SDHCI_RESET_DATA);
|
2016-06-29 21:24:29 +08:00
|
|
|
|
|
|
|
host->pending_reset = false;
|
2006-03-24 19:18:17 +08:00
|
|
|
}
|
|
|
|
|
2016-11-02 21:49:08 +08:00
|
|
|
host->mrqs_done[i] = NULL;
|
|
|
|
|
2006-03-24 19:18:17 +08:00
|
|
|
spin_unlock_irqrestore(&host->lock, flags);
|
|
|
|
|
2020-02-12 12:12:58 +08:00
|
|
|
if (host->ops->request_done)
|
|
|
|
host->ops->request_done(host, mrq);
|
|
|
|
else
|
|
|
|
mmc_request_done(host->mmc, mrq);
|
2016-06-29 21:24:34 +08:00
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2019-04-05 20:40:20 +08:00
|
|
|
static void sdhci_complete_work(struct work_struct *work)
|
2016-06-29 21:24:34 +08:00
|
|
|
{
|
2019-04-05 20:40:20 +08:00
|
|
|
struct sdhci_host *host = container_of(work, struct sdhci_host,
|
|
|
|
complete_work);
|
2016-06-29 21:24:34 +08:00
|
|
|
|
|
|
|
while (!sdhci_request_done(host))
|
|
|
|
;
|
2006-03-24 19:18:17 +08:00
|
|
|
}
|
|
|
|
|
2017-10-24 23:03:45 +08:00
|
|
|
static void sdhci_timeout_timer(struct timer_list *t)
|
2006-03-24 19:18:17 +08:00
|
|
|
{
|
|
|
|
struct sdhci_host *host;
|
|
|
|
unsigned long flags;
|
|
|
|
|
2017-10-24 23:03:45 +08:00
|
|
|
host = from_timer(host, t, timer);
|
2006-03-24 19:18:17 +08:00
|
|
|
|
|
|
|
spin_lock_irqsave(&host->lock, flags);
|
|
|
|
|
2016-06-29 21:24:33 +08:00
|
|
|
if (host->cmd && !sdhci_data_line_cmd(host->cmd)) {
|
|
|
|
pr_err("%s: Timeout waiting for hardware cmd interrupt.\n",
|
|
|
|
mmc_hostname(host->mmc));
|
|
|
|
sdhci_dumpregs(host);
|
|
|
|
|
|
|
|
host->cmd->error = -ETIMEDOUT;
|
|
|
|
sdhci_finish_mrq(host, host->cmd->mrq);
|
|
|
|
}
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&host->lock, flags);
|
|
|
|
}
|
|
|
|
|
2017-10-24 23:03:45 +08:00
|
|
|
static void sdhci_timeout_data_timer(struct timer_list *t)
|
2016-06-29 21:24:33 +08:00
|
|
|
{
|
|
|
|
struct sdhci_host *host;
|
|
|
|
unsigned long flags;
|
|
|
|
|
2017-10-24 23:03:45 +08:00
|
|
|
host = from_timer(host, t, data_timer);
|
2016-06-29 21:24:33 +08:00
|
|
|
|
|
|
|
spin_lock_irqsave(&host->lock, flags);
|
|
|
|
|
|
|
|
if (host->data || host->data_cmd ||
|
|
|
|
(host->cmd && sdhci_data_line_cmd(host->cmd))) {
|
2015-11-18 17:47:02 +08:00
|
|
|
pr_err("%s: Timeout waiting for hardware interrupt.\n",
|
|
|
|
mmc_hostname(host->mmc));
|
2006-03-24 19:18:17 +08:00
|
|
|
sdhci_dumpregs(host);
|
|
|
|
|
|
|
|
if (host->data) {
|
2007-07-23 04:18:46 +08:00
|
|
|
host->data->error = -ETIMEDOUT;
|
2020-04-12 17:03:49 +08:00
|
|
|
__sdhci_finish_data(host, true);
|
2019-04-05 20:40:20 +08:00
|
|
|
queue_work(host->complete_wq, &host->complete_work);
|
2016-06-29 21:24:33 +08:00
|
|
|
} else if (host->data_cmd) {
|
|
|
|
host->data_cmd->error = -ETIMEDOUT;
|
|
|
|
sdhci_finish_mrq(host, host->data_cmd->mrq);
|
2006-03-24 19:18:17 +08:00
|
|
|
} else {
|
2016-06-29 21:24:33 +08:00
|
|
|
host->cmd->error = -ETIMEDOUT;
|
|
|
|
sdhci_finish_mrq(host, host->cmd->mrq);
|
2006-03-24 19:18:17 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&host->lock, flags);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*****************************************************************************\
|
|
|
|
* *
|
|
|
|
* Interrupt handling *
|
|
|
|
* *
|
|
|
|
\*****************************************************************************/
|
|
|
|
|
2018-11-15 21:53:41 +08:00
|
|
|
static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *intmask_p)
|
2006-03-24 19:18:17 +08:00
|
|
|
{
|
2018-11-15 21:53:43 +08:00
|
|
|
/* Handle auto-CMD12 error */
|
|
|
|
if (intmask & SDHCI_INT_AUTO_CMD_ERR && host->data_cmd) {
|
|
|
|
struct mmc_request *mrq = host->data_cmd->mrq;
|
|
|
|
u16 auto_cmd_status = sdhci_readw(host, SDHCI_AUTO_CMD_STATUS);
|
|
|
|
int data_err_bit = (auto_cmd_status & SDHCI_AUTO_CMD_TIMEOUT) ?
|
|
|
|
SDHCI_INT_DATA_TIMEOUT :
|
|
|
|
SDHCI_INT_DATA_CRC;
|
|
|
|
|
|
|
|
/* Treat auto-CMD12 error the same as data error */
|
|
|
|
if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
|
|
|
|
*intmask_p |= data_err_bit;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2006-03-24 19:18:17 +08:00
|
|
|
if (!host->cmd) {
|
2016-06-29 21:24:29 +08:00
|
|
|
/*
|
|
|
|
* SDHCI recovers from errors by resetting the cmd and data
|
|
|
|
* circuits. Until that is done, there very well might be more
|
|
|
|
* interrupts, so ignore them in that case.
|
|
|
|
*/
|
|
|
|
if (host->pending_reset)
|
|
|
|
return;
|
2015-11-18 17:47:02 +08:00
|
|
|
pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n",
|
|
|
|
mmc_hostname(host->mmc), (unsigned)intmask);
|
2006-03-24 19:18:17 +08:00
|
|
|
sdhci_dumpregs(host);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2016-01-26 21:39:39 +08:00
|
|
|
if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC |
|
|
|
|
SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) {
|
|
|
|
if (intmask & SDHCI_INT_TIMEOUT)
|
|
|
|
host->cmd->error = -ETIMEDOUT;
|
|
|
|
else
|
|
|
|
host->cmd->error = -EILSEQ;
|
2007-07-26 05:15:27 +08:00
|
|
|
|
2018-11-15 21:53:41 +08:00
|
|
|
/* Treat data command CRC error the same as data CRC error */
|
mmc: sdhci: fix command response CRC error handling
When we get a response CRC error on a command, it means that the
response we received back from the card was not correct. It does not
mean that the card did not receive the command correctly. If the
command is one which initiates a data transfer, the card can enter the
data transfer state, and start sending data.
Moreover, if the request contained a data phase, we do not clean this
up, and this results in the driver triggering DMA API debug warnings,
and also creates a race condition in the driver, between running the
finish_tasklet and the data transfer interrupts, which can trigger a
"Got data interrupt" state dump.
Fix this by handing a response CRC error slightly differently: record
the failure of the data initiating command, but allow the remainder of
the request to be processed normally. This is safe as core MMC checks
the status of all commands and data transfer phases of the request.
If the card does not initiate a data transfer, then we should time out
according to the data transfer parameters.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
[ Fix missing parenthesis around bitwise-AND expression, and tweak subject ]
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Cc: stable@vger.kernel.org # v4.5+
Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2016-01-26 21:39:45 +08:00
|
|
|
if (host->cmd->data &&
|
|
|
|
(intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) ==
|
|
|
|
SDHCI_INT_CRC) {
|
|
|
|
host->cmd = NULL;
|
2018-11-15 21:53:41 +08:00
|
|
|
*intmask_p |= SDHCI_INT_DATA_CRC;
|
mmc: sdhci: fix command response CRC error handling
When we get a response CRC error on a command, it means that the
response we received back from the card was not correct. It does not
mean that the card did not receive the command correctly. If the
command is one which initiates a data transfer, the card can enter the
data transfer state, and start sending data.
Moreover, if the request contained a data phase, we do not clean this
up, and this results in the driver triggering DMA API debug warnings,
and also creates a race condition in the driver, between running the
finish_tasklet and the data transfer interrupts, which can trigger a
"Got data interrupt" state dump.
Fix this by handing a response CRC error slightly differently: record
the failure of the data initiating command, but allow the remainder of
the request to be processed normally. This is safe as core MMC checks
the status of all commands and data transfer phases of the request.
If the card does not initiate a data transfer, then we should time out
according to the data transfer parameters.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
[ Fix missing parenthesis around bitwise-AND expression, and tweak subject ]
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Cc: stable@vger.kernel.org # v4.5+
Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2016-01-26 21:39:45 +08:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2019-04-05 20:40:19 +08:00
|
|
|
__sdhci_finish_mrq(host, host->cmd->mrq);
|
2008-07-25 07:09:08 +08:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2018-11-15 21:53:43 +08:00
|
|
|
/* Handle auto-CMD23 error */
|
|
|
|
if (intmask & SDHCI_INT_AUTO_CMD_ERR) {
|
|
|
|
struct mmc_request *mrq = host->cmd->mrq;
|
|
|
|
u16 auto_cmd_status = sdhci_readw(host, SDHCI_AUTO_CMD_STATUS);
|
|
|
|
int err = (auto_cmd_status & SDHCI_AUTO_CMD_TIMEOUT) ?
|
|
|
|
-ETIMEDOUT :
|
|
|
|
-EILSEQ;
|
|
|
|
|
|
|
|
if (mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
|
|
|
|
mrq->sbc->error = err;
|
2019-04-05 20:40:19 +08:00
|
|
|
__sdhci_finish_mrq(host, mrq);
|
2018-11-15 21:53:43 +08:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2008-07-25 07:09:08 +08:00
|
|
|
if (intmask & SDHCI_INT_RESPONSE)
|
2007-07-26 05:15:27 +08:00
|
|
|
sdhci_finish_command(host);
|
2006-03-24 19:18:17 +08:00
|
|
|
}
|
|
|
|
|
2014-11-04 18:42:38 +08:00
|
|
|
static void sdhci_adma_show_error(struct sdhci_host *host)
|
2009-06-14 20:52:38 +08:00
|
|
|
{
|
2014-11-04 18:42:41 +08:00
|
|
|
void *desc = host->adma_table;
|
2019-09-22 18:26:53 +08:00
|
|
|
dma_addr_t dma = host->adma_addr;
|
2009-06-14 20:52:38 +08:00
|
|
|
|
|
|
|
sdhci_dumpregs(host);
|
|
|
|
|
|
|
|
while (true) {
|
2014-11-04 18:42:46 +08:00
|
|
|
struct sdhci_adma2_64_desc *dma_desc = desc;
|
|
|
|
|
|
|
|
if (host->flags & SDHCI_USE_64_BIT_DMA)
|
2019-09-22 18:26:53 +08:00
|
|
|
SDHCI_DUMP("%08llx: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
|
|
|
|
(unsigned long long)dma,
|
|
|
|
le32_to_cpu(dma_desc->addr_hi),
|
2014-11-04 18:42:46 +08:00
|
|
|
le32_to_cpu(dma_desc->addr_lo),
|
|
|
|
le16_to_cpu(dma_desc->len),
|
|
|
|
le16_to_cpu(dma_desc->cmd));
|
|
|
|
else
|
2019-09-22 18:26:53 +08:00
|
|
|
SDHCI_DUMP("%08llx: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
|
|
|
|
(unsigned long long)dma,
|
|
|
|
le32_to_cpu(dma_desc->addr_lo),
|
2014-11-04 18:42:46 +08:00
|
|
|
le16_to_cpu(dma_desc->len),
|
|
|
|
le16_to_cpu(dma_desc->cmd));
|
2009-06-14 20:52:38 +08:00
|
|
|
|
2014-11-04 18:42:42 +08:00
|
|
|
desc += host->desc_sz;
|
2019-09-22 18:26:53 +08:00
|
|
|
dma += host->desc_sz;
|
2009-06-14 20:52:38 +08:00
|
|
|
|
2014-11-04 18:42:45 +08:00
|
|
|
if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
|
2009-06-14 20:52:38 +08:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2006-03-24 19:18:17 +08:00
|
|
|
static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
|
|
|
|
{
|
2012-01-06 12:26:39 +08:00
|
|
|
u32 command;
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2011-05-05 14:49:04 +08:00
|
|
|
/* CMD19 generates _only_ Buffer Read Ready interrupt */
|
|
|
|
if (intmask & SDHCI_INT_DATA_AVAIL) {
|
2012-01-06 12:26:39 +08:00
|
|
|
command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
|
|
|
|
if (command == MMC_SEND_TUNING_BLOCK ||
|
|
|
|
command == MMC_SEND_TUNING_BLOCK_HS200) {
|
2011-05-05 14:49:04 +08:00
|
|
|
host->tuning_done = 1;
|
|
|
|
wake_up(&host->buf_ready_int);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2006-03-24 19:18:17 +08:00
|
|
|
if (!host->data) {
|
2016-06-29 21:24:23 +08:00
|
|
|
struct mmc_command *data_cmd = host->data_cmd;
|
|
|
|
|
2006-03-24 19:18:17 +08:00
|
|
|
/*
|
2008-07-25 07:09:08 +08:00
|
|
|
* The "data complete" interrupt is also used to
|
|
|
|
* indicate that a busy state has ended. See comment
|
|
|
|
* above in sdhci_cmd_irq().
|
2006-03-24 19:18:17 +08:00
|
|
|
*/
|
2016-06-29 21:24:23 +08:00
|
|
|
if (data_cmd && (data_cmd->flags & MMC_RSP_BUSY)) {
|
2014-08-14 22:03:17 +08:00
|
|
|
if (intmask & SDHCI_INT_DATA_TIMEOUT) {
|
2016-11-02 21:49:09 +08:00
|
|
|
host->data_cmd = NULL;
|
2016-06-29 21:24:23 +08:00
|
|
|
data_cmd->error = -ETIMEDOUT;
|
2019-04-05 20:40:19 +08:00
|
|
|
__sdhci_finish_mrq(host, data_cmd->mrq);
|
2014-08-14 22:03:17 +08:00
|
|
|
return;
|
|
|
|
}
|
2008-07-25 07:09:08 +08:00
|
|
|
if (intmask & SDHCI_INT_DATA_END) {
|
2016-11-02 21:49:09 +08:00
|
|
|
host->data_cmd = NULL;
|
2014-08-30 11:40:40 +08:00
|
|
|
/*
|
|
|
|
* Some cards handle busy-end interrupt
|
|
|
|
* before the command completed, so make
|
|
|
|
* sure we do things in the proper order.
|
|
|
|
*/
|
2016-06-29 21:24:24 +08:00
|
|
|
if (host->cmd == data_cmd)
|
|
|
|
return;
|
|
|
|
|
2019-04-05 20:40:19 +08:00
|
|
|
__sdhci_finish_mrq(host, data_cmd->mrq);
|
2008-07-25 07:09:08 +08:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2016-06-29 21:24:29 +08:00
|
|
|
/*
|
|
|
|
* SDHCI recovers from errors by resetting the cmd and data
|
|
|
|
* circuits. Until that is done, there very well might be more
|
|
|
|
* interrupts, so ignore them in that case.
|
|
|
|
*/
|
|
|
|
if (host->pending_reset)
|
|
|
|
return;
|
|
|
|
|
2015-11-18 17:47:02 +08:00
|
|
|
pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n",
|
|
|
|
mmc_hostname(host->mmc), (unsigned)intmask);
|
2006-03-24 19:18:17 +08:00
|
|
|
sdhci_dumpregs(host);
|
|
|
|
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (intmask & SDHCI_INT_DATA_TIMEOUT)
|
2007-07-23 04:18:46 +08:00
|
|
|
host->data->error = -ETIMEDOUT;
|
2010-12-15 15:14:24 +08:00
|
|
|
else if (intmask & SDHCI_INT_DATA_END_BIT)
|
|
|
|
host->data->error = -EILSEQ;
|
|
|
|
else if ((intmask & SDHCI_INT_DATA_CRC) &&
|
|
|
|
SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
|
|
|
|
!= MMC_BUS_TEST_R)
|
2007-07-23 04:18:46 +08:00
|
|
|
host->data->error = -EILSEQ;
|
2009-06-14 20:52:38 +08:00
|
|
|
else if (intmask & SDHCI_INT_ADMA_ERROR) {
|
2019-09-22 18:26:53 +08:00
|
|
|
pr_err("%s: ADMA error: 0x%08x\n", mmc_hostname(host->mmc),
|
|
|
|
intmask);
|
2014-11-04 18:42:38 +08:00
|
|
|
sdhci_adma_show_error(host);
|
2008-06-29 00:28:51 +08:00
|
|
|
host->data->error = -EIO;
|
2012-12-04 10:41:28 +08:00
|
|
|
if (host->ops->adma_workaround)
|
|
|
|
host->ops->adma_workaround(host, intmask);
|
2009-06-14 20:52:38 +08:00
|
|
|
}
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2007-07-23 04:18:46 +08:00
|
|
|
if (host->data->error)
|
2006-03-24 19:18:17 +08:00
|
|
|
sdhci_finish_data(host);
|
|
|
|
else {
|
2006-07-02 23:50:59 +08:00
|
|
|
if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
|
2006-03-24 19:18:17 +08:00
|
|
|
sdhci_transfer_pio(host);
|
|
|
|
|
2007-05-14 04:39:23 +08:00
|
|
|
/*
|
|
|
|
* We currently don't do anything fancy with DMA
|
|
|
|
* boundaries, but as we can't disable the feature
|
|
|
|
* we need to at least restart the transfer.
|
2011-04-12 21:36:18 +08:00
|
|
|
*
|
|
|
|
* According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
|
|
|
|
* should return a valid address to continue from, but as
|
|
|
|
* some controllers are faulty, don't trust them.
|
2007-05-14 04:39:23 +08:00
|
|
|
*/
|
2011-04-12 21:36:18 +08:00
|
|
|
if (intmask & SDHCI_INT_DMA_END) {
|
2018-08-30 16:21:39 +08:00
|
|
|
dma_addr_t dmastart, dmanow;
|
2018-01-29 07:44:53 +08:00
|
|
|
|
|
|
|
dmastart = sdhci_sdma_address(host);
|
2011-04-12 21:36:18 +08:00
|
|
|
dmanow = dmastart + host->data->bytes_xfered;
|
|
|
|
/*
|
|
|
|
* Force update to the next DMA block boundary.
|
|
|
|
*/
|
|
|
|
dmanow = (dmanow &
|
2018-08-30 16:21:39 +08:00
|
|
|
~((dma_addr_t)SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
|
2011-04-12 21:36:18 +08:00
|
|
|
SDHCI_DEFAULT_BOUNDARY_SIZE;
|
|
|
|
host->data->bytes_xfered = dmanow - dmastart;
|
2018-08-30 16:21:39 +08:00
|
|
|
DBG("DMA base %pad, transferred 0x%06x bytes, next %pad\n",
|
|
|
|
&dmastart, host->data->bytes_xfered, &dmanow);
|
|
|
|
sdhci_set_sdma_addr(host, dmanow);
|
2011-04-12 21:36:18 +08:00
|
|
|
}
|
2007-05-14 04:39:23 +08:00
|
|
|
|
2007-08-12 22:46:32 +08:00
|
|
|
if (intmask & SDHCI_INT_DATA_END) {
|
2016-06-29 21:24:23 +08:00
|
|
|
if (host->cmd == host->data_cmd) {
|
2007-08-12 22:46:32 +08:00
|
|
|
/*
|
|
|
|
* Data managed to finish before the
|
|
|
|
* command completed. Make sure we do
|
|
|
|
* things in the proper order.
|
|
|
|
*/
|
|
|
|
host->data_early = 1;
|
|
|
|
} else {
|
|
|
|
sdhci_finish_data(host);
|
|
|
|
}
|
|
|
|
}
|
2006-03-24 19:18:17 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-04-05 20:40:19 +08:00
|
|
|
static inline bool sdhci_defer_done(struct sdhci_host *host,
|
|
|
|
struct mmc_request *mrq)
|
|
|
|
{
|
|
|
|
struct mmc_data *data = mrq->data;
|
|
|
|
|
2020-02-12 12:12:59 +08:00
|
|
|
return host->pending_reset || host->always_defer_done ||
|
2019-04-05 20:40:19 +08:00
|
|
|
((host->flags & SDHCI_REQ_USE_DMA) && data &&
|
|
|
|
data->host_cookie == COOKIE_MAPPED);
|
|
|
|
}
|
|
|
|
|
IRQ: Maintain regs pointer globally rather than passing to IRQ handlers
Maintain a per-CPU global "struct pt_regs *" variable which can be used instead
of passing regs around manually through all ~1800 interrupt handlers in the
Linux kernel.
The regs pointer is used in few places, but it potentially costs both stack
space and code to pass it around. On the FRV arch, removing the regs parameter
from all the genirq function results in a 20% speed up of the IRQ exit path
(ie: from leaving timer_interrupt() to leaving do_IRQ()).
Where appropriate, an arch may override the generic storage facility and do
something different with the variable. On FRV, for instance, the address is
maintained in GR28 at all times inside the kernel as part of general exception
handling.
Having looked over the code, it appears that the parameter may be handed down
through up to twenty or so layers of functions. Consider a USB character
device attached to a USB hub, attached to a USB controller that posts its
interrupts through a cascaded auxiliary interrupt controller. A character
device driver may want to pass regs to the sysrq handler through the input
layer which adds another few layers of parameter passing.
I've build this code with allyesconfig for x86_64 and i386. I've runtested the
main part of the code on FRV and i386, though I can't test most of the drivers.
I've also done partial conversion for powerpc and MIPS - these at least compile
with minimal configurations.
This will affect all archs. Mostly the changes should be relatively easy.
Take do_IRQ(), store the regs pointer at the beginning, saving the old one:
struct pt_regs *old_regs = set_irq_regs(regs);
And put the old one back at the end:
set_irq_regs(old_regs);
Don't pass regs through to generic_handle_irq() or __do_IRQ().
In timer_interrupt(), this sort of change will be necessary:
- update_process_times(user_mode(regs));
- profile_tick(CPU_PROFILING, regs);
+ update_process_times(user_mode(get_irq_regs()));
+ profile_tick(CPU_PROFILING);
I'd like to move update_process_times()'s use of get_irq_regs() into itself,
except that i386, alone of the archs, uses something other than user_mode().
Some notes on the interrupt handling in the drivers:
(*) input_dev() is now gone entirely. The regs pointer is no longer stored in
the input_dev struct.
(*) finish_unlinks() in drivers/usb/host/ohci-q.c needs checking. It does
something different depending on whether it's been supplied with a regs
pointer or not.
(*) Various IRQ handler function pointers have been moved to type
irq_handler_t.
Signed-Off-By: David Howells <dhowells@redhat.com>
(cherry picked from 1b16e7ac850969f38b375e511e3fa2f474a33867 commit)
2006-10-05 21:55:46 +08:00
|
|
|
static irqreturn_t sdhci_irq(int irq, void *dev_id)
|
2006-03-24 19:18:17 +08:00
|
|
|
{
|
2019-04-05 20:40:19 +08:00
|
|
|
struct mmc_request *mrqs_done[SDHCI_MAX_MRQS] = {0};
|
2014-04-25 19:55:46 +08:00
|
|
|
irqreturn_t result = IRQ_NONE;
|
2011-10-03 20:33:34 +08:00
|
|
|
struct sdhci_host *host = dev_id;
|
2014-04-25 19:55:36 +08:00
|
|
|
u32 intmask, mask, unexpected = 0;
|
2014-04-25 19:55:46 +08:00
|
|
|
int max_loops = 16;
|
2019-04-05 20:40:19 +08:00
|
|
|
int i;
|
2006-03-24 19:18:17 +08:00
|
|
|
|
|
|
|
spin_lock(&host->lock);
|
|
|
|
|
2019-09-08 18:12:35 +08:00
|
|
|
if (host->runtime_suspended) {
|
2011-10-03 20:33:34 +08:00
|
|
|
spin_unlock(&host->lock);
|
2014-03-11 16:09:36 +08:00
|
|
|
return IRQ_NONE;
|
2011-10-03 20:33:34 +08:00
|
|
|
}
|
|
|
|
|
2009-03-17 05:13:46 +08:00
|
|
|
intmask = sdhci_readl(host, SDHCI_INT_STATUS);
|
2007-03-06 20:30:13 +08:00
|
|
|
if (!intmask || intmask == 0xffffffff) {
|
2006-03-24 19:18:17 +08:00
|
|
|
result = IRQ_NONE;
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
2014-04-25 19:55:36 +08:00
|
|
|
do {
|
2017-03-21 01:50:47 +08:00
|
|
|
DBG("IRQ status 0x%08x\n", intmask);
|
|
|
|
|
|
|
|
if (host->ops->irq) {
|
|
|
|
intmask = host->ops->irq(host, intmask);
|
|
|
|
if (!intmask)
|
|
|
|
goto cont;
|
|
|
|
}
|
|
|
|
|
2014-04-25 19:55:36 +08:00
|
|
|
/* Clear selected interrupts. */
|
|
|
|
mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
|
|
|
|
SDHCI_INT_BUS_POWER);
|
|
|
|
sdhci_writel(host, mask, SDHCI_INT_STATUS);
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2014-04-25 19:55:36 +08:00
|
|
|
if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
|
|
|
|
u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
|
|
|
|
SDHCI_CARD_PRESENT;
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2014-04-25 19:55:36 +08:00
|
|
|
/*
|
|
|
|
* There is a observation on i.mx esdhc. INSERT
|
|
|
|
* bit will be immediately set again when it gets
|
|
|
|
* cleared, if a card is inserted. We have to mask
|
|
|
|
* the irq to prevent interrupt storm which will
|
|
|
|
* freeze the system. And the REMOVE gets the
|
|
|
|
* same situation.
|
|
|
|
*
|
|
|
|
* More testing are needed here to ensure it works
|
|
|
|
* for other platforms though.
|
|
|
|
*/
|
2014-04-25 19:56:01 +08:00
|
|
|
host->ier &= ~(SDHCI_INT_CARD_INSERT |
|
|
|
|
SDHCI_INT_CARD_REMOVE);
|
|
|
|
host->ier |= present ? SDHCI_INT_CARD_REMOVE :
|
|
|
|
SDHCI_INT_CARD_INSERT;
|
|
|
|
sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
|
|
|
|
sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
|
2014-04-25 19:55:36 +08:00
|
|
|
|
|
|
|
sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
|
|
|
|
SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
|
2014-04-25 19:55:51 +08:00
|
|
|
|
|
|
|
host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
|
|
|
|
SDHCI_INT_CARD_REMOVE);
|
|
|
|
result = IRQ_WAKE_THREAD;
|
2014-04-25 19:55:36 +08:00
|
|
|
}
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2014-04-25 19:55:36 +08:00
|
|
|
if (intmask & SDHCI_INT_CMD_MASK)
|
2018-11-15 21:53:41 +08:00
|
|
|
sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK, &intmask);
|
2007-07-21 00:20:36 +08:00
|
|
|
|
2014-04-25 19:55:36 +08:00
|
|
|
if (intmask & SDHCI_INT_DATA_MASK)
|
|
|
|
sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2014-04-25 19:55:36 +08:00
|
|
|
if (intmask & SDHCI_INT_BUS_POWER)
|
|
|
|
pr_err("%s: Card is consuming too much power!\n",
|
|
|
|
mmc_hostname(host->mmc));
|
2006-06-30 17:22:26 +08:00
|
|
|
|
2016-07-12 15:46:17 +08:00
|
|
|
if (intmask & SDHCI_INT_RETUNE)
|
|
|
|
mmc_retune_needed(host->mmc);
|
|
|
|
|
2017-01-16 22:23:42 +08:00
|
|
|
if ((intmask & SDHCI_INT_CARD_INT) &&
|
|
|
|
(host->ier & SDHCI_INT_CARD_INT)) {
|
2014-04-25 19:55:46 +08:00
|
|
|
sdhci_enable_sdio_irq_nolock(host, false);
|
2019-05-27 19:45:55 +08:00
|
|
|
sdio_signal_irq(host->mmc);
|
2014-04-25 19:55:46 +08:00
|
|
|
}
|
2007-09-04 13:59:18 +08:00
|
|
|
|
2014-04-25 19:55:36 +08:00
|
|
|
intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
|
|
|
|
SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
|
|
|
|
SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
|
2016-07-12 15:46:17 +08:00
|
|
|
SDHCI_INT_RETUNE | SDHCI_INT_CARD_INT);
|
2007-09-04 13:59:18 +08:00
|
|
|
|
2014-04-25 19:55:36 +08:00
|
|
|
if (intmask) {
|
|
|
|
unexpected |= intmask;
|
|
|
|
sdhci_writel(host, intmask, SDHCI_INT_STATUS);
|
|
|
|
}
|
2017-03-21 01:50:47 +08:00
|
|
|
cont:
|
2014-04-25 19:55:46 +08:00
|
|
|
if (result == IRQ_NONE)
|
|
|
|
result = IRQ_HANDLED;
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2014-04-25 19:55:36 +08:00
|
|
|
intmask = sdhci_readl(host, SDHCI_INT_STATUS);
|
|
|
|
} while (intmask && --max_loops);
|
2019-04-05 20:40:19 +08:00
|
|
|
|
|
|
|
/* Determine if mrqs can be completed immediately */
|
|
|
|
for (i = 0; i < SDHCI_MAX_MRQS; i++) {
|
|
|
|
struct mmc_request *mrq = host->mrqs_done[i];
|
|
|
|
|
|
|
|
if (!mrq)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (sdhci_defer_done(host, mrq)) {
|
2019-04-05 20:40:20 +08:00
|
|
|
result = IRQ_WAKE_THREAD;
|
2019-04-05 20:40:19 +08:00
|
|
|
} else {
|
|
|
|
mrqs_done[i] = mrq;
|
|
|
|
host->mrqs_done[i] = NULL;
|
|
|
|
}
|
|
|
|
}
|
2006-03-24 19:18:17 +08:00
|
|
|
out:
|
2020-04-12 17:03:49 +08:00
|
|
|
if (host->deferred_cmd)
|
|
|
|
result = IRQ_WAKE_THREAD;
|
|
|
|
|
2006-03-24 19:18:17 +08:00
|
|
|
spin_unlock(&host->lock);
|
|
|
|
|
2019-04-05 20:40:19 +08:00
|
|
|
/* Process mrqs ready for immediate completion */
|
|
|
|
for (i = 0; i < SDHCI_MAX_MRQS; i++) {
|
2020-02-12 12:12:58 +08:00
|
|
|
if (!mrqs_done[i])
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (host->ops->request_done)
|
|
|
|
host->ops->request_done(host, mrqs_done[i]);
|
|
|
|
else
|
2019-04-05 20:40:19 +08:00
|
|
|
mmc_request_done(host->mmc, mrqs_done[i]);
|
|
|
|
}
|
|
|
|
|
2012-03-14 16:52:10 +08:00
|
|
|
if (unexpected) {
|
|
|
|
pr_err("%s: Unexpected interrupt 0x%08x.\n",
|
|
|
|
mmc_hostname(host->mmc), unexpected);
|
|
|
|
sdhci_dumpregs(host);
|
|
|
|
}
|
2007-09-04 13:59:18 +08:00
|
|
|
|
2006-03-24 19:18:17 +08:00
|
|
|
return result;
|
|
|
|
}
|
|
|
|
|
2014-04-25 19:55:46 +08:00
|
|
|
static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
|
|
|
|
{
|
|
|
|
struct sdhci_host *host = dev_id;
|
2020-04-12 17:03:49 +08:00
|
|
|
struct mmc_command *cmd;
|
2014-04-25 19:55:46 +08:00
|
|
|
unsigned long flags;
|
|
|
|
u32 isr;
|
|
|
|
|
2019-04-05 20:40:20 +08:00
|
|
|
while (!sdhci_request_done(host))
|
|
|
|
;
|
|
|
|
|
2014-04-25 19:55:46 +08:00
|
|
|
spin_lock_irqsave(&host->lock, flags);
|
2020-04-12 17:03:49 +08:00
|
|
|
|
2014-04-25 19:55:46 +08:00
|
|
|
isr = host->thread_isr;
|
|
|
|
host->thread_isr = 0;
|
2020-04-12 17:03:49 +08:00
|
|
|
|
|
|
|
cmd = host->deferred_cmd;
|
|
|
|
if (cmd && !sdhci_send_command_retry(host, cmd, flags))
|
|
|
|
sdhci_finish_mrq(host, cmd->mrq);
|
|
|
|
|
2014-04-25 19:55:46 +08:00
|
|
|
spin_unlock_irqrestore(&host->lock, flags);
|
|
|
|
|
2014-04-25 19:55:51 +08:00
|
|
|
if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
|
2016-06-29 21:24:14 +08:00
|
|
|
struct mmc_host *mmc = host->mmc;
|
|
|
|
|
|
|
|
mmc->ops->card_event(mmc);
|
|
|
|
mmc_detect_change(mmc, msecs_to_jiffies(200));
|
2014-04-25 19:55:51 +08:00
|
|
|
}
|
|
|
|
|
2019-04-05 20:40:20 +08:00
|
|
|
return IRQ_HANDLED;
|
2014-04-25 19:55:46 +08:00
|
|
|
}
|
|
|
|
|
2006-03-24 19:18:17 +08:00
|
|
|
/*****************************************************************************\
|
|
|
|
* *
|
|
|
|
* Suspend/resume *
|
|
|
|
* *
|
|
|
|
\*****************************************************************************/
|
|
|
|
|
|
|
|
#ifdef CONFIG_PM
|
2018-02-27 20:51:23 +08:00
|
|
|
|
|
|
|
static bool sdhci_cd_irq_can_wakeup(struct sdhci_host *host)
|
|
|
|
{
|
|
|
|
return mmc_card_is_removable(host->mmc) &&
|
|
|
|
!(host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
|
|
|
|
!mmc_can_gpio_cd(host->mmc);
|
|
|
|
}
|
|
|
|
|
2016-05-13 21:16:02 +08:00
|
|
|
/*
|
|
|
|
* To enable wakeup events, the corresponding events have to be enabled in
|
|
|
|
* the Interrupt Status Enable register too. See 'Table 1-6: Wakeup Signal
|
|
|
|
* Table' in the SD Host Controller Standard Specification.
|
|
|
|
* It is useless to restore SDHCI_INT_ENABLE state in
|
|
|
|
* sdhci_disable_irq_wakeups() since it will be set by
|
|
|
|
* sdhci_enable_card_detection() or sdhci_init().
|
|
|
|
*/
|
2018-01-09 15:52:21 +08:00
|
|
|
static bool sdhci_enable_irq_wakeups(struct sdhci_host *host)
|
2013-01-05 17:21:33 +08:00
|
|
|
{
|
2018-01-09 15:52:22 +08:00
|
|
|
u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE |
|
|
|
|
SDHCI_WAKE_ON_INT;
|
|
|
|
u32 irq_val = 0;
|
|
|
|
u8 wake_val = 0;
|
2013-01-05 17:21:33 +08:00
|
|
|
u8 val;
|
|
|
|
|
2018-02-27 20:51:23 +08:00
|
|
|
if (sdhci_cd_irq_can_wakeup(host)) {
|
2018-01-09 15:52:22 +08:00
|
|
|
wake_val |= SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE;
|
|
|
|
irq_val |= SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE;
|
2016-05-13 21:16:02 +08:00
|
|
|
}
|
2018-01-09 15:52:22 +08:00
|
|
|
|
2018-02-27 20:51:24 +08:00
|
|
|
if (mmc_card_wake_sdio_irq(host->mmc)) {
|
|
|
|
wake_val |= SDHCI_WAKE_ON_INT;
|
|
|
|
irq_val |= SDHCI_INT_CARD_INT;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!irq_val)
|
|
|
|
return false;
|
2018-01-09 15:52:22 +08:00
|
|
|
|
|
|
|
val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
|
|
|
|
val &= ~mask;
|
|
|
|
val |= wake_val;
|
2013-01-05 17:21:33 +08:00
|
|
|
sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
|
2018-01-09 15:52:22 +08:00
|
|
|
|
2016-05-13 21:16:02 +08:00
|
|
|
sdhci_writel(host, irq_val, SDHCI_INT_ENABLE);
|
2018-01-09 15:52:21 +08:00
|
|
|
|
|
|
|
host->irq_wake_enabled = !enable_irq_wake(host->irq);
|
|
|
|
|
|
|
|
return host->irq_wake_enabled;
|
2013-01-05 17:21:33 +08:00
|
|
|
}
|
|
|
|
|
2014-08-31 01:53:13 +08:00
|
|
|
static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
|
2013-01-05 17:21:33 +08:00
|
|
|
{
|
|
|
|
u8 val;
|
|
|
|
u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
|
|
|
|
| SDHCI_WAKE_ON_INT;
|
|
|
|
|
|
|
|
val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
|
|
|
|
val &= ~mask;
|
|
|
|
sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
|
2018-01-09 15:52:21 +08:00
|
|
|
|
|
|
|
disable_irq_wake(host->irq);
|
|
|
|
|
|
|
|
host->irq_wake_enabled = false;
|
2013-01-05 17:21:33 +08:00
|
|
|
}
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2011-11-03 18:09:45 +08:00
|
|
|
int sdhci_suspend_host(struct sdhci_host *host)
|
2006-03-24 19:18:17 +08:00
|
|
|
{
|
2009-03-17 05:13:48 +08:00
|
|
|
sdhci_disable_card_detection(host);
|
|
|
|
|
2015-05-07 18:10:21 +08:00
|
|
|
mmc_retune_timer_stop(host->mmc);
|
2011-05-05 14:49:07 +08:00
|
|
|
|
2018-01-09 15:52:21 +08:00
|
|
|
if (!device_may_wakeup(mmc_dev(host->mmc)) ||
|
|
|
|
!sdhci_enable_irq_wakeups(host)) {
|
2014-04-25 19:56:01 +08:00
|
|
|
host->ier = 0;
|
|
|
|
sdhci_writel(host, 0, SDHCI_INT_ENABLE);
|
|
|
|
sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
|
2013-01-05 17:21:33 +08:00
|
|
|
free_irq(host->irq, host);
|
|
|
|
}
|
2018-01-09 15:52:21 +08:00
|
|
|
|
2013-09-25 20:15:24 +08:00
|
|
|
return 0;
|
2006-03-24 19:18:17 +08:00
|
|
|
}
|
|
|
|
|
2008-03-19 00:35:49 +08:00
|
|
|
EXPORT_SYMBOL_GPL(sdhci_suspend_host);
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2008-03-19 00:35:49 +08:00
|
|
|
int sdhci_resume_host(struct sdhci_host *host)
|
|
|
|
{
|
2016-06-29 21:24:14 +08:00
|
|
|
struct mmc_host *mmc = host->mmc;
|
2013-09-25 20:15:24 +08:00
|
|
|
int ret = 0;
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2009-09-23 07:45:30 +08:00
|
|
|
if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
|
2008-03-19 00:35:49 +08:00
|
|
|
if (host->ops->enable_dma)
|
|
|
|
host->ops->enable_dma(host);
|
|
|
|
}
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2012-02-07 20:48:54 +08:00
|
|
|
if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
|
|
|
|
(host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
|
|
|
|
/* Card keeps power but host controller does not */
|
|
|
|
sdhci_init(host, 0);
|
|
|
|
host->pwr = 0;
|
|
|
|
host->clock = 0;
|
2016-06-29 21:24:14 +08:00
|
|
|
mmc->ops->set_ios(mmc, &mmc->ios);
|
2012-02-07 20:48:54 +08:00
|
|
|
} else {
|
|
|
|
sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
|
|
|
|
}
|
2008-03-19 00:35:49 +08:00
|
|
|
|
2018-01-09 15:52:21 +08:00
|
|
|
if (host->irq_wake_enabled) {
|
|
|
|
sdhci_disable_irq_wakeups(host);
|
|
|
|
} else {
|
mmc: sdhci: call sdhci_init() before request irq
sdhci_init() will clear all irqs and set the needed irqs. So
logically sdhci_init() should be called before request irq.
If not, some irqs may be triggled and handled wrongly. Take
the following into consideration, after request irq, if
SDIO card interrupt enabled, a sd card in the sd slot will
trigger a mass of interrupt(SDHCI_INT_CARD_INT), because at
this time, the vmmc-regulator still not restore, no voltage
supply for the sd card, so the pin of data0~data3 change and
keep low, interrupt(SDHCI_INT_CARD_INT) will rise up ceaselessly.
Due to we already reguest irq, system will be busy in handling
this endless irq, can't response to other event.
So we should call sdhci_init() before request irq in sd resume.
Signed-off-by: Haibo Chen <haibo.chen@freescale.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-09-15 18:32:58 +08:00
|
|
|
ret = request_threaded_irq(host->irq, sdhci_irq,
|
|
|
|
sdhci_thread_irq, IRQF_SHARED,
|
|
|
|
mmc_hostname(host->mmc), host);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2009-03-17 05:13:48 +08:00
|
|
|
sdhci_enable_card_detection(host);
|
|
|
|
|
2010-03-06 05:43:32 +08:00
|
|
|
return ret;
|
2006-03-24 19:18:17 +08:00
|
|
|
}
|
|
|
|
|
2008-03-19 00:35:49 +08:00
|
|
|
EXPORT_SYMBOL_GPL(sdhci_resume_host);
|
2011-10-03 20:33:34 +08:00
|
|
|
|
|
|
|
int sdhci_runtime_suspend_host(struct sdhci_host *host)
|
|
|
|
{
|
|
|
|
unsigned long flags;
|
|
|
|
|
2015-05-07 18:10:21 +08:00
|
|
|
mmc_retune_timer_stop(host->mmc);
|
2011-10-03 20:33:34 +08:00
|
|
|
|
|
|
|
spin_lock_irqsave(&host->lock, flags);
|
2014-04-25 19:56:01 +08:00
|
|
|
host->ier &= SDHCI_INT_CARD_INT;
|
|
|
|
sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
|
|
|
|
sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
|
2011-10-03 20:33:34 +08:00
|
|
|
spin_unlock_irqrestore(&host->lock, flags);
|
|
|
|
|
2014-04-25 19:55:46 +08:00
|
|
|
synchronize_hardirq(host->irq);
|
2011-10-03 20:33:34 +08:00
|
|
|
|
|
|
|
spin_lock_irqsave(&host->lock, flags);
|
|
|
|
host->runtime_suspended = true;
|
|
|
|
spin_unlock_irqrestore(&host->lock, flags);
|
|
|
|
|
2014-06-04 21:24:29 +08:00
|
|
|
return 0;
|
2011-10-03 20:33:34 +08:00
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
|
|
|
|
|
2019-07-25 11:14:22 +08:00
|
|
|
int sdhci_runtime_resume_host(struct sdhci_host *host, int soft_reset)
|
2011-10-03 20:33:34 +08:00
|
|
|
{
|
2016-06-29 21:24:14 +08:00
|
|
|
struct mmc_host *mmc = host->mmc;
|
2011-10-03 20:33:34 +08:00
|
|
|
unsigned long flags;
|
2014-06-04 21:24:29 +08:00
|
|
|
int host_flags = host->flags;
|
2011-10-03 20:33:34 +08:00
|
|
|
|
|
|
|
if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
|
|
|
|
if (host->ops->enable_dma)
|
|
|
|
host->ops->enable_dma(host);
|
|
|
|
}
|
|
|
|
|
2019-07-25 11:14:22 +08:00
|
|
|
sdhci_init(host, soft_reset);
|
2011-10-03 20:33:34 +08:00
|
|
|
|
2017-08-04 03:28:40 +08:00
|
|
|
if (mmc->ios.power_mode != MMC_POWER_UNDEFINED &&
|
|
|
|
mmc->ios.power_mode != MMC_POWER_OFF) {
|
2016-12-19 21:33:11 +08:00
|
|
|
/* Force clock and power re-program */
|
|
|
|
host->pwr = 0;
|
|
|
|
host->clock = 0;
|
|
|
|
mmc->ops->start_signal_voltage_switch(mmc, &mmc->ios);
|
|
|
|
mmc->ops->set_ios(mmc, &mmc->ios);
|
2011-10-03 20:33:34 +08:00
|
|
|
|
2016-12-19 21:33:11 +08:00
|
|
|
if ((host_flags & SDHCI_PV_ENABLED) &&
|
|
|
|
!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
|
|
|
|
spin_lock_irqsave(&host->lock, flags);
|
|
|
|
sdhci_enable_preset_value(host, true);
|
|
|
|
spin_unlock_irqrestore(&host->lock, flags);
|
|
|
|
}
|
2011-10-03 20:33:34 +08:00
|
|
|
|
2016-12-19 21:33:11 +08:00
|
|
|
if ((mmc->caps2 & MMC_CAP2_HS400_ES) &&
|
|
|
|
mmc->ops->hs400_enhanced_strobe)
|
|
|
|
mmc->ops->hs400_enhanced_strobe(mmc, &mmc->ios);
|
|
|
|
}
|
2016-11-02 21:49:11 +08:00
|
|
|
|
2011-10-03 20:33:34 +08:00
|
|
|
spin_lock_irqsave(&host->lock, flags);
|
|
|
|
|
|
|
|
host->runtime_suspended = false;
|
|
|
|
|
|
|
|
/* Enable SDIO IRQ */
|
2019-09-08 18:12:36 +08:00
|
|
|
if (sdio_irq_claimed(mmc))
|
2011-10-03 20:33:34 +08:00
|
|
|
sdhci_enable_sdio_irq_nolock(host, true);
|
|
|
|
|
|
|
|
/* Enable Card Detection */
|
|
|
|
sdhci_enable_card_detection(host);
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&host->lock, flags);
|
|
|
|
|
2014-06-04 21:24:29 +08:00
|
|
|
return 0;
|
2011-10-03 20:33:34 +08:00
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
|
|
|
|
|
2014-12-05 10:05:33 +08:00
|
|
|
#endif /* CONFIG_PM */
|
2011-10-03 20:33:34 +08:00
|
|
|
|
2017-03-21 01:50:47 +08:00
|
|
|
/*****************************************************************************\
|
|
|
|
* *
|
|
|
|
* Command Queue Engine (CQE) helpers *
|
|
|
|
* *
|
|
|
|
\*****************************************************************************/
|
|
|
|
|
|
|
|
void sdhci_cqe_enable(struct mmc_host *mmc)
|
|
|
|
{
|
|
|
|
struct sdhci_host *host = mmc_priv(mmc);
|
|
|
|
unsigned long flags;
|
|
|
|
u8 ctrl;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&host->lock, flags);
|
|
|
|
|
|
|
|
ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
|
|
|
|
ctrl &= ~SDHCI_CTRL_DMA_MASK;
|
2019-01-24 03:30:53 +08:00
|
|
|
/*
|
|
|
|
* Host from V4.10 supports ADMA3 DMA type.
|
|
|
|
* ADMA3 performs integrated descriptor which is more suitable
|
|
|
|
* for cmd queuing to fetch both command and transfer descriptors.
|
|
|
|
*/
|
|
|
|
if (host->v4_mode && (host->caps1 & SDHCI_CAN_DO_ADMA3))
|
|
|
|
ctrl |= SDHCI_CTRL_ADMA3;
|
|
|
|
else if (host->flags & SDHCI_USE_64_BIT_DMA)
|
2017-03-21 01:50:47 +08:00
|
|
|
ctrl |= SDHCI_CTRL_ADMA64;
|
|
|
|
else
|
|
|
|
ctrl |= SDHCI_CTRL_ADMA32;
|
|
|
|
sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
|
|
|
|
|
2017-08-03 20:46:13 +08:00
|
|
|
sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, 512),
|
2017-03-21 01:50:47 +08:00
|
|
|
SDHCI_BLOCK_SIZE);
|
|
|
|
|
|
|
|
/* Set maximum timeout */
|
2019-01-07 18:11:36 +08:00
|
|
|
sdhci_set_timeout(host, NULL);
|
2017-03-21 01:50:47 +08:00
|
|
|
|
|
|
|
host->ier = host->cqe_ier;
|
|
|
|
|
|
|
|
sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
|
|
|
|
sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
|
|
|
|
|
|
|
|
host->cqe_on = true;
|
|
|
|
|
|
|
|
pr_debug("%s: sdhci: CQE on, IRQ mask %#x, IRQ status %#x\n",
|
|
|
|
mmc_hostname(mmc), host->ier,
|
|
|
|
sdhci_readl(host, SDHCI_INT_STATUS));
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&host->lock, flags);
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(sdhci_cqe_enable);
|
|
|
|
|
|
|
|
void sdhci_cqe_disable(struct mmc_host *mmc, bool recovery)
|
|
|
|
{
|
|
|
|
struct sdhci_host *host = mmc_priv(mmc);
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&host->lock, flags);
|
|
|
|
|
|
|
|
sdhci_set_default_irqs(host);
|
|
|
|
|
|
|
|
host->cqe_on = false;
|
|
|
|
|
|
|
|
if (recovery) {
|
|
|
|
sdhci_do_reset(host, SDHCI_RESET_CMD);
|
|
|
|
sdhci_do_reset(host, SDHCI_RESET_DATA);
|
|
|
|
}
|
|
|
|
|
|
|
|
pr_debug("%s: sdhci: CQE off, IRQ mask %#x, IRQ status %#x\n",
|
|
|
|
mmc_hostname(mmc), host->ier,
|
|
|
|
sdhci_readl(host, SDHCI_INT_STATUS));
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&host->lock, flags);
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(sdhci_cqe_disable);
|
|
|
|
|
|
|
|
bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error,
|
|
|
|
int *data_error)
|
|
|
|
{
|
|
|
|
u32 mask;
|
|
|
|
|
|
|
|
if (!host->cqe_on)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
if (intmask & (SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC))
|
|
|
|
*cmd_error = -EILSEQ;
|
|
|
|
else if (intmask & SDHCI_INT_TIMEOUT)
|
|
|
|
*cmd_error = -ETIMEDOUT;
|
|
|
|
else
|
|
|
|
*cmd_error = 0;
|
|
|
|
|
|
|
|
if (intmask & (SDHCI_INT_DATA_END_BIT | SDHCI_INT_DATA_CRC))
|
|
|
|
*data_error = -EILSEQ;
|
|
|
|
else if (intmask & SDHCI_INT_DATA_TIMEOUT)
|
|
|
|
*data_error = -ETIMEDOUT;
|
|
|
|
else if (intmask & SDHCI_INT_ADMA_ERROR)
|
|
|
|
*data_error = -EIO;
|
|
|
|
else
|
|
|
|
*data_error = 0;
|
|
|
|
|
|
|
|
/* Clear selected interrupts. */
|
|
|
|
mask = intmask & host->cqe_ier;
|
|
|
|
sdhci_writel(host, mask, SDHCI_INT_STATUS);
|
|
|
|
|
|
|
|
if (intmask & SDHCI_INT_BUS_POWER)
|
|
|
|
pr_err("%s: Card is consuming too much power!\n",
|
|
|
|
mmc_hostname(host->mmc));
|
|
|
|
|
|
|
|
intmask &= ~(host->cqe_ier | SDHCI_INT_ERROR);
|
|
|
|
if (intmask) {
|
|
|
|
sdhci_writel(host, intmask, SDHCI_INT_STATUS);
|
|
|
|
pr_err("%s: CQE: Unexpected interrupt 0x%08x.\n",
|
|
|
|
mmc_hostname(host->mmc), intmask);
|
|
|
|
sdhci_dumpregs(host);
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(sdhci_cqe_irq);
|
|
|
|
|
2006-03-24 19:18:17 +08:00
|
|
|
/*****************************************************************************\
|
|
|
|
* *
|
2008-03-19 00:35:49 +08:00
|
|
|
* Device allocation/registration *
|
2006-03-24 19:18:17 +08:00
|
|
|
* *
|
|
|
|
\*****************************************************************************/
|
|
|
|
|
2008-03-19 00:35:49 +08:00
|
|
|
struct sdhci_host *sdhci_alloc_host(struct device *dev,
|
|
|
|
size_t priv_size)
|
2006-03-24 19:18:17 +08:00
|
|
|
{
|
|
|
|
struct mmc_host *mmc;
|
|
|
|
struct sdhci_host *host;
|
|
|
|
|
2008-03-19 00:35:49 +08:00
|
|
|
WARN_ON(dev == NULL);
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2008-03-19 00:35:49 +08:00
|
|
|
mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
|
2006-03-24 19:18:17 +08:00
|
|
|
if (!mmc)
|
2008-03-19 00:35:49 +08:00
|
|
|
return ERR_PTR(-ENOMEM);
|
2006-03-24 19:18:17 +08:00
|
|
|
|
|
|
|
host = mmc_priv(mmc);
|
|
|
|
host->mmc = mmc;
|
2016-02-09 22:12:35 +08:00
|
|
|
host->mmc_host_ops = sdhci_ops;
|
|
|
|
mmc->ops = &host->mmc_host_ops;
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2016-06-29 21:24:16 +08:00
|
|
|
host->flags = SDHCI_SIGNALING_330;
|
|
|
|
|
2017-03-21 01:50:47 +08:00
|
|
|
host->cqe_ier = SDHCI_CQE_INT_MASK;
|
|
|
|
host->cqe_err_ier = SDHCI_CQE_INT_ERR_MASK;
|
|
|
|
|
2017-04-20 16:14:43 +08:00
|
|
|
host->tuning_delay = -1;
|
2019-03-24 12:45:19 +08:00
|
|
|
host->tuning_loop_count = MAX_TUNING_LOOP;
|
2017-04-20 16:14:43 +08:00
|
|
|
|
2017-08-03 20:46:13 +08:00
|
|
|
host->sdma_boundary = SDHCI_DEFAULT_BOUNDARY_ARG;
|
|
|
|
|
2018-08-28 17:46:35 +08:00
|
|
|
/*
|
|
|
|
* The DMA table descriptor count is calculated as the maximum
|
|
|
|
* number of segments times 2, to allow for an alignment
|
|
|
|
* descriptor for each segment, plus 1 for a nop end descriptor.
|
|
|
|
*/
|
|
|
|
host->adma_table_cnt = SDHCI_MAX_SEGS * 2 + 1;
|
|
|
|
|
2008-03-19 00:35:49 +08:00
|
|
|
return host;
|
|
|
|
}
|
2006-10-04 17:15:40 +08:00
|
|
|
|
2008-03-19 00:35:49 +08:00
|
|
|
EXPORT_SYMBOL_GPL(sdhci_alloc_host);
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2016-03-07 10:07:55 +08:00
|
|
|
static int sdhci_set_dma_mask(struct sdhci_host *host)
|
|
|
|
{
|
|
|
|
struct mmc_host *mmc = host->mmc;
|
|
|
|
struct device *dev = mmc_dev(mmc);
|
|
|
|
int ret = -EINVAL;
|
|
|
|
|
|
|
|
if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA)
|
|
|
|
host->flags &= ~SDHCI_USE_64_BIT_DMA;
|
|
|
|
|
|
|
|
/* Try 64-bit mask if hardware is capable of it */
|
|
|
|
if (host->flags & SDHCI_USE_64_BIT_DMA) {
|
|
|
|
ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
|
|
|
|
if (ret) {
|
|
|
|
pr_warn("%s: Failed to set 64-bit DMA mask.\n",
|
|
|
|
mmc_hostname(mmc));
|
|
|
|
host->flags &= ~SDHCI_USE_64_BIT_DMA;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* 32-bit mask as default & fallback */
|
|
|
|
if (ret) {
|
|
|
|
ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
|
|
|
|
if (ret)
|
|
|
|
pr_warn("%s: Failed to set 32-bit DMA mask.\n",
|
|
|
|
mmc_hostname(mmc));
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2019-08-29 18:49:27 +08:00
|
|
|
void __sdhci_read_caps(struct sdhci_host *host, const u16 *ver,
|
|
|
|
const u32 *caps, const u32 *caps1)
|
2016-06-29 21:24:18 +08:00
|
|
|
{
|
|
|
|
u16 v;
|
2016-11-02 23:26:16 +08:00
|
|
|
u64 dt_caps_mask = 0;
|
|
|
|
u64 dt_caps = 0;
|
2016-06-29 21:24:18 +08:00
|
|
|
|
|
|
|
if (host->read_caps)
|
|
|
|
return;
|
|
|
|
|
|
|
|
host->read_caps = true;
|
|
|
|
|
|
|
|
if (debug_quirks)
|
|
|
|
host->quirks = debug_quirks;
|
|
|
|
|
|
|
|
if (debug_quirks2)
|
|
|
|
host->quirks2 = debug_quirks2;
|
|
|
|
|
|
|
|
sdhci_do_reset(host, SDHCI_RESET_ALL);
|
|
|
|
|
2018-08-30 16:21:38 +08:00
|
|
|
if (host->v4_mode)
|
|
|
|
sdhci_do_enable_v4_mode(host);
|
|
|
|
|
2016-11-02 23:26:16 +08:00
|
|
|
of_property_read_u64(mmc_dev(host->mmc)->of_node,
|
|
|
|
"sdhci-caps-mask", &dt_caps_mask);
|
|
|
|
of_property_read_u64(mmc_dev(host->mmc)->of_node,
|
|
|
|
"sdhci-caps", &dt_caps);
|
|
|
|
|
2016-06-29 21:24:18 +08:00
|
|
|
v = ver ? *ver : sdhci_readw(host, SDHCI_HOST_VERSION);
|
|
|
|
host->version = (v & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
|
|
|
|
|
|
|
|
if (host->quirks & SDHCI_QUIRK_MISSING_CAPS)
|
|
|
|
return;
|
|
|
|
|
2016-11-02 23:26:16 +08:00
|
|
|
if (caps) {
|
|
|
|
host->caps = *caps;
|
|
|
|
} else {
|
|
|
|
host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
|
|
|
|
host->caps &= ~lower_32_bits(dt_caps_mask);
|
|
|
|
host->caps |= lower_32_bits(dt_caps);
|
|
|
|
}
|
2016-06-29 21:24:18 +08:00
|
|
|
|
|
|
|
if (host->version < SDHCI_SPEC_300)
|
|
|
|
return;
|
|
|
|
|
2016-11-02 23:26:16 +08:00
|
|
|
if (caps1) {
|
|
|
|
host->caps1 = *caps1;
|
|
|
|
} else {
|
|
|
|
host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
|
|
|
|
host->caps1 &= ~upper_32_bits(dt_caps_mask);
|
|
|
|
host->caps1 |= upper_32_bits(dt_caps);
|
|
|
|
}
|
2016-06-29 21:24:18 +08:00
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(__sdhci_read_caps);
|
|
|
|
|
2018-10-25 10:12:36 +08:00
|
|
|
static void sdhci_allocate_bounce_buffer(struct sdhci_host *host)
|
2018-01-29 07:44:53 +08:00
|
|
|
{
|
|
|
|
struct mmc_host *mmc = host->mmc;
|
|
|
|
unsigned int max_blocks;
|
|
|
|
unsigned int bounce_size;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Cap the bounce buffer at 64KB. Using a bigger bounce buffer
|
|
|
|
* has diminishing returns, this is probably because SD/MMC
|
|
|
|
* cards are usually optimized to handle this size of requests.
|
|
|
|
*/
|
|
|
|
bounce_size = SZ_64K;
|
|
|
|
/*
|
|
|
|
* Adjust downwards to maximum request size if this is less
|
|
|
|
* than our segment size, else hammer down the maximum
|
|
|
|
* request size to the maximum buffer size.
|
|
|
|
*/
|
|
|
|
if (mmc->max_req_size < bounce_size)
|
|
|
|
bounce_size = mmc->max_req_size;
|
|
|
|
max_blocks = bounce_size / 512;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* When we just support one segment, we can get significant
|
|
|
|
* speedups by the help of a bounce buffer to group scattered
|
|
|
|
* reads/writes together.
|
|
|
|
*/
|
|
|
|
host->bounce_buffer = devm_kmalloc(mmc->parent,
|
|
|
|
bounce_size,
|
|
|
|
GFP_KERNEL);
|
|
|
|
if (!host->bounce_buffer) {
|
|
|
|
pr_err("%s: failed to allocate %u bytes for bounce buffer, falling back to single segments\n",
|
|
|
|
mmc_hostname(mmc),
|
|
|
|
bounce_size);
|
|
|
|
/*
|
|
|
|
* Exiting with zero here makes sure we proceed with
|
|
|
|
* mmc->max_segs == 1.
|
|
|
|
*/
|
2018-10-25 10:12:36 +08:00
|
|
|
return;
|
2018-01-29 07:44:53 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
host->bounce_addr = dma_map_single(mmc->parent,
|
|
|
|
host->bounce_buffer,
|
|
|
|
bounce_size,
|
|
|
|
DMA_BIDIRECTIONAL);
|
|
|
|
ret = dma_mapping_error(mmc->parent, host->bounce_addr);
|
|
|
|
if (ret)
|
|
|
|
/* Again fall back to max_segs == 1 */
|
2018-10-25 10:12:36 +08:00
|
|
|
return;
|
2018-01-29 07:44:53 +08:00
|
|
|
host->bounce_buffer_size = bounce_size;
|
|
|
|
|
|
|
|
/* Lie about this since we're bouncing */
|
|
|
|
mmc->max_segs = max_blocks;
|
|
|
|
mmc->max_seg_size = bounce_size;
|
|
|
|
mmc->max_req_size = bounce_size;
|
|
|
|
|
|
|
|
pr_info("%s bounce up to %u segments into one, max segment size %u bytes\n",
|
|
|
|
mmc_hostname(mmc), max_blocks, bounce_size);
|
|
|
|
}
|
|
|
|
|
2018-08-30 16:21:40 +08:00
|
|
|
static inline bool sdhci_can_64bit_dma(struct sdhci_host *host)
|
|
|
|
{
|
|
|
|
/*
|
|
|
|
* According to SD Host Controller spec v4.10, bit[27] added from
|
|
|
|
* version 4.10 in Capabilities Register is used as 64-bit System
|
|
|
|
* Address support for V4 mode.
|
|
|
|
*/
|
|
|
|
if (host->version >= SDHCI_SPEC_410 && host->v4_mode)
|
|
|
|
return host->caps & SDHCI_CAN_64BIT_V4;
|
|
|
|
|
|
|
|
return host->caps & SDHCI_CAN_64BIT;
|
|
|
|
}
|
|
|
|
|
2016-06-29 21:24:15 +08:00
|
|
|
int sdhci_setup_host(struct sdhci_host *host)
|
2008-03-19 00:35:49 +08:00
|
|
|
{
|
|
|
|
struct mmc_host *mmc;
|
mmc: sd: add support for signal voltage switch procedure
Host Controller v3.00 adds another Capabilities register. Apart
from other things, this new register indicates whether the Host
Controller supports SDR50, SDR104, and DDR50 UHS-I modes. The spec
doesn't mention about explicit support for SDR12 and SDR25 UHS-I
modes, so the Host Controller v3.00 should support them by default.
Also if the controller supports SDR104 mode, it will also support
SDR50 mode as well. So depending on the host support, we set the
corresponding MMC_CAP_* flags. One more new register. Host Control2
is added in v3.00, which is used during Signal Voltage Switch
procedure described below.
Since as per v3.00 spec, UHS-I supported hosts should set S18R
to 1, we set S18R (bit 24) of OCR before sending ACMD41. We also
need to set XPC (bit 28) of OCR in case the host can supply >150mA.
This support is indicated by the Maximum Current Capabilities
register of the Host Controller.
If the response of ACMD41 has both CCS and S18A set, we start the
signal voltage switch procedure, which if successfull, will switch
the card from 3.3V signalling to 1.8V signalling. Signal voltage
switch procedure adds support for a new command CMD11 in the
Physical Layer Spec v3.01. As part of this procedure, we need to
set 1.8V Signalling Enable (bit 3) of Host Control2 register, which
if remains set after 5ms, means the switch to 1.8V signalling is
successfull. Otherwise, we clear bit 24 of OCR and retry the
initialization sequence. When we remove the card, and insert the
same or another card, we need to make sure that we start with 3.3V
signalling voltage. So we call mmc_set_signal_voltage() with
MMC_SIGNAL_VOLTAGE_330 set so that we are back to 3.3V signalling
voltage before we actually start initializing the card.
Tested by Zhangfei Gao with a Toshiba uhs card and general hs card,
on mmp2 in SDMA mode.
Signed-off-by: Arindam Nath <arindam.nath@amd.com>
Reviewed-by: Philip Rakity <prakity@marvell.com>
Tested-by: Philip Rakity <prakity@marvell.com>
Acked-by: Zhangfei Gao <zhangfei.gao@marvell.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
2011-05-05 14:48:57 +08:00
|
|
|
u32 max_current_caps;
|
|
|
|
unsigned int ocr_avail;
|
2014-09-24 15:27:32 +08:00
|
|
|
unsigned int override_timeout_clk;
|
2015-07-22 20:53:07 +08:00
|
|
|
u32 max_clk;
|
2008-03-19 00:35:49 +08:00
|
|
|
int ret;
|
2020-06-23 21:34:46 +08:00
|
|
|
bool enable_vqmmc = false;
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2008-03-19 00:35:49 +08:00
|
|
|
WARN_ON(host == NULL);
|
|
|
|
if (host == NULL)
|
|
|
|
return -EINVAL;
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2008-03-19 00:35:49 +08:00
|
|
|
mmc = host->mmc;
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2016-07-12 21:53:36 +08:00
|
|
|
/*
|
|
|
|
* If there are external regulators, get them. Note this must be done
|
|
|
|
* early before resetting the host and reading the capabilities so that
|
|
|
|
* the host can take the appropriate action if regulators are not
|
|
|
|
* available.
|
|
|
|
*/
|
2020-06-23 21:34:46 +08:00
|
|
|
if (!mmc->supply.vqmmc) {
|
|
|
|
ret = mmc_regulator_get_supply(mmc);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
enable_vqmmc = true;
|
|
|
|
}
|
2016-07-12 21:53:36 +08:00
|
|
|
|
2017-07-19 15:55:49 +08:00
|
|
|
DBG("Version: 0x%08x | Present: 0x%08x\n",
|
|
|
|
sdhci_readw(host, SDHCI_HOST_VERSION),
|
|
|
|
sdhci_readl(host, SDHCI_PRESENT_STATE));
|
|
|
|
DBG("Caps: 0x%08x | Caps_1: 0x%08x\n",
|
|
|
|
sdhci_readl(host, SDHCI_CAPABILITIES),
|
|
|
|
sdhci_readl(host, SDHCI_CAPABILITIES_1));
|
|
|
|
|
2016-06-29 21:24:18 +08:00
|
|
|
sdhci_read_caps(host);
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2014-09-24 15:27:32 +08:00
|
|
|
override_timeout_clk = host->timeout_clk;
|
|
|
|
|
2018-08-30 16:21:37 +08:00
|
|
|
if (host->version > SDHCI_SPEC_420) {
|
2015-11-18 17:47:02 +08:00
|
|
|
pr_err("%s: Unknown controller version (%d). You may experience problems.\n",
|
|
|
|
mmc_hostname(mmc), host->version);
|
2006-06-30 17:22:29 +08:00
|
|
|
}
|
|
|
|
|
2008-03-19 00:35:49 +08:00
|
|
|
if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
|
2009-09-23 07:45:30 +08:00
|
|
|
host->flags |= SDHCI_USE_SDMA;
|
2016-06-29 21:24:17 +08:00
|
|
|
else if (!(host->caps & SDHCI_CAN_DO_SDMA))
|
2009-09-23 07:45:30 +08:00
|
|
|
DBG("Controller doesn't have SDMA capability\n");
|
2006-06-30 17:22:31 +08:00
|
|
|
else
|
2009-09-23 07:45:30 +08:00
|
|
|
host->flags |= SDHCI_USE_SDMA;
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2008-03-19 00:35:49 +08:00
|
|
|
if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
|
2009-09-23 07:45:30 +08:00
|
|
|
(host->flags & SDHCI_USE_SDMA)) {
|
2007-11-02 22:22:30 +08:00
|
|
|
DBG("Disabling DMA as it is marked broken\n");
|
2009-09-23 07:45:30 +08:00
|
|
|
host->flags &= ~SDHCI_USE_SDMA;
|
2007-09-30 18:44:18 +08:00
|
|
|
}
|
|
|
|
|
mmc: sd: add support for signal voltage switch procedure
Host Controller v3.00 adds another Capabilities register. Apart
from other things, this new register indicates whether the Host
Controller supports SDR50, SDR104, and DDR50 UHS-I modes. The spec
doesn't mention about explicit support for SDR12 and SDR25 UHS-I
modes, so the Host Controller v3.00 should support them by default.
Also if the controller supports SDR104 mode, it will also support
SDR50 mode as well. So depending on the host support, we set the
corresponding MMC_CAP_* flags. One more new register. Host Control2
is added in v3.00, which is used during Signal Voltage Switch
procedure described below.
Since as per v3.00 spec, UHS-I supported hosts should set S18R
to 1, we set S18R (bit 24) of OCR before sending ACMD41. We also
need to set XPC (bit 28) of OCR in case the host can supply >150mA.
This support is indicated by the Maximum Current Capabilities
register of the Host Controller.
If the response of ACMD41 has both CCS and S18A set, we start the
signal voltage switch procedure, which if successfull, will switch
the card from 3.3V signalling to 1.8V signalling. Signal voltage
switch procedure adds support for a new command CMD11 in the
Physical Layer Spec v3.01. As part of this procedure, we need to
set 1.8V Signalling Enable (bit 3) of Host Control2 register, which
if remains set after 5ms, means the switch to 1.8V signalling is
successfull. Otherwise, we clear bit 24 of OCR and retry the
initialization sequence. When we remove the card, and insert the
same or another card, we need to make sure that we start with 3.3V
signalling voltage. So we call mmc_set_signal_voltage() with
MMC_SIGNAL_VOLTAGE_330 set so that we are back to 3.3V signalling
voltage before we actually start initializing the card.
Tested by Zhangfei Gao with a Toshiba uhs card and general hs card,
on mmp2 in SDMA mode.
Signed-off-by: Arindam Nath <arindam.nath@amd.com>
Reviewed-by: Philip Rakity <prakity@marvell.com>
Tested-by: Philip Rakity <prakity@marvell.com>
Acked-by: Zhangfei Gao <zhangfei.gao@marvell.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
2011-05-05 14:48:57 +08:00
|
|
|
if ((host->version >= SDHCI_SPEC_200) &&
|
2016-06-29 21:24:17 +08:00
|
|
|
(host->caps & SDHCI_CAN_DO_ADMA2))
|
2009-09-23 07:45:30 +08:00
|
|
|
host->flags |= SDHCI_USE_ADMA;
|
2008-06-29 00:28:51 +08:00
|
|
|
|
|
|
|
if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
|
|
|
|
(host->flags & SDHCI_USE_ADMA)) {
|
|
|
|
DBG("Disabling ADMA as it is marked broken\n");
|
|
|
|
host->flags &= ~SDHCI_USE_ADMA;
|
|
|
|
}
|
|
|
|
|
2018-08-30 16:21:40 +08:00
|
|
|
if (sdhci_can_64bit_dma(host))
|
2014-11-04 18:42:46 +08:00
|
|
|
host->flags |= SDHCI_USE_64_BIT_DMA;
|
|
|
|
|
2020-01-16 18:51:47 +08:00
|
|
|
if (host->use_external_dma) {
|
|
|
|
ret = sdhci_external_dma_init(host);
|
|
|
|
if (ret == -EPROBE_DEFER)
|
|
|
|
goto unreg;
|
|
|
|
/*
|
|
|
|
* Fall back to use the DMA/PIO integrated in standard SDHCI
|
|
|
|
* instead of external DMA devices.
|
|
|
|
*/
|
|
|
|
else if (ret)
|
|
|
|
sdhci_switch_external_dma(host, false);
|
|
|
|
/* Disable internal DMA sources */
|
|
|
|
else
|
|
|
|
host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
|
|
|
|
}
|
|
|
|
|
2009-09-23 07:45:30 +08:00
|
|
|
if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
|
2019-09-23 18:08:09 +08:00
|
|
|
if (host->ops->set_dma_mask)
|
|
|
|
ret = host->ops->set_dma_mask(host);
|
|
|
|
else
|
|
|
|
ret = sdhci_set_dma_mask(host);
|
2016-03-07 10:07:55 +08:00
|
|
|
|
|
|
|
if (!ret && host->ops->enable_dma)
|
|
|
|
ret = host->ops->enable_dma(host);
|
|
|
|
|
|
|
|
if (ret) {
|
|
|
|
pr_warn("%s: No suitable DMA available - falling back to PIO\n",
|
|
|
|
mmc_hostname(mmc));
|
|
|
|
host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
|
|
|
|
|
|
|
|
ret = 0;
|
2006-03-24 19:18:17 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-08-30 16:21:39 +08:00
|
|
|
/* SDMA does not support 64-bit DMA if v4 mode not set */
|
|
|
|
if ((host->flags & SDHCI_USE_64_BIT_DMA) && !host->v4_mode)
|
2014-11-04 18:42:46 +08:00
|
|
|
host->flags &= ~SDHCI_USE_SDMA;
|
|
|
|
|
2008-06-29 00:28:51 +08:00
|
|
|
if (host->flags & SDHCI_USE_ADMA) {
|
2016-01-26 21:39:55 +08:00
|
|
|
dma_addr_t dma;
|
|
|
|
void *buf;
|
|
|
|
|
2020-01-20 22:38:38 +08:00
|
|
|
if (!(host->flags & SDHCI_USE_64_BIT_DMA))
|
|
|
|
host->alloc_desc_sz = SDHCI_ADMA2_32_DESC_SZ;
|
|
|
|
else if (!host->alloc_desc_sz)
|
|
|
|
host->alloc_desc_sz = SDHCI_ADMA2_64_DESC_SZ(host);
|
|
|
|
|
|
|
|
host->desc_sz = host->alloc_desc_sz;
|
|
|
|
host->adma_table_sz = host->adma_table_cnt * host->desc_sz;
|
2016-01-26 21:39:55 +08:00
|
|
|
|
2015-11-26 20:00:49 +08:00
|
|
|
host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN;
|
2018-08-30 16:21:40 +08:00
|
|
|
/*
|
|
|
|
* Use zalloc to zero the reserved high 32-bits of 128-bit
|
|
|
|
* descriptors so that they never need to be written.
|
|
|
|
*/
|
cross-tree: phase out dma_zalloc_coherent()
We already need to zero out memory for dma_alloc_coherent(), as such
using dma_zalloc_coherent() is superflous. Phase it out.
This change was generated with the following Coccinelle SmPL patch:
@ replace_dma_zalloc_coherent @
expression dev, size, data, handle, flags;
@@
-dma_zalloc_coherent(dev, size, handle, flags)
+dma_alloc_coherent(dev, size, handle, flags)
Suggested-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Luis Chamberlain <mcgrof@kernel.org>
[hch: re-ran the script on the latest tree]
Signed-off-by: Christoph Hellwig <hch@lst.de>
2019-01-04 16:23:09 +08:00
|
|
|
buf = dma_alloc_coherent(mmc_dev(mmc),
|
|
|
|
host->align_buffer_sz + host->adma_table_sz,
|
|
|
|
&dma, GFP_KERNEL);
|
2016-01-26 21:39:55 +08:00
|
|
|
if (!buf) {
|
2014-09-13 05:56:56 +08:00
|
|
|
pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
|
2008-06-29 00:28:51 +08:00
|
|
|
mmc_hostname(mmc));
|
|
|
|
host->flags &= ~SDHCI_USE_ADMA;
|
2016-01-26 21:39:55 +08:00
|
|
|
} else if ((dma + host->align_buffer_sz) &
|
|
|
|
(SDHCI_ADMA2_DESC_ALIGN - 1)) {
|
2014-09-13 05:56:56 +08:00
|
|
|
pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
|
|
|
|
mmc_hostname(mmc));
|
2014-04-25 19:58:34 +08:00
|
|
|
host->flags &= ~SDHCI_USE_ADMA;
|
2016-01-26 21:39:55 +08:00
|
|
|
dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
|
|
|
|
host->adma_table_sz, buf, dma);
|
|
|
|
} else {
|
|
|
|
host->align_buffer = buf;
|
|
|
|
host->align_addr = dma;
|
2016-01-26 21:39:50 +08:00
|
|
|
|
2016-01-26 21:39:55 +08:00
|
|
|
host->adma_table = buf + host->align_buffer_sz;
|
|
|
|
host->adma_addr = dma + host->align_buffer_sz;
|
|
|
|
}
|
2008-06-29 00:28:51 +08:00
|
|
|
}
|
|
|
|
|
2008-07-21 06:32:11 +08:00
|
|
|
/*
|
|
|
|
* If we use DMA, then it's up to the caller to set the DMA
|
|
|
|
* mask, but PIO does not need the hw shim so we set a new
|
|
|
|
* mask here in that case.
|
|
|
|
*/
|
2009-09-23 07:45:30 +08:00
|
|
|
if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
|
2008-07-21 06:32:11 +08:00
|
|
|
host->dma_mask = DMA_BIT_MASK(64);
|
2014-07-04 04:27:42 +08:00
|
|
|
mmc_dev(mmc)->dma_mask = &host->dma_mask;
|
2008-07-21 06:32:11 +08:00
|
|
|
}
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2010-08-21 02:02:36 +08:00
|
|
|
if (host->version >= SDHCI_SPEC_300)
|
2020-04-08 15:21:05 +08:00
|
|
|
host->max_clk = FIELD_GET(SDHCI_CLOCK_V3_BASE_MASK, host->caps);
|
2010-08-21 02:02:36 +08:00
|
|
|
else
|
2020-04-08 15:21:05 +08:00
|
|
|
host->max_clk = FIELD_GET(SDHCI_CLOCK_BASE_MASK, host->caps);
|
2010-08-21 02:02:36 +08:00
|
|
|
|
2009-03-17 05:13:57 +08:00
|
|
|
host->max_clk *= 1000000;
|
2010-05-27 05:41:53 +08:00
|
|
|
if (host->max_clk == 0 || host->quirks &
|
|
|
|
SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
|
2009-03-17 05:13:57 +08:00
|
|
|
if (!host->ops->get_max_clock) {
|
2015-11-18 17:47:02 +08:00
|
|
|
pr_err("%s: Hardware doesn't specify base clock frequency.\n",
|
|
|
|
mmc_hostname(mmc));
|
2016-04-12 19:25:08 +08:00
|
|
|
ret = -ENODEV;
|
|
|
|
goto undma;
|
2009-03-17 05:13:57 +08:00
|
|
|
}
|
|
|
|
host->max_clk = host->ops->get_max_clock(host);
|
2006-06-30 17:22:21 +08:00
|
|
|
}
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2011-05-05 14:49:06 +08:00
|
|
|
/*
|
|
|
|
* In case of Host Controller v3.00, find out whether clock
|
|
|
|
* multiplier is supported.
|
|
|
|
*/
|
2020-04-08 15:21:05 +08:00
|
|
|
host->clk_mul = FIELD_GET(SDHCI_CLOCK_MUL_MASK, host->caps1);
|
2011-05-05 14:49:06 +08:00
|
|
|
|
|
|
|
/*
|
|
|
|
* In case the value in Clock Multiplier is 0, then programmable
|
|
|
|
* clock mode is not supported, otherwise the actual clock
|
|
|
|
* multiplier is one more than the value of Clock Multiplier
|
|
|
|
* in the Capabilities Register.
|
|
|
|
*/
|
|
|
|
if (host->clk_mul)
|
|
|
|
host->clk_mul += 1;
|
|
|
|
|
2006-03-24 19:18:17 +08:00
|
|
|
/*
|
|
|
|
* Set host parameters.
|
|
|
|
*/
|
2015-07-22 20:53:07 +08:00
|
|
|
max_clk = host->max_clk;
|
|
|
|
|
2010-08-11 09:01:56 +08:00
|
|
|
if (host->ops->get_min_clock)
|
2009-07-30 06:04:16 +08:00
|
|
|
mmc->f_min = host->ops->get_min_clock(host);
|
2011-05-05 14:49:06 +08:00
|
|
|
else if (host->version >= SDHCI_SPEC_300) {
|
2020-01-15 17:54:35 +08:00
|
|
|
if (host->clk_mul)
|
2015-07-22 20:53:07 +08:00
|
|
|
max_clk = host->max_clk * host->clk_mul;
|
2020-01-15 17:54:35 +08:00
|
|
|
/*
|
|
|
|
* Divided Clock Mode minimum clock rate is always less than
|
|
|
|
* Programmable Clock Mode minimum clock rate.
|
|
|
|
*/
|
|
|
|
mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
|
2011-05-05 14:49:06 +08:00
|
|
|
} else
|
2010-09-21 03:15:18 +08:00
|
|
|
mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
|
2010-11-20 05:48:39 +08:00
|
|
|
|
2016-04-12 19:25:07 +08:00
|
|
|
if (!mmc->f_max || mmc->f_max > max_clk)
|
2015-07-22 20:53:07 +08:00
|
|
|
mmc->f_max = max_clk;
|
|
|
|
|
2014-08-27 15:26:31 +08:00
|
|
|
if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
|
2020-04-08 15:21:05 +08:00
|
|
|
host->timeout_clk = FIELD_GET(SDHCI_TIMEOUT_CLK_MASK, host->caps);
|
2017-03-24 15:50:12 +08:00
|
|
|
|
|
|
|
if (host->caps & SDHCI_TIMEOUT_CLK_UNIT)
|
|
|
|
host->timeout_clk *= 1000;
|
|
|
|
|
2014-08-27 15:26:31 +08:00
|
|
|
if (host->timeout_clk == 0) {
|
2017-03-24 15:50:12 +08:00
|
|
|
if (!host->ops->get_timeout_clock) {
|
2014-08-27 15:26:31 +08:00
|
|
|
pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
|
|
|
|
mmc_hostname(mmc));
|
2016-04-12 19:25:08 +08:00
|
|
|
ret = -ENODEV;
|
|
|
|
goto undma;
|
2014-08-27 15:26:31 +08:00
|
|
|
}
|
2011-08-03 23:36:00 +08:00
|
|
|
|
2017-03-24 15:50:12 +08:00
|
|
|
host->timeout_clk =
|
|
|
|
DIV_ROUND_UP(host->ops->get_timeout_clock(host),
|
|
|
|
1000);
|
|
|
|
}
|
2011-08-03 23:36:00 +08:00
|
|
|
|
2016-03-07 19:33:55 +08:00
|
|
|
if (override_timeout_clk)
|
|
|
|
host->timeout_clk = override_timeout_clk;
|
|
|
|
|
2014-08-27 15:26:31 +08:00
|
|
|
mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
|
2014-08-27 15:26:27 +08:00
|
|
|
host->ops->get_max_timeout_count(host) : 1 << 27;
|
2014-08-27 15:26:31 +08:00
|
|
|
mmc->max_busy_timeout /= host->timeout_clk;
|
|
|
|
}
|
2011-06-28 22:16:03 +08:00
|
|
|
|
2018-04-27 19:47:15 +08:00
|
|
|
if (host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT &&
|
|
|
|
!host->ops->get_max_timeout_count)
|
|
|
|
mmc->max_busy_timeout = 0;
|
|
|
|
|
2020-05-08 19:29:02 +08:00
|
|
|
mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_CMD23;
|
2014-04-25 19:55:46 +08:00
|
|
|
mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
|
2011-05-24 04:06:37 +08:00
|
|
|
|
|
|
|
if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
|
|
|
|
host->flags |= SDHCI_AUTO_CMD12;
|
2009-06-18 04:14:08 +08:00
|
|
|
|
2018-08-30 16:21:43 +08:00
|
|
|
/*
|
|
|
|
* For v3 mode, Auto-CMD23 stuff only works in ADMA or PIO.
|
|
|
|
* For v4 mode, SDMA may use Auto-CMD23 as well.
|
|
|
|
*/
|
2011-05-25 22:42:50 +08:00
|
|
|
if ((host->version >= SDHCI_SPEC_300) &&
|
2011-05-24 04:06:39 +08:00
|
|
|
((host->flags & SDHCI_USE_ADMA) ||
|
2018-08-30 16:21:43 +08:00
|
|
|
!(host->flags & SDHCI_USE_SDMA) || host->v4_mode) &&
|
2015-02-10 08:06:28 +08:00
|
|
|
!(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
|
2011-05-24 04:06:39 +08:00
|
|
|
host->flags |= SDHCI_AUTO_CMD23;
|
2017-03-21 01:50:39 +08:00
|
|
|
DBG("Auto-CMD23 available\n");
|
2011-05-24 04:06:39 +08:00
|
|
|
} else {
|
2017-03-21 01:50:39 +08:00
|
|
|
DBG("Auto-CMD23 unavailable\n");
|
2011-05-24 04:06:39 +08:00
|
|
|
}
|
|
|
|
|
2010-11-20 05:48:39 +08:00
|
|
|
/*
|
|
|
|
* A controller may support 8-bit width, but the board itself
|
|
|
|
* might not have the pins brought out. Boards that support
|
|
|
|
* 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
|
|
|
|
* their platform code before calling sdhci_add_host(), and we
|
|
|
|
* won't assume 8-bit width for hosts without that CAP.
|
|
|
|
*/
|
2009-06-18 04:14:08 +08:00
|
|
|
if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
|
2010-11-20 05:48:39 +08:00
|
|
|
mmc->caps |= MMC_CAP_4_BIT_DATA;
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2012-10-25 13:47:19 +08:00
|
|
|
if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
|
|
|
|
mmc->caps &= ~MMC_CAP_CMD23;
|
|
|
|
|
2016-06-29 21:24:17 +08:00
|
|
|
if (host->caps & SDHCI_CAN_DO_HISPD)
|
2010-08-17 09:15:32 +08:00
|
|
|
mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
|
2007-02-18 19:07:47 +08:00
|
|
|
|
2010-09-27 16:42:20 +08:00
|
|
|
if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
|
2016-06-21 09:13:26 +08:00
|
|
|
mmc_card_is_removable(mmc) &&
|
remove lots of IS_ERR_VALUE abuses
Most users of IS_ERR_VALUE() in the kernel are wrong, as they
pass an 'int' into a function that takes an 'unsigned long'
argument. This happens to work because the type is sign-extended
on 64-bit architectures before it gets converted into an
unsigned type.
However, anything that passes an 'unsigned short' or 'unsigned int'
argument into IS_ERR_VALUE() is guaranteed to be broken, as are
8-bit integers and types that are wider than 'unsigned long'.
Andrzej Hajda has already fixed a lot of the worst abusers that
were causing actual bugs, but it would be nice to prevent any
users that are not passing 'unsigned long' arguments.
This patch changes all users of IS_ERR_VALUE() that I could find
on 32-bit ARM randconfig builds and x86 allmodconfig. For the
moment, this doesn't change the definition of IS_ERR_VALUE()
because there are probably still architecture specific users
elsewhere.
Almost all the warnings I got are for files that are better off
using 'if (err)' or 'if (err < 0)'.
The only legitimate user I could find that we get a warning for
is the (32-bit only) freescale fman driver, so I did not remove
the IS_ERR_VALUE() there but changed the type to 'unsigned long'.
For 9pfs, I just worked around one user whose calling conventions
are so obscure that I did not dare change the behavior.
I was using this definition for testing:
#define IS_ERR_VALUE(x) ((unsigned long*)NULL == (typeof (x)*)NULL && \
unlikely((unsigned long long)(x) >= (unsigned long long)(typeof(x))-MAX_ERRNO))
which ends up making all 16-bit or wider types work correctly with
the most plausible interpretation of what IS_ERR_VALUE() was supposed
to return according to its users, but also causes a compile-time
warning for any users that do not pass an 'unsigned long' argument.
I suggested this approach earlier this year, but back then we ended
up deciding to just fix the users that are obviously broken. After
the initial warning that caused me to get involved in the discussion
(fs/gfs2/dir.c) showed up again in the mainline kernel, Linus
asked me to send the whole thing again.
[ Updated the 9p parts as per Al Viro - Linus ]
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Cc: Andrzej Hajda <a.hajda@samsung.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Link: https://lkml.org/lkml/2016/1/7/363
Link: https://lkml.org/lkml/2016/5/27/486
Acked-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> # For nvmem part
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2016-05-28 05:23:25 +08:00
|
|
|
mmc_gpio_get_cd(host->mmc) < 0)
|
2009-03-17 05:13:52 +08:00
|
|
|
mmc->caps |= MMC_CAP_NEEDS_POLL;
|
|
|
|
|
2014-06-14 01:13:56 +08:00
|
|
|
if (!IS_ERR(mmc->supply.vqmmc)) {
|
2020-06-23 21:34:46 +08:00
|
|
|
if (enable_vqmmc) {
|
|
|
|
ret = regulator_enable(mmc->supply.vqmmc);
|
|
|
|
if (ret) {
|
|
|
|
pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
|
|
|
|
mmc_hostname(mmc), ret);
|
|
|
|
mmc->supply.vqmmc = ERR_PTR(-EINVAL);
|
|
|
|
}
|
|
|
|
host->sdhci_core_to_disable_vqmmc = !ret;
|
|
|
|
}
|
2018-07-05 20:18:19 +08:00
|
|
|
|
|
|
|
/* If vqmmc provides no 1.8V signalling, then there's no UHS */
|
2014-06-14 01:13:56 +08:00
|
|
|
if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
|
|
|
|
1950000))
|
2016-06-29 21:24:17 +08:00
|
|
|
host->caps1 &= ~(SDHCI_SUPPORT_SDR104 |
|
|
|
|
SDHCI_SUPPORT_SDR50 |
|
|
|
|
SDHCI_SUPPORT_DDR50);
|
2018-07-05 20:18:19 +08:00
|
|
|
|
|
|
|
/* In eMMC case vqmmc might be a fixed 1.8V regulator */
|
|
|
|
if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 2700000,
|
|
|
|
3600000))
|
|
|
|
host->flags &= ~SDHCI_SIGNALING_330;
|
2012-11-18 06:55:51 +08:00
|
|
|
}
|
2012-07-24 06:56:23 +08:00
|
|
|
|
2016-06-29 21:24:17 +08:00
|
|
|
if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) {
|
|
|
|
host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
|
|
|
|
SDHCI_SUPPORT_DDR50);
|
2018-04-27 19:47:14 +08:00
|
|
|
/*
|
|
|
|
* The SDHCI controller in a SoC might support HS200/HS400
|
|
|
|
* (indicated using mmc-hs200-1_8v/mmc-hs400-1_8v dt property),
|
|
|
|
* but if the board is modeled such that the IO lines are not
|
|
|
|
* connected to 1.8v then HS200/HS400 cannot be supported.
|
|
|
|
* Disable HS200/HS400 if the board does not have 1.8v connected
|
|
|
|
* to the IO lines. (Applicable for other modes in 1.8v)
|
|
|
|
*/
|
|
|
|
mmc->caps2 &= ~(MMC_CAP2_HSX00_1_8V | MMC_CAP2_HS400_ES);
|
|
|
|
mmc->caps &= ~(MMC_CAP_1_8V_DDR | MMC_CAP_UHS);
|
2016-06-29 21:24:17 +08:00
|
|
|
}
|
2012-11-26 02:01:19 +08:00
|
|
|
|
2012-03-17 03:54:17 +08:00
|
|
|
/* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
|
2016-06-29 21:24:17 +08:00
|
|
|
if (host->caps1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
|
|
|
|
SDHCI_SUPPORT_DDR50))
|
mmc: sd: add support for signal voltage switch procedure
Host Controller v3.00 adds another Capabilities register. Apart
from other things, this new register indicates whether the Host
Controller supports SDR50, SDR104, and DDR50 UHS-I modes. The spec
doesn't mention about explicit support for SDR12 and SDR25 UHS-I
modes, so the Host Controller v3.00 should support them by default.
Also if the controller supports SDR104 mode, it will also support
SDR50 mode as well. So depending on the host support, we set the
corresponding MMC_CAP_* flags. One more new register. Host Control2
is added in v3.00, which is used during Signal Voltage Switch
procedure described below.
Since as per v3.00 spec, UHS-I supported hosts should set S18R
to 1, we set S18R (bit 24) of OCR before sending ACMD41. We also
need to set XPC (bit 28) of OCR in case the host can supply >150mA.
This support is indicated by the Maximum Current Capabilities
register of the Host Controller.
If the response of ACMD41 has both CCS and S18A set, we start the
signal voltage switch procedure, which if successfull, will switch
the card from 3.3V signalling to 1.8V signalling. Signal voltage
switch procedure adds support for a new command CMD11 in the
Physical Layer Spec v3.01. As part of this procedure, we need to
set 1.8V Signalling Enable (bit 3) of Host Control2 register, which
if remains set after 5ms, means the switch to 1.8V signalling is
successfull. Otherwise, we clear bit 24 of OCR and retry the
initialization sequence. When we remove the card, and insert the
same or another card, we need to make sure that we start with 3.3V
signalling voltage. So we call mmc_set_signal_voltage() with
MMC_SIGNAL_VOLTAGE_330 set so that we are back to 3.3V signalling
voltage before we actually start initializing the card.
Tested by Zhangfei Gao with a Toshiba uhs card and general hs card,
on mmp2 in SDMA mode.
Signed-off-by: Arindam Nath <arindam.nath@amd.com>
Reviewed-by: Philip Rakity <prakity@marvell.com>
Tested-by: Philip Rakity <prakity@marvell.com>
Acked-by: Zhangfei Gao <zhangfei.gao@marvell.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
2011-05-05 14:48:57 +08:00
|
|
|
mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
|
|
|
|
|
|
|
|
/* SDR104 supports also implies SDR50 support */
|
2016-06-29 21:24:17 +08:00
|
|
|
if (host->caps1 & SDHCI_SUPPORT_SDR104) {
|
mmc: sd: add support for signal voltage switch procedure
Host Controller v3.00 adds another Capabilities register. Apart
from other things, this new register indicates whether the Host
Controller supports SDR50, SDR104, and DDR50 UHS-I modes. The spec
doesn't mention about explicit support for SDR12 and SDR25 UHS-I
modes, so the Host Controller v3.00 should support them by default.
Also if the controller supports SDR104 mode, it will also support
SDR50 mode as well. So depending on the host support, we set the
corresponding MMC_CAP_* flags. One more new register. Host Control2
is added in v3.00, which is used during Signal Voltage Switch
procedure described below.
Since as per v3.00 spec, UHS-I supported hosts should set S18R
to 1, we set S18R (bit 24) of OCR before sending ACMD41. We also
need to set XPC (bit 28) of OCR in case the host can supply >150mA.
This support is indicated by the Maximum Current Capabilities
register of the Host Controller.
If the response of ACMD41 has both CCS and S18A set, we start the
signal voltage switch procedure, which if successfull, will switch
the card from 3.3V signalling to 1.8V signalling. Signal voltage
switch procedure adds support for a new command CMD11 in the
Physical Layer Spec v3.01. As part of this procedure, we need to
set 1.8V Signalling Enable (bit 3) of Host Control2 register, which
if remains set after 5ms, means the switch to 1.8V signalling is
successfull. Otherwise, we clear bit 24 of OCR and retry the
initialization sequence. When we remove the card, and insert the
same or another card, we need to make sure that we start with 3.3V
signalling voltage. So we call mmc_set_signal_voltage() with
MMC_SIGNAL_VOLTAGE_330 set so that we are back to 3.3V signalling
voltage before we actually start initializing the card.
Tested by Zhangfei Gao with a Toshiba uhs card and general hs card,
on mmp2 in SDMA mode.
Signed-off-by: Arindam Nath <arindam.nath@amd.com>
Reviewed-by: Philip Rakity <prakity@marvell.com>
Tested-by: Philip Rakity <prakity@marvell.com>
Acked-by: Zhangfei Gao <zhangfei.gao@marvell.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
2011-05-05 14:48:57 +08:00
|
|
|
mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
|
2013-06-12 14:16:38 +08:00
|
|
|
/* SD3.0: SDR104 is supported so (for eMMC) the caps2
|
|
|
|
* field can be promoted to support HS200.
|
|
|
|
*/
|
2014-11-06 21:19:05 +08:00
|
|
|
if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
|
2013-10-30 01:58:26 +08:00
|
|
|
mmc->caps2 |= MMC_CAP2_HS200;
|
2016-06-29 21:24:17 +08:00
|
|
|
} else if (host->caps1 & SDHCI_SUPPORT_SDR50) {
|
mmc: sd: add support for signal voltage switch procedure
Host Controller v3.00 adds another Capabilities register. Apart
from other things, this new register indicates whether the Host
Controller supports SDR50, SDR104, and DDR50 UHS-I modes. The spec
doesn't mention about explicit support for SDR12 and SDR25 UHS-I
modes, so the Host Controller v3.00 should support them by default.
Also if the controller supports SDR104 mode, it will also support
SDR50 mode as well. So depending on the host support, we set the
corresponding MMC_CAP_* flags. One more new register. Host Control2
is added in v3.00, which is used during Signal Voltage Switch
procedure described below.
Since as per v3.00 spec, UHS-I supported hosts should set S18R
to 1, we set S18R (bit 24) of OCR before sending ACMD41. We also
need to set XPC (bit 28) of OCR in case the host can supply >150mA.
This support is indicated by the Maximum Current Capabilities
register of the Host Controller.
If the response of ACMD41 has both CCS and S18A set, we start the
signal voltage switch procedure, which if successfull, will switch
the card from 3.3V signalling to 1.8V signalling. Signal voltage
switch procedure adds support for a new command CMD11 in the
Physical Layer Spec v3.01. As part of this procedure, we need to
set 1.8V Signalling Enable (bit 3) of Host Control2 register, which
if remains set after 5ms, means the switch to 1.8V signalling is
successfull. Otherwise, we clear bit 24 of OCR and retry the
initialization sequence. When we remove the card, and insert the
same or another card, we need to make sure that we start with 3.3V
signalling voltage. So we call mmc_set_signal_voltage() with
MMC_SIGNAL_VOLTAGE_330 set so that we are back to 3.3V signalling
voltage before we actually start initializing the card.
Tested by Zhangfei Gao with a Toshiba uhs card and general hs card,
on mmp2 in SDMA mode.
Signed-off-by: Arindam Nath <arindam.nath@amd.com>
Reviewed-by: Philip Rakity <prakity@marvell.com>
Tested-by: Philip Rakity <prakity@marvell.com>
Acked-by: Zhangfei Gao <zhangfei.gao@marvell.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
2011-05-05 14:48:57 +08:00
|
|
|
mmc->caps |= MMC_CAP_UHS_SDR50;
|
2016-06-29 21:24:17 +08:00
|
|
|
}
|
mmc: sd: add support for signal voltage switch procedure
Host Controller v3.00 adds another Capabilities register. Apart
from other things, this new register indicates whether the Host
Controller supports SDR50, SDR104, and DDR50 UHS-I modes. The spec
doesn't mention about explicit support for SDR12 and SDR25 UHS-I
modes, so the Host Controller v3.00 should support them by default.
Also if the controller supports SDR104 mode, it will also support
SDR50 mode as well. So depending on the host support, we set the
corresponding MMC_CAP_* flags. One more new register. Host Control2
is added in v3.00, which is used during Signal Voltage Switch
procedure described below.
Since as per v3.00 spec, UHS-I supported hosts should set S18R
to 1, we set S18R (bit 24) of OCR before sending ACMD41. We also
need to set XPC (bit 28) of OCR in case the host can supply >150mA.
This support is indicated by the Maximum Current Capabilities
register of the Host Controller.
If the response of ACMD41 has both CCS and S18A set, we start the
signal voltage switch procedure, which if successfull, will switch
the card from 3.3V signalling to 1.8V signalling. Signal voltage
switch procedure adds support for a new command CMD11 in the
Physical Layer Spec v3.01. As part of this procedure, we need to
set 1.8V Signalling Enable (bit 3) of Host Control2 register, which
if remains set after 5ms, means the switch to 1.8V signalling is
successfull. Otherwise, we clear bit 24 of OCR and retry the
initialization sequence. When we remove the card, and insert the
same or another card, we need to make sure that we start with 3.3V
signalling voltage. So we call mmc_set_signal_voltage() with
MMC_SIGNAL_VOLTAGE_330 set so that we are back to 3.3V signalling
voltage before we actually start initializing the card.
Tested by Zhangfei Gao with a Toshiba uhs card and general hs card,
on mmp2 in SDMA mode.
Signed-off-by: Arindam Nath <arindam.nath@amd.com>
Reviewed-by: Philip Rakity <prakity@marvell.com>
Tested-by: Philip Rakity <prakity@marvell.com>
Acked-by: Zhangfei Gao <zhangfei.gao@marvell.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
2011-05-05 14:48:57 +08:00
|
|
|
|
2014-11-06 21:19:06 +08:00
|
|
|
if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
|
2016-06-29 21:24:17 +08:00
|
|
|
(host->caps1 & SDHCI_SUPPORT_HS400))
|
2014-11-06 21:19:06 +08:00
|
|
|
mmc->caps2 |= MMC_CAP2_HS400;
|
|
|
|
|
2014-11-06 21:19:05 +08:00
|
|
|
if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
|
|
|
|
(IS_ERR(mmc->supply.vqmmc) ||
|
|
|
|
!regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
|
|
|
|
1300000)))
|
|
|
|
mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
|
|
|
|
|
2016-06-29 21:24:17 +08:00
|
|
|
if ((host->caps1 & SDHCI_SUPPORT_DDR50) &&
|
|
|
|
!(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
|
mmc: sd: add support for signal voltage switch procedure
Host Controller v3.00 adds another Capabilities register. Apart
from other things, this new register indicates whether the Host
Controller supports SDR50, SDR104, and DDR50 UHS-I modes. The spec
doesn't mention about explicit support for SDR12 and SDR25 UHS-I
modes, so the Host Controller v3.00 should support them by default.
Also if the controller supports SDR104 mode, it will also support
SDR50 mode as well. So depending on the host support, we set the
corresponding MMC_CAP_* flags. One more new register. Host Control2
is added in v3.00, which is used during Signal Voltage Switch
procedure described below.
Since as per v3.00 spec, UHS-I supported hosts should set S18R
to 1, we set S18R (bit 24) of OCR before sending ACMD41. We also
need to set XPC (bit 28) of OCR in case the host can supply >150mA.
This support is indicated by the Maximum Current Capabilities
register of the Host Controller.
If the response of ACMD41 has both CCS and S18A set, we start the
signal voltage switch procedure, which if successfull, will switch
the card from 3.3V signalling to 1.8V signalling. Signal voltage
switch procedure adds support for a new command CMD11 in the
Physical Layer Spec v3.01. As part of this procedure, we need to
set 1.8V Signalling Enable (bit 3) of Host Control2 register, which
if remains set after 5ms, means the switch to 1.8V signalling is
successfull. Otherwise, we clear bit 24 of OCR and retry the
initialization sequence. When we remove the card, and insert the
same or another card, we need to make sure that we start with 3.3V
signalling voltage. So we call mmc_set_signal_voltage() with
MMC_SIGNAL_VOLTAGE_330 set so that we are back to 3.3V signalling
voltage before we actually start initializing the card.
Tested by Zhangfei Gao with a Toshiba uhs card and general hs card,
on mmp2 in SDMA mode.
Signed-off-by: Arindam Nath <arindam.nath@amd.com>
Reviewed-by: Philip Rakity <prakity@marvell.com>
Tested-by: Philip Rakity <prakity@marvell.com>
Acked-by: Zhangfei Gao <zhangfei.gao@marvell.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
2011-05-05 14:48:57 +08:00
|
|
|
mmc->caps |= MMC_CAP_UHS_DDR50;
|
|
|
|
|
2012-01-06 12:26:39 +08:00
|
|
|
/* Does the host need tuning for SDR50? */
|
2016-06-29 21:24:17 +08:00
|
|
|
if (host->caps1 & SDHCI_USE_SDR50_TUNING)
|
2011-05-05 14:49:04 +08:00
|
|
|
host->flags |= SDHCI_SDR50_NEEDS_TUNING;
|
|
|
|
|
2011-05-05 14:48:59 +08:00
|
|
|
/* Driver Type(s) (A, C, D) supported by the host */
|
2016-06-29 21:24:17 +08:00
|
|
|
if (host->caps1 & SDHCI_DRIVER_TYPE_A)
|
2011-05-05 14:48:59 +08:00
|
|
|
mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
|
2016-06-29 21:24:17 +08:00
|
|
|
if (host->caps1 & SDHCI_DRIVER_TYPE_C)
|
2011-05-05 14:48:59 +08:00
|
|
|
mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
|
2016-06-29 21:24:17 +08:00
|
|
|
if (host->caps1 & SDHCI_DRIVER_TYPE_D)
|
2011-05-05 14:48:59 +08:00
|
|
|
mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
|
|
|
|
|
2011-05-05 14:49:07 +08:00
|
|
|
/* Initial value for re-tuning timer count */
|
2020-04-08 15:21:05 +08:00
|
|
|
host->tuning_count = FIELD_GET(SDHCI_RETUNING_TIMER_COUNT_MASK,
|
|
|
|
host->caps1);
|
2011-05-05 14:49:07 +08:00
|
|
|
|
|
|
|
/*
|
|
|
|
* In case Re-tuning Timer is not disabled, the actual value of
|
|
|
|
* re-tuning timer will be 2 ^ (n - 1).
|
|
|
|
*/
|
|
|
|
if (host->tuning_count)
|
|
|
|
host->tuning_count = 1 << (host->tuning_count - 1);
|
|
|
|
|
|
|
|
/* Re-tuning mode supported by the Host Controller */
|
2020-04-08 15:21:05 +08:00
|
|
|
host->tuning_mode = FIELD_GET(SDHCI_RETUNING_MODE_MASK, host->caps1);
|
2011-05-05 14:49:07 +08:00
|
|
|
|
2010-12-08 17:04:30 +08:00
|
|
|
ocr_avail = 0;
|
2012-05-28 09:36:44 +08:00
|
|
|
|
mmc: sd: add support for signal voltage switch procedure
Host Controller v3.00 adds another Capabilities register. Apart
from other things, this new register indicates whether the Host
Controller supports SDR50, SDR104, and DDR50 UHS-I modes. The spec
doesn't mention about explicit support for SDR12 and SDR25 UHS-I
modes, so the Host Controller v3.00 should support them by default.
Also if the controller supports SDR104 mode, it will also support
SDR50 mode as well. So depending on the host support, we set the
corresponding MMC_CAP_* flags. One more new register. Host Control2
is added in v3.00, which is used during Signal Voltage Switch
procedure described below.
Since as per v3.00 spec, UHS-I supported hosts should set S18R
to 1, we set S18R (bit 24) of OCR before sending ACMD41. We also
need to set XPC (bit 28) of OCR in case the host can supply >150mA.
This support is indicated by the Maximum Current Capabilities
register of the Host Controller.
If the response of ACMD41 has both CCS and S18A set, we start the
signal voltage switch procedure, which if successfull, will switch
the card from 3.3V signalling to 1.8V signalling. Signal voltage
switch procedure adds support for a new command CMD11 in the
Physical Layer Spec v3.01. As part of this procedure, we need to
set 1.8V Signalling Enable (bit 3) of Host Control2 register, which
if remains set after 5ms, means the switch to 1.8V signalling is
successfull. Otherwise, we clear bit 24 of OCR and retry the
initialization sequence. When we remove the card, and insert the
same or another card, we need to make sure that we start with 3.3V
signalling voltage. So we call mmc_set_signal_voltage() with
MMC_SIGNAL_VOLTAGE_330 set so that we are back to 3.3V signalling
voltage before we actually start initializing the card.
Tested by Zhangfei Gao with a Toshiba uhs card and general hs card,
on mmp2 in SDMA mode.
Signed-off-by: Arindam Nath <arindam.nath@amd.com>
Reviewed-by: Philip Rakity <prakity@marvell.com>
Tested-by: Philip Rakity <prakity@marvell.com>
Acked-by: Zhangfei Gao <zhangfei.gao@marvell.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
2011-05-05 14:48:57 +08:00
|
|
|
/*
|
|
|
|
* According to SD Host Controller spec v3.00, if the Host System
|
|
|
|
* can afford more than 150mA, Host Driver should set XPC to 1. Also
|
|
|
|
* the value is meaningful only if Voltage Support in the Capabilities
|
|
|
|
* register is set. The actual current value is 4 times the register
|
|
|
|
* value.
|
|
|
|
*/
|
|
|
|
max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
|
2014-06-14 01:13:56 +08:00
|
|
|
if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
|
2014-08-01 14:00:13 +08:00
|
|
|
int curr = regulator_get_current_limit(mmc->supply.vmmc);
|
2012-05-28 09:36:44 +08:00
|
|
|
if (curr > 0) {
|
|
|
|
|
|
|
|
/* convert to SDHCI_MAX_CURRENT format */
|
|
|
|
curr = curr/1000; /* convert to mA */
|
|
|
|
curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
|
|
|
|
|
|
|
|
curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
|
|
|
|
max_current_caps =
|
2020-05-11 14:28:27 +08:00
|
|
|
FIELD_PREP(SDHCI_MAX_CURRENT_330_MASK, curr) |
|
|
|
|
FIELD_PREP(SDHCI_MAX_CURRENT_300_MASK, curr) |
|
|
|
|
FIELD_PREP(SDHCI_MAX_CURRENT_180_MASK, curr);
|
2012-05-28 09:36:44 +08:00
|
|
|
}
|
|
|
|
}
|
mmc: sd: add support for signal voltage switch procedure
Host Controller v3.00 adds another Capabilities register. Apart
from other things, this new register indicates whether the Host
Controller supports SDR50, SDR104, and DDR50 UHS-I modes. The spec
doesn't mention about explicit support for SDR12 and SDR25 UHS-I
modes, so the Host Controller v3.00 should support them by default.
Also if the controller supports SDR104 mode, it will also support
SDR50 mode as well. So depending on the host support, we set the
corresponding MMC_CAP_* flags. One more new register. Host Control2
is added in v3.00, which is used during Signal Voltage Switch
procedure described below.
Since as per v3.00 spec, UHS-I supported hosts should set S18R
to 1, we set S18R (bit 24) of OCR before sending ACMD41. We also
need to set XPC (bit 28) of OCR in case the host can supply >150mA.
This support is indicated by the Maximum Current Capabilities
register of the Host Controller.
If the response of ACMD41 has both CCS and S18A set, we start the
signal voltage switch procedure, which if successfull, will switch
the card from 3.3V signalling to 1.8V signalling. Signal voltage
switch procedure adds support for a new command CMD11 in the
Physical Layer Spec v3.01. As part of this procedure, we need to
set 1.8V Signalling Enable (bit 3) of Host Control2 register, which
if remains set after 5ms, means the switch to 1.8V signalling is
successfull. Otherwise, we clear bit 24 of OCR and retry the
initialization sequence. When we remove the card, and insert the
same or another card, we need to make sure that we start with 3.3V
signalling voltage. So we call mmc_set_signal_voltage() with
MMC_SIGNAL_VOLTAGE_330 set so that we are back to 3.3V signalling
voltage before we actually start initializing the card.
Tested by Zhangfei Gao with a Toshiba uhs card and general hs card,
on mmp2 in SDMA mode.
Signed-off-by: Arindam Nath <arindam.nath@amd.com>
Reviewed-by: Philip Rakity <prakity@marvell.com>
Tested-by: Philip Rakity <prakity@marvell.com>
Acked-by: Zhangfei Gao <zhangfei.gao@marvell.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
2011-05-05 14:48:57 +08:00
|
|
|
|
2016-06-29 21:24:17 +08:00
|
|
|
if (host->caps & SDHCI_CAN_VDD_330) {
|
2010-12-08 17:04:30 +08:00
|
|
|
ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
|
mmc: sd: add support for signal voltage switch procedure
Host Controller v3.00 adds another Capabilities register. Apart
from other things, this new register indicates whether the Host
Controller supports SDR50, SDR104, and DDR50 UHS-I modes. The spec
doesn't mention about explicit support for SDR12 and SDR25 UHS-I
modes, so the Host Controller v3.00 should support them by default.
Also if the controller supports SDR104 mode, it will also support
SDR50 mode as well. So depending on the host support, we set the
corresponding MMC_CAP_* flags. One more new register. Host Control2
is added in v3.00, which is used during Signal Voltage Switch
procedure described below.
Since as per v3.00 spec, UHS-I supported hosts should set S18R
to 1, we set S18R (bit 24) of OCR before sending ACMD41. We also
need to set XPC (bit 28) of OCR in case the host can supply >150mA.
This support is indicated by the Maximum Current Capabilities
register of the Host Controller.
If the response of ACMD41 has both CCS and S18A set, we start the
signal voltage switch procedure, which if successfull, will switch
the card from 3.3V signalling to 1.8V signalling. Signal voltage
switch procedure adds support for a new command CMD11 in the
Physical Layer Spec v3.01. As part of this procedure, we need to
set 1.8V Signalling Enable (bit 3) of Host Control2 register, which
if remains set after 5ms, means the switch to 1.8V signalling is
successfull. Otherwise, we clear bit 24 of OCR and retry the
initialization sequence. When we remove the card, and insert the
same or another card, we need to make sure that we start with 3.3V
signalling voltage. So we call mmc_set_signal_voltage() with
MMC_SIGNAL_VOLTAGE_330 set so that we are back to 3.3V signalling
voltage before we actually start initializing the card.
Tested by Zhangfei Gao with a Toshiba uhs card and general hs card,
on mmp2 in SDMA mode.
Signed-off-by: Arindam Nath <arindam.nath@amd.com>
Reviewed-by: Philip Rakity <prakity@marvell.com>
Tested-by: Philip Rakity <prakity@marvell.com>
Acked-by: Zhangfei Gao <zhangfei.gao@marvell.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
2011-05-05 14:48:57 +08:00
|
|
|
|
2020-05-11 14:28:27 +08:00
|
|
|
mmc->max_current_330 = FIELD_GET(SDHCI_MAX_CURRENT_330_MASK,
|
|
|
|
max_current_caps) *
|
|
|
|
SDHCI_MAX_CURRENT_MULTIPLIER;
|
mmc: sd: add support for signal voltage switch procedure
Host Controller v3.00 adds another Capabilities register. Apart
from other things, this new register indicates whether the Host
Controller supports SDR50, SDR104, and DDR50 UHS-I modes. The spec
doesn't mention about explicit support for SDR12 and SDR25 UHS-I
modes, so the Host Controller v3.00 should support them by default.
Also if the controller supports SDR104 mode, it will also support
SDR50 mode as well. So depending on the host support, we set the
corresponding MMC_CAP_* flags. One more new register. Host Control2
is added in v3.00, which is used during Signal Voltage Switch
procedure described below.
Since as per v3.00 spec, UHS-I supported hosts should set S18R
to 1, we set S18R (bit 24) of OCR before sending ACMD41. We also
need to set XPC (bit 28) of OCR in case the host can supply >150mA.
This support is indicated by the Maximum Current Capabilities
register of the Host Controller.
If the response of ACMD41 has both CCS and S18A set, we start the
signal voltage switch procedure, which if successfull, will switch
the card from 3.3V signalling to 1.8V signalling. Signal voltage
switch procedure adds support for a new command CMD11 in the
Physical Layer Spec v3.01. As part of this procedure, we need to
set 1.8V Signalling Enable (bit 3) of Host Control2 register, which
if remains set after 5ms, means the switch to 1.8V signalling is
successfull. Otherwise, we clear bit 24 of OCR and retry the
initialization sequence. When we remove the card, and insert the
same or another card, we need to make sure that we start with 3.3V
signalling voltage. So we call mmc_set_signal_voltage() with
MMC_SIGNAL_VOLTAGE_330 set so that we are back to 3.3V signalling
voltage before we actually start initializing the card.
Tested by Zhangfei Gao with a Toshiba uhs card and general hs card,
on mmp2 in SDMA mode.
Signed-off-by: Arindam Nath <arindam.nath@amd.com>
Reviewed-by: Philip Rakity <prakity@marvell.com>
Tested-by: Philip Rakity <prakity@marvell.com>
Acked-by: Zhangfei Gao <zhangfei.gao@marvell.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
2011-05-05 14:48:57 +08:00
|
|
|
}
|
2016-06-29 21:24:17 +08:00
|
|
|
if (host->caps & SDHCI_CAN_VDD_300) {
|
2010-12-08 17:04:30 +08:00
|
|
|
ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
|
mmc: sd: add support for signal voltage switch procedure
Host Controller v3.00 adds another Capabilities register. Apart
from other things, this new register indicates whether the Host
Controller supports SDR50, SDR104, and DDR50 UHS-I modes. The spec
doesn't mention about explicit support for SDR12 and SDR25 UHS-I
modes, so the Host Controller v3.00 should support them by default.
Also if the controller supports SDR104 mode, it will also support
SDR50 mode as well. So depending on the host support, we set the
corresponding MMC_CAP_* flags. One more new register. Host Control2
is added in v3.00, which is used during Signal Voltage Switch
procedure described below.
Since as per v3.00 spec, UHS-I supported hosts should set S18R
to 1, we set S18R (bit 24) of OCR before sending ACMD41. We also
need to set XPC (bit 28) of OCR in case the host can supply >150mA.
This support is indicated by the Maximum Current Capabilities
register of the Host Controller.
If the response of ACMD41 has both CCS and S18A set, we start the
signal voltage switch procedure, which if successfull, will switch
the card from 3.3V signalling to 1.8V signalling. Signal voltage
switch procedure adds support for a new command CMD11 in the
Physical Layer Spec v3.01. As part of this procedure, we need to
set 1.8V Signalling Enable (bit 3) of Host Control2 register, which
if remains set after 5ms, means the switch to 1.8V signalling is
successfull. Otherwise, we clear bit 24 of OCR and retry the
initialization sequence. When we remove the card, and insert the
same or another card, we need to make sure that we start with 3.3V
signalling voltage. So we call mmc_set_signal_voltage() with
MMC_SIGNAL_VOLTAGE_330 set so that we are back to 3.3V signalling
voltage before we actually start initializing the card.
Tested by Zhangfei Gao with a Toshiba uhs card and general hs card,
on mmp2 in SDMA mode.
Signed-off-by: Arindam Nath <arindam.nath@amd.com>
Reviewed-by: Philip Rakity <prakity@marvell.com>
Tested-by: Philip Rakity <prakity@marvell.com>
Acked-by: Zhangfei Gao <zhangfei.gao@marvell.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
2011-05-05 14:48:57 +08:00
|
|
|
|
2020-05-11 14:28:27 +08:00
|
|
|
mmc->max_current_300 = FIELD_GET(SDHCI_MAX_CURRENT_300_MASK,
|
|
|
|
max_current_caps) *
|
|
|
|
SDHCI_MAX_CURRENT_MULTIPLIER;
|
mmc: sd: add support for signal voltage switch procedure
Host Controller v3.00 adds another Capabilities register. Apart
from other things, this new register indicates whether the Host
Controller supports SDR50, SDR104, and DDR50 UHS-I modes. The spec
doesn't mention about explicit support for SDR12 and SDR25 UHS-I
modes, so the Host Controller v3.00 should support them by default.
Also if the controller supports SDR104 mode, it will also support
SDR50 mode as well. So depending on the host support, we set the
corresponding MMC_CAP_* flags. One more new register. Host Control2
is added in v3.00, which is used during Signal Voltage Switch
procedure described below.
Since as per v3.00 spec, UHS-I supported hosts should set S18R
to 1, we set S18R (bit 24) of OCR before sending ACMD41. We also
need to set XPC (bit 28) of OCR in case the host can supply >150mA.
This support is indicated by the Maximum Current Capabilities
register of the Host Controller.
If the response of ACMD41 has both CCS and S18A set, we start the
signal voltage switch procedure, which if successfull, will switch
the card from 3.3V signalling to 1.8V signalling. Signal voltage
switch procedure adds support for a new command CMD11 in the
Physical Layer Spec v3.01. As part of this procedure, we need to
set 1.8V Signalling Enable (bit 3) of Host Control2 register, which
if remains set after 5ms, means the switch to 1.8V signalling is
successfull. Otherwise, we clear bit 24 of OCR and retry the
initialization sequence. When we remove the card, and insert the
same or another card, we need to make sure that we start with 3.3V
signalling voltage. So we call mmc_set_signal_voltage() with
MMC_SIGNAL_VOLTAGE_330 set so that we are back to 3.3V signalling
voltage before we actually start initializing the card.
Tested by Zhangfei Gao with a Toshiba uhs card and general hs card,
on mmp2 in SDMA mode.
Signed-off-by: Arindam Nath <arindam.nath@amd.com>
Reviewed-by: Philip Rakity <prakity@marvell.com>
Tested-by: Philip Rakity <prakity@marvell.com>
Acked-by: Zhangfei Gao <zhangfei.gao@marvell.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
2011-05-05 14:48:57 +08:00
|
|
|
}
|
2016-06-29 21:24:17 +08:00
|
|
|
if (host->caps & SDHCI_CAN_VDD_180) {
|
2010-12-08 17:04:30 +08:00
|
|
|
ocr_avail |= MMC_VDD_165_195;
|
|
|
|
|
2020-05-11 14:28:27 +08:00
|
|
|
mmc->max_current_180 = FIELD_GET(SDHCI_MAX_CURRENT_180_MASK,
|
|
|
|
max_current_caps) *
|
|
|
|
SDHCI_MAX_CURRENT_MULTIPLIER;
|
mmc: sd: add support for signal voltage switch procedure
Host Controller v3.00 adds another Capabilities register. Apart
from other things, this new register indicates whether the Host
Controller supports SDR50, SDR104, and DDR50 UHS-I modes. The spec
doesn't mention about explicit support for SDR12 and SDR25 UHS-I
modes, so the Host Controller v3.00 should support them by default.
Also if the controller supports SDR104 mode, it will also support
SDR50 mode as well. So depending on the host support, we set the
corresponding MMC_CAP_* flags. One more new register. Host Control2
is added in v3.00, which is used during Signal Voltage Switch
procedure described below.
Since as per v3.00 spec, UHS-I supported hosts should set S18R
to 1, we set S18R (bit 24) of OCR before sending ACMD41. We also
need to set XPC (bit 28) of OCR in case the host can supply >150mA.
This support is indicated by the Maximum Current Capabilities
register of the Host Controller.
If the response of ACMD41 has both CCS and S18A set, we start the
signal voltage switch procedure, which if successfull, will switch
the card from 3.3V signalling to 1.8V signalling. Signal voltage
switch procedure adds support for a new command CMD11 in the
Physical Layer Spec v3.01. As part of this procedure, we need to
set 1.8V Signalling Enable (bit 3) of Host Control2 register, which
if remains set after 5ms, means the switch to 1.8V signalling is
successfull. Otherwise, we clear bit 24 of OCR and retry the
initialization sequence. When we remove the card, and insert the
same or another card, we need to make sure that we start with 3.3V
signalling voltage. So we call mmc_set_signal_voltage() with
MMC_SIGNAL_VOLTAGE_330 set so that we are back to 3.3V signalling
voltage before we actually start initializing the card.
Tested by Zhangfei Gao with a Toshiba uhs card and general hs card,
on mmp2 in SDMA mode.
Signed-off-by: Arindam Nath <arindam.nath@amd.com>
Reviewed-by: Philip Rakity <prakity@marvell.com>
Tested-by: Philip Rakity <prakity@marvell.com>
Acked-by: Zhangfei Gao <zhangfei.gao@marvell.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
2011-05-05 14:48:57 +08:00
|
|
|
}
|
|
|
|
|
2015-06-05 17:40:08 +08:00
|
|
|
/* If OCR set by host, use it instead. */
|
|
|
|
if (host->ocr_mask)
|
|
|
|
ocr_avail = host->ocr_mask;
|
|
|
|
|
|
|
|
/* If OCR set by external regulators, give it highest prio. */
|
2014-06-14 01:13:56 +08:00
|
|
|
if (mmc->ocr_avail)
|
2014-06-25 15:25:34 +08:00
|
|
|
ocr_avail = mmc->ocr_avail;
|
2014-06-14 01:13:56 +08:00
|
|
|
|
2010-12-08 17:04:30 +08:00
|
|
|
mmc->ocr_avail = ocr_avail;
|
|
|
|
mmc->ocr_avail_sdio = ocr_avail;
|
|
|
|
if (host->ocr_avail_sdio)
|
|
|
|
mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
|
|
|
|
mmc->ocr_avail_sd = ocr_avail;
|
|
|
|
if (host->ocr_avail_sd)
|
|
|
|
mmc->ocr_avail_sd &= host->ocr_avail_sd;
|
|
|
|
else /* normal SD controllers don't support 1.8V */
|
|
|
|
mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
|
|
|
|
mmc->ocr_avail_mmc = ocr_avail;
|
|
|
|
if (host->ocr_avail_mmc)
|
|
|
|
mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
|
2006-06-30 17:22:23 +08:00
|
|
|
|
|
|
|
if (mmc->ocr_avail == 0) {
|
2015-11-18 17:47:02 +08:00
|
|
|
pr_err("%s: Hardware doesn't report any support voltages.\n",
|
|
|
|
mmc_hostname(mmc));
|
2016-04-12 19:25:08 +08:00
|
|
|
ret = -ENODEV;
|
|
|
|
goto unreg;
|
2006-06-30 17:22:23 +08:00
|
|
|
}
|
|
|
|
|
2016-06-29 21:24:16 +08:00
|
|
|
if ((mmc->caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
|
|
|
|
MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 |
|
|
|
|
MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR)) ||
|
|
|
|
(mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS400_1_8V)))
|
|
|
|
host->flags |= SDHCI_SIGNALING_180;
|
|
|
|
|
|
|
|
if (mmc->caps2 & MMC_CAP2_HSX00_1_2V)
|
|
|
|
host->flags |= SDHCI_SIGNALING_120;
|
|
|
|
|
2006-03-24 19:18:17 +08:00
|
|
|
spin_lock_init(&host->lock);
|
|
|
|
|
2017-11-27 18:28:50 +08:00
|
|
|
/*
|
|
|
|
* Maximum number of sectors in one transfer. Limited by SDMA boundary
|
|
|
|
* size (512KiB). Note some tuning modes impose a 4MiB limit, but this
|
|
|
|
* is less anyway.
|
|
|
|
*/
|
|
|
|
mmc->max_req_size = 524288;
|
|
|
|
|
2006-03-24 19:18:17 +08:00
|
|
|
/*
|
2008-06-29 00:28:51 +08:00
|
|
|
* Maximum number of segments. Depends on if the hardware
|
|
|
|
* can do scatter/gather or not.
|
2006-03-24 19:18:17 +08:00
|
|
|
*/
|
2017-11-27 18:28:50 +08:00
|
|
|
if (host->flags & SDHCI_USE_ADMA) {
|
2014-11-04 18:42:43 +08:00
|
|
|
mmc->max_segs = SDHCI_MAX_SEGS;
|
2017-11-27 18:28:50 +08:00
|
|
|
} else if (host->flags & SDHCI_USE_SDMA) {
|
2010-09-10 13:33:59 +08:00
|
|
|
mmc->max_segs = 1;
|
2017-11-27 18:28:50 +08:00
|
|
|
if (swiotlb_max_segment()) {
|
|
|
|
unsigned int max_req_size = (1 << IO_TLB_SHIFT) *
|
|
|
|
IO_TLB_SEGSIZE;
|
|
|
|
mmc->max_req_size = min(mmc->max_req_size,
|
|
|
|
max_req_size);
|
|
|
|
}
|
|
|
|
} else { /* PIO */
|
2014-11-04 18:42:43 +08:00
|
|
|
mmc->max_segs = SDHCI_MAX_SEGS;
|
2017-11-27 18:28:50 +08:00
|
|
|
}
|
2006-03-24 19:18:17 +08:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Maximum segment size. Could be one segment with the maximum number
|
2008-06-29 00:28:51 +08:00
|
|
|
* of bytes. When doing hardware scatter/gather, each entry cannot
|
|
|
|
* be larger than 64 KiB though.
|
2006-03-24 19:18:17 +08:00
|
|
|
*/
|
2011-01-02 08:37:32 +08:00
|
|
|
if (host->flags & SDHCI_USE_ADMA) {
|
|
|
|
if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
|
|
|
|
mmc->max_seg_size = 65535;
|
|
|
|
else
|
|
|
|
mmc->max_seg_size = 65536;
|
|
|
|
} else {
|
2008-06-29 00:28:51 +08:00
|
|
|
mmc->max_seg_size = mmc->max_req_size;
|
2011-01-02 08:37:32 +08:00
|
|
|
}
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2006-11-22 00:54:23 +08:00
|
|
|
/*
|
|
|
|
* Maximum block size. This varies from controller to controller and
|
|
|
|
* is specified in the capabilities register.
|
|
|
|
*/
|
2009-03-17 05:14:03 +08:00
|
|
|
if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
|
|
|
|
mmc->max_blk_size = 2;
|
|
|
|
} else {
|
2016-06-29 21:24:17 +08:00
|
|
|
mmc->max_blk_size = (host->caps & SDHCI_MAX_BLOCK_MASK) >>
|
2009-03-17 05:14:03 +08:00
|
|
|
SDHCI_MAX_BLOCK_SHIFT;
|
|
|
|
if (mmc->max_blk_size >= 3) {
|
2014-09-13 05:56:56 +08:00
|
|
|
pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
|
|
|
|
mmc_hostname(mmc));
|
2009-03-17 05:14:03 +08:00
|
|
|
mmc->max_blk_size = 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
mmc->max_blk_size = 512 << mmc->max_blk_size;
|
2006-11-22 00:54:23 +08:00
|
|
|
|
2006-11-22 00:55:45 +08:00
|
|
|
/*
|
|
|
|
* Maximum block count.
|
|
|
|
*/
|
2009-06-14 19:40:53 +08:00
|
|
|
mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
|
2006-11-22 00:55:45 +08:00
|
|
|
|
2018-10-25 10:12:36 +08:00
|
|
|
if (mmc->max_segs == 1)
|
2018-01-29 07:44:53 +08:00
|
|
|
/* This may alter mmc->*_blk_* parameters */
|
2018-10-25 10:12:36 +08:00
|
|
|
sdhci_allocate_bounce_buffer(host);
|
2018-01-29 07:44:53 +08:00
|
|
|
|
2016-06-29 21:24:15 +08:00
|
|
|
return 0;
|
|
|
|
|
|
|
|
unreg:
|
2020-06-23 21:34:46 +08:00
|
|
|
if (host->sdhci_core_to_disable_vqmmc)
|
2016-06-29 21:24:15 +08:00
|
|
|
regulator_disable(mmc->supply.vqmmc);
|
|
|
|
undma:
|
|
|
|
if (host->align_buffer)
|
|
|
|
dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
|
|
|
|
host->adma_table_sz, host->align_buffer,
|
|
|
|
host->align_addr);
|
|
|
|
host->adma_table = NULL;
|
|
|
|
host->align_buffer = NULL;
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(sdhci_setup_host);
|
|
|
|
|
2017-03-21 01:50:45 +08:00
|
|
|
void sdhci_cleanup_host(struct sdhci_host *host)
|
|
|
|
{
|
|
|
|
struct mmc_host *mmc = host->mmc;
|
|
|
|
|
2020-06-23 21:34:46 +08:00
|
|
|
if (host->sdhci_core_to_disable_vqmmc)
|
2017-03-21 01:50:45 +08:00
|
|
|
regulator_disable(mmc->supply.vqmmc);
|
|
|
|
|
|
|
|
if (host->align_buffer)
|
|
|
|
dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
|
|
|
|
host->adma_table_sz, host->align_buffer,
|
|
|
|
host->align_addr);
|
2020-01-16 18:51:47 +08:00
|
|
|
|
|
|
|
if (host->use_external_dma)
|
|
|
|
sdhci_external_dma_release(host);
|
|
|
|
|
2017-03-21 01:50:45 +08:00
|
|
|
host->adma_table = NULL;
|
|
|
|
host->align_buffer = NULL;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(sdhci_cleanup_host);
|
|
|
|
|
2016-06-29 21:24:15 +08:00
|
|
|
int __sdhci_add_host(struct sdhci_host *host)
|
|
|
|
{
|
2019-04-05 20:40:20 +08:00
|
|
|
unsigned int flags = WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_HIGHPRI;
|
2016-06-29 21:24:15 +08:00
|
|
|
struct mmc_host *mmc = host->mmc;
|
|
|
|
int ret;
|
|
|
|
|
2020-05-18 20:09:39 +08:00
|
|
|
if ((mmc->caps2 & MMC_CAP2_CQE) &&
|
|
|
|
(host->quirks & SDHCI_QUIRK_BROKEN_CQE)) {
|
|
|
|
mmc->caps2 &= ~MMC_CAP2_CQE;
|
|
|
|
mmc->cqe_ops = NULL;
|
|
|
|
}
|
|
|
|
|
2019-04-05 20:40:20 +08:00
|
|
|
host->complete_wq = alloc_workqueue("sdhci", flags, 0);
|
|
|
|
if (!host->complete_wq)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
INIT_WORK(&host->complete_work, sdhci_complete_work);
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2017-10-24 23:03:45 +08:00
|
|
|
timer_setup(&host->timer, sdhci_timeout_timer, 0);
|
|
|
|
timer_setup(&host->data_timer, sdhci_timeout_data_timer, 0);
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2014-12-06 01:41:10 +08:00
|
|
|
init_waitqueue_head(&host->buf_ready_int);
|
2011-05-05 14:49:04 +08:00
|
|
|
|
2013-07-05 14:38:55 +08:00
|
|
|
sdhci_init(host, 0);
|
|
|
|
|
2014-04-25 19:55:46 +08:00
|
|
|
ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
|
|
|
|
IRQF_SHARED, mmc_hostname(mmc), host);
|
2012-07-02 21:26:15 +08:00
|
|
|
if (ret) {
|
|
|
|
pr_err("%s: Failed to request IRQ %d: %d\n",
|
|
|
|
mmc_hostname(mmc), host->irq, ret);
|
2019-04-05 20:40:20 +08:00
|
|
|
goto unwq;
|
2012-07-02 21:26:15 +08:00
|
|
|
}
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2016-04-12 19:25:09 +08:00
|
|
|
ret = sdhci_led_register(host);
|
2012-07-02 21:26:15 +08:00
|
|
|
if (ret) {
|
|
|
|
pr_err("%s: Failed to register LED device: %d\n",
|
|
|
|
mmc_hostname(mmc), ret);
|
2016-04-12 19:25:08 +08:00
|
|
|
goto unirq;
|
2012-07-02 21:26:15 +08:00
|
|
|
}
|
2008-03-17 17:29:38 +08:00
|
|
|
|
2016-04-12 19:25:08 +08:00
|
|
|
ret = mmc_add_host(mmc);
|
|
|
|
if (ret)
|
|
|
|
goto unled;
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2011-10-11 14:14:09 +08:00
|
|
|
pr_info("%s: SDHCI controller on %s [%s] using %s\n",
|
2008-11-09 04:37:46 +08:00
|
|
|
mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
|
2020-01-16 18:51:47 +08:00
|
|
|
host->use_external_dma ? "External DMA" :
|
2014-11-04 18:42:46 +08:00
|
|
|
(host->flags & SDHCI_USE_ADMA) ?
|
|
|
|
(host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
|
2009-09-23 07:45:30 +08:00
|
|
|
(host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2009-03-17 05:13:48 +08:00
|
|
|
sdhci_enable_card_detection(host);
|
|
|
|
|
2006-03-24 19:18:17 +08:00
|
|
|
return 0;
|
|
|
|
|
2016-04-12 19:25:08 +08:00
|
|
|
unled:
|
2016-04-12 19:25:09 +08:00
|
|
|
sdhci_led_unregister(host);
|
2016-04-12 19:25:08 +08:00
|
|
|
unirq:
|
2014-04-25 19:57:12 +08:00
|
|
|
sdhci_do_reset(host, SDHCI_RESET_ALL);
|
2014-04-25 19:56:01 +08:00
|
|
|
sdhci_writel(host, 0, SDHCI_INT_ENABLE);
|
|
|
|
sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
|
2008-03-17 17:29:38 +08:00
|
|
|
free_irq(host->irq, host);
|
2019-04-05 20:40:20 +08:00
|
|
|
unwq:
|
|
|
|
destroy_workqueue(host->complete_wq);
|
2016-06-29 21:24:15 +08:00
|
|
|
|
2006-03-24 19:18:17 +08:00
|
|
|
return ret;
|
|
|
|
}
|
2016-06-29 21:24:15 +08:00
|
|
|
EXPORT_SYMBOL_GPL(__sdhci_add_host);
|
|
|
|
|
|
|
|
int sdhci_add_host(struct sdhci_host *host)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = sdhci_setup_host(host);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2017-03-21 01:50:45 +08:00
|
|
|
ret = __sdhci_add_host(host);
|
|
|
|
if (ret)
|
|
|
|
goto cleanup;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
cleanup:
|
|
|
|
sdhci_cleanup_host(host);
|
|
|
|
|
|
|
|
return ret;
|
2016-06-29 21:24:15 +08:00
|
|
|
}
|
2008-03-19 00:35:49 +08:00
|
|
|
EXPORT_SYMBOL_GPL(sdhci_add_host);
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2008-04-17 01:13:13 +08:00
|
|
|
void sdhci_remove_host(struct sdhci_host *host, int dead)
|
2008-03-19 00:35:49 +08:00
|
|
|
{
|
2014-06-14 01:13:56 +08:00
|
|
|
struct mmc_host *mmc = host->mmc;
|
2008-04-17 01:13:13 +08:00
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
if (dead) {
|
|
|
|
spin_lock_irqsave(&host->lock, flags);
|
|
|
|
|
|
|
|
host->flags |= SDHCI_DEVICE_DEAD;
|
|
|
|
|
2016-06-29 21:24:31 +08:00
|
|
|
if (sdhci_has_requests(host)) {
|
2011-10-11 14:14:09 +08:00
|
|
|
pr_err("%s: Controller removed during "
|
2014-07-04 04:27:42 +08:00
|
|
|
" transfer!\n", mmc_hostname(mmc));
|
2016-06-29 21:24:31 +08:00
|
|
|
sdhci_error_out_mrqs(host, -ENOMEDIUM);
|
2008-04-17 01:13:13 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&host->lock, flags);
|
|
|
|
}
|
|
|
|
|
2009-03-17 05:13:48 +08:00
|
|
|
sdhci_disable_card_detection(host);
|
|
|
|
|
2014-07-04 04:27:42 +08:00
|
|
|
mmc_remove_host(mmc);
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2016-04-12 19:25:09 +08:00
|
|
|
sdhci_led_unregister(host);
|
2008-03-17 17:29:38 +08:00
|
|
|
|
2008-04-17 01:13:13 +08:00
|
|
|
if (!dead)
|
2014-04-25 19:57:12 +08:00
|
|
|
sdhci_do_reset(host, SDHCI_RESET_ALL);
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2014-04-25 19:56:01 +08:00
|
|
|
sdhci_writel(host, 0, SDHCI_INT_ENABLE);
|
|
|
|
sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
|
2006-03-24 19:18:17 +08:00
|
|
|
free_irq(host->irq, host);
|
|
|
|
|
|
|
|
del_timer_sync(&host->timer);
|
2016-06-29 21:24:33 +08:00
|
|
|
del_timer_sync(&host->data_timer);
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2019-04-05 20:40:20 +08:00
|
|
|
destroy_workqueue(host->complete_wq);
|
2008-06-29 00:28:51 +08:00
|
|
|
|
2020-06-23 21:34:46 +08:00
|
|
|
if (host->sdhci_core_to_disable_vqmmc)
|
2014-06-14 01:13:56 +08:00
|
|
|
regulator_disable(mmc->supply.vqmmc);
|
2012-07-24 06:56:23 +08:00
|
|
|
|
2016-01-26 21:39:50 +08:00
|
|
|
if (host->align_buffer)
|
2016-01-26 21:39:55 +08:00
|
|
|
dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
|
|
|
|
host->adma_table_sz, host->align_buffer,
|
|
|
|
host->align_addr);
|
2008-06-29 00:28:51 +08:00
|
|
|
|
2020-01-16 18:51:47 +08:00
|
|
|
if (host->use_external_dma)
|
|
|
|
sdhci_external_dma_release(host);
|
|
|
|
|
2014-11-04 18:42:39 +08:00
|
|
|
host->adma_table = NULL;
|
2008-06-29 00:28:51 +08:00
|
|
|
host->align_buffer = NULL;
|
2006-03-24 19:18:17 +08:00
|
|
|
}
|
|
|
|
|
2008-03-19 00:35:49 +08:00
|
|
|
EXPORT_SYMBOL_GPL(sdhci_remove_host);
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2008-03-19 00:35:49 +08:00
|
|
|
void sdhci_free_host(struct sdhci_host *host)
|
2006-03-24 19:18:17 +08:00
|
|
|
{
|
2008-03-19 00:35:49 +08:00
|
|
|
mmc_free_host(host->mmc);
|
2006-03-24 19:18:17 +08:00
|
|
|
}
|
|
|
|
|
2008-03-19 00:35:49 +08:00
|
|
|
EXPORT_SYMBOL_GPL(sdhci_free_host);
|
2006-03-24 19:18:17 +08:00
|
|
|
|
|
|
|
/*****************************************************************************\
|
|
|
|
* *
|
|
|
|
* Driver init/exit *
|
|
|
|
* *
|
|
|
|
\*****************************************************************************/
|
|
|
|
|
|
|
|
static int __init sdhci_drv_init(void)
|
|
|
|
{
|
2011-10-11 14:14:09 +08:00
|
|
|
pr_info(DRIVER_NAME
|
2007-02-09 15:23:41 +08:00
|
|
|
": Secure Digital Host Controller Interface driver\n");
|
2011-10-11 14:14:09 +08:00
|
|
|
pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
|
2006-03-24 19:18:17 +08:00
|
|
|
|
2008-03-19 00:35:49 +08:00
|
|
|
return 0;
|
2006-03-24 19:18:17 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static void __exit sdhci_drv_exit(void)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
|
|
|
module_init(sdhci_drv_init);
|
|
|
|
module_exit(sdhci_drv_exit);
|
|
|
|
|
2006-06-30 17:22:31 +08:00
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module_param(debug_quirks, uint, 0444);
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2011-10-03 20:33:34 +08:00
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module_param(debug_quirks2, uint, 0444);
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2006-06-30 17:22:31 +08:00
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2009-04-09 02:14:54 +08:00
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MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
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2008-03-19 00:35:49 +08:00
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MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
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2006-03-24 19:18:17 +08:00
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MODULE_LICENSE("GPL");
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2006-06-30 17:22:31 +08:00
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2006-06-30 17:22:31 +08:00
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MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
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2011-10-03 20:33:34 +08:00
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MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
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