2019-06-04 16:11:33 +08:00
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/* SPDX-License-Identifier: GPL-2.0-only */
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2013-11-13 01:46:16 +08:00
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/*
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* AMD Cryptographic Coprocessor (CCP) driver
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*
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2017-07-18 04:00:49 +08:00
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* Copyright (C) 2013,2017 Advanced Micro Devices, Inc.
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2013-11-13 01:46:16 +08:00
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*
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* Author: Tom Lendacky <thomas.lendacky@amd.com>
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2016-07-27 08:09:20 +08:00
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* Author: Gary R Hook <gary.hook@amd.com>
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2013-11-13 01:46:16 +08:00
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*/
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#ifndef __CCP_DEV_H__
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#define __CCP_DEV_H__
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#include <linux/device.h>
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#include <linux/spinlock.h>
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#include <linux/mutex.h>
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#include <linux/list.h>
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#include <linux/wait.h>
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2019-08-03 07:20:11 +08:00
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#include <linux/dma-direction.h>
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2013-11-13 01:46:16 +08:00
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#include <linux/dmapool.h>
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#include <linux/hw_random.h>
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2015-02-04 03:07:05 +08:00
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#include <linux/bitops.h>
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2016-04-18 22:21:44 +08:00
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#include <linux/interrupt.h>
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#include <linux/irqreturn.h>
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#include <linux/dmaengine.h>
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2013-11-13 01:46:16 +08:00
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2017-07-06 22:59:14 +08:00
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#include "sp-dev.h"
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2016-03-02 03:49:04 +08:00
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#define MAX_CCP_NAME_LEN 16
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2013-11-13 01:46:16 +08:00
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#define MAX_DMAPOOL_NAME_LEN 32
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#define MAX_HW_QUEUES 5
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#define MAX_CMD_QLEN 100
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#define TRNG_RETRIES 10
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2014-07-10 23:58:35 +08:00
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#define CACHE_NONE 0x00
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2014-06-05 23:17:57 +08:00
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#define CACHE_WB_NO_ALLOC 0xb7
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2013-11-13 01:46:16 +08:00
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/****** Register Mappings ******/
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#define Q_MASK_REG 0x000
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#define TRNG_OUT_REG 0x00c
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#define IRQ_MASK_REG 0x040
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#define IRQ_STATUS_REG 0x200
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#define DEL_CMD_Q_JOB 0x124
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#define DEL_Q_ACTIVE 0x00000200
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#define DEL_Q_ID_SHIFT 6
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#define CMD_REQ0 0x180
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#define CMD_REQ_INCR 0x04
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#define CMD_Q_STATUS_BASE 0x210
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#define CMD_Q_INT_STATUS_BASE 0x214
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#define CMD_Q_STATUS_INCR 0x20
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2014-06-05 23:17:57 +08:00
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#define CMD_Q_CACHE_BASE 0x228
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2013-11-13 01:46:16 +08:00
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#define CMD_Q_CACHE_INC 0x20
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2015-02-04 03:07:05 +08:00
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#define CMD_Q_ERROR(__qs) ((__qs) & 0x0000003f)
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#define CMD_Q_DEPTH(__qs) (((__qs) >> 12) & 0x0000000f)
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2013-11-13 01:46:16 +08:00
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2016-07-27 08:10:21 +08:00
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/* ------------------------ CCP Version 5 Specifics ------------------------ */
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#define CMD5_QUEUE_MASK_OFFSET 0x00
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2016-07-27 08:10:49 +08:00
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#define CMD5_QUEUE_PRIO_OFFSET 0x04
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2016-07-27 08:10:21 +08:00
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#define CMD5_REQID_CONFIG_OFFSET 0x08
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2016-07-27 08:10:49 +08:00
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#define CMD5_CMD_TIMEOUT_OFFSET 0x10
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2016-07-27 08:10:21 +08:00
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#define LSB_PUBLIC_MASK_LO_OFFSET 0x18
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#define LSB_PUBLIC_MASK_HI_OFFSET 0x1C
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#define LSB_PRIVATE_MASK_LO_OFFSET 0x20
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#define LSB_PRIVATE_MASK_HI_OFFSET 0x24
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2017-05-03 06:33:40 +08:00
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#define CMD5_PSP_CCP_VERSION 0x100
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2016-07-27 08:10:21 +08:00
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#define CMD5_Q_CONTROL_BASE 0x0000
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#define CMD5_Q_TAIL_LO_BASE 0x0004
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#define CMD5_Q_HEAD_LO_BASE 0x0008
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#define CMD5_Q_INT_ENABLE_BASE 0x000C
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#define CMD5_Q_INTERRUPT_STATUS_BASE 0x0010
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#define CMD5_Q_STATUS_BASE 0x0100
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#define CMD5_Q_INT_STATUS_BASE 0x0104
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#define CMD5_Q_DMA_STATUS_BASE 0x0108
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#define CMD5_Q_DMA_READ_STATUS_BASE 0x010C
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#define CMD5_Q_DMA_WRITE_STATUS_BASE 0x0110
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#define CMD5_Q_ABORT_BASE 0x0114
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#define CMD5_Q_AX_CACHE_BASE 0x0118
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2016-07-27 08:10:49 +08:00
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#define CMD5_CONFIG_0_OFFSET 0x6000
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#define CMD5_TRNG_CTL_OFFSET 0x6008
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#define CMD5_AES_MASK_OFFSET 0x6010
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#define CMD5_CLK_GATE_CTL_OFFSET 0x603C
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2016-07-27 08:10:21 +08:00
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/* Address offset between two virtual queue registers */
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#define CMD5_Q_STATUS_INCR 0x1000
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/* Bit masks */
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#define CMD5_Q_RUN 0x1
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#define CMD5_Q_HALT 0x2
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#define CMD5_Q_MEM_LOCATION 0x4
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#define CMD5_Q_SIZE 0x1F
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#define CMD5_Q_SHIFT 3
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#define COMMANDS_PER_QUEUE 16
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#define QUEUE_SIZE_VAL ((ffs(COMMANDS_PER_QUEUE) - 2) & \
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CMD5_Q_SIZE)
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#define Q_PTR_MASK (2 << (QUEUE_SIZE_VAL + 5) - 1)
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#define Q_DESC_SIZE sizeof(struct ccp5_desc)
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#define Q_SIZE(n) (COMMANDS_PER_QUEUE*(n))
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#define INT_COMPLETION 0x1
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#define INT_ERROR 0x2
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#define INT_QUEUE_STOPPED 0x4
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2017-04-21 04:24:09 +08:00
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#define INT_EMPTY_QUEUE 0x8
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#define SUPPORTED_INTERRUPTS (INT_COMPLETION | INT_ERROR)
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2016-07-27 08:10:21 +08:00
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#define LSB_REGION_WIDTH 5
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#define MAX_LSB_CNT 8
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#define LSB_SIZE 16
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#define LSB_ITEM_SIZE 32
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#define PLSB_MAP_SIZE (LSB_SIZE)
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#define SLSB_MAP_SIZE (MAX_LSB_CNT * LSB_SIZE)
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#define LSB_ENTRY_NUMBER(LSB_ADDR) (LSB_ADDR / LSB_ITEM_SIZE)
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/* ------------------------ CCP Version 3 Specifics ------------------------ */
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2013-11-13 01:46:16 +08:00
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#define REQ0_WAIT_FOR_WRITE 0x00000004
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#define REQ0_INT_ON_COMPLETE 0x00000002
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#define REQ0_STOP_ON_COMPLETE 0x00000001
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#define REQ0_CMD_Q_SHIFT 9
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#define REQ0_JOBID_SHIFT 3
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/****** REQ1 Related Values ******/
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#define REQ1_PROTECT_SHIFT 27
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#define REQ1_ENGINE_SHIFT 23
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#define REQ1_KEY_KSB_SHIFT 2
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#define REQ1_EOM 0x00000002
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#define REQ1_INIT 0x00000001
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/* AES Related Values */
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#define REQ1_AES_TYPE_SHIFT 21
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#define REQ1_AES_MODE_SHIFT 18
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#define REQ1_AES_ACTION_SHIFT 17
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#define REQ1_AES_CFB_SIZE_SHIFT 10
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/* XTS-AES Related Values */
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#define REQ1_XTS_AES_SIZE_SHIFT 10
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/* SHA Related Values */
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#define REQ1_SHA_TYPE_SHIFT 21
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/* RSA Related Values */
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#define REQ1_RSA_MOD_SIZE_SHIFT 10
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/* Pass-Through Related Values */
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#define REQ1_PT_BW_SHIFT 12
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#define REQ1_PT_BS_SHIFT 10
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/* ECC Related Values */
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#define REQ1_ECC_AFFINE_CONVERT 0x00200000
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#define REQ1_ECC_FUNCTION_SHIFT 18
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/****** REQ4 Related Values ******/
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#define REQ4_KSB_SHIFT 18
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#define REQ4_MEMTYPE_SHIFT 16
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/****** REQ6 Related Values ******/
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#define REQ6_MEMTYPE_SHIFT 16
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/****** Key Storage Block ******/
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#define KSB_START 77
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#define KSB_END 127
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#define KSB_COUNT (KSB_END - KSB_START + 1)
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2016-07-27 08:09:40 +08:00
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#define CCP_SB_BITS 256
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2013-11-13 01:46:16 +08:00
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#define CCP_JOBID_MASK 0x0000003f
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2016-07-27 08:10:21 +08:00
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/* ------------------------ General CCP Defines ------------------------ */
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2017-03-24 01:53:30 +08:00
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#define CCP_DMA_DFLT 0x0
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#define CCP_DMA_PRIV 0x1
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#define CCP_DMA_PUB 0x2
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2013-11-13 01:46:16 +08:00
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#define CCP_DMAPOOL_MAX_SIZE 64
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2015-02-04 03:07:05 +08:00
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#define CCP_DMAPOOL_ALIGN BIT(5)
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2013-11-13 01:46:16 +08:00
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#define CCP_REVERSE_BUF_SIZE 64
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2016-07-27 08:09:40 +08:00
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#define CCP_AES_KEY_SB_COUNT 1
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#define CCP_AES_CTX_SB_COUNT 1
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2013-11-13 01:46:16 +08:00
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2016-07-27 08:09:40 +08:00
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#define CCP_XTS_AES_KEY_SB_COUNT 1
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2017-07-26 03:12:11 +08:00
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#define CCP5_XTS_AES_KEY_SB_COUNT 2
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2016-07-27 08:09:40 +08:00
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#define CCP_XTS_AES_CTX_SB_COUNT 1
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2013-11-13 01:46:16 +08:00
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2017-03-16 02:20:52 +08:00
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#define CCP_DES3_KEY_SB_COUNT 1
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#define CCP_DES3_CTX_SB_COUNT 1
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2016-07-27 08:09:40 +08:00
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#define CCP_SHA_SB_COUNT 1
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2013-11-13 01:46:16 +08:00
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#define CCP_RSA_MAX_WIDTH 4096
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2017-07-18 04:16:42 +08:00
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#define CCP5_RSA_MAX_WIDTH 16384
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2013-11-13 01:46:16 +08:00
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#define CCP_PASSTHRU_BLOCKSIZE 256
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#define CCP_PASSTHRU_MASKSIZE 32
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2016-07-27 08:09:40 +08:00
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#define CCP_PASSTHRU_SB_COUNT 1
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2013-11-13 01:46:16 +08:00
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#define CCP_ECC_MODULUS_BYTES 48 /* 384-bits */
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#define CCP_ECC_MAX_OPERANDS 6
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#define CCP_ECC_MAX_OUTPUTS 3
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#define CCP_ECC_SRC_BUF_SIZE 448
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#define CCP_ECC_DST_BUF_SIZE 192
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#define CCP_ECC_OPERAND_SIZE 64
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#define CCP_ECC_OUTPUT_SIZE 64
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#define CCP_ECC_RESULT_OFFSET 60
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#define CCP_ECC_RESULT_SUCCESS 0x0001
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2016-07-27 08:09:40 +08:00
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#define CCP_SB_BYTES 32
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2016-03-02 03:49:25 +08:00
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struct ccp_op;
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2013-11-13 01:46:16 +08:00
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struct ccp_device;
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struct ccp_cmd;
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2016-07-27 08:10:21 +08:00
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struct ccp_fns;
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2013-11-13 01:46:16 +08:00
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2016-04-18 22:21:44 +08:00
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struct ccp_dma_cmd {
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struct list_head entry;
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struct ccp_cmd ccp_cmd;
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};
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struct ccp_dma_desc {
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struct list_head entry;
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struct ccp_device *ccp;
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struct list_head pending;
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struct list_head active;
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enum dma_status status;
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struct dma_async_tx_descriptor tx_desc;
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size_t len;
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};
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struct ccp_dma_chan {
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struct ccp_device *ccp;
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spinlock_t lock;
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2017-01-28 07:09:04 +08:00
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struct list_head created;
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2016-04-18 22:21:44 +08:00
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struct list_head pending;
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struct list_head active;
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struct list_head complete;
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struct tasklet_struct cleanup_tasklet;
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enum dma_status status;
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struct dma_chan dma_chan;
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};
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2013-11-13 01:46:16 +08:00
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struct ccp_cmd_queue {
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struct ccp_device *ccp;
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/* Queue identifier */
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u32 id;
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/* Queue dma pool */
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struct dma_pool *dma_pool;
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2016-07-27 08:10:21 +08:00
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/* Queue base address (not neccessarily aligned)*/
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struct ccp5_desc *qbase;
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/* Aligned queue start address (per requirement) */
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struct mutex q_mutex ____cacheline_aligned;
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unsigned int qidx;
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/* Version 5 has different requirements for queue memory */
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unsigned int qsize;
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dma_addr_t qbase_dma;
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dma_addr_t qdma_tail;
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2016-07-27 08:09:40 +08:00
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/* Per-queue reserved storage block(s) */
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u32 sb_key;
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u32 sb_ctx;
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2013-11-13 01:46:16 +08:00
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2016-07-27 08:10:21 +08:00
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/* Bitmap of LSBs that can be accessed by this queue */
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DECLARE_BITMAP(lsbmask, MAX_LSB_CNT);
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/* Private LSB that is assigned to this queue, or -1 if none.
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* Bitmap for my private LSB, unused otherwise
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*/
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2016-10-12 21:47:03 +08:00
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int lsb;
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2016-07-27 08:10:21 +08:00
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DECLARE_BITMAP(lsbmap, PLSB_MAP_SIZE);
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2013-11-13 01:46:16 +08:00
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/* Queue processing thread */
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struct task_struct *kthread;
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unsigned int active;
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unsigned int suspended;
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/* Number of free command slots available */
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unsigned int free_slots;
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/* Interrupt masks */
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u32 int_ok;
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u32 int_err;
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/* Register addresses for queue */
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2016-07-27 08:10:21 +08:00
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void __iomem *reg_control;
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void __iomem *reg_tail_lo;
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void __iomem *reg_head_lo;
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void __iomem *reg_int_enable;
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void __iomem *reg_interrupt_status;
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2013-11-13 01:46:16 +08:00
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void __iomem *reg_status;
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void __iomem *reg_int_status;
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2016-07-27 08:10:21 +08:00
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void __iomem *reg_dma_status;
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void __iomem *reg_dma_read_status;
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void __iomem *reg_dma_write_status;
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u32 qcontrol; /* Cached control register */
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2013-11-13 01:46:16 +08:00
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/* Status values from job */
|
|
|
|
u32 int_status;
|
|
|
|
u32 q_status;
|
|
|
|
u32 q_int_status;
|
|
|
|
u32 cmd_error;
|
|
|
|
|
|
|
|
/* Interrupt wait queue */
|
|
|
|
wait_queue_head_t int_queue;
|
|
|
|
unsigned int int_rcvd;
|
2017-05-03 06:33:40 +08:00
|
|
|
|
|
|
|
/* Per-queue Statistics */
|
|
|
|
unsigned long total_ops;
|
|
|
|
unsigned long total_aes_ops;
|
|
|
|
unsigned long total_xts_aes_ops;
|
|
|
|
unsigned long total_3des_ops;
|
|
|
|
unsigned long total_sha_ops;
|
|
|
|
unsigned long total_rsa_ops;
|
|
|
|
unsigned long total_pt_ops;
|
|
|
|
unsigned long total_ecc_ops;
|
2013-11-13 01:46:16 +08:00
|
|
|
} ____cacheline_aligned;
|
|
|
|
|
|
|
|
struct ccp_device {
|
2016-03-02 03:49:04 +08:00
|
|
|
struct list_head entry;
|
|
|
|
|
2016-03-02 03:49:15 +08:00
|
|
|
struct ccp_vdata *vdata;
|
2016-03-02 03:49:04 +08:00
|
|
|
unsigned int ord;
|
|
|
|
char name[MAX_CCP_NAME_LEN];
|
|
|
|
char rngname[MAX_CCP_NAME_LEN];
|
|
|
|
|
2013-11-13 01:46:16 +08:00
|
|
|
struct device *dev;
|
2017-07-06 22:59:14 +08:00
|
|
|
struct sp_device *sp;
|
2013-11-13 01:46:16 +08:00
|
|
|
|
2016-07-27 07:09:46 +08:00
|
|
|
/* Bus specific device information
|
2013-11-13 01:46:16 +08:00
|
|
|
*/
|
|
|
|
void *dev_specific;
|
2017-04-21 23:50:05 +08:00
|
|
|
unsigned int qim;
|
2014-06-05 23:17:45 +08:00
|
|
|
unsigned int irq;
|
2017-04-21 23:50:05 +08:00
|
|
|
bool use_tasklet;
|
|
|
|
struct tasklet_struct irq_tasklet;
|
2013-11-13 01:46:16 +08:00
|
|
|
|
2016-07-27 07:09:46 +08:00
|
|
|
/* I/O area used for device communication. The register mapping
|
2013-11-13 01:46:16 +08:00
|
|
|
* starts at an offset into the mapped bar.
|
|
|
|
* The CMD_REQx registers and the Delete_Cmd_Queue_Job register
|
|
|
|
* need to be protected while a command queue thread is accessing
|
|
|
|
* them.
|
|
|
|
*/
|
|
|
|
struct mutex req_mutex ____cacheline_aligned;
|
|
|
|
void __iomem *io_regs;
|
|
|
|
|
2016-07-27 07:09:46 +08:00
|
|
|
/* Master lists that all cmds are queued on. Because there can be
|
2013-11-13 01:46:16 +08:00
|
|
|
* more than one CCP command queue that can process a cmd a separate
|
|
|
|
* backlog list is neeeded so that the backlog completion call
|
|
|
|
* completes before the cmd is available for execution.
|
|
|
|
*/
|
|
|
|
spinlock_t cmd_lock ____cacheline_aligned;
|
|
|
|
unsigned int cmd_count;
|
|
|
|
struct list_head cmd;
|
|
|
|
struct list_head backlog;
|
|
|
|
|
2016-07-27 07:09:46 +08:00
|
|
|
/* The command queues. These represent the queues available on the
|
2013-11-13 01:46:16 +08:00
|
|
|
* CCP that are available for processing cmds
|
|
|
|
*/
|
|
|
|
struct ccp_cmd_queue cmd_q[MAX_HW_QUEUES];
|
|
|
|
unsigned int cmd_q_count;
|
2019-07-09 23:07:22 +08:00
|
|
|
unsigned int max_q_count;
|
2013-11-13 01:46:16 +08:00
|
|
|
|
2016-07-27 07:09:46 +08:00
|
|
|
/* Support for the CCP True RNG
|
2013-11-13 01:46:16 +08:00
|
|
|
*/
|
|
|
|
struct hwrng hwrng;
|
|
|
|
unsigned int hwrng_retries;
|
|
|
|
|
2016-07-27 07:09:46 +08:00
|
|
|
/* Support for the CCP DMA capabilities
|
2016-04-18 22:21:44 +08:00
|
|
|
*/
|
|
|
|
struct dma_device dma_dev;
|
|
|
|
struct ccp_dma_chan *ccp_dma_chan;
|
|
|
|
struct kmem_cache *dma_cmd_cache;
|
|
|
|
struct kmem_cache *dma_desc_cache;
|
|
|
|
|
2016-07-27 07:09:46 +08:00
|
|
|
/* A counter used to generate job-ids for cmds submitted to the CCP
|
2013-11-13 01:46:16 +08:00
|
|
|
*/
|
|
|
|
atomic_t current_id ____cacheline_aligned;
|
|
|
|
|
2016-07-27 08:09:50 +08:00
|
|
|
/* The v3 CCP uses key storage blocks (SB) to maintain context for
|
|
|
|
* certain operations. To prevent multiple cmds from using the same
|
|
|
|
* SB range a command queue reserves an SB range for the duration of
|
|
|
|
* the cmd. Each queue, will however, reserve 2 SB blocks for
|
|
|
|
* operations that only require single SB entries (eg. AES context/iv
|
|
|
|
* and key) in order to avoid allocation contention. This will reserve
|
|
|
|
* at most 10 SB entries, leaving 40 SB entries available for dynamic
|
|
|
|
* allocation.
|
|
|
|
*
|
|
|
|
* The v5 CCP Local Storage Block (LSB) is broken up into 8
|
|
|
|
* memrory ranges, each of which can be enabled for access by one
|
|
|
|
* or more queues. Device initialization takes this into account,
|
|
|
|
* and attempts to assign one region for exclusive use by each
|
|
|
|
* available queue; the rest are then aggregated as "public" use.
|
|
|
|
* If there are fewer regions than queues, all regions are shared
|
|
|
|
* amongst all queues.
|
2013-11-13 01:46:16 +08:00
|
|
|
*/
|
2016-07-27 08:09:40 +08:00
|
|
|
struct mutex sb_mutex ____cacheline_aligned;
|
|
|
|
DECLARE_BITMAP(sb, KSB_COUNT);
|
|
|
|
wait_queue_head_t sb_queue;
|
|
|
|
unsigned int sb_avail;
|
|
|
|
unsigned int sb_count;
|
|
|
|
u32 sb_start;
|
2013-11-13 01:46:16 +08:00
|
|
|
|
2016-07-27 08:10:21 +08:00
|
|
|
/* Bitmap of shared LSBs, if any */
|
|
|
|
DECLARE_BITMAP(lsbmap, SLSB_MAP_SIZE);
|
|
|
|
|
2013-11-13 01:46:16 +08:00
|
|
|
/* Suspend support */
|
|
|
|
unsigned int suspending;
|
|
|
|
wait_queue_head_t suspend_queue;
|
2014-07-10 23:58:35 +08:00
|
|
|
|
|
|
|
/* DMA caching attribute support */
|
|
|
|
unsigned int axcache;
|
2017-05-03 06:33:40 +08:00
|
|
|
|
|
|
|
/* Device Statistics */
|
|
|
|
unsigned long total_interrupts;
|
|
|
|
|
|
|
|
/* DebugFS info */
|
|
|
|
struct dentry *debugfs_instance;
|
2013-11-13 01:46:16 +08:00
|
|
|
};
|
|
|
|
|
2016-03-02 03:49:25 +08:00
|
|
|
enum ccp_memtype {
|
|
|
|
CCP_MEMTYPE_SYSTEM = 0,
|
2016-07-27 08:09:40 +08:00
|
|
|
CCP_MEMTYPE_SB,
|
2016-03-02 03:49:25 +08:00
|
|
|
CCP_MEMTYPE_LOCAL,
|
|
|
|
CCP_MEMTYPE__LAST,
|
|
|
|
};
|
2016-07-27 08:10:21 +08:00
|
|
|
#define CCP_MEMTYPE_LSB CCP_MEMTYPE_KSB
|
2016-03-02 03:49:25 +08:00
|
|
|
|
2017-03-28 23:57:26 +08:00
|
|
|
|
2016-03-02 03:49:25 +08:00
|
|
|
struct ccp_dma_info {
|
|
|
|
dma_addr_t address;
|
|
|
|
unsigned int offset;
|
|
|
|
unsigned int length;
|
|
|
|
enum dma_data_direction dir;
|
2017-03-28 23:57:26 +08:00
|
|
|
} __packed __aligned(4);
|
2016-03-02 03:49:25 +08:00
|
|
|
|
|
|
|
struct ccp_dm_workarea {
|
|
|
|
struct device *dev;
|
|
|
|
struct dma_pool *dma_pool;
|
|
|
|
|
|
|
|
u8 *address;
|
|
|
|
struct ccp_dma_info dma;
|
2017-03-28 23:57:26 +08:00
|
|
|
unsigned int length;
|
2016-03-02 03:49:25 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
struct ccp_sg_workarea {
|
|
|
|
struct scatterlist *sg;
|
|
|
|
int nents;
|
2017-03-28 23:57:26 +08:00
|
|
|
unsigned int sg_used;
|
2016-03-02 03:49:25 +08:00
|
|
|
|
|
|
|
struct scatterlist *dma_sg;
|
2020-06-23 04:24:02 +08:00
|
|
|
struct scatterlist *dma_sg_head;
|
2016-03-02 03:49:25 +08:00
|
|
|
struct device *dma_dev;
|
|
|
|
unsigned int dma_count;
|
|
|
|
enum dma_data_direction dma_dir;
|
|
|
|
|
|
|
|
u64 bytes_left;
|
|
|
|
};
|
|
|
|
|
|
|
|
struct ccp_data {
|
|
|
|
struct ccp_sg_workarea sg_wa;
|
|
|
|
struct ccp_dm_workarea dm_wa;
|
|
|
|
};
|
|
|
|
|
|
|
|
struct ccp_mem {
|
|
|
|
enum ccp_memtype type;
|
|
|
|
union {
|
|
|
|
struct ccp_dma_info dma;
|
2016-07-27 08:09:40 +08:00
|
|
|
u32 sb;
|
2016-03-02 03:49:25 +08:00
|
|
|
} u;
|
|
|
|
};
|
|
|
|
|
|
|
|
struct ccp_aes_op {
|
|
|
|
enum ccp_aes_type type;
|
|
|
|
enum ccp_aes_mode mode;
|
|
|
|
enum ccp_aes_action action;
|
2017-02-09 03:07:06 +08:00
|
|
|
unsigned int size;
|
2016-03-02 03:49:25 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
struct ccp_xts_aes_op {
|
2017-07-26 03:12:11 +08:00
|
|
|
enum ccp_aes_type type;
|
2016-03-02 03:49:25 +08:00
|
|
|
enum ccp_aes_action action;
|
|
|
|
enum ccp_xts_aes_unit_size unit_size;
|
|
|
|
};
|
|
|
|
|
2017-03-16 02:20:52 +08:00
|
|
|
struct ccp_des3_op {
|
|
|
|
enum ccp_des3_type type;
|
|
|
|
enum ccp_des3_mode mode;
|
|
|
|
enum ccp_des3_action action;
|
|
|
|
};
|
|
|
|
|
2016-03-02 03:49:25 +08:00
|
|
|
struct ccp_sha_op {
|
|
|
|
enum ccp_sha_type type;
|
|
|
|
u64 msg_bits;
|
|
|
|
};
|
|
|
|
|
|
|
|
struct ccp_rsa_op {
|
|
|
|
u32 mod_size;
|
|
|
|
u32 input_len;
|
|
|
|
};
|
|
|
|
|
|
|
|
struct ccp_passthru_op {
|
|
|
|
enum ccp_passthru_bitwise bit_mod;
|
|
|
|
enum ccp_passthru_byteswap byte_swap;
|
|
|
|
};
|
|
|
|
|
|
|
|
struct ccp_ecc_op {
|
|
|
|
enum ccp_ecc_function function;
|
|
|
|
};
|
|
|
|
|
|
|
|
struct ccp_op {
|
|
|
|
struct ccp_cmd_queue *cmd_q;
|
|
|
|
|
|
|
|
u32 jobid;
|
|
|
|
u32 ioc;
|
|
|
|
u32 soc;
|
2016-07-27 08:09:40 +08:00
|
|
|
u32 sb_key;
|
|
|
|
u32 sb_ctx;
|
2016-03-02 03:49:25 +08:00
|
|
|
u32 init;
|
|
|
|
u32 eom;
|
|
|
|
|
|
|
|
struct ccp_mem src;
|
|
|
|
struct ccp_mem dst;
|
2016-07-27 08:10:21 +08:00
|
|
|
struct ccp_mem exp;
|
2016-03-02 03:49:25 +08:00
|
|
|
|
|
|
|
union {
|
|
|
|
struct ccp_aes_op aes;
|
|
|
|
struct ccp_xts_aes_op xts;
|
2017-03-16 02:20:52 +08:00
|
|
|
struct ccp_des3_op des3;
|
2016-03-02 03:49:25 +08:00
|
|
|
struct ccp_sha_op sha;
|
|
|
|
struct ccp_rsa_op rsa;
|
|
|
|
struct ccp_passthru_op passthru;
|
|
|
|
struct ccp_ecc_op ecc;
|
|
|
|
} u;
|
|
|
|
};
|
|
|
|
|
|
|
|
static inline u32 ccp_addr_lo(struct ccp_dma_info *info)
|
|
|
|
{
|
|
|
|
return lower_32_bits(info->address + info->offset);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline u32 ccp_addr_hi(struct ccp_dma_info *info)
|
|
|
|
{
|
|
|
|
return upper_32_bits(info->address + info->offset) & 0x0000ffff;
|
|
|
|
}
|
|
|
|
|
2016-07-27 08:10:21 +08:00
|
|
|
/**
|
|
|
|
* descriptor for version 5 CPP commands
|
|
|
|
* 8 32-bit words:
|
|
|
|
* word 0: function; engine; control bits
|
|
|
|
* word 1: length of source data
|
|
|
|
* word 2: low 32 bits of source pointer
|
|
|
|
* word 3: upper 16 bits of source pointer; source memory type
|
|
|
|
* word 4: low 32 bits of destination pointer
|
|
|
|
* word 5: upper 16 bits of destination pointer; destination memory type
|
|
|
|
* word 6: low 32 bits of key pointer
|
|
|
|
* word 7: upper 16 bits of key pointer; key memory type
|
|
|
|
*/
|
|
|
|
struct dword0 {
|
2016-10-19 06:28:35 +08:00
|
|
|
unsigned int soc:1;
|
|
|
|
unsigned int ioc:1;
|
|
|
|
unsigned int rsvd1:1;
|
|
|
|
unsigned int init:1;
|
|
|
|
unsigned int eom:1; /* AES/SHA only */
|
|
|
|
unsigned int function:15;
|
|
|
|
unsigned int engine:4;
|
|
|
|
unsigned int prot:1;
|
|
|
|
unsigned int rsvd2:7;
|
2016-07-27 08:10:21 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
struct dword3 {
|
2016-10-19 06:28:35 +08:00
|
|
|
unsigned int src_hi:16;
|
|
|
|
unsigned int src_mem:2;
|
|
|
|
unsigned int lsb_cxt_id:8;
|
|
|
|
unsigned int rsvd1:5;
|
|
|
|
unsigned int fixed:1;
|
2016-07-27 08:10:21 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
union dword4 {
|
2020-07-03 12:46:52 +08:00
|
|
|
u32 dst_lo; /* NON-SHA */
|
|
|
|
u32 sha_len_lo; /* SHA */
|
2016-07-27 08:10:21 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
union dword5 {
|
|
|
|
struct {
|
2016-10-19 06:28:35 +08:00
|
|
|
unsigned int dst_hi:16;
|
|
|
|
unsigned int dst_mem:2;
|
|
|
|
unsigned int rsvd1:13;
|
|
|
|
unsigned int fixed:1;
|
2016-07-27 08:10:21 +08:00
|
|
|
} fields;
|
2020-07-03 12:46:52 +08:00
|
|
|
u32 sha_len_hi;
|
2016-07-27 08:10:21 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
struct dword7 {
|
2016-10-19 06:28:35 +08:00
|
|
|
unsigned int key_hi:16;
|
|
|
|
unsigned int key_mem:2;
|
|
|
|
unsigned int rsvd1:14;
|
2016-07-27 08:10:21 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
struct ccp5_desc {
|
|
|
|
struct dword0 dw0;
|
2020-07-03 12:46:52 +08:00
|
|
|
u32 length;
|
|
|
|
u32 src_lo;
|
2016-07-27 08:10:21 +08:00
|
|
|
struct dword3 dw3;
|
|
|
|
union dword4 dw4;
|
|
|
|
union dword5 dw5;
|
2020-07-03 12:46:52 +08:00
|
|
|
u32 key_lo;
|
2016-07-27 08:10:21 +08:00
|
|
|
struct dword7 dw7;
|
|
|
|
};
|
|
|
|
|
2016-03-02 03:49:25 +08:00
|
|
|
void ccp_add_device(struct ccp_device *ccp);
|
|
|
|
void ccp_del_device(struct ccp_device *ccp);
|
|
|
|
|
2019-06-28 00:16:23 +08:00
|
|
|
extern void ccp_log_error(struct ccp_device *, unsigned int);
|
2016-09-29 00:53:56 +08:00
|
|
|
|
2017-07-06 22:59:14 +08:00
|
|
|
struct ccp_device *ccp_alloc_struct(struct sp_device *sp);
|
2013-11-13 01:46:16 +08:00
|
|
|
bool ccp_queues_suspended(struct ccp_device *ccp);
|
2016-03-02 03:49:25 +08:00
|
|
|
int ccp_cmd_queue_thread(void *data);
|
2016-07-27 08:10:02 +08:00
|
|
|
int ccp_trng_read(struct hwrng *rng, void *data, size_t max, bool wait);
|
2013-11-13 01:46:16 +08:00
|
|
|
|
|
|
|
int ccp_run_cmd(struct ccp_cmd_queue *cmd_q, struct ccp_cmd *cmd);
|
|
|
|
|
2016-07-27 08:10:31 +08:00
|
|
|
int ccp_register_rng(struct ccp_device *ccp);
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void ccp_unregister_rng(struct ccp_device *ccp);
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2016-04-18 22:21:44 +08:00
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int ccp_dmaengine_register(struct ccp_device *ccp);
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void ccp_dmaengine_unregister(struct ccp_device *ccp);
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2017-05-03 06:33:40 +08:00
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void ccp5_debugfs_setup(struct ccp_device *ccp);
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void ccp5_debugfs_destroy(void);
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2016-07-27 08:09:50 +08:00
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/* Structure for computation functions that are device-specific */
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struct ccp_actions {
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int (*aes)(struct ccp_op *);
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int (*xts_aes)(struct ccp_op *);
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2017-03-16 02:20:52 +08:00
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int (*des3)(struct ccp_op *);
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2016-07-27 08:09:50 +08:00
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int (*sha)(struct ccp_op *);
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int (*rsa)(struct ccp_op *);
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int (*passthru)(struct ccp_op *);
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int (*ecc)(struct ccp_op *);
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u32 (*sballoc)(struct ccp_cmd_queue *, unsigned int);
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2017-03-16 02:20:52 +08:00
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void (*sbfree)(struct ccp_cmd_queue *, unsigned int, unsigned int);
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2016-07-27 08:10:13 +08:00
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unsigned int (*get_free_slots)(struct ccp_cmd_queue *);
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2016-07-27 08:09:50 +08:00
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int (*init)(struct ccp_device *);
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void (*destroy)(struct ccp_device *);
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irqreturn_t (*irqhandler)(int, void *);
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};
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2017-07-06 22:59:13 +08:00
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extern const struct ccp_vdata ccpv3_platform;
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2016-09-29 00:53:47 +08:00
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extern const struct ccp_vdata ccpv3;
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extern const struct ccp_vdata ccpv5a;
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extern const struct ccp_vdata ccpv5b;
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2016-07-27 08:09:50 +08:00
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2013-11-13 01:46:16 +08:00
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#endif
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