2016-11-11 05:17:40 +08:00
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==================================
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ASoC Digital Audio Interface (DAI)
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==================================
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2006-10-07 00:34:51 +08:00
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ASoC currently supports the three main Digital Audio Interfaces (DAI) found on
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2008-01-23 15:41:46 +08:00
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SoC controllers and portable audio CODECs today, namely AC97, I2S and PCM.
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2006-10-07 00:34:51 +08:00
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AC97
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====
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2016-11-11 05:17:40 +08:00
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AC97 is a five wire interface commonly found on many PC sound cards. It is
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2006-10-07 00:34:51 +08:00
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now also popular in many portable devices. This DAI has a reset line and time
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multiplexes its data on its SDATA_OUT (playback) and SDATA_IN (capture) lines.
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The bit clock (BCLK) is always driven by the CODEC (usually 12.288MHz) and the
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frame (FRAME) (usually 48kHz) is always driven by the controller. Each AC97
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frame is 21uS long and is divided into 13 time slots.
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2016-11-11 05:17:40 +08:00
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The AC97 specification can be found at :
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2020-07-19 23:38:22 +08:00
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https://www.intel.com/p/en_US/business/design
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2006-10-07 00:34:51 +08:00
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I2S
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===
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2016-11-11 05:17:40 +08:00
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I2S is a common 4 wire DAI used in HiFi, STB and portable devices. The Tx and
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2018-11-19 19:02:45 +08:00
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Rx lines are used for audio transmission, while the bit clock (BCLK) and
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2006-10-07 00:34:51 +08:00
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left/right clock (LRC) synchronise the link. I2S is flexible in that either the
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controller or CODEC can drive (master) the BCLK and LRC clock lines. Bit clock
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usually varies depending on the sample rate and the master system clock
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(SYSCLK). LRCLK is the same as the sample rate. A few devices support separate
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2008-01-23 15:41:46 +08:00
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ADC and DAC LRCLKs, this allows for simultaneous capture and playback at
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2006-10-07 00:34:51 +08:00
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different sample rates.
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I2S has several different operating modes:-
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2016-11-11 05:17:40 +08:00
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I2S
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MSB is transmitted on the falling edge of the first BCLK after LRC
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transition.
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2006-10-07 00:34:51 +08:00
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2016-11-11 05:17:40 +08:00
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Left Justified
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MSB is transmitted on transition of LRC.
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2016-11-11 05:17:40 +08:00
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Right Justified
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MSB is transmitted sample size BCLKs before LRC transition.
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2006-10-07 00:34:51 +08:00
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PCM
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===
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2007-10-20 07:34:40 +08:00
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PCM is another 4 wire interface, very similar to I2S, which can support a more
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2006-10-07 00:34:51 +08:00
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flexible protocol. It has bit clock (BCLK) and sync (SYNC) lines that are used
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2018-11-19 19:02:45 +08:00
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to synchronise the link while the Tx and Rx lines are used to transmit and
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2006-10-07 00:34:51 +08:00
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receive the audio data. Bit clock usually varies depending on sample rate
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2018-11-19 19:02:45 +08:00
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while sync runs at the sample rate. PCM also supports Time Division
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Multiplexing (TDM) in that several devices can use the bus simultaneously (this
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2006-10-07 00:34:51 +08:00
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is sometimes referred to as network mode).
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Common PCM operating modes:-
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Mode A
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MSB is transmitted on falling edge of first BCLK after FRAME/SYNC.
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2006-10-07 00:34:51 +08:00
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2016-11-11 05:17:40 +08:00
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Mode B
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MSB is transmitted on rising edge of FRAME/SYNC.
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