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75 lines
2.1 KiB
C
75 lines
2.1 KiB
C
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/*
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* Copyright (c) 2015 Joachim Eastwood <manabian@gmail.com>
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*
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* This code is released using a dual license strategy: BSD/GPL
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* You can choose the licence that better fits your requirements.
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*
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* Released under the terms of 3-clause BSD License
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* Released under the terms of GNU General Public License Version 2.0
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*
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*/
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/* Clock Control Unit 1 (CCU1) clock offsets */
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#define CLK_APB3_BUS 0x100
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#define CLK_APB3_I2C1 0x108
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#define CLK_APB3_DAC 0x110
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#define CLK_APB3_ADC0 0x118
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#define CLK_APB3_ADC1 0x120
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#define CLK_APB3_CAN0 0x128
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#define CLK_APB1_BUS 0x200
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#define CLK_APB1_MOTOCON_PWM 0x208
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#define CLK_APB1_I2C0 0x210
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#define CLK_APB1_I2S 0x218
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#define CLK_APB1_CAN1 0x220
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#define CLK_SPIFI 0x300
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#define CLK_CPU_BUS 0x400
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#define CLK_CPU_SPIFI 0x408
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#define CLK_CPU_GPIO 0x410
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#define CLK_CPU_LCD 0x418
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#define CLK_CPU_ETHERNET 0x420
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#define CLK_CPU_USB0 0x428
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#define CLK_CPU_EMC 0x430
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#define CLK_CPU_SDIO 0x438
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#define CLK_CPU_DMA 0x440
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#define CLK_CPU_CORE 0x448
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#define CLK_CPU_SCT 0x468
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#define CLK_CPU_USB1 0x470
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#define CLK_CPU_EMCDIV 0x478
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#define CLK_CPU_FLASHA 0x480
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#define CLK_CPU_FLASHB 0x488
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#define CLK_CPU_M0APP 0x490
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#define CLK_CPU_ADCHS 0x498
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#define CLK_CPU_EEPROM 0x4a0
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#define CLK_CPU_WWDT 0x500
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#define CLK_CPU_UART0 0x508
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#define CLK_CPU_UART1 0x510
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#define CLK_CPU_SSP0 0x518
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#define CLK_CPU_TIMER0 0x520
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#define CLK_CPU_TIMER1 0x528
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#define CLK_CPU_SCU 0x530
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#define CLK_CPU_CREG 0x538
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#define CLK_CPU_RITIMER 0x600
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#define CLK_CPU_UART2 0x608
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#define CLK_CPU_UART3 0x610
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#define CLK_CPU_TIMER2 0x618
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#define CLK_CPU_TIMER3 0x620
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#define CLK_CPU_SSP1 0x628
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#define CLK_CPU_QEI 0x630
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#define CLK_PERIPH_BUS 0x700
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#define CLK_PERIPH_CORE 0x710
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#define CLK_PERIPH_SGPIO 0x718
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#define CLK_USB0 0x800
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#define CLK_USB1 0x900
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#define CLK_SPI 0xA00
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#define CLK_ADCHS 0xB00
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/* Clock Control Unit 2 (CCU2) clock offsets */
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#define CLK_AUDIO 0x100
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#define CLK_APB2_UART3 0x200
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#define CLK_APB2_UART2 0x300
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#define CLK_APB0_UART1 0x400
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#define CLK_APB0_UART0 0x500
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#define CLK_APB2_SSP1 0x600
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#define CLK_APB0_SSP0 0x700
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#define CLK_SDIO 0x800
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