2019-06-04 16:11:33 +08:00
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/* SPDX-License-Identifier: GPL-2.0-only */
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2009-05-29 01:56:16 +08:00
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/*
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* OMAP2/3 Power Management Routines
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*
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* Copyright (C) 2008 Nokia Corporation
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* Jouni Hogander
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*/
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#ifndef __ARCH_ARM_MACH_OMAP2_PM_H
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#define __ARCH_ARM_MACH_OMAP2_PM_H
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2010-05-30 00:32:23 +08:00
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#include <linux/err.h>
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2010-12-22 12:05:16 +08:00
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#include "powerdomain.h"
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2008-10-15 23:13:48 +08:00
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2012-05-10 18:02:57 +08:00
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#ifdef CONFIG_CPU_IDLE
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extern int __init omap3_idle_init(void);
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extern int __init omap4_idle_init(void);
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#else
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static inline int omap3_idle_init(void)
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{
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return 0;
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}
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static inline int omap4_idle_init(void)
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{
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return 0;
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}
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#endif
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2008-10-13 18:15:00 +08:00
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extern void *omap3_secure_ram_storage;
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2009-10-07 05:25:09 +08:00
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extern void omap3_pm_off_mode_enable(int);
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2023-01-13 03:43:51 +08:00
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extern void omap_sram_idle(bool rcuidle);
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2012-02-02 17:38:50 +08:00
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extern int omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused);
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2008-10-13 18:15:00 +08:00
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2008-11-26 18:26:24 +08:00
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extern int omap3_pm_get_suspend_state(struct powerdomain *pwrdm);
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extern int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state);
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2010-09-28 05:04:20 +08:00
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extern u32 enable_off_mode;
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2009-11-16 22:46:52 +08:00
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#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
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2008-10-15 23:13:48 +08:00
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extern void pm_dbg_update_time(struct powerdomain *pwrdm, int prev);
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2009-05-29 01:56:16 +08:00
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#else
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2008-10-15 23:13:48 +08:00
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#define pm_dbg_update_time(pwrdm, prev) do {} while (0);
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2009-05-29 01:56:16 +08:00
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#endif /* CONFIG_PM_DEBUG */
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2011-06-30 00:40:23 +08:00
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/* 24xx */
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2009-05-29 01:56:16 +08:00
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extern void omap24xx_cpu_suspend(u32 dll_ctrl, void __iomem *sdrc_dlla_ctrl,
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void __iomem *sdrc_power);
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2011-06-30 00:40:23 +08:00
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extern unsigned int omap24xx_cpu_suspend_sz;
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/* 3xxx */
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2011-06-30 15:45:49 +08:00
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extern void omap34xx_cpu_suspend(int save_state);
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2009-05-29 01:56:16 +08:00
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2011-06-30 00:40:23 +08:00
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/* omap3_do_wfi function pointer and size, for copy to SRAM */
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extern void omap3_do_wfi(void);
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extern unsigned int omap3_do_wfi_sz;
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/* ... and its pointer from SRAM after copy */
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extern void (*omap3_do_wfi_sram)(void);
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2018-02-23 23:43:56 +08:00
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extern struct am33xx_pm_sram_addr am33xx_pm_sram;
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extern struct am33xx_pm_sram_addr am43xx_pm_sram;
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2011-06-30 00:40:23 +08:00
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extern void omap3_save_scratchpad_contents(void);
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2009-05-29 01:56:16 +08:00
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2010-12-21 04:05:06 +08:00
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#define PM_RTA_ERRATUM_i608 (1 << 0)
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2010-12-21 04:05:09 +08:00
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#define PM_SDRC_WAKEUP_ERRATUM_i583 (1 << 1)
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2012-10-16 14:08:53 +08:00
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#define PM_PER_MEMORIES_ERRATUM_i582 (1 << 2)
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2010-12-21 04:05:06 +08:00
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2010-12-21 04:05:05 +08:00
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#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
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extern u16 pm34xx_errata;
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#define IS_PM34XX_ERRATUM(id) (pm34xx_errata & (id))
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2010-12-21 04:05:07 +08:00
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extern void enable_omap3630_toggle_l2_on_restore(void);
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2010-12-21 04:05:05 +08:00
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#else
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#define IS_PM34XX_ERRATUM(id) 0
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2010-12-21 04:05:07 +08:00
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static inline void enable_omap3630_toggle_l2_on_restore(void) { }
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2010-12-21 04:05:05 +08:00
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#endif /* defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) */
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ARM: OMAP4460: Workaround for ROM bug because of CA9 r2pX GIC control register change.
On OMAP4+ devices, GIC register context is lost when MPUSS hits
the OSWR(Open Switch Retention). On the CPU wakeup path, ROM code
gets executed and one of the steps in it is to restore the
saved context of the GIC. The ROM Code GIC distributor restoration
is split in two parts: CPU specific register done by each CPU and
common register done by only one CPU.
Below is the abstract flow.
...............................................................
- MPUSS in OSWR state.
- CPU0 wakes up on the event(interrupt) and start executing ROM code.
[..]
- CPU0 executes "GIC Restoration:"
[...]
- CPU0 swicthes to non-secure mode and jumps to OS resume code.
[...]
- CPU0 is online in OS
- CPU0 enables the GIC distributor. GICD.Enable Non-secure = 1
- CPU0 wakes up CPU1 with clock-domain force wakeup method.
- CPU0 continues it's execution.
[..]
- CPU1 wakes up and start executing ROM code.
[..]
- CPU1 executes "GIC Restoration:"
[..]
- CPU1 swicthes to non-secure mode and jumps to OS resume code.
[...]
- CPU1 is online in OS and start executing.
[...] -
GIC Restoration: /* Common routine for HS and GP devices */
{
if (GICD != 1) { /* This will be true in OSWR state */
if (GIC_SAR_BACKUP_STATE == SAVED)
- CPU restores GIC distributor
else
- reconfigure GIC distributor to boot values.
GICD.Enable secure = 1
}
if (GIC_SAR_BACKUP_STATE == SAVED)
- CPU restore its GIC CPU interface registers if saved.
else
- reconfigure its GIC CPU interface registers to boot
values.
}
...............................................................
So as mentioned in the flow, GICD != 1 condition decides how
the GIC registers are handled in ROM code wakeup path from
OSWR. As evident from the flow, ROM code relies on the entire
GICD register value and not specific register bits.
The assumption was valid till CortexA9 r1pX version since there
was only one banked bit to control secure and non-secure GICD.
Secure view which ROM code sees:
bit 0 == Enable Non-secure
Non-secure view which HLOS sees:
bit 0 == Enable secure
But GICD register has changed between CortexA9 r1pX and r2pX.
On r2pX GICD register is composed of 2 bits.
Secure view which ROM code sees:
bit 1 == Enable Non-secure
bit 0 == Enable secure
Non-secure view which HLOS sees:
bit 0 == Enable Non-secure
Hence on OMAP4460(r2pX) devices, if you go through the
above flow again during CPU1 wakeup, GICD == 3 and hence
ROM code fails to understand the real wakeup power state
and reconfigures GIC distributor to boot values. This is
nasty since you loose the entire interrupt controller
context in a live system.
The ROM code fix done on next OMAP4 device (OMAP4470 - r2px) is to
check "GICD.Enable secure != 1" for GIC restoration in OSWR wakeup path.
Since ROM code can't be fixed on OMAP4460 devices, a work around
needs to be implemented. As evident from the flow, as long as
CPU1 sees GICD == 1 in it's wakeup path from OSWR, the issue
won't happen. Below is the flow with the work-around.
...............................................................
- MPUSS in OSWR state.
- CPU0 wakes up on the event(interrupt) and start executing ROM code.
[..]
- CPU0 executes "GIC Restoration:"
[..]
- CPU0 swicthes to non-secure mode and jumps to OS resume code.
[..]
- CPU0 is online in OS.
- CPU0 does GICD.Enable Non-secure = 0
- CPU0 wakes up CPU1 with clock domain force wakeup method.
- CPU0 waits for GICD.Enable Non-secure = 1
- CPU0 coninues it's execution.
[..]
- CPU1 wakes up and start executing ROM code.
[..]
- CPU1 executes "GIC Restoration:"
[..]
- CPU1 swicthes to non-secure mode and jumps to OS resume code.
[..]
- CPU1 is online in OS
- CPU1 does GICD.Enable Non-secure = 1
- CPU1 start executing
[...]
...............................................................
With this procedure, the GIC configuration done between the
CPU0 wakeup and CPU1 wakeup will not be lost but during this
short windows, the CPU0 will not receive interrupts.
The BUG is applicable to only OMAP4460(r2pX) devices.
OMAP4470 (also r2pX) is not affected by this bug because
ROM code has been fixed.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
2012-10-18 17:20:05 +08:00
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#define PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD (1 << 0)
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2013-05-27 18:16:44 +08:00
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#define PM_OMAP4_CPU_OSWR_DISABLE (1 << 1)
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ARM: OMAP4460: Workaround for ROM bug because of CA9 r2pX GIC control register change.
On OMAP4+ devices, GIC register context is lost when MPUSS hits
the OSWR(Open Switch Retention). On the CPU wakeup path, ROM code
gets executed and one of the steps in it is to restore the
saved context of the GIC. The ROM Code GIC distributor restoration
is split in two parts: CPU specific register done by each CPU and
common register done by only one CPU.
Below is the abstract flow.
...............................................................
- MPUSS in OSWR state.
- CPU0 wakes up on the event(interrupt) and start executing ROM code.
[..]
- CPU0 executes "GIC Restoration:"
[...]
- CPU0 swicthes to non-secure mode and jumps to OS resume code.
[...]
- CPU0 is online in OS
- CPU0 enables the GIC distributor. GICD.Enable Non-secure = 1
- CPU0 wakes up CPU1 with clock-domain force wakeup method.
- CPU0 continues it's execution.
[..]
- CPU1 wakes up and start executing ROM code.
[..]
- CPU1 executes "GIC Restoration:"
[..]
- CPU1 swicthes to non-secure mode and jumps to OS resume code.
[...]
- CPU1 is online in OS and start executing.
[...] -
GIC Restoration: /* Common routine for HS and GP devices */
{
if (GICD != 1) { /* This will be true in OSWR state */
if (GIC_SAR_BACKUP_STATE == SAVED)
- CPU restores GIC distributor
else
- reconfigure GIC distributor to boot values.
GICD.Enable secure = 1
}
if (GIC_SAR_BACKUP_STATE == SAVED)
- CPU restore its GIC CPU interface registers if saved.
else
- reconfigure its GIC CPU interface registers to boot
values.
}
...............................................................
So as mentioned in the flow, GICD != 1 condition decides how
the GIC registers are handled in ROM code wakeup path from
OSWR. As evident from the flow, ROM code relies on the entire
GICD register value and not specific register bits.
The assumption was valid till CortexA9 r1pX version since there
was only one banked bit to control secure and non-secure GICD.
Secure view which ROM code sees:
bit 0 == Enable Non-secure
Non-secure view which HLOS sees:
bit 0 == Enable secure
But GICD register has changed between CortexA9 r1pX and r2pX.
On r2pX GICD register is composed of 2 bits.
Secure view which ROM code sees:
bit 1 == Enable Non-secure
bit 0 == Enable secure
Non-secure view which HLOS sees:
bit 0 == Enable Non-secure
Hence on OMAP4460(r2pX) devices, if you go through the
above flow again during CPU1 wakeup, GICD == 3 and hence
ROM code fails to understand the real wakeup power state
and reconfigures GIC distributor to boot values. This is
nasty since you loose the entire interrupt controller
context in a live system.
The ROM code fix done on next OMAP4 device (OMAP4470 - r2px) is to
check "GICD.Enable secure != 1" for GIC restoration in OSWR wakeup path.
Since ROM code can't be fixed on OMAP4460 devices, a work around
needs to be implemented. As evident from the flow, as long as
CPU1 sees GICD == 1 in it's wakeup path from OSWR, the issue
won't happen. Below is the flow with the work-around.
...............................................................
- MPUSS in OSWR state.
- CPU0 wakes up on the event(interrupt) and start executing ROM code.
[..]
- CPU0 executes "GIC Restoration:"
[..]
- CPU0 swicthes to non-secure mode and jumps to OS resume code.
[..]
- CPU0 is online in OS.
- CPU0 does GICD.Enable Non-secure = 0
- CPU0 wakes up CPU1 with clock domain force wakeup method.
- CPU0 waits for GICD.Enable Non-secure = 1
- CPU0 coninues it's execution.
[..]
- CPU1 wakes up and start executing ROM code.
[..]
- CPU1 executes "GIC Restoration:"
[..]
- CPU1 swicthes to non-secure mode and jumps to OS resume code.
[..]
- CPU1 is online in OS
- CPU1 does GICD.Enable Non-secure = 1
- CPU1 start executing
[...]
...............................................................
With this procedure, the GIC configuration done between the
CPU0 wakeup and CPU1 wakeup will not be lost but during this
short windows, the CPU0 will not receive interrupts.
The BUG is applicable to only OMAP4460(r2pX) devices.
OMAP4470 (also r2pX) is not affected by this bug because
ROM code has been fixed.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
2012-10-18 17:20:05 +08:00
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2015-09-10 05:18:11 +08:00
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#if defined(CONFIG_PM) && (defined(CONFIG_ARCH_OMAP4) ||\
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defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX))
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2012-10-18 17:20:04 +08:00
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extern u16 pm44xx_errata;
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#define IS_PM44XX_ERRATUM(id) (pm44xx_errata & (id))
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#else
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#define IS_PM44XX_ERRATUM(id) 0
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#endif
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2019-10-16 22:37:06 +08:00
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#define OMAP4_VP_CONFIG_ERROROFFSET 0x00
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#define OMAP4_VP_VSTEPMIN_VSTEPMIN 0x01
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#define OMAP4_VP_VSTEPMAX_VSTEPMAX 0x04
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#define OMAP4_VP_VLIMITTO_TIMEOUT_US 200
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2012-04-24 14:08:50 +08:00
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#ifdef CONFIG_POWER_AVS_OMAP
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2010-05-30 00:32:23 +08:00
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extern int omap_devinit_smartreflex(void);
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#else
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static inline int omap_devinit_smartreflex(void)
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{
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return -EINVAL;
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}
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#endif
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2010-12-11 01:21:05 +08:00
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#ifdef CONFIG_TWL4030_CORE
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extern int omap3_twl_init(void);
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2010-12-11 01:45:16 +08:00
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extern int omap4_twl_init(void);
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2010-12-11 01:21:05 +08:00
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#else
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static inline int omap3_twl_init(void)
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{
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return -EINVAL;
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}
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2010-12-11 01:45:16 +08:00
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static inline int omap4_twl_init(void)
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{
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return -EINVAL;
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}
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2010-12-11 01:21:05 +08:00
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#endif
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2019-10-16 22:37:06 +08:00
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#if IS_ENABLED(CONFIG_MFD_CPCAP)
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extern int omap4_cpcap_init(void);
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#else
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static inline int omap4_cpcap_init(void)
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{
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return -EINVAL;
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}
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#endif
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2012-09-26 00:33:39 +08:00
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#ifdef CONFIG_PM
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extern void omap_pm_get_oscillator(u32 *tstart, u32 *tshut);
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#else
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2012-11-15 09:13:04 +08:00
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static inline void omap_pm_get_oscillator(u32 *tstart, u32 *tshut) { *tstart = *tshut = 0; }
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2012-09-26 00:33:39 +08:00
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#endif
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2014-05-13 02:33:21 +08:00
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#ifdef CONFIG_SUSPEND
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void omap_common_suspend_init(void *pm_suspend);
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#else
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static inline void omap_common_suspend_init(void *pm_suspend)
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{
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}
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#endif /* CONFIG_SUSPEND */
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2009-05-29 01:56:16 +08:00
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#endif
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