2018-06-29 20:36:34 +08:00
|
|
|
# SPDX-License-Identifier: GPL-2.0
|
2014-10-24 20:16:52 +08:00
|
|
|
# Intel pin control drivers
|
2021-09-18 13:46:29 +08:00
|
|
|
menu "Intel pinctrl drivers"
|
|
|
|
depends on X86 || COMPILE_TEST
|
2014-10-24 20:16:52 +08:00
|
|
|
|
|
|
|
config PINCTRL_BAYTRAIL
|
|
|
|
bool "Intel Baytrail GPIO pin control"
|
2017-10-11 18:04:35 +08:00
|
|
|
depends on ACPI
|
2020-07-29 19:57:07 +08:00
|
|
|
select PINCTRL_INTEL
|
2014-10-24 20:16:52 +08:00
|
|
|
help
|
|
|
|
driver for memory mapped GPIO functionality on Intel Baytrail
|
|
|
|
platforms. Supports 3 banks with 102, 28 and 44 gpios.
|
|
|
|
Most pins are usually muxed to some other functionality by firmware,
|
|
|
|
so only a small amount is available for gpio use.
|
|
|
|
|
|
|
|
Requires ACPI device enumeration code to set up a platform device.
|
2014-11-03 19:01:33 +08:00
|
|
|
|
|
|
|
config PINCTRL_CHERRYVIEW
|
|
|
|
tristate "Intel Cherryview/Braswell pinctrl and GPIO driver"
|
|
|
|
depends on ACPI
|
2020-07-29 19:57:08 +08:00
|
|
|
select PINCTRL_INTEL
|
2014-11-03 19:01:33 +08:00
|
|
|
help
|
|
|
|
Cherryview/Braswell pinctrl driver provides an interface that
|
|
|
|
allows configuring of SoC pins and using them as GPIOs.
|
2015-03-30 22:31:49 +08:00
|
|
|
|
2019-08-22 23:40:50 +08:00
|
|
|
config PINCTRL_LYNXPOINT
|
|
|
|
tristate "Intel Lynxpoint pinctrl and GPIO driver"
|
|
|
|
depends on ACPI
|
2019-11-26 01:30:57 +08:00
|
|
|
select PINMUX
|
|
|
|
select PINCONF
|
|
|
|
select GENERIC_PINCONF
|
2019-08-22 23:40:50 +08:00
|
|
|
select GPIOLIB
|
|
|
|
select GPIOLIB_IRQCHIP
|
|
|
|
help
|
|
|
|
Lynxpoint is the PCH of Intel Haswell. This pinctrl driver
|
|
|
|
provides an interface that allows configuring of PCH pins and
|
|
|
|
using them as GPIOs.
|
|
|
|
|
2016-06-23 18:49:36 +08:00
|
|
|
config PINCTRL_MERRIFIELD
|
|
|
|
tristate "Intel Merrifield pinctrl driver"
|
|
|
|
depends on X86_INTEL_MID
|
|
|
|
select PINMUX
|
|
|
|
select PINCONF
|
|
|
|
select GENERIC_PINCONF
|
|
|
|
help
|
|
|
|
Merrifield Family-Level Interface Shim (FLIS) driver provides an
|
|
|
|
interface that allows configuring of SoC pins and using them as
|
|
|
|
GPIOs.
|
|
|
|
|
2022-11-08 22:09:31 +08:00
|
|
|
config PINCTRL_MOOREFIELD
|
|
|
|
tristate "Intel Moorefield pinctrl driver"
|
|
|
|
depends on X86_INTEL_MID
|
|
|
|
select PINMUX
|
|
|
|
select PINCONF
|
|
|
|
select GENERIC_PINCONF
|
|
|
|
help
|
|
|
|
Moorefield Family-Level Interface Shim (FLIS) driver provides an
|
|
|
|
interface that allows configuring of SoC pins and using them as
|
|
|
|
GPIOs.
|
|
|
|
|
2015-03-30 22:31:49 +08:00
|
|
|
config PINCTRL_INTEL
|
|
|
|
tristate
|
|
|
|
select PINMUX
|
|
|
|
select PINCONF
|
|
|
|
select GENERIC_PINCONF
|
|
|
|
select GPIOLIB
|
|
|
|
select GPIOLIB_IRQCHIP
|
|
|
|
|
2020-10-29 19:13:15 +08:00
|
|
|
config PINCTRL_ALDERLAKE
|
|
|
|
tristate "Intel Alder Lake pinctrl and GPIO driver"
|
|
|
|
depends on ACPI
|
|
|
|
select PINCTRL_INTEL
|
|
|
|
help
|
|
|
|
This pinctrl driver provides an interface that allows configuring
|
|
|
|
of Intel Alder Lake PCH pins and using them as GPIOs.
|
|
|
|
|
2015-10-21 18:08:45 +08:00
|
|
|
config PINCTRL_BROXTON
|
|
|
|
tristate "Intel Broxton pinctrl and GPIO driver"
|
|
|
|
depends on ACPI
|
|
|
|
select PINCTRL_INTEL
|
|
|
|
help
|
|
|
|
Broxton pinctrl driver provides an interface that allows
|
|
|
|
configuring of SoC pins and using them as GPIOs.
|
|
|
|
|
2017-06-06 21:18:19 +08:00
|
|
|
config PINCTRL_CANNONLAKE
|
|
|
|
tristate "Intel Cannon Lake PCH pinctrl and GPIO driver"
|
|
|
|
depends on ACPI
|
|
|
|
select PINCTRL_INTEL
|
|
|
|
help
|
|
|
|
This pinctrl driver provides an interface that allows configuring
|
|
|
|
of Intel Cannon Lake PCH pins and using them as GPIOs.
|
|
|
|
|
2017-10-23 20:40:26 +08:00
|
|
|
config PINCTRL_CEDARFORK
|
|
|
|
tristate "Intel Cedar Fork pinctrl and GPIO driver"
|
|
|
|
depends on ACPI
|
|
|
|
select PINCTRL_INTEL
|
|
|
|
help
|
|
|
|
This pinctrl driver provides an interface that allows configuring
|
|
|
|
of Intel Cedar Fork PCH pins and using them as GPIOs.
|
|
|
|
|
2017-08-04 00:36:02 +08:00
|
|
|
config PINCTRL_DENVERTON
|
|
|
|
tristate "Intel Denverton pinctrl and GPIO driver"
|
|
|
|
depends on ACPI
|
|
|
|
select PINCTRL_INTEL
|
|
|
|
help
|
|
|
|
This pinctrl driver provides an interface that allows configuring
|
|
|
|
of Intel Denverton SoC pins and using them as GPIOs.
|
2020-11-02 20:21:07 +08:00
|
|
|
|
|
|
|
config PINCTRL_ELKHARTLAKE
|
|
|
|
tristate "Intel Elkhart Lake SoC pinctrl and GPIO driver"
|
|
|
|
depends on ACPI
|
|
|
|
select PINCTRL_INTEL
|
|
|
|
help
|
|
|
|
This pinctrl driver provides an interface that allows configuring
|
|
|
|
of Intel Elkhart Lake SoC pins and using them as GPIOs.
|
2017-08-04 00:36:02 +08:00
|
|
|
|
2020-07-16 20:42:44 +08:00
|
|
|
config PINCTRL_EMMITSBURG
|
|
|
|
tristate "Intel Emmitsburg pinctrl and GPIO driver"
|
|
|
|
depends on ACPI
|
|
|
|
select PINCTRL_INTEL
|
|
|
|
help
|
|
|
|
This pinctrl driver provides an interface that allows configuring
|
|
|
|
of Intel Emmitsburg pins and using them as GPIOs.
|
|
|
|
|
2017-01-27 18:07:16 +08:00
|
|
|
config PINCTRL_GEMINILAKE
|
|
|
|
tristate "Intel Gemini Lake SoC pinctrl and GPIO driver"
|
|
|
|
depends on ACPI
|
|
|
|
select PINCTRL_INTEL
|
|
|
|
help
|
|
|
|
This pinctrl driver provides an interface that allows configuring
|
|
|
|
of Intel Gemini Lake SoC pins and using them as GPIOs.
|
|
|
|
|
2018-06-27 20:05:53 +08:00
|
|
|
config PINCTRL_ICELAKE
|
|
|
|
tristate "Intel Ice Lake PCH pinctrl and GPIO driver"
|
|
|
|
depends on ACPI
|
|
|
|
select PINCTRL_INTEL
|
|
|
|
help
|
|
|
|
This pinctrl driver provides an interface that allows configuring
|
|
|
|
of Intel Ice Lake PCH pins and using them as GPIOs.
|
|
|
|
|
2020-04-13 19:18:25 +08:00
|
|
|
config PINCTRL_JASPERLAKE
|
|
|
|
tristate "Intel Jasper Lake PCH pinctrl and GPIO driver"
|
|
|
|
depends on ACPI
|
|
|
|
select PINCTRL_INTEL
|
|
|
|
help
|
|
|
|
This pinctrl driver provides an interface that allows configuring
|
|
|
|
of Intel Jasper Lake PCH pins and using them as GPIOs.
|
|
|
|
|
2020-10-27 03:23:25 +08:00
|
|
|
config PINCTRL_LAKEFIELD
|
|
|
|
tristate "Intel Lakefield SoC pinctrl and GPIO driver"
|
|
|
|
depends on ACPI
|
|
|
|
select PINCTRL_INTEL
|
|
|
|
help
|
|
|
|
This pinctrl driver provides an interface that allows configuring
|
|
|
|
of Intel Lakefield SoC pins and using them as GPIOs.
|
|
|
|
|
2017-08-18 18:05:55 +08:00
|
|
|
config PINCTRL_LEWISBURG
|
|
|
|
tristate "Intel Lewisburg pinctrl and GPIO driver"
|
|
|
|
depends on ACPI
|
|
|
|
select PINCTRL_INTEL
|
|
|
|
help
|
|
|
|
This pinctrl driver provides an interface that allows configuring
|
|
|
|
of Intel Lewisburg pins and using them as GPIOs.
|
|
|
|
|
2022-06-30 20:38:58 +08:00
|
|
|
config PINCTRL_METEORLAKE
|
|
|
|
tristate "Intel Meteor Lake pinctrl and GPIO driver"
|
|
|
|
depends on ACPI
|
|
|
|
select PINCTRL_INTEL
|
|
|
|
help
|
|
|
|
This pinctrl driver provides an interface that allows configuring
|
|
|
|
of Intel Meteor Lake pins and using them as GPIOs.
|
|
|
|
|
2015-03-30 22:31:49 +08:00
|
|
|
config PINCTRL_SUNRISEPOINT
|
|
|
|
tristate "Intel Sunrisepoint pinctrl and GPIO driver"
|
|
|
|
depends on ACPI
|
|
|
|
select PINCTRL_INTEL
|
|
|
|
help
|
|
|
|
Sunrisepoint is the PCH of Intel Skylake. This pinctrl driver
|
|
|
|
provides an interface that allows configuring of PCH pins and
|
|
|
|
using them as GPIOs.
|
2017-07-04 14:49:47 +08:00
|
|
|
|
2019-10-22 00:45:28 +08:00
|
|
|
config PINCTRL_TIGERLAKE
|
|
|
|
tristate "Intel Tiger Lake pinctrl and GPIO driver"
|
|
|
|
depends on ACPI
|
|
|
|
select PINCTRL_INTEL
|
|
|
|
help
|
|
|
|
This pinctrl driver provides an interface that allows configuring
|
|
|
|
of Intel Tiger Lake PCH pins and using them as GPIOs.
|
2020-10-29 19:17:28 +08:00
|
|
|
|
2021-09-18 13:46:29 +08:00
|
|
|
endmenu
|