2019-05-19 20:08:20 +08:00
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// SPDX-License-Identifier: GPL-2.0-only
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2017-05-15 17:24:37 +08:00
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/* MCP23S08 SPI/I2C GPIO driver */
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2008-02-05 14:28:25 +08:00
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2020-04-08 01:38:48 +08:00
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#include <linux/bitops.h>
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2008-02-05 14:28:25 +08:00
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#include <linux/kernel.h>
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#include <linux/device.h>
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#include <linux/mutex.h>
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2020-04-08 01:38:47 +08:00
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#include <linux/mod_devicetable.h>
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2011-07-04 01:38:09 +08:00
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#include <linux/module.h>
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2020-04-08 01:38:49 +08:00
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#include <linux/export.h>
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2018-09-13 19:58:21 +08:00
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#include <linux/gpio/driver.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 16:04:11 +08:00
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#include <linux/slab.h>
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2011-03-10 00:56:30 +08:00
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#include <asm/byteorder.h>
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2014-01-16 18:44:15 +08:00
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#include <linux/interrupt.h>
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2017-01-27 22:47:37 +08:00
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#include <linux/regmap.h>
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2017-05-15 17:24:26 +08:00
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/pinctrl/pinconf.h>
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#include <linux/pinctrl/pinconf-generic.h>
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2008-02-05 14:28:25 +08:00
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2020-04-08 01:38:49 +08:00
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#include "pinctrl-mcp23s08.h"
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2008-02-05 14:28:25 +08:00
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/* Registers are all 8 bits wide.
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*
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* The mcp23s17 has twice as many bits, and can be configured to work
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* with either 16 bit registers or with two adjacent 8 bit banks.
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*/
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#define MCP_IODIR 0x00 /* init/reset: all ones */
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#define MCP_IPOL 0x01
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#define MCP_GPINTEN 0x02
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#define MCP_DEFVAL 0x03
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#define MCP_INTCON 0x04
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#define MCP_IOCON 0x05
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2014-01-16 18:44:15 +08:00
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# define IOCON_MIRROR (1 << 6)
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2008-02-05 14:28:25 +08:00
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# define IOCON_SEQOP (1 << 5)
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# define IOCON_HAEN (1 << 3)
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# define IOCON_ODR (1 << 2)
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# define IOCON_INTPOL (1 << 1)
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2016-03-15 15:46:30 +08:00
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# define IOCON_INTCC (1)
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2008-02-05 14:28:25 +08:00
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#define MCP_GPPU 0x06
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#define MCP_INTF 0x07
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#define MCP_INTCAP 0x08
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#define MCP_GPIO 0x09
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#define MCP_OLAT 0x0a
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2017-05-15 17:24:28 +08:00
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static const struct reg_default mcp23x08_defaults[] = {
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{.reg = MCP_IODIR, .def = 0xff},
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{.reg = MCP_IPOL, .def = 0x00},
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{.reg = MCP_GPINTEN, .def = 0x00},
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{.reg = MCP_DEFVAL, .def = 0x00},
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{.reg = MCP_INTCON, .def = 0x00},
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{.reg = MCP_IOCON, .def = 0x00},
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{.reg = MCP_GPPU, .def = 0x00},
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{.reg = MCP_OLAT, .def = 0x00},
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};
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static const struct regmap_range mcp23x08_volatile_range = {
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.range_min = MCP_INTF,
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.range_max = MCP_GPIO,
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};
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static const struct regmap_access_table mcp23x08_volatile_table = {
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.yes_ranges = &mcp23x08_volatile_range,
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.n_yes_ranges = 1,
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};
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static const struct regmap_range mcp23x08_precious_range = {
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.range_min = MCP_GPIO,
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.range_max = MCP_GPIO,
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};
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static const struct regmap_access_table mcp23x08_precious_table = {
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.yes_ranges = &mcp23x08_precious_range,
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.n_yes_ranges = 1,
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};
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2020-04-08 01:38:49 +08:00
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const struct regmap_config mcp23x08_regmap = {
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2017-01-27 22:47:37 +08:00
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.reg_bits = 8,
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.val_bits = 8,
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mcp23s08: add i2c support
Add i2c bindings for the mcp230xx devices. This is quite a lot simpler
than the spi one as there's no funky sub addressing done (one struct
i2c_client per struct gpio_chip).
The mcp23s08_platform_data structure is reused for i2c, even though
only a single mcp23s08_chip_info structure is needed.
To use, simply fill out a platform_data structure and pass it in
i2c_board_info, E.G.:
static const struct mcp23s08_platform_data mcp23017_data = {
.chip[0] = {
.pullups = 0x00ff,
},
.base = 240,
};
static struct i2c_board_info __initdata i2c_devs[] = {
{ I2C_BOARD_INFO("mcp23017", 0x20),
.platform_data = &smartview_mcp23017_data, },
...
};
Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2011-07-15 16:25:32 +08:00
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2017-01-27 22:47:37 +08:00
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.reg_stride = 1,
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2017-05-15 17:24:28 +08:00
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.volatile_table = &mcp23x08_volatile_table,
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.precious_table = &mcp23x08_precious_table,
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.reg_defaults = mcp23x08_defaults,
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.num_reg_defaults = ARRAY_SIZE(mcp23x08_defaults),
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.cache_type = REGCACHE_FLAT,
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2017-01-27 22:47:37 +08:00
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.max_register = MCP_OLAT,
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mcp23s08: add i2c support
Add i2c bindings for the mcp230xx devices. This is quite a lot simpler
than the spi one as there's no funky sub addressing done (one struct
i2c_client per struct gpio_chip).
The mcp23s08_platform_data structure is reused for i2c, even though
only a single mcp23s08_chip_info structure is needed.
To use, simply fill out a platform_data structure and pass it in
i2c_board_info, E.G.:
static const struct mcp23s08_platform_data mcp23017_data = {
.chip[0] = {
.pullups = 0x00ff,
},
.base = 240,
};
static struct i2c_board_info __initdata i2c_devs[] = {
{ I2C_BOARD_INFO("mcp23017", 0x20),
.platform_data = &smartview_mcp23017_data, },
...
};
Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2011-07-15 16:25:32 +08:00
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};
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2020-04-08 01:38:49 +08:00
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EXPORT_SYMBOL_GPL(mcp23x08_regmap);
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mcp23s08: add i2c support
Add i2c bindings for the mcp230xx devices. This is quite a lot simpler
than the spi one as there's no funky sub addressing done (one struct
i2c_client per struct gpio_chip).
The mcp23s08_platform_data structure is reused for i2c, even though
only a single mcp23s08_chip_info structure is needed.
To use, simply fill out a platform_data structure and pass it in
i2c_board_info, E.G.:
static const struct mcp23s08_platform_data mcp23017_data = {
.chip[0] = {
.pullups = 0x00ff,
},
.base = 240,
};
static struct i2c_board_info __initdata i2c_devs[] = {
{ I2C_BOARD_INFO("mcp23017", 0x20),
.platform_data = &smartview_mcp23017_data, },
...
};
Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2011-07-15 16:25:32 +08:00
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2020-08-29 05:32:25 +08:00
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static const struct reg_default mcp23x17_defaults[] = {
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2017-05-15 17:24:28 +08:00
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{.reg = MCP_IODIR << 1, .def = 0xffff},
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{.reg = MCP_IPOL << 1, .def = 0x0000},
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{.reg = MCP_GPINTEN << 1, .def = 0x0000},
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{.reg = MCP_DEFVAL << 1, .def = 0x0000},
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{.reg = MCP_INTCON << 1, .def = 0x0000},
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{.reg = MCP_IOCON << 1, .def = 0x0000},
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{.reg = MCP_GPPU << 1, .def = 0x0000},
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{.reg = MCP_OLAT << 1, .def = 0x0000},
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};
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2020-08-29 05:32:25 +08:00
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static const struct regmap_range mcp23x17_volatile_range = {
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2017-05-15 17:24:28 +08:00
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.range_min = MCP_INTF << 1,
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.range_max = MCP_GPIO << 1,
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};
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2020-08-29 05:32:25 +08:00
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static const struct regmap_access_table mcp23x17_volatile_table = {
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.yes_ranges = &mcp23x17_volatile_range,
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2017-05-15 17:24:28 +08:00
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.n_yes_ranges = 1,
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};
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2020-08-29 05:32:25 +08:00
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static const struct regmap_range mcp23x17_precious_range = {
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2020-08-29 05:32:26 +08:00
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.range_min = MCP_INTCAP << 1,
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2017-05-15 17:24:28 +08:00
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.range_max = MCP_GPIO << 1,
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};
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2020-08-29 05:32:25 +08:00
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static const struct regmap_access_table mcp23x17_precious_table = {
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.yes_ranges = &mcp23x17_precious_range,
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2017-05-15 17:24:28 +08:00
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.n_yes_ranges = 1,
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};
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2020-04-08 01:38:49 +08:00
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const struct regmap_config mcp23x17_regmap = {
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2017-01-27 22:47:37 +08:00
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.reg_bits = 8,
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.val_bits = 16,
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mcp23s08: add i2c support
Add i2c bindings for the mcp230xx devices. This is quite a lot simpler
than the spi one as there's no funky sub addressing done (one struct
i2c_client per struct gpio_chip).
The mcp23s08_platform_data structure is reused for i2c, even though
only a single mcp23s08_chip_info structure is needed.
To use, simply fill out a platform_data structure and pass it in
i2c_board_info, E.G.:
static const struct mcp23s08_platform_data mcp23017_data = {
.chip[0] = {
.pullups = 0x00ff,
},
.base = 240,
};
static struct i2c_board_info __initdata i2c_devs[] = {
{ I2C_BOARD_INFO("mcp23017", 0x20),
.platform_data = &smartview_mcp23017_data, },
...
};
Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2011-07-15 16:25:32 +08:00
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2017-01-27 22:47:37 +08:00
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.reg_stride = 2,
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.max_register = MCP_OLAT << 1,
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2020-08-29 05:32:25 +08:00
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.volatile_table = &mcp23x17_volatile_table,
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.precious_table = &mcp23x17_precious_table,
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.reg_defaults = mcp23x17_defaults,
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.num_reg_defaults = ARRAY_SIZE(mcp23x17_defaults),
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2017-05-15 17:24:28 +08:00
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.cache_type = REGCACHE_FLAT,
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2017-01-27 22:47:37 +08:00
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.val_format_endian = REGMAP_ENDIAN_LITTLE,
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};
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2020-04-08 01:38:49 +08:00
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EXPORT_SYMBOL_GPL(mcp23x17_regmap);
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mcp23s08: add i2c support
Add i2c bindings for the mcp230xx devices. This is quite a lot simpler
than the spi one as there's no funky sub addressing done (one struct
i2c_client per struct gpio_chip).
The mcp23s08_platform_data structure is reused for i2c, even though
only a single mcp23s08_chip_info structure is needed.
To use, simply fill out a platform_data structure and pass it in
i2c_board_info, E.G.:
static const struct mcp23s08_platform_data mcp23017_data = {
.chip[0] = {
.pullups = 0x00ff,
},
.base = 240,
};
static struct i2c_board_info __initdata i2c_devs[] = {
{ I2C_BOARD_INFO("mcp23017", 0x20),
.platform_data = &smartview_mcp23017_data, },
...
};
Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2011-07-15 16:25:32 +08:00
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2017-05-15 17:24:26 +08:00
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static int mcp_read(struct mcp23s08 *mcp, unsigned int reg, unsigned int *val)
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{
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return regmap_read(mcp->regmap, reg << mcp->reg_shift, val);
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}
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static int mcp_write(struct mcp23s08 *mcp, unsigned int reg, unsigned int val)
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{
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return regmap_write(mcp->regmap, reg << mcp->reg_shift, val);
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}
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2017-05-15 17:24:28 +08:00
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static int mcp_set_mask(struct mcp23s08 *mcp, unsigned int reg,
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unsigned int mask, bool enabled)
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2017-05-15 17:24:26 +08:00
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{
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u16 val = enabled ? 0xffff : 0x0000;
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return regmap_update_bits(mcp->regmap, reg << mcp->reg_shift,
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mask, val);
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}
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2017-05-15 17:24:28 +08:00
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static int mcp_set_bit(struct mcp23s08 *mcp, unsigned int reg,
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unsigned int pin, bool enabled)
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2017-05-15 17:24:26 +08:00
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{
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2017-05-15 17:24:28 +08:00
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u16 mask = BIT(pin);
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return mcp_set_mask(mcp, reg, mask, enabled);
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2017-05-15 17:24:26 +08:00
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}
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static const struct pinctrl_pin_desc mcp23x08_pins[] = {
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PINCTRL_PIN(0, "gpio0"),
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PINCTRL_PIN(1, "gpio1"),
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PINCTRL_PIN(2, "gpio2"),
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PINCTRL_PIN(3, "gpio3"),
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PINCTRL_PIN(4, "gpio4"),
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PINCTRL_PIN(5, "gpio5"),
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PINCTRL_PIN(6, "gpio6"),
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PINCTRL_PIN(7, "gpio7"),
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};
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static const struct pinctrl_pin_desc mcp23x17_pins[] = {
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PINCTRL_PIN(0, "gpio0"),
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PINCTRL_PIN(1, "gpio1"),
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PINCTRL_PIN(2, "gpio2"),
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PINCTRL_PIN(3, "gpio3"),
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PINCTRL_PIN(4, "gpio4"),
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PINCTRL_PIN(5, "gpio5"),
|
|
|
|
|
PINCTRL_PIN(6, "gpio6"),
|
|
|
|
|
PINCTRL_PIN(7, "gpio7"),
|
|
|
|
|
PINCTRL_PIN(8, "gpio8"),
|
|
|
|
|
PINCTRL_PIN(9, "gpio9"),
|
|
|
|
|
PINCTRL_PIN(10, "gpio10"),
|
|
|
|
|
PINCTRL_PIN(11, "gpio11"),
|
|
|
|
|
PINCTRL_PIN(12, "gpio12"),
|
|
|
|
|
PINCTRL_PIN(13, "gpio13"),
|
|
|
|
|
PINCTRL_PIN(14, "gpio14"),
|
|
|
|
|
PINCTRL_PIN(15, "gpio15"),
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static int mcp_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
|
|
|
|
|
{
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static const char *mcp_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
|
|
|
|
|
unsigned int group)
|
|
|
|
|
{
|
|
|
|
|
return NULL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int mcp_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
|
|
|
|
|
unsigned int group,
|
|
|
|
|
const unsigned int **pins,
|
|
|
|
|
unsigned int *num_pins)
|
|
|
|
|
{
|
|
|
|
|
return -ENOTSUPP;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static const struct pinctrl_ops mcp_pinctrl_ops = {
|
|
|
|
|
.get_groups_count = mcp_pinctrl_get_groups_count,
|
|
|
|
|
.get_group_name = mcp_pinctrl_get_group_name,
|
|
|
|
|
.get_group_pins = mcp_pinctrl_get_group_pins,
|
|
|
|
|
#ifdef CONFIG_OF
|
|
|
|
|
.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
|
|
|
|
|
.dt_free_map = pinconf_generic_dt_free_map,
|
|
|
|
|
#endif
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static int mcp_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
|
|
|
|
|
unsigned long *config)
|
|
|
|
|
{
|
|
|
|
|
struct mcp23s08 *mcp = pinctrl_dev_get_drvdata(pctldev);
|
|
|
|
|
enum pin_config_param param = pinconf_to_config_param(*config);
|
|
|
|
|
unsigned int data, status;
|
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
|
|
switch (param) {
|
|
|
|
|
case PIN_CONFIG_BIAS_PULL_UP:
|
|
|
|
|
ret = mcp_read(mcp, MCP_GPPU, &data);
|
|
|
|
|
if (ret < 0)
|
|
|
|
|
return ret;
|
|
|
|
|
status = (data & BIT(pin)) ? 1 : 0;
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
return -ENOTSUPP;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
*config = 0;
|
|
|
|
|
|
|
|
|
|
return status ? 0 : -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int mcp_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
|
|
|
|
|
unsigned long *configs, unsigned int num_configs)
|
|
|
|
|
{
|
|
|
|
|
struct mcp23s08 *mcp = pinctrl_dev_get_drvdata(pctldev);
|
|
|
|
|
enum pin_config_param param;
|
2017-10-06 13:08:11 +08:00
|
|
|
u32 arg;
|
2017-05-15 17:24:26 +08:00
|
|
|
int ret = 0;
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < num_configs; i++) {
|
|
|
|
|
param = pinconf_to_config_param(configs[i]);
|
|
|
|
|
arg = pinconf_to_config_argument(configs[i]);
|
|
|
|
|
|
|
|
|
|
switch (param) {
|
|
|
|
|
case PIN_CONFIG_BIAS_PULL_UP:
|
|
|
|
|
ret = mcp_set_bit(mcp, MCP_GPPU, pin, arg);
|
|
|
|
|
break;
|
|
|
|
|
default:
|
2019-03-07 21:16:51 +08:00
|
|
|
dev_dbg(mcp->dev, "Invalid config param %04x\n", param);
|
2017-05-15 17:24:26 +08:00
|
|
|
return -ENOTSUPP;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static const struct pinconf_ops mcp_pinconf_ops = {
|
|
|
|
|
.pin_config_get = mcp_pinconf_get,
|
|
|
|
|
.pin_config_set = mcp_pinconf_set,
|
|
|
|
|
.is_generic = true,
|
|
|
|
|
};
|
|
|
|
|
|
mcp23s08: add i2c support
Add i2c bindings for the mcp230xx devices. This is quite a lot simpler
than the spi one as there's no funky sub addressing done (one struct
i2c_client per struct gpio_chip).
The mcp23s08_platform_data structure is reused for i2c, even though
only a single mcp23s08_chip_info structure is needed.
To use, simply fill out a platform_data structure and pass it in
i2c_board_info, E.G.:
static const struct mcp23s08_platform_data mcp23017_data = {
.chip[0] = {
.pullups = 0x00ff,
},
.base = 240,
};
static struct i2c_board_info __initdata i2c_devs[] = {
{ I2C_BOARD_INFO("mcp23017", 0x20),
.platform_data = &smartview_mcp23017_data, },
...
};
Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2011-07-15 16:25:32 +08:00
|
|
|
/*----------------------------------------------------------------------*/
|
|
|
|
|
|
2008-02-05 14:28:25 +08:00
|
|
|
static int mcp23s08_direction_input(struct gpio_chip *chip, unsigned offset)
|
|
|
|
|
{
|
2015-12-07 17:09:36 +08:00
|
|
|
struct mcp23s08 *mcp = gpiochip_get_data(chip);
|
2008-02-05 14:28:25 +08:00
|
|
|
int status;
|
|
|
|
|
|
|
|
|
|
mutex_lock(&mcp->lock);
|
2017-05-15 17:24:28 +08:00
|
|
|
status = mcp_set_bit(mcp, MCP_IODIR, offset, true);
|
2008-02-05 14:28:25 +08:00
|
|
|
mutex_unlock(&mcp->lock);
|
2017-05-15 17:24:28 +08:00
|
|
|
|
2008-02-05 14:28:25 +08:00
|
|
|
return status;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int mcp23s08_get(struct gpio_chip *chip, unsigned offset)
|
|
|
|
|
{
|
2015-12-07 17:09:36 +08:00
|
|
|
struct mcp23s08 *mcp = gpiochip_get_data(chip);
|
2017-01-27 22:47:37 +08:00
|
|
|
int status, ret;
|
2008-02-05 14:28:25 +08:00
|
|
|
|
|
|
|
|
mutex_lock(&mcp->lock);
|
|
|
|
|
|
|
|
|
|
/* REVISIT reading this clears any IRQ ... */
|
2017-01-27 22:47:37 +08:00
|
|
|
ret = mcp_read(mcp, MCP_GPIO, &status);
|
|
|
|
|
if (ret < 0)
|
2008-02-05 14:28:25 +08:00
|
|
|
status = 0;
|
2017-10-18 22:21:02 +08:00
|
|
|
else {
|
|
|
|
|
mcp->cached_gpio = status;
|
2008-02-05 14:28:25 +08:00
|
|
|
status = !!(status & (1 << offset));
|
2017-10-18 22:21:02 +08:00
|
|
|
}
|
2017-05-15 17:24:28 +08:00
|
|
|
|
2008-02-05 14:28:25 +08:00
|
|
|
mutex_unlock(&mcp->lock);
|
|
|
|
|
return status;
|
|
|
|
|
}
|
|
|
|
|
|
2017-05-15 17:24:28 +08:00
|
|
|
static int __mcp23s08_set(struct mcp23s08 *mcp, unsigned mask, bool value)
|
2008-02-05 14:28:25 +08:00
|
|
|
{
|
2017-05-15 17:24:28 +08:00
|
|
|
return mcp_set_mask(mcp, MCP_OLAT, mask, value);
|
2008-02-05 14:28:25 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void mcp23s08_set(struct gpio_chip *chip, unsigned offset, int value)
|
|
|
|
|
{
|
2015-12-07 17:09:36 +08:00
|
|
|
struct mcp23s08 *mcp = gpiochip_get_data(chip);
|
2017-05-15 17:24:28 +08:00
|
|
|
unsigned mask = BIT(offset);
|
2008-02-05 14:28:25 +08:00
|
|
|
|
|
|
|
|
mutex_lock(&mcp->lock);
|
2017-05-15 17:24:28 +08:00
|
|
|
__mcp23s08_set(mcp, mask, !!value);
|
2008-02-05 14:28:25 +08:00
|
|
|
mutex_unlock(&mcp->lock);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int
|
|
|
|
|
mcp23s08_direction_output(struct gpio_chip *chip, unsigned offset, int value)
|
|
|
|
|
{
|
2015-12-07 17:09:36 +08:00
|
|
|
struct mcp23s08 *mcp = gpiochip_get_data(chip);
|
2017-05-15 17:24:28 +08:00
|
|
|
unsigned mask = BIT(offset);
|
2008-02-05 14:28:25 +08:00
|
|
|
int status;
|
|
|
|
|
|
|
|
|
|
mutex_lock(&mcp->lock);
|
|
|
|
|
status = __mcp23s08_set(mcp, mask, value);
|
|
|
|
|
if (status == 0) {
|
2017-05-15 17:24:28 +08:00
|
|
|
status = mcp_set_mask(mcp, MCP_IODIR, mask, false);
|
2008-02-05 14:28:25 +08:00
|
|
|
}
|
|
|
|
|
mutex_unlock(&mcp->lock);
|
|
|
|
|
return status;
|
|
|
|
|
}
|
|
|
|
|
|
2014-01-16 18:44:15 +08:00
|
|
|
/*----------------------------------------------------------------------*/
|
|
|
|
|
static irqreturn_t mcp23s08_irq(int irq, void *data)
|
|
|
|
|
{
|
|
|
|
|
struct mcp23s08 *mcp = data;
|
2017-05-15 17:24:28 +08:00
|
|
|
int intcap, intcon, intf, i, gpio, gpio_orig, intcap_mask, defval;
|
2014-01-16 18:44:15 +08:00
|
|
|
unsigned int child_irq;
|
2017-03-16 04:56:47 +08:00
|
|
|
bool intf_set, intcap_changed, gpio_bit_changed,
|
|
|
|
|
defval_changed, gpio_set;
|
2014-01-16 18:44:15 +08:00
|
|
|
|
|
|
|
|
mutex_lock(&mcp->lock);
|
2017-10-30 23:03:12 +08:00
|
|
|
if (mcp_read(mcp, MCP_INTF, &intf))
|
|
|
|
|
goto unlock;
|
2014-01-16 18:44:15 +08:00
|
|
|
|
2017-10-30 23:03:12 +08:00
|
|
|
if (mcp_read(mcp, MCP_INTCAP, &intcap))
|
|
|
|
|
goto unlock;
|
2014-01-16 18:44:15 +08:00
|
|
|
|
2017-10-30 23:03:12 +08:00
|
|
|
if (mcp_read(mcp, MCP_INTCON, &intcon))
|
|
|
|
|
goto unlock;
|
2017-05-15 17:24:28 +08:00
|
|
|
|
2017-10-30 23:03:12 +08:00
|
|
|
if (mcp_read(mcp, MCP_DEFVAL, &defval))
|
|
|
|
|
goto unlock;
|
2017-03-16 04:56:47 +08:00
|
|
|
|
|
|
|
|
/* This clears the interrupt(configurable on S18) */
|
2017-10-30 23:03:12 +08:00
|
|
|
if (mcp_read(mcp, MCP_GPIO, &gpio))
|
|
|
|
|
goto unlock;
|
|
|
|
|
|
2017-05-15 17:24:28 +08:00
|
|
|
gpio_orig = mcp->cached_gpio;
|
|
|
|
|
mcp->cached_gpio = gpio;
|
2014-01-16 18:44:15 +08:00
|
|
|
mutex_unlock(&mcp->lock);
|
|
|
|
|
|
2017-05-15 17:24:28 +08:00
|
|
|
if (intf == 0) {
|
2017-03-16 04:56:47 +08:00
|
|
|
/* There is no interrupt pending */
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
dev_dbg(mcp->chip.parent,
|
|
|
|
|
"intcap 0x%04X intf 0x%04X gpio_orig 0x%04X gpio 0x%04X\n",
|
|
|
|
|
intcap, intf, gpio_orig, gpio);
|
2014-01-16 18:44:15 +08:00
|
|
|
|
|
|
|
|
for (i = 0; i < mcp->chip.ngpio; i++) {
|
2017-03-16 04:56:47 +08:00
|
|
|
/* We must check all of the inputs on the chip,
|
|
|
|
|
* otherwise we may not notice a change on >=2 pins.
|
|
|
|
|
*
|
|
|
|
|
* On at least the mcp23s17, INTCAP is only updated
|
|
|
|
|
* one byte at a time(INTCAPA and INTCAPB are
|
|
|
|
|
* not written to at the same time - only on a per-bank
|
|
|
|
|
* basis).
|
|
|
|
|
*
|
|
|
|
|
* INTF only contains the single bit that caused the
|
|
|
|
|
* interrupt per-bank. On the mcp23s17, there is
|
|
|
|
|
* INTFA and INTFB. If two pins are changed on the A
|
|
|
|
|
* side at the same time, INTF will only have one bit
|
|
|
|
|
* set. If one pin on the A side and one pin on the B
|
|
|
|
|
* side are changed at the same time, INTF will have
|
|
|
|
|
* two bits set. Thus, INTF can't be the only check
|
|
|
|
|
* to see if the input has changed.
|
|
|
|
|
*/
|
|
|
|
|
|
2017-05-15 17:24:28 +08:00
|
|
|
intf_set = intf & BIT(i);
|
2017-03-16 04:56:47 +08:00
|
|
|
if (i < 8 && intf_set)
|
|
|
|
|
intcap_mask = 0x00FF;
|
|
|
|
|
else if (i >= 8 && intf_set)
|
|
|
|
|
intcap_mask = 0xFF00;
|
|
|
|
|
else
|
|
|
|
|
intcap_mask = 0x00;
|
|
|
|
|
|
|
|
|
|
intcap_changed = (intcap_mask &
|
2017-05-15 17:24:28 +08:00
|
|
|
(intcap & BIT(i))) !=
|
2017-03-16 04:56:47 +08:00
|
|
|
(intcap_mask & (BIT(i) & gpio_orig));
|
2017-05-15 17:24:28 +08:00
|
|
|
gpio_set = BIT(i) & gpio;
|
2017-03-16 04:56:47 +08:00
|
|
|
gpio_bit_changed = (BIT(i) & gpio_orig) !=
|
2017-05-15 17:24:28 +08:00
|
|
|
(BIT(i) & gpio);
|
|
|
|
|
defval_changed = (BIT(i) & intcon) &&
|
|
|
|
|
((BIT(i) & gpio) !=
|
|
|
|
|
(BIT(i) & defval));
|
2017-03-16 04:56:47 +08:00
|
|
|
|
|
|
|
|
if (((gpio_bit_changed || intcap_changed) &&
|
|
|
|
|
(BIT(i) & mcp->irq_rise) && gpio_set) ||
|
|
|
|
|
((gpio_bit_changed || intcap_changed) &&
|
|
|
|
|
(BIT(i) & mcp->irq_fall) && !gpio_set) ||
|
|
|
|
|
defval_changed) {
|
2017-11-08 02:15:47 +08:00
|
|
|
child_irq = irq_find_mapping(mcp->chip.irq.domain, i);
|
2014-01-16 18:44:15 +08:00
|
|
|
handle_nested_irq(child_irq);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return IRQ_HANDLED;
|
2017-10-30 23:03:12 +08:00
|
|
|
|
|
|
|
|
unlock:
|
|
|
|
|
mutex_unlock(&mcp->lock);
|
|
|
|
|
return IRQ_HANDLED;
|
2014-01-16 18:44:15 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void mcp23s08_irq_mask(struct irq_data *data)
|
|
|
|
|
{
|
2016-03-18 16:07:06 +08:00
|
|
|
struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
|
|
|
|
|
struct mcp23s08 *mcp = gpiochip_get_data(gc);
|
2014-01-16 18:44:15 +08:00
|
|
|
unsigned int pos = data->hwirq;
|
|
|
|
|
|
2017-05-15 17:24:28 +08:00
|
|
|
mcp_set_bit(mcp, MCP_GPINTEN, pos, false);
|
2014-01-16 18:44:15 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void mcp23s08_irq_unmask(struct irq_data *data)
|
|
|
|
|
{
|
2016-03-18 16:07:06 +08:00
|
|
|
struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
|
|
|
|
|
struct mcp23s08 *mcp = gpiochip_get_data(gc);
|
2014-01-16 18:44:15 +08:00
|
|
|
unsigned int pos = data->hwirq;
|
|
|
|
|
|
2017-05-15 17:24:28 +08:00
|
|
|
mcp_set_bit(mcp, MCP_GPINTEN, pos, true);
|
2014-01-16 18:44:15 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int mcp23s08_irq_set_type(struct irq_data *data, unsigned int type)
|
|
|
|
|
{
|
2016-03-18 16:07:06 +08:00
|
|
|
struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
|
|
|
|
|
struct mcp23s08 *mcp = gpiochip_get_data(gc);
|
2014-01-16 18:44:15 +08:00
|
|
|
unsigned int pos = data->hwirq;
|
|
|
|
|
|
|
|
|
|
if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
|
2017-05-15 17:24:28 +08:00
|
|
|
mcp_set_bit(mcp, MCP_INTCON, pos, false);
|
2014-01-16 18:44:15 +08:00
|
|
|
mcp->irq_rise |= BIT(pos);
|
|
|
|
|
mcp->irq_fall |= BIT(pos);
|
|
|
|
|
} else if (type & IRQ_TYPE_EDGE_RISING) {
|
2017-05-15 17:24:28 +08:00
|
|
|
mcp_set_bit(mcp, MCP_INTCON, pos, false);
|
2014-01-16 18:44:15 +08:00
|
|
|
mcp->irq_rise |= BIT(pos);
|
|
|
|
|
mcp->irq_fall &= ~BIT(pos);
|
|
|
|
|
} else if (type & IRQ_TYPE_EDGE_FALLING) {
|
2017-05-15 17:24:28 +08:00
|
|
|
mcp_set_bit(mcp, MCP_INTCON, pos, false);
|
2014-01-16 18:44:15 +08:00
|
|
|
mcp->irq_rise &= ~BIT(pos);
|
|
|
|
|
mcp->irq_fall |= BIT(pos);
|
2016-03-24 01:01:27 +08:00
|
|
|
} else if (type & IRQ_TYPE_LEVEL_HIGH) {
|
2017-05-15 17:24:28 +08:00
|
|
|
mcp_set_bit(mcp, MCP_INTCON, pos, true);
|
|
|
|
|
mcp_set_bit(mcp, MCP_DEFVAL, pos, false);
|
2016-03-24 01:01:27 +08:00
|
|
|
} else if (type & IRQ_TYPE_LEVEL_LOW) {
|
2017-05-15 17:24:28 +08:00
|
|
|
mcp_set_bit(mcp, MCP_INTCON, pos, true);
|
|
|
|
|
mcp_set_bit(mcp, MCP_DEFVAL, pos, true);
|
2014-01-16 18:44:15 +08:00
|
|
|
} else
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
2020-04-08 01:38:46 +08:00
|
|
|
return 0;
|
2014-01-16 18:44:15 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void mcp23s08_irq_bus_lock(struct irq_data *data)
|
|
|
|
|
{
|
2016-03-18 16:07:06 +08:00
|
|
|
struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
|
|
|
|
|
struct mcp23s08 *mcp = gpiochip_get_data(gc);
|
2014-01-16 18:44:15 +08:00
|
|
|
|
2017-05-15 17:24:28 +08:00
|
|
|
mutex_lock(&mcp->lock);
|
|
|
|
|
regcache_cache_only(mcp->regmap, true);
|
2014-01-16 18:44:15 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void mcp23s08_irq_bus_unlock(struct irq_data *data)
|
|
|
|
|
{
|
2016-03-18 16:07:06 +08:00
|
|
|
struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
|
|
|
|
|
struct mcp23s08 *mcp = gpiochip_get_data(gc);
|
2014-01-16 18:44:15 +08:00
|
|
|
|
2017-05-15 17:24:28 +08:00
|
|
|
regcache_cache_only(mcp->regmap, false);
|
|
|
|
|
regcache_sync(mcp->regmap);
|
|
|
|
|
|
2014-01-16 18:44:15 +08:00
|
|
|
mutex_unlock(&mcp->lock);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int mcp23s08_irq_setup(struct mcp23s08 *mcp)
|
|
|
|
|
{
|
|
|
|
|
struct gpio_chip *chip = &mcp->chip;
|
2016-03-18 16:07:06 +08:00
|
|
|
int err;
|
2014-12-01 15:26:00 +08:00
|
|
|
unsigned long irqflags = IRQF_ONESHOT | IRQF_SHARED;
|
2014-01-16 18:44:15 +08:00
|
|
|
|
2014-12-01 15:26:00 +08:00
|
|
|
if (mcp->irq_active_high)
|
|
|
|
|
irqflags |= IRQF_TRIGGER_HIGH;
|
|
|
|
|
else
|
|
|
|
|
irqflags |= IRQF_TRIGGER_LOW;
|
|
|
|
|
|
2015-11-04 16:56:26 +08:00
|
|
|
err = devm_request_threaded_irq(chip->parent, mcp->irq, NULL,
|
|
|
|
|
mcp23s08_irq,
|
|
|
|
|
irqflags, dev_name(chip->parent), mcp);
|
2014-01-16 18:44:15 +08:00
|
|
|
if (err != 0) {
|
2015-11-04 16:56:26 +08:00
|
|
|
dev_err(chip->parent, "unable to request IRQ#%d: %d\n",
|
2014-01-16 18:44:15 +08:00
|
|
|
mcp->irq, err);
|
|
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
|
2018-10-02 16:06:46 +08:00
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2008-02-05 14:28:25 +08:00
|
|
|
/*----------------------------------------------------------------------*/
|
|
|
|
|
|
2020-04-08 01:38:49 +08:00
|
|
|
int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev,
|
|
|
|
|
unsigned int addr, unsigned int type, unsigned int base)
|
2008-02-05 14:28:25 +08:00
|
|
|
{
|
2017-01-27 22:47:37 +08:00
|
|
|
int status, ret;
|
2014-01-16 18:44:15 +08:00
|
|
|
bool mirror = false;
|
2018-02-19 17:25:20 +08:00
|
|
|
bool open_drain = false;
|
2008-02-05 14:28:25 +08:00
|
|
|
|
|
|
|
|
mutex_init(&mcp->lock);
|
|
|
|
|
|
2017-01-27 22:47:37 +08:00
|
|
|
mcp->dev = dev;
|
2011-07-15 16:25:31 +08:00
|
|
|
mcp->addr = addr;
|
2020-04-08 01:38:42 +08:00
|
|
|
|
2014-12-01 15:26:00 +08:00
|
|
|
mcp->irq_active_high = false;
|
2020-04-08 01:38:42 +08:00
|
|
|
mcp->irq_chip.name = dev_name(dev);
|
|
|
|
|
mcp->irq_chip.irq_mask = mcp23s08_irq_mask;
|
|
|
|
|
mcp->irq_chip.irq_unmask = mcp23s08_irq_unmask;
|
|
|
|
|
mcp->irq_chip.irq_set_type = mcp23s08_irq_set_type;
|
|
|
|
|
mcp->irq_chip.irq_bus_lock = mcp23s08_irq_bus_lock;
|
|
|
|
|
mcp->irq_chip.irq_bus_sync_unlock = mcp23s08_irq_bus_unlock;
|
2008-02-05 14:28:25 +08:00
|
|
|
|
|
|
|
|
mcp->chip.direction_input = mcp23s08_direction_input;
|
|
|
|
|
mcp->chip.get = mcp23s08_get;
|
|
|
|
|
mcp->chip.direction_output = mcp23s08_direction_output;
|
|
|
|
|
mcp->chip.set = mcp23s08_set;
|
2016-09-08 05:13:20 +08:00
|
|
|
#ifdef CONFIG_OF_GPIO
|
2013-04-04 18:02:02 +08:00
|
|
|
mcp->chip.of_gpio_n_cells = 2;
|
|
|
|
|
mcp->chip.of_node = dev->of_node;
|
|
|
|
|
#endif
|
2008-02-05 14:28:25 +08:00
|
|
|
|
2017-05-15 17:24:35 +08:00
|
|
|
mcp->chip.base = base;
|
2013-12-04 21:42:46 +08:00
|
|
|
mcp->chip.can_sleep = true;
|
2015-11-04 16:56:26 +08:00
|
|
|
mcp->chip.parent = dev;
|
2008-04-28 17:14:45 +08:00
|
|
|
mcp->chip.owner = THIS_MODULE;
|
2008-02-05 14:28:25 +08:00
|
|
|
|
gpio: mcp23s08 handles multiple chips per chipselect
Teach the mcp23s08 driver about a curious feature of these chips: up to
four of them can share the same chipselect, with the SPI signals wired in
parallel, by matching two bits in the first protocol byte against two
address lines on the chip.
This is handled by three software changes:
* Platform data now holds an array of per-chip structs, not
just one chip's address and pullup configuration.
* Probe() and remove() now use another level of structure,
wrapping an instance of the original structure for each
mcp23s08 chip sharing that chipselect.
* The HAEN bit is set, so that the hardware address bits can no
longer be ignored (boot firmware may not have enabled them).
The "one struct per chip" preserves the guts of the current code,
but platform_data will need minor changes.
OLD:
/* incorrect "slave" ID may not have mattered */
.slave = 3,
.pullups = BIT(3) | BIT(1) | BIT(0),
NEW:
/* slave address _must_ match chip's wiring */
.chip[3] = {
.is_present = true,
.pullups = BIT(3) | BIT(1) | BIT(0),
},
There's no change in how things _behave_ for spi_device nodes with a
single mcp23s08 chip. New multi-chip configurations assign GPIOs in
sequence, without holes. The spi_device just resembles a bigger
controller, but internally it has multiple gpio_chip instances.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2008-07-25 16:46:09 +08:00
|
|
|
/* verify MCP_IOCON.SEQOP = 0, so sequential reads work,
|
|
|
|
|
* and MCP_IOCON.HAEN = 1, so we work with all chips.
|
|
|
|
|
*/
|
2014-01-16 18:44:15 +08:00
|
|
|
|
2017-01-27 22:47:37 +08:00
|
|
|
ret = mcp_read(mcp, MCP_IOCON, &status);
|
|
|
|
|
if (ret < 0)
|
2020-08-28 18:32:35 +08:00
|
|
|
return dev_err_probe(dev, ret, "can't identify chip %d\n", addr);
|
2014-01-16 18:44:15 +08:00
|
|
|
|
2017-05-15 17:24:35 +08:00
|
|
|
mcp->irq_controller =
|
|
|
|
|
device_property_read_bool(dev, "interrupt-controller");
|
2014-12-01 15:26:00 +08:00
|
|
|
if (mcp->irq && mcp->irq_controller) {
|
2014-12-12 18:22:11 +08:00
|
|
|
mcp->irq_active_high =
|
2017-05-15 17:24:35 +08:00
|
|
|
device_property_read_bool(dev,
|
2014-12-12 18:22:11 +08:00
|
|
|
"microchip,irq-active-high");
|
2014-01-16 18:44:15 +08:00
|
|
|
|
2017-05-15 17:24:35 +08:00
|
|
|
mirror = device_property_read_bool(dev, "microchip,irq-mirror");
|
2018-02-19 17:25:20 +08:00
|
|
|
open_drain = device_property_read_bool(dev, "drive-open-drain");
|
2014-12-01 15:26:00 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if ((status & IOCON_SEQOP) || !(status & IOCON_HAEN) || mirror ||
|
2018-02-19 17:25:20 +08:00
|
|
|
mcp->irq_active_high || open_drain) {
|
2011-03-10 00:56:30 +08:00
|
|
|
/* mcp23s17 has IOCON twice, make sure they are in sync */
|
|
|
|
|
status &= ~(IOCON_SEQOP | (IOCON_SEQOP << 8));
|
|
|
|
|
status |= IOCON_HAEN | (IOCON_HAEN << 8);
|
2014-12-01 15:26:00 +08:00
|
|
|
if (mcp->irq_active_high)
|
|
|
|
|
status |= IOCON_INTPOL | (IOCON_INTPOL << 8);
|
|
|
|
|
else
|
|
|
|
|
status &= ~(IOCON_INTPOL | (IOCON_INTPOL << 8));
|
|
|
|
|
|
2014-01-16 18:44:15 +08:00
|
|
|
if (mirror)
|
|
|
|
|
status |= IOCON_MIRROR | (IOCON_MIRROR << 8);
|
|
|
|
|
|
2018-02-19 17:25:20 +08:00
|
|
|
if (open_drain)
|
|
|
|
|
status |= IOCON_ODR | (IOCON_ODR << 8);
|
|
|
|
|
|
2017-10-06 13:08:07 +08:00
|
|
|
if (type == MCP_TYPE_S18 || type == MCP_TYPE_018)
|
2016-03-15 15:46:30 +08:00
|
|
|
status |= IOCON_INTCC | (IOCON_INTCC << 8);
|
|
|
|
|
|
2017-01-27 22:47:37 +08:00
|
|
|
ret = mcp_write(mcp, MCP_IOCON, status);
|
|
|
|
|
if (ret < 0)
|
2020-08-28 18:32:35 +08:00
|
|
|
return dev_err_probe(dev, ret, "can't write IOCON %d\n", addr);
|
2008-02-05 14:28:25 +08:00
|
|
|
}
|
|
|
|
|
|
2014-01-16 18:44:15 +08:00
|
|
|
if (mcp->irq && mcp->irq_controller) {
|
2020-07-21 20:52:23 +08:00
|
|
|
struct gpio_irq_chip *girq = &mcp->chip.irq;
|
|
|
|
|
|
|
|
|
|
girq->chip = &mcp->irq_chip;
|
|
|
|
|
/* This will let us handle the parent IRQ in the driver */
|
|
|
|
|
girq->parent_handler = NULL;
|
|
|
|
|
girq->num_parents = 0;
|
|
|
|
|
girq->parents = NULL;
|
|
|
|
|
girq->default_type = IRQ_TYPE_NONE;
|
|
|
|
|
girq->handler = handle_simple_irq;
|
|
|
|
|
girq->threaded = true;
|
2014-01-16 18:44:15 +08:00
|
|
|
}
|
2017-05-15 17:24:26 +08:00
|
|
|
|
2020-07-21 20:52:23 +08:00
|
|
|
ret = devm_gpiochip_add_data(dev, &mcp->chip, mcp);
|
|
|
|
|
if (ret < 0)
|
2020-08-28 18:32:35 +08:00
|
|
|
return dev_err_probe(dev, ret, "can't add GPIO chip\n");
|
2020-07-21 20:52:23 +08:00
|
|
|
|
2017-05-15 17:24:26 +08:00
|
|
|
mcp->pinctrl_desc.pctlops = &mcp_pinctrl_ops;
|
|
|
|
|
mcp->pinctrl_desc.confops = &mcp_pinconf_ops;
|
|
|
|
|
mcp->pinctrl_desc.npins = mcp->chip.ngpio;
|
|
|
|
|
if (mcp->pinctrl_desc.npins == 8)
|
|
|
|
|
mcp->pinctrl_desc.pins = mcp23x08_pins;
|
|
|
|
|
else if (mcp->pinctrl_desc.npins == 16)
|
|
|
|
|
mcp->pinctrl_desc.pins = mcp23x17_pins;
|
|
|
|
|
mcp->pinctrl_desc.owner = THIS_MODULE;
|
|
|
|
|
|
|
|
|
|
mcp->pctldev = devm_pinctrl_register(dev, &mcp->pinctrl_desc, mcp);
|
2020-08-28 18:32:35 +08:00
|
|
|
if (IS_ERR(mcp->pctldev))
|
|
|
|
|
return dev_err_probe(dev, PTR_ERR(mcp->pctldev), "can't register controller\n");
|
2017-05-15 17:24:26 +08:00
|
|
|
|
2020-08-28 18:32:35 +08:00
|
|
|
if (mcp->irq) {
|
2018-10-02 16:06:46 +08:00
|
|
|
ret = mcp23s08_irq_setup(mcp);
|
2020-08-28 18:32:35 +08:00
|
|
|
if (ret)
|
|
|
|
|
return dev_err_probe(dev, ret, "can't setup IRQ\n");
|
|
|
|
|
}
|
2018-10-02 16:06:46 +08:00
|
|
|
|
2020-08-28 18:32:35 +08:00
|
|
|
return 0;
|
gpio: mcp23s08 handles multiple chips per chipselect
Teach the mcp23s08 driver about a curious feature of these chips: up to
four of them can share the same chipselect, with the SPI signals wired in
parallel, by matching two bits in the first protocol byte against two
address lines on the chip.
This is handled by three software changes:
* Platform data now holds an array of per-chip structs, not
just one chip's address and pullup configuration.
* Probe() and remove() now use another level of structure,
wrapping an instance of the original structure for each
mcp23s08 chip sharing that chipselect.
* The HAEN bit is set, so that the hardware address bits can no
longer be ignored (boot firmware may not have enabled them).
The "one struct per chip" preserves the guts of the current code,
but platform_data will need minor changes.
OLD:
/* incorrect "slave" ID may not have mattered */
.slave = 3,
.pullups = BIT(3) | BIT(1) | BIT(0),
NEW:
/* slave address _must_ match chip's wiring */
.chip[3] = {
.is_present = true,
.pullups = BIT(3) | BIT(1) | BIT(0),
},
There's no change in how things _behave_ for spi_device nodes with a
single mcp23s08 chip. New multi-chip configurations assign GPIOs in
sequence, without holes. The spi_device just resembles a bigger
controller, but internally it has multiple gpio_chip instances.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2008-07-25 16:46:09 +08:00
|
|
|
}
|
2020-04-08 01:38:49 +08:00
|
|
|
EXPORT_SYMBOL_GPL(mcp23s08_probe_one);
|
2020-08-28 18:32:35 +08:00
|
|
|
|
2020-04-17 17:21:25 +08:00
|
|
|
MODULE_LICENSE("GPL");
|
