2009-11-20 02:49:17 +08:00
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/*
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* driver/dma/coh901318.c
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*
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* Copyright (C) 2007-2009 ST-Ericsson
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* License terms: GNU General Public License (GPL) version 2
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* DMA driver for COH 901 318
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* Author: Per Friden <per.friden@stericsson.com>
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/kernel.h> /* printk() */
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#include <linux/fs.h> /* everything... */
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2011-06-16 19:01:34 +08:00
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#include <linux/scatterlist.h>
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2009-11-20 02:49:17 +08:00
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#include <linux/slab.h> /* kmalloc() */
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#include <linux/dmaengine.h>
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#include <linux/platform_device.h>
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#include <linux/device.h>
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#include <linux/irqreturn.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/uaccess.h>
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#include <linux/debugfs.h>
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2013-01-04 17:35:06 +08:00
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#include <linux/platform_data/dma-coh901318.h>
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2013-04-19 19:42:55 +08:00
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#include <linux/of_dma.h>
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2009-11-20 02:49:17 +08:00
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2013-01-04 20:56:16 +08:00
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#include "coh901318.h"
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2012-03-07 06:34:26 +08:00
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#include "dmaengine.h"
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2009-11-20 02:49:17 +08:00
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2013-01-04 21:07:51 +08:00
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#define COH901318_MOD32_MASK (0x1F)
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#define COH901318_WORD_MASK (0xFFFFFFFF)
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/* INT_STATUS - Interrupt Status Registers 32bit (R/-) */
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#define COH901318_INT_STATUS1 (0x0000)
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#define COH901318_INT_STATUS2 (0x0004)
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/* TC_INT_STATUS - Terminal Count Interrupt Status Registers 32bit (R/-) */
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#define COH901318_TC_INT_STATUS1 (0x0008)
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#define COH901318_TC_INT_STATUS2 (0x000C)
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/* TC_INT_CLEAR - Terminal Count Interrupt Clear Registers 32bit (-/W) */
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#define COH901318_TC_INT_CLEAR1 (0x0010)
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#define COH901318_TC_INT_CLEAR2 (0x0014)
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/* RAW_TC_INT_STATUS - Raw Term Count Interrupt Status Registers 32bit (R/-) */
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#define COH901318_RAW_TC_INT_STATUS1 (0x0018)
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#define COH901318_RAW_TC_INT_STATUS2 (0x001C)
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/* BE_INT_STATUS - Bus Error Interrupt Status Registers 32bit (R/-) */
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#define COH901318_BE_INT_STATUS1 (0x0020)
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#define COH901318_BE_INT_STATUS2 (0x0024)
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/* BE_INT_CLEAR - Bus Error Interrupt Clear Registers 32bit (-/W) */
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#define COH901318_BE_INT_CLEAR1 (0x0028)
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#define COH901318_BE_INT_CLEAR2 (0x002C)
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/* RAW_BE_INT_STATUS - Raw Term Count Interrupt Status Registers 32bit (R/-) */
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#define COH901318_RAW_BE_INT_STATUS1 (0x0030)
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#define COH901318_RAW_BE_INT_STATUS2 (0x0034)
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/*
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* CX_CFG - Channel Configuration Registers 32bit (R/W)
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*/
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#define COH901318_CX_CFG (0x0100)
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#define COH901318_CX_CFG_SPACING (0x04)
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/* Channel enable activates tha dma job */
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#define COH901318_CX_CFG_CH_ENABLE (0x00000001)
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#define COH901318_CX_CFG_CH_DISABLE (0x00000000)
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/* Request Mode */
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#define COH901318_CX_CFG_RM_MASK (0x00000006)
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#define COH901318_CX_CFG_RM_MEMORY_TO_MEMORY (0x0 << 1)
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#define COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY (0x1 << 1)
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#define COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY (0x1 << 1)
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#define COH901318_CX_CFG_RM_PRIMARY_TO_SECONDARY (0x3 << 1)
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#define COH901318_CX_CFG_RM_SECONDARY_TO_PRIMARY (0x3 << 1)
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/* Linked channel request field. RM must == 11 */
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#define COH901318_CX_CFG_LCRF_SHIFT 3
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#define COH901318_CX_CFG_LCRF_MASK (0x000001F8)
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#define COH901318_CX_CFG_LCR_DISABLE (0x00000000)
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/* Terminal Counter Interrupt Request Mask */
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#define COH901318_CX_CFG_TC_IRQ_ENABLE (0x00000200)
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#define COH901318_CX_CFG_TC_IRQ_DISABLE (0x00000000)
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/* Bus Error interrupt Mask */
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#define COH901318_CX_CFG_BE_IRQ_ENABLE (0x00000400)
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#define COH901318_CX_CFG_BE_IRQ_DISABLE (0x00000000)
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/*
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* CX_STAT - Channel Status Registers 32bit (R/-)
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*/
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#define COH901318_CX_STAT (0x0200)
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#define COH901318_CX_STAT_SPACING (0x04)
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#define COH901318_CX_STAT_RBE_IRQ_IND (0x00000008)
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#define COH901318_CX_STAT_RTC_IRQ_IND (0x00000004)
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#define COH901318_CX_STAT_ACTIVE (0x00000002)
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#define COH901318_CX_STAT_ENABLED (0x00000001)
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/*
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* CX_CTRL - Channel Control Registers 32bit (R/W)
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*/
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#define COH901318_CX_CTRL (0x0400)
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#define COH901318_CX_CTRL_SPACING (0x10)
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/* Transfer Count Enable */
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#define COH901318_CX_CTRL_TC_ENABLE (0x00001000)
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#define COH901318_CX_CTRL_TC_DISABLE (0x00000000)
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/* Transfer Count Value 0 - 4095 */
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#define COH901318_CX_CTRL_TC_VALUE_MASK (0x00000FFF)
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/* Burst count */
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#define COH901318_CX_CTRL_BURST_COUNT_MASK (0x0000E000)
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#define COH901318_CX_CTRL_BURST_COUNT_64_BYTES (0x7 << 13)
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#define COH901318_CX_CTRL_BURST_COUNT_48_BYTES (0x6 << 13)
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#define COH901318_CX_CTRL_BURST_COUNT_32_BYTES (0x5 << 13)
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#define COH901318_CX_CTRL_BURST_COUNT_16_BYTES (0x4 << 13)
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#define COH901318_CX_CTRL_BURST_COUNT_8_BYTES (0x3 << 13)
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#define COH901318_CX_CTRL_BURST_COUNT_4_BYTES (0x2 << 13)
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#define COH901318_CX_CTRL_BURST_COUNT_2_BYTES (0x1 << 13)
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#define COH901318_CX_CTRL_BURST_COUNT_1_BYTE (0x0 << 13)
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/* Source bus size */
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#define COH901318_CX_CTRL_SRC_BUS_SIZE_MASK (0x00030000)
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#define COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS (0x2 << 16)
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#define COH901318_CX_CTRL_SRC_BUS_SIZE_16_BITS (0x1 << 16)
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#define COH901318_CX_CTRL_SRC_BUS_SIZE_8_BITS (0x0 << 16)
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/* Source address increment */
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#define COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE (0x00040000)
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#define COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE (0x00000000)
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/* Destination Bus Size */
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#define COH901318_CX_CTRL_DST_BUS_SIZE_MASK (0x00180000)
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#define COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS (0x2 << 19)
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#define COH901318_CX_CTRL_DST_BUS_SIZE_16_BITS (0x1 << 19)
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#define COH901318_CX_CTRL_DST_BUS_SIZE_8_BITS (0x0 << 19)
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/* Destination address increment */
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#define COH901318_CX_CTRL_DST_ADDR_INC_ENABLE (0x00200000)
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#define COH901318_CX_CTRL_DST_ADDR_INC_DISABLE (0x00000000)
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/* Master Mode (Master2 is only connected to MSL) */
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#define COH901318_CX_CTRL_MASTER_MODE_MASK (0x00C00000)
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#define COH901318_CX_CTRL_MASTER_MODE_M2R_M1W (0x3 << 22)
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#define COH901318_CX_CTRL_MASTER_MODE_M1R_M2W (0x2 << 22)
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#define COH901318_CX_CTRL_MASTER_MODE_M2RW (0x1 << 22)
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#define COH901318_CX_CTRL_MASTER_MODE_M1RW (0x0 << 22)
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/* Terminal Count flag to PER enable */
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#define COH901318_CX_CTRL_TCP_ENABLE (0x01000000)
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#define COH901318_CX_CTRL_TCP_DISABLE (0x00000000)
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/* Terminal Count flags to CPU enable */
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#define COH901318_CX_CTRL_TC_IRQ_ENABLE (0x02000000)
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#define COH901318_CX_CTRL_TC_IRQ_DISABLE (0x00000000)
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/* Hand shake to peripheral */
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#define COH901318_CX_CTRL_HSP_ENABLE (0x04000000)
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#define COH901318_CX_CTRL_HSP_DISABLE (0x00000000)
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#define COH901318_CX_CTRL_HSS_ENABLE (0x08000000)
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#define COH901318_CX_CTRL_HSS_DISABLE (0x00000000)
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/* DMA mode */
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#define COH901318_CX_CTRL_DDMA_MASK (0x30000000)
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#define COH901318_CX_CTRL_DDMA_LEGACY (0x0 << 28)
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#define COH901318_CX_CTRL_DDMA_DEMAND_DMA1 (0x1 << 28)
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#define COH901318_CX_CTRL_DDMA_DEMAND_DMA2 (0x2 << 28)
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/* Primary Request Data Destination */
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#define COH901318_CX_CTRL_PRDD_MASK (0x40000000)
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#define COH901318_CX_CTRL_PRDD_DEST (0x1 << 30)
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#define COH901318_CX_CTRL_PRDD_SOURCE (0x0 << 30)
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/*
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* CX_SRC_ADDR - Channel Source Address Registers 32bit (R/W)
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*/
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#define COH901318_CX_SRC_ADDR (0x0404)
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#define COH901318_CX_SRC_ADDR_SPACING (0x10)
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/*
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* CX_DST_ADDR - Channel Destination Address Registers 32bit R/W
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*/
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#define COH901318_CX_DST_ADDR (0x0408)
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#define COH901318_CX_DST_ADDR_SPACING (0x10)
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/*
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* CX_LNK_ADDR - Channel Link Address Registers 32bit (R/W)
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*/
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#define COH901318_CX_LNK_ADDR (0x040C)
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#define COH901318_CX_LNK_ADDR_SPACING (0x10)
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#define COH901318_CX_LNK_LINK_IMMEDIATE (0x00000001)
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/**
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* struct coh901318_params - parameters for DMAC configuration
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* @config: DMA config register
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* @ctrl_lli_last: DMA control register for the last lli in the list
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* @ctrl_lli: DMA control register for an lli
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* @ctrl_lli_chained: DMA control register for a chained lli
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*/
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struct coh901318_params {
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u32 config;
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u32 ctrl_lli_last;
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u32 ctrl_lli;
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u32 ctrl_lli_chained;
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};
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/**
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* struct coh_dma_channel - dma channel base
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* @name: ascii name of dma channel
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* @number: channel id number
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* @desc_nbr_max: number of preallocated descriptors
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* @priority_high: prio of channel, 0 low otherwise high.
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* @param: configuration parameters
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*/
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struct coh_dma_channel {
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const char name[32];
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const int number;
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const int desc_nbr_max;
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const int priority_high;
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const struct coh901318_params param;
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};
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/**
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* struct powersave - DMA power save structure
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* @lock: lock protecting data in this struct
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* @started_channels: bit mask indicating active dma channels
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*/
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struct powersave {
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spinlock_t lock;
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u64 started_channels;
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};
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2013-01-04 20:38:18 +08:00
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/* points out all dma slave channels.
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* Syntax is [A1, B1, A2, B2, .... ,-1,-1]
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* Select all channels from A to B, end of list is marked with -1,-1
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*/
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static int dma_slave_channels[] = {
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U300_DMA_MSL_TX_0, U300_DMA_SPI_RX,
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U300_DMA_UART1_TX, U300_DMA_UART1_RX, -1, -1};
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/* points out all dma memcpy channels. */
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static int dma_memcpy_channels[] = {
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U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_8, -1, -1};
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#define flags_memcpy_config (COH901318_CX_CFG_CH_DISABLE | \
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COH901318_CX_CFG_RM_MEMORY_TO_MEMORY | \
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COH901318_CX_CFG_LCR_DISABLE | \
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COH901318_CX_CFG_TC_IRQ_ENABLE | \
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COH901318_CX_CFG_BE_IRQ_ENABLE)
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#define flags_memcpy_lli_chained (COH901318_CX_CTRL_TC_ENABLE | \
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COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
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COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
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COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
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COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
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COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
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COH901318_CX_CTRL_MASTER_MODE_M1RW | \
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COH901318_CX_CTRL_TCP_DISABLE | \
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COH901318_CX_CTRL_TC_IRQ_DISABLE | \
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COH901318_CX_CTRL_HSP_DISABLE | \
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COH901318_CX_CTRL_HSS_DISABLE | \
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COH901318_CX_CTRL_DDMA_LEGACY | \
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COH901318_CX_CTRL_PRDD_SOURCE)
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#define flags_memcpy_lli (COH901318_CX_CTRL_TC_ENABLE | \
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COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
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COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
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COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
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COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
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COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
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COH901318_CX_CTRL_MASTER_MODE_M1RW | \
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COH901318_CX_CTRL_TCP_DISABLE | \
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COH901318_CX_CTRL_TC_IRQ_DISABLE | \
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COH901318_CX_CTRL_HSP_DISABLE | \
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COH901318_CX_CTRL_HSS_DISABLE | \
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COH901318_CX_CTRL_DDMA_LEGACY | \
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COH901318_CX_CTRL_PRDD_SOURCE)
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#define flags_memcpy_lli_last (COH901318_CX_CTRL_TC_ENABLE | \
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COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
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COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
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COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
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COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
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COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
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COH901318_CX_CTRL_MASTER_MODE_M1RW | \
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COH901318_CX_CTRL_TCP_DISABLE | \
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COH901318_CX_CTRL_TC_IRQ_ENABLE | \
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COH901318_CX_CTRL_HSP_DISABLE | \
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COH901318_CX_CTRL_HSS_DISABLE | \
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COH901318_CX_CTRL_DDMA_LEGACY | \
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COH901318_CX_CTRL_PRDD_SOURCE)
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const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
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{
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.number = U300_DMA_MSL_TX_0,
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.name = "MSL TX 0",
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.priority_high = 0,
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},
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{
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.number = U300_DMA_MSL_TX_1,
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.name = "MSL TX 1",
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.priority_high = 0,
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.param.config = COH901318_CX_CFG_CH_DISABLE |
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COH901318_CX_CFG_LCR_DISABLE |
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COH901318_CX_CFG_TC_IRQ_ENABLE |
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COH901318_CX_CFG_BE_IRQ_ENABLE,
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.param.ctrl_lli_chained = 0 |
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COH901318_CX_CTRL_TC_ENABLE |
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COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
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COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
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COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
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COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
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COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
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COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
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COH901318_CX_CTRL_TCP_DISABLE |
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COH901318_CX_CTRL_TC_IRQ_DISABLE |
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COH901318_CX_CTRL_HSP_ENABLE |
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COH901318_CX_CTRL_HSS_DISABLE |
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COH901318_CX_CTRL_DDMA_LEGACY |
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COH901318_CX_CTRL_PRDD_SOURCE,
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.param.ctrl_lli = 0 |
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COH901318_CX_CTRL_TC_ENABLE |
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COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
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COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
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COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
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COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
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COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
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COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
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COH901318_CX_CTRL_TCP_ENABLE |
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COH901318_CX_CTRL_TC_IRQ_DISABLE |
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COH901318_CX_CTRL_HSP_ENABLE |
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COH901318_CX_CTRL_HSS_DISABLE |
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COH901318_CX_CTRL_DDMA_LEGACY |
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COH901318_CX_CTRL_PRDD_SOURCE,
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.param.ctrl_lli_last = 0 |
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COH901318_CX_CTRL_TC_ENABLE |
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COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
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COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
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COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
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COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
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COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
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COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
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COH901318_CX_CTRL_TCP_ENABLE |
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COH901318_CX_CTRL_TC_IRQ_ENABLE |
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COH901318_CX_CTRL_HSP_ENABLE |
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COH901318_CX_CTRL_HSS_DISABLE |
|
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COH901318_CX_CTRL_DDMA_LEGACY |
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COH901318_CX_CTRL_PRDD_SOURCE,
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},
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{
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.number = U300_DMA_MSL_TX_2,
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.name = "MSL TX 2",
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.priority_high = 0,
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.param.config = COH901318_CX_CFG_CH_DISABLE |
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COH901318_CX_CFG_LCR_DISABLE |
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COH901318_CX_CFG_TC_IRQ_ENABLE |
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COH901318_CX_CFG_BE_IRQ_ENABLE,
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.param.ctrl_lli_chained = 0 |
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COH901318_CX_CTRL_TC_ENABLE |
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COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
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COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
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COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
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COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
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COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
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COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
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COH901318_CX_CTRL_TCP_DISABLE |
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COH901318_CX_CTRL_TC_IRQ_DISABLE |
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COH901318_CX_CTRL_HSP_ENABLE |
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COH901318_CX_CTRL_HSS_DISABLE |
|
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COH901318_CX_CTRL_DDMA_LEGACY |
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COH901318_CX_CTRL_PRDD_SOURCE,
|
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.param.ctrl_lli = 0 |
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COH901318_CX_CTRL_TC_ENABLE |
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COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
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COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
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COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
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COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
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COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
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COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
|
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COH901318_CX_CTRL_TCP_ENABLE |
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COH901318_CX_CTRL_TC_IRQ_DISABLE |
|
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COH901318_CX_CTRL_HSP_ENABLE |
|
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COH901318_CX_CTRL_HSS_DISABLE |
|
|
|
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|
COH901318_CX_CTRL_DDMA_LEGACY |
|
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|
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|
COH901318_CX_CTRL_PRDD_SOURCE,
|
|
|
|
|
.param.ctrl_lli_last = 0 |
|
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COH901318_CX_CTRL_TC_ENABLE |
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COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
|
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COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
|
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COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
|
|
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COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
|
|
|
|
|
COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
|
|
|
|
|
COH901318_CX_CTRL_TCP_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_TC_IRQ_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSP_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSS_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_DDMA_LEGACY |
|
|
|
|
|
COH901318_CX_CTRL_PRDD_SOURCE,
|
|
|
|
|
.desc_nbr_max = 10,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.number = U300_DMA_MSL_TX_3,
|
|
|
|
|
.name = "MSL TX 3",
|
|
|
|
|
.priority_high = 0,
|
|
|
|
|
.param.config = COH901318_CX_CFG_CH_DISABLE |
|
|
|
|
|
COH901318_CX_CFG_LCR_DISABLE |
|
|
|
|
|
COH901318_CX_CFG_TC_IRQ_ENABLE |
|
|
|
|
|
COH901318_CX_CFG_BE_IRQ_ENABLE,
|
|
|
|
|
.param.ctrl_lli_chained = 0 |
|
|
|
|
|
COH901318_CX_CTRL_TC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
|
|
|
|
|
COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
|
|
|
|
|
COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
|
|
|
|
|
COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
|
|
|
|
|
COH901318_CX_CTRL_TCP_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_TC_IRQ_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSP_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSS_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_DDMA_LEGACY |
|
|
|
|
|
COH901318_CX_CTRL_PRDD_SOURCE,
|
|
|
|
|
.param.ctrl_lli = 0 |
|
|
|
|
|
COH901318_CX_CTRL_TC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
|
|
|
|
|
COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
|
|
|
|
|
COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
|
|
|
|
|
COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
|
|
|
|
|
COH901318_CX_CTRL_TCP_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_TC_IRQ_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSP_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSS_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_DDMA_LEGACY |
|
|
|
|
|
COH901318_CX_CTRL_PRDD_SOURCE,
|
|
|
|
|
.param.ctrl_lli_last = 0 |
|
|
|
|
|
COH901318_CX_CTRL_TC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
|
|
|
|
|
COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
|
|
|
|
|
COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
|
|
|
|
|
COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
|
|
|
|
|
COH901318_CX_CTRL_TCP_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_TC_IRQ_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSP_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSS_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_DDMA_LEGACY |
|
|
|
|
|
COH901318_CX_CTRL_PRDD_SOURCE,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.number = U300_DMA_MSL_TX_4,
|
|
|
|
|
.name = "MSL TX 4",
|
|
|
|
|
.priority_high = 0,
|
|
|
|
|
.param.config = COH901318_CX_CFG_CH_DISABLE |
|
|
|
|
|
COH901318_CX_CFG_LCR_DISABLE |
|
|
|
|
|
COH901318_CX_CFG_TC_IRQ_ENABLE |
|
|
|
|
|
COH901318_CX_CFG_BE_IRQ_ENABLE,
|
|
|
|
|
.param.ctrl_lli_chained = 0 |
|
|
|
|
|
COH901318_CX_CTRL_TC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
|
|
|
|
|
COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
|
|
|
|
|
COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
|
|
|
|
|
COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
|
|
|
|
|
COH901318_CX_CTRL_TCP_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_TC_IRQ_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSP_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSS_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_DDMA_LEGACY |
|
|
|
|
|
COH901318_CX_CTRL_PRDD_SOURCE,
|
|
|
|
|
.param.ctrl_lli = 0 |
|
|
|
|
|
COH901318_CX_CTRL_TC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
|
|
|
|
|
COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
|
|
|
|
|
COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
|
|
|
|
|
COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
|
|
|
|
|
COH901318_CX_CTRL_TCP_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_TC_IRQ_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSP_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSS_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_DDMA_LEGACY |
|
|
|
|
|
COH901318_CX_CTRL_PRDD_SOURCE,
|
|
|
|
|
.param.ctrl_lli_last = 0 |
|
|
|
|
|
COH901318_CX_CTRL_TC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
|
|
|
|
|
COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
|
|
|
|
|
COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
|
|
|
|
|
COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
|
|
|
|
|
COH901318_CX_CTRL_TCP_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_TC_IRQ_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSP_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSS_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_DDMA_LEGACY |
|
|
|
|
|
COH901318_CX_CTRL_PRDD_SOURCE,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.number = U300_DMA_MSL_TX_5,
|
|
|
|
|
.name = "MSL TX 5",
|
|
|
|
|
.priority_high = 0,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.number = U300_DMA_MSL_TX_6,
|
|
|
|
|
.name = "MSL TX 6",
|
|
|
|
|
.priority_high = 0,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.number = U300_DMA_MSL_RX_0,
|
|
|
|
|
.name = "MSL RX 0",
|
|
|
|
|
.priority_high = 0,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.number = U300_DMA_MSL_RX_1,
|
|
|
|
|
.name = "MSL RX 1",
|
|
|
|
|
.priority_high = 0,
|
|
|
|
|
.param.config = COH901318_CX_CFG_CH_DISABLE |
|
|
|
|
|
COH901318_CX_CFG_LCR_DISABLE |
|
|
|
|
|
COH901318_CX_CFG_TC_IRQ_ENABLE |
|
|
|
|
|
COH901318_CX_CFG_BE_IRQ_ENABLE,
|
|
|
|
|
.param.ctrl_lli_chained = 0 |
|
|
|
|
|
COH901318_CX_CTRL_TC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
|
|
|
|
|
COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
|
|
|
|
|
COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
|
|
|
|
|
COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
|
|
|
|
|
COH901318_CX_CTRL_TCP_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_TC_IRQ_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSP_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSS_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
|
|
|
|
|
COH901318_CX_CTRL_PRDD_DEST,
|
|
|
|
|
.param.ctrl_lli = 0,
|
|
|
|
|
.param.ctrl_lli_last = 0 |
|
|
|
|
|
COH901318_CX_CTRL_TC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
|
|
|
|
|
COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
|
|
|
|
|
COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
|
|
|
|
|
COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
|
|
|
|
|
COH901318_CX_CTRL_TCP_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_TC_IRQ_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSP_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSS_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
|
|
|
|
|
COH901318_CX_CTRL_PRDD_DEST,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.number = U300_DMA_MSL_RX_2,
|
|
|
|
|
.name = "MSL RX 2",
|
|
|
|
|
.priority_high = 0,
|
|
|
|
|
.param.config = COH901318_CX_CFG_CH_DISABLE |
|
|
|
|
|
COH901318_CX_CFG_LCR_DISABLE |
|
|
|
|
|
COH901318_CX_CFG_TC_IRQ_ENABLE |
|
|
|
|
|
COH901318_CX_CFG_BE_IRQ_ENABLE,
|
|
|
|
|
.param.ctrl_lli_chained = 0 |
|
|
|
|
|
COH901318_CX_CTRL_TC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
|
|
|
|
|
COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
|
|
|
|
|
COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
|
|
|
|
|
COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
|
|
|
|
|
COH901318_CX_CTRL_TCP_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_TC_IRQ_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSP_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSS_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
|
|
|
|
|
COH901318_CX_CTRL_PRDD_DEST,
|
|
|
|
|
.param.ctrl_lli = 0 |
|
|
|
|
|
COH901318_CX_CTRL_TC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
|
|
|
|
|
COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
|
|
|
|
|
COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
|
|
|
|
|
COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
|
|
|
|
|
COH901318_CX_CTRL_TCP_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_TC_IRQ_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSP_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSS_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
|
|
|
|
|
COH901318_CX_CTRL_PRDD_DEST,
|
|
|
|
|
.param.ctrl_lli_last = 0 |
|
|
|
|
|
COH901318_CX_CTRL_TC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
|
|
|
|
|
COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
|
|
|
|
|
COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
|
|
|
|
|
COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
|
|
|
|
|
COH901318_CX_CTRL_TCP_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_TC_IRQ_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSP_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSS_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
|
|
|
|
|
COH901318_CX_CTRL_PRDD_DEST,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.number = U300_DMA_MSL_RX_3,
|
|
|
|
|
.name = "MSL RX 3",
|
|
|
|
|
.priority_high = 0,
|
|
|
|
|
.param.config = COH901318_CX_CFG_CH_DISABLE |
|
|
|
|
|
COH901318_CX_CFG_LCR_DISABLE |
|
|
|
|
|
COH901318_CX_CFG_TC_IRQ_ENABLE |
|
|
|
|
|
COH901318_CX_CFG_BE_IRQ_ENABLE,
|
|
|
|
|
.param.ctrl_lli_chained = 0 |
|
|
|
|
|
COH901318_CX_CTRL_TC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
|
|
|
|
|
COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
|
|
|
|
|
COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
|
|
|
|
|
COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
|
|
|
|
|
COH901318_CX_CTRL_TCP_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_TC_IRQ_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSP_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSS_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
|
|
|
|
|
COH901318_CX_CTRL_PRDD_DEST,
|
|
|
|
|
.param.ctrl_lli = 0 |
|
|
|
|
|
COH901318_CX_CTRL_TC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
|
|
|
|
|
COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
|
|
|
|
|
COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
|
|
|
|
|
COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
|
|
|
|
|
COH901318_CX_CTRL_TCP_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_TC_IRQ_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSP_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSS_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
|
|
|
|
|
COH901318_CX_CTRL_PRDD_DEST,
|
|
|
|
|
.param.ctrl_lli_last = 0 |
|
|
|
|
|
COH901318_CX_CTRL_TC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
|
|
|
|
|
COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
|
|
|
|
|
COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
|
|
|
|
|
COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
|
|
|
|
|
COH901318_CX_CTRL_TCP_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_TC_IRQ_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSP_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSS_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
|
|
|
|
|
COH901318_CX_CTRL_PRDD_DEST,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.number = U300_DMA_MSL_RX_4,
|
|
|
|
|
.name = "MSL RX 4",
|
|
|
|
|
.priority_high = 0,
|
|
|
|
|
.param.config = COH901318_CX_CFG_CH_DISABLE |
|
|
|
|
|
COH901318_CX_CFG_LCR_DISABLE |
|
|
|
|
|
COH901318_CX_CFG_TC_IRQ_ENABLE |
|
|
|
|
|
COH901318_CX_CFG_BE_IRQ_ENABLE,
|
|
|
|
|
.param.ctrl_lli_chained = 0 |
|
|
|
|
|
COH901318_CX_CTRL_TC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
|
|
|
|
|
COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
|
|
|
|
|
COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
|
|
|
|
|
COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
|
|
|
|
|
COH901318_CX_CTRL_TCP_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_TC_IRQ_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSP_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSS_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
|
|
|
|
|
COH901318_CX_CTRL_PRDD_DEST,
|
|
|
|
|
.param.ctrl_lli = 0 |
|
|
|
|
|
COH901318_CX_CTRL_TC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
|
|
|
|
|
COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
|
|
|
|
|
COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
|
|
|
|
|
COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
|
|
|
|
|
COH901318_CX_CTRL_TCP_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_TC_IRQ_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSP_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSS_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
|
|
|
|
|
COH901318_CX_CTRL_PRDD_DEST,
|
|
|
|
|
.param.ctrl_lli_last = 0 |
|
|
|
|
|
COH901318_CX_CTRL_TC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
|
|
|
|
|
COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
|
|
|
|
|
COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
|
|
|
|
|
COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
|
|
|
|
|
COH901318_CX_CTRL_TCP_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_TC_IRQ_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSP_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSS_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
|
|
|
|
|
COH901318_CX_CTRL_PRDD_DEST,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.number = U300_DMA_MSL_RX_5,
|
|
|
|
|
.name = "MSL RX 5",
|
|
|
|
|
.priority_high = 0,
|
|
|
|
|
.param.config = COH901318_CX_CFG_CH_DISABLE |
|
|
|
|
|
COH901318_CX_CFG_LCR_DISABLE |
|
|
|
|
|
COH901318_CX_CFG_TC_IRQ_ENABLE |
|
|
|
|
|
COH901318_CX_CFG_BE_IRQ_ENABLE,
|
|
|
|
|
.param.ctrl_lli_chained = 0 |
|
|
|
|
|
COH901318_CX_CTRL_TC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
|
|
|
|
|
COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
|
|
|
|
|
COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
|
|
|
|
|
COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
|
|
|
|
|
COH901318_CX_CTRL_TCP_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_TC_IRQ_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSP_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSS_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
|
|
|
|
|
COH901318_CX_CTRL_PRDD_DEST,
|
|
|
|
|
.param.ctrl_lli = 0 |
|
|
|
|
|
COH901318_CX_CTRL_TC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
|
|
|
|
|
COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
|
|
|
|
|
COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
|
|
|
|
|
COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
|
|
|
|
|
COH901318_CX_CTRL_TCP_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_TC_IRQ_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSP_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSS_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
|
|
|
|
|
COH901318_CX_CTRL_PRDD_DEST,
|
|
|
|
|
.param.ctrl_lli_last = 0 |
|
|
|
|
|
COH901318_CX_CTRL_TC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
|
|
|
|
|
COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
|
|
|
|
|
COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
|
|
|
|
|
COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
|
|
|
|
|
COH901318_CX_CTRL_TCP_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_TC_IRQ_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSP_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSS_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
|
|
|
|
|
COH901318_CX_CTRL_PRDD_DEST,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.number = U300_DMA_MSL_RX_6,
|
|
|
|
|
.name = "MSL RX 6",
|
|
|
|
|
.priority_high = 0,
|
|
|
|
|
},
|
|
|
|
|
/*
|
|
|
|
|
* Don't set up device address, burst count or size of src
|
|
|
|
|
* or dst bus for this peripheral - handled by PrimeCell
|
|
|
|
|
* DMA extension.
|
|
|
|
|
*/
|
|
|
|
|
{
|
|
|
|
|
.number = U300_DMA_MMCSD_RX_TX,
|
|
|
|
|
.name = "MMCSD RX TX",
|
|
|
|
|
.priority_high = 0,
|
|
|
|
|
.param.config = COH901318_CX_CFG_CH_DISABLE |
|
|
|
|
|
COH901318_CX_CFG_LCR_DISABLE |
|
|
|
|
|
COH901318_CX_CFG_TC_IRQ_ENABLE |
|
|
|
|
|
COH901318_CX_CFG_BE_IRQ_ENABLE,
|
|
|
|
|
.param.ctrl_lli_chained = 0 |
|
|
|
|
|
COH901318_CX_CTRL_TC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_MASTER_MODE_M1RW |
|
|
|
|
|
COH901318_CX_CTRL_TCP_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_TC_IRQ_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSP_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSS_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_DDMA_LEGACY,
|
|
|
|
|
.param.ctrl_lli = 0 |
|
|
|
|
|
COH901318_CX_CTRL_TC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_MASTER_MODE_M1RW |
|
|
|
|
|
COH901318_CX_CTRL_TCP_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_TC_IRQ_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSP_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSS_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_DDMA_LEGACY,
|
|
|
|
|
.param.ctrl_lli_last = 0 |
|
|
|
|
|
COH901318_CX_CTRL_TC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_MASTER_MODE_M1RW |
|
|
|
|
|
COH901318_CX_CTRL_TCP_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_TC_IRQ_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSP_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSS_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_DDMA_LEGACY,
|
|
|
|
|
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.number = U300_DMA_MSPRO_TX,
|
|
|
|
|
.name = "MSPRO TX",
|
|
|
|
|
.priority_high = 0,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.number = U300_DMA_MSPRO_RX,
|
|
|
|
|
.name = "MSPRO RX",
|
|
|
|
|
.priority_high = 0,
|
|
|
|
|
},
|
|
|
|
|
/*
|
|
|
|
|
* Don't set up device address, burst count or size of src
|
|
|
|
|
* or dst bus for this peripheral - handled by PrimeCell
|
|
|
|
|
* DMA extension.
|
|
|
|
|
*/
|
|
|
|
|
{
|
|
|
|
|
.number = U300_DMA_UART0_TX,
|
|
|
|
|
.name = "UART0 TX",
|
|
|
|
|
.priority_high = 0,
|
|
|
|
|
.param.config = COH901318_CX_CFG_CH_DISABLE |
|
|
|
|
|
COH901318_CX_CFG_LCR_DISABLE |
|
|
|
|
|
COH901318_CX_CFG_TC_IRQ_ENABLE |
|
|
|
|
|
COH901318_CX_CFG_BE_IRQ_ENABLE,
|
|
|
|
|
.param.ctrl_lli_chained = 0 |
|
|
|
|
|
COH901318_CX_CTRL_TC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_MASTER_MODE_M1RW |
|
|
|
|
|
COH901318_CX_CTRL_TCP_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_TC_IRQ_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSP_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSS_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_DDMA_LEGACY,
|
|
|
|
|
.param.ctrl_lli = 0 |
|
|
|
|
|
COH901318_CX_CTRL_TC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_MASTER_MODE_M1RW |
|
|
|
|
|
COH901318_CX_CTRL_TCP_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_TC_IRQ_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSP_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSS_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_DDMA_LEGACY,
|
|
|
|
|
.param.ctrl_lli_last = 0 |
|
|
|
|
|
COH901318_CX_CTRL_TC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_MASTER_MODE_M1RW |
|
|
|
|
|
COH901318_CX_CTRL_TCP_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_TC_IRQ_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSP_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSS_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_DDMA_LEGACY,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.number = U300_DMA_UART0_RX,
|
|
|
|
|
.name = "UART0 RX",
|
|
|
|
|
.priority_high = 0,
|
|
|
|
|
.param.config = COH901318_CX_CFG_CH_DISABLE |
|
|
|
|
|
COH901318_CX_CFG_LCR_DISABLE |
|
|
|
|
|
COH901318_CX_CFG_TC_IRQ_ENABLE |
|
|
|
|
|
COH901318_CX_CFG_BE_IRQ_ENABLE,
|
|
|
|
|
.param.ctrl_lli_chained = 0 |
|
|
|
|
|
COH901318_CX_CTRL_TC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_MASTER_MODE_M1RW |
|
|
|
|
|
COH901318_CX_CTRL_TCP_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_TC_IRQ_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSP_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSS_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_DDMA_LEGACY,
|
|
|
|
|
.param.ctrl_lli = 0 |
|
|
|
|
|
COH901318_CX_CTRL_TC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_MASTER_MODE_M1RW |
|
|
|
|
|
COH901318_CX_CTRL_TCP_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_TC_IRQ_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSP_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSS_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_DDMA_LEGACY,
|
|
|
|
|
.param.ctrl_lli_last = 0 |
|
|
|
|
|
COH901318_CX_CTRL_TC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_MASTER_MODE_M1RW |
|
|
|
|
|
COH901318_CX_CTRL_TCP_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_TC_IRQ_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSP_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSS_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_DDMA_LEGACY,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.number = U300_DMA_APEX_TX,
|
|
|
|
|
.name = "APEX TX",
|
|
|
|
|
.priority_high = 0,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.number = U300_DMA_APEX_RX,
|
|
|
|
|
.name = "APEX RX",
|
|
|
|
|
.priority_high = 0,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.number = U300_DMA_PCM_I2S0_TX,
|
|
|
|
|
.name = "PCM I2S0 TX",
|
|
|
|
|
.priority_high = 1,
|
|
|
|
|
.param.config = COH901318_CX_CFG_CH_DISABLE |
|
|
|
|
|
COH901318_CX_CFG_LCR_DISABLE |
|
|
|
|
|
COH901318_CX_CFG_TC_IRQ_ENABLE |
|
|
|
|
|
COH901318_CX_CFG_BE_IRQ_ENABLE,
|
|
|
|
|
.param.ctrl_lli_chained = 0 |
|
|
|
|
|
COH901318_CX_CTRL_TC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
|
|
|
|
|
COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
|
|
|
|
|
COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
|
|
|
|
|
COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_MASTER_MODE_M1RW |
|
|
|
|
|
COH901318_CX_CTRL_TCP_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_TC_IRQ_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSP_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSS_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_DDMA_LEGACY |
|
|
|
|
|
COH901318_CX_CTRL_PRDD_SOURCE,
|
|
|
|
|
.param.ctrl_lli = 0 |
|
|
|
|
|
COH901318_CX_CTRL_TC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
|
|
|
|
|
COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
|
|
|
|
|
COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
|
|
|
|
|
COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_MASTER_MODE_M1RW |
|
|
|
|
|
COH901318_CX_CTRL_TCP_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_TC_IRQ_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSP_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSS_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_DDMA_LEGACY |
|
|
|
|
|
COH901318_CX_CTRL_PRDD_SOURCE,
|
|
|
|
|
.param.ctrl_lli_last = 0 |
|
|
|
|
|
COH901318_CX_CTRL_TC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
|
|
|
|
|
COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
|
|
|
|
|
COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
|
|
|
|
|
COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_MASTER_MODE_M1RW |
|
|
|
|
|
COH901318_CX_CTRL_TCP_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_TC_IRQ_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSP_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSS_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_DDMA_LEGACY |
|
|
|
|
|
COH901318_CX_CTRL_PRDD_SOURCE,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.number = U300_DMA_PCM_I2S0_RX,
|
|
|
|
|
.name = "PCM I2S0 RX",
|
|
|
|
|
.priority_high = 1,
|
|
|
|
|
.param.config = COH901318_CX_CFG_CH_DISABLE |
|
|
|
|
|
COH901318_CX_CFG_LCR_DISABLE |
|
|
|
|
|
COH901318_CX_CFG_TC_IRQ_ENABLE |
|
|
|
|
|
COH901318_CX_CFG_BE_IRQ_ENABLE,
|
|
|
|
|
.param.ctrl_lli_chained = 0 |
|
|
|
|
|
COH901318_CX_CTRL_TC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
|
|
|
|
|
COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
|
|
|
|
|
COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
|
|
|
|
|
COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_MASTER_MODE_M1RW |
|
|
|
|
|
COH901318_CX_CTRL_TCP_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_TC_IRQ_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSP_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSS_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_DDMA_LEGACY |
|
|
|
|
|
COH901318_CX_CTRL_PRDD_DEST,
|
|
|
|
|
.param.ctrl_lli = 0 |
|
|
|
|
|
COH901318_CX_CTRL_TC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
|
|
|
|
|
COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
|
|
|
|
|
COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
|
|
|
|
|
COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_MASTER_MODE_M1RW |
|
|
|
|
|
COH901318_CX_CTRL_TCP_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_TC_IRQ_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSP_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSS_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_DDMA_LEGACY |
|
|
|
|
|
COH901318_CX_CTRL_PRDD_DEST,
|
|
|
|
|
.param.ctrl_lli_last = 0 |
|
|
|
|
|
COH901318_CX_CTRL_TC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
|
|
|
|
|
COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
|
|
|
|
|
COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
|
|
|
|
|
COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_MASTER_MODE_M1RW |
|
|
|
|
|
COH901318_CX_CTRL_TCP_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_TC_IRQ_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSP_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSS_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_DDMA_LEGACY |
|
|
|
|
|
COH901318_CX_CTRL_PRDD_DEST,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.number = U300_DMA_PCM_I2S1_TX,
|
|
|
|
|
.name = "PCM I2S1 TX",
|
|
|
|
|
.priority_high = 1,
|
|
|
|
|
.param.config = COH901318_CX_CFG_CH_DISABLE |
|
|
|
|
|
COH901318_CX_CFG_LCR_DISABLE |
|
|
|
|
|
COH901318_CX_CFG_TC_IRQ_ENABLE |
|
|
|
|
|
COH901318_CX_CFG_BE_IRQ_ENABLE,
|
|
|
|
|
.param.ctrl_lli_chained = 0 |
|
|
|
|
|
COH901318_CX_CTRL_TC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
|
|
|
|
|
COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
|
|
|
|
|
COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
|
|
|
|
|
COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_MASTER_MODE_M1RW |
|
|
|
|
|
COH901318_CX_CTRL_TCP_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_TC_IRQ_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSP_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSS_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_DDMA_LEGACY |
|
|
|
|
|
COH901318_CX_CTRL_PRDD_SOURCE,
|
|
|
|
|
.param.ctrl_lli = 0 |
|
|
|
|
|
COH901318_CX_CTRL_TC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
|
|
|
|
|
COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
|
|
|
|
|
COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
|
|
|
|
|
COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_MASTER_MODE_M1RW |
|
|
|
|
|
COH901318_CX_CTRL_TCP_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_TC_IRQ_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSP_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSS_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_DDMA_LEGACY |
|
|
|
|
|
COH901318_CX_CTRL_PRDD_SOURCE,
|
|
|
|
|
.param.ctrl_lli_last = 0 |
|
|
|
|
|
COH901318_CX_CTRL_TC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
|
|
|
|
|
COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
|
|
|
|
|
COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
|
|
|
|
|
COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_MASTER_MODE_M1RW |
|
|
|
|
|
COH901318_CX_CTRL_TCP_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_TC_IRQ_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSP_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSS_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_DDMA_LEGACY |
|
|
|
|
|
COH901318_CX_CTRL_PRDD_SOURCE,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.number = U300_DMA_PCM_I2S1_RX,
|
|
|
|
|
.name = "PCM I2S1 RX",
|
|
|
|
|
.priority_high = 1,
|
|
|
|
|
.param.config = COH901318_CX_CFG_CH_DISABLE |
|
|
|
|
|
COH901318_CX_CFG_LCR_DISABLE |
|
|
|
|
|
COH901318_CX_CFG_TC_IRQ_ENABLE |
|
|
|
|
|
COH901318_CX_CFG_BE_IRQ_ENABLE,
|
|
|
|
|
.param.ctrl_lli_chained = 0 |
|
|
|
|
|
COH901318_CX_CTRL_TC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
|
|
|
|
|
COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
|
|
|
|
|
COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
|
|
|
|
|
COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_MASTER_MODE_M1RW |
|
|
|
|
|
COH901318_CX_CTRL_TCP_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_TC_IRQ_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSP_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSS_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_DDMA_LEGACY |
|
|
|
|
|
COH901318_CX_CTRL_PRDD_DEST,
|
|
|
|
|
.param.ctrl_lli = 0 |
|
|
|
|
|
COH901318_CX_CTRL_TC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
|
|
|
|
|
COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
|
|
|
|
|
COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
|
|
|
|
|
COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_MASTER_MODE_M1RW |
|
|
|
|
|
COH901318_CX_CTRL_TCP_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_TC_IRQ_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSP_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSS_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_DDMA_LEGACY |
|
|
|
|
|
COH901318_CX_CTRL_PRDD_DEST,
|
|
|
|
|
.param.ctrl_lli_last = 0 |
|
|
|
|
|
COH901318_CX_CTRL_TC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
|
|
|
|
|
COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
|
|
|
|
|
COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
|
|
|
|
|
COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_MASTER_MODE_M1RW |
|
|
|
|
|
COH901318_CX_CTRL_TCP_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_TC_IRQ_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSP_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSS_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_DDMA_LEGACY |
|
|
|
|
|
COH901318_CX_CTRL_PRDD_DEST,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.number = U300_DMA_XGAM_CDI,
|
|
|
|
|
.name = "XGAM CDI",
|
|
|
|
|
.priority_high = 0,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.number = U300_DMA_XGAM_PDI,
|
|
|
|
|
.name = "XGAM PDI",
|
|
|
|
|
.priority_high = 0,
|
|
|
|
|
},
|
|
|
|
|
/*
|
|
|
|
|
* Don't set up device address, burst count or size of src
|
|
|
|
|
* or dst bus for this peripheral - handled by PrimeCell
|
|
|
|
|
* DMA extension.
|
|
|
|
|
*/
|
|
|
|
|
{
|
|
|
|
|
.number = U300_DMA_SPI_TX,
|
|
|
|
|
.name = "SPI TX",
|
|
|
|
|
.priority_high = 0,
|
|
|
|
|
.param.config = COH901318_CX_CFG_CH_DISABLE |
|
|
|
|
|
COH901318_CX_CFG_LCR_DISABLE |
|
|
|
|
|
COH901318_CX_CFG_TC_IRQ_ENABLE |
|
|
|
|
|
COH901318_CX_CFG_BE_IRQ_ENABLE,
|
|
|
|
|
.param.ctrl_lli_chained = 0 |
|
|
|
|
|
COH901318_CX_CTRL_TC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_MASTER_MODE_M1RW |
|
|
|
|
|
COH901318_CX_CTRL_TCP_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_TC_IRQ_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSP_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSS_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_DDMA_LEGACY,
|
|
|
|
|
.param.ctrl_lli = 0 |
|
|
|
|
|
COH901318_CX_CTRL_TC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_MASTER_MODE_M1RW |
|
|
|
|
|
COH901318_CX_CTRL_TCP_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_TC_IRQ_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSP_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSS_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_DDMA_LEGACY,
|
|
|
|
|
.param.ctrl_lli_last = 0 |
|
|
|
|
|
COH901318_CX_CTRL_TC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_MASTER_MODE_M1RW |
|
|
|
|
|
COH901318_CX_CTRL_TCP_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_TC_IRQ_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSP_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSS_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_DDMA_LEGACY,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.number = U300_DMA_SPI_RX,
|
|
|
|
|
.name = "SPI RX",
|
|
|
|
|
.priority_high = 0,
|
|
|
|
|
.param.config = COH901318_CX_CFG_CH_DISABLE |
|
|
|
|
|
COH901318_CX_CFG_LCR_DISABLE |
|
|
|
|
|
COH901318_CX_CFG_TC_IRQ_ENABLE |
|
|
|
|
|
COH901318_CX_CFG_BE_IRQ_ENABLE,
|
|
|
|
|
.param.ctrl_lli_chained = 0 |
|
|
|
|
|
COH901318_CX_CTRL_TC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_MASTER_MODE_M1RW |
|
|
|
|
|
COH901318_CX_CTRL_TCP_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_TC_IRQ_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSP_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSS_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_DDMA_LEGACY,
|
|
|
|
|
.param.ctrl_lli = 0 |
|
|
|
|
|
COH901318_CX_CTRL_TC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_MASTER_MODE_M1RW |
|
|
|
|
|
COH901318_CX_CTRL_TCP_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_TC_IRQ_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSP_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSS_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_DDMA_LEGACY,
|
|
|
|
|
.param.ctrl_lli_last = 0 |
|
|
|
|
|
COH901318_CX_CTRL_TC_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_MASTER_MODE_M1RW |
|
|
|
|
|
COH901318_CX_CTRL_TCP_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_TC_IRQ_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSP_ENABLE |
|
|
|
|
|
COH901318_CX_CTRL_HSS_DISABLE |
|
|
|
|
|
COH901318_CX_CTRL_DDMA_LEGACY,
|
|
|
|
|
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.number = U300_DMA_GENERAL_PURPOSE_0,
|
|
|
|
|
.name = "GENERAL 00",
|
|
|
|
|
.priority_high = 0,
|
|
|
|
|
|
|
|
|
|
.param.config = flags_memcpy_config,
|
|
|
|
|
.param.ctrl_lli_chained = flags_memcpy_lli_chained,
|
|
|
|
|
.param.ctrl_lli = flags_memcpy_lli,
|
|
|
|
|
.param.ctrl_lli_last = flags_memcpy_lli_last,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.number = U300_DMA_GENERAL_PURPOSE_1,
|
|
|
|
|
.name = "GENERAL 01",
|
|
|
|
|
.priority_high = 0,
|
|
|
|
|
|
|
|
|
|
.param.config = flags_memcpy_config,
|
|
|
|
|
.param.ctrl_lli_chained = flags_memcpy_lli_chained,
|
|
|
|
|
.param.ctrl_lli = flags_memcpy_lli,
|
|
|
|
|
.param.ctrl_lli_last = flags_memcpy_lli_last,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.number = U300_DMA_GENERAL_PURPOSE_2,
|
|
|
|
|
.name = "GENERAL 02",
|
|
|
|
|
.priority_high = 0,
|
|
|
|
|
|
|
|
|
|
.param.config = flags_memcpy_config,
|
|
|
|
|
.param.ctrl_lli_chained = flags_memcpy_lli_chained,
|
|
|
|
|
.param.ctrl_lli = flags_memcpy_lli,
|
|
|
|
|
.param.ctrl_lli_last = flags_memcpy_lli_last,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.number = U300_DMA_GENERAL_PURPOSE_3,
|
|
|
|
|
.name = "GENERAL 03",
|
|
|
|
|
.priority_high = 0,
|
|
|
|
|
|
|
|
|
|
.param.config = flags_memcpy_config,
|
|
|
|
|
.param.ctrl_lli_chained = flags_memcpy_lli_chained,
|
|
|
|
|
.param.ctrl_lli = flags_memcpy_lli,
|
|
|
|
|
.param.ctrl_lli_last = flags_memcpy_lli_last,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.number = U300_DMA_GENERAL_PURPOSE_4,
|
|
|
|
|
.name = "GENERAL 04",
|
|
|
|
|
.priority_high = 0,
|
|
|
|
|
|
|
|
|
|
.param.config = flags_memcpy_config,
|
|
|
|
|
.param.ctrl_lli_chained = flags_memcpy_lli_chained,
|
|
|
|
|
.param.ctrl_lli = flags_memcpy_lli,
|
|
|
|
|
.param.ctrl_lli_last = flags_memcpy_lli_last,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.number = U300_DMA_GENERAL_PURPOSE_5,
|
|
|
|
|
.name = "GENERAL 05",
|
|
|
|
|
.priority_high = 0,
|
|
|
|
|
|
|
|
|
|
.param.config = flags_memcpy_config,
|
|
|
|
|
.param.ctrl_lli_chained = flags_memcpy_lli_chained,
|
|
|
|
|
.param.ctrl_lli = flags_memcpy_lli,
|
|
|
|
|
.param.ctrl_lli_last = flags_memcpy_lli_last,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.number = U300_DMA_GENERAL_PURPOSE_6,
|
|
|
|
|
.name = "GENERAL 06",
|
|
|
|
|
.priority_high = 0,
|
|
|
|
|
|
|
|
|
|
.param.config = flags_memcpy_config,
|
|
|
|
|
.param.ctrl_lli_chained = flags_memcpy_lli_chained,
|
|
|
|
|
.param.ctrl_lli = flags_memcpy_lli,
|
|
|
|
|
.param.ctrl_lli_last = flags_memcpy_lli_last,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.number = U300_DMA_GENERAL_PURPOSE_7,
|
|
|
|
|
.name = "GENERAL 07",
|
|
|
|
|
.priority_high = 0,
|
|
|
|
|
|
|
|
|
|
.param.config = flags_memcpy_config,
|
|
|
|
|
.param.ctrl_lli_chained = flags_memcpy_lli_chained,
|
|
|
|
|
.param.ctrl_lli = flags_memcpy_lli,
|
|
|
|
|
.param.ctrl_lli_last = flags_memcpy_lli_last,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.number = U300_DMA_GENERAL_PURPOSE_8,
|
|
|
|
|
.name = "GENERAL 08",
|
|
|
|
|
.priority_high = 0,
|
|
|
|
|
|
|
|
|
|
.param.config = flags_memcpy_config,
|
|
|
|
|
.param.ctrl_lli_chained = flags_memcpy_lli_chained,
|
|
|
|
|
.param.ctrl_lli = flags_memcpy_lli,
|
|
|
|
|
.param.ctrl_lli_last = flags_memcpy_lli_last,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.number = U300_DMA_UART1_TX,
|
|
|
|
|
.name = "UART1 TX",
|
|
|
|
|
.priority_high = 0,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.number = U300_DMA_UART1_RX,
|
|
|
|
|
.name = "UART1 RX",
|
|
|
|
|
.priority_high = 0,
|
|
|
|
|
}
|
|
|
|
|
};
|
|
|
|
|
|
2009-11-20 02:49:17 +08:00
|
|
|
#define COHC_2_DEV(cohc) (&cohc->chan.dev->device)
|
|
|
|
|
|
|
|
|
|
#ifdef VERBOSE_DEBUG
|
|
|
|
|
#define COH_DBG(x) ({ if (1) x; 0; })
|
|
|
|
|
#else
|
|
|
|
|
#define COH_DBG(x) ({ if (0) x; 0; })
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
struct coh901318_desc {
|
|
|
|
|
struct dma_async_tx_descriptor desc;
|
|
|
|
|
struct list_head node;
|
|
|
|
|
struct scatterlist *sg;
|
|
|
|
|
unsigned int sg_len;
|
2010-03-04 21:31:47 +08:00
|
|
|
struct coh901318_lli *lli;
|
2011-10-14 01:04:23 +08:00
|
|
|
enum dma_transfer_direction dir;
|
2009-11-20 02:49:17 +08:00
|
|
|
unsigned long flags;
|
2011-07-01 22:47:28 +08:00
|
|
|
u32 head_config;
|
|
|
|
|
u32 head_ctrl;
|
2009-11-20 02:49:17 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
struct coh901318_base {
|
|
|
|
|
struct device *dev;
|
|
|
|
|
void __iomem *virtbase;
|
|
|
|
|
struct coh901318_pool pool;
|
|
|
|
|
struct powersave pm;
|
|
|
|
|
struct dma_device dma_slave;
|
|
|
|
|
struct dma_device dma_memcpy;
|
|
|
|
|
struct coh901318_chan *chans;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
struct coh901318_chan {
|
|
|
|
|
spinlock_t lock;
|
|
|
|
|
int allocated;
|
|
|
|
|
int id;
|
|
|
|
|
int stopped;
|
|
|
|
|
|
|
|
|
|
struct work_struct free_work;
|
|
|
|
|
struct dma_chan chan;
|
|
|
|
|
|
|
|
|
|
struct tasklet_struct tasklet;
|
|
|
|
|
|
|
|
|
|
struct list_head active;
|
|
|
|
|
struct list_head queue;
|
|
|
|
|
struct list_head free;
|
|
|
|
|
|
|
|
|
|
unsigned long nbr_active_done;
|
|
|
|
|
unsigned long busy;
|
|
|
|
|
|
2013-01-04 20:50:49 +08:00
|
|
|
u32 addr;
|
|
|
|
|
u32 ctrl;
|
2010-08-04 19:37:53 +08:00
|
|
|
|
2009-11-20 02:49:17 +08:00
|
|
|
struct coh901318_base *base;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static void coh901318_list_print(struct coh901318_chan *cohc,
|
|
|
|
|
struct coh901318_lli *lli)
|
|
|
|
|
{
|
2010-03-03 05:17:15 +08:00
|
|
|
struct coh901318_lli *l = lli;
|
2009-11-20 02:49:17 +08:00
|
|
|
int i = 0;
|
|
|
|
|
|
2010-03-03 05:17:15 +08:00
|
|
|
while (l) {
|
2009-11-20 02:49:17 +08:00
|
|
|
dev_vdbg(COHC_2_DEV(cohc), "i %d, lli %p, ctrl 0x%x, src 0x%x"
|
2010-03-03 05:17:15 +08:00
|
|
|
", dst 0x%x, link 0x%x virt_link_addr 0x%p\n",
|
2009-11-20 02:49:17 +08:00
|
|
|
i, l, l->control, l->src_addr, l->dst_addr,
|
2010-03-03 05:17:15 +08:00
|
|
|
l->link_addr, l->virt_link_addr);
|
2009-11-20 02:49:17 +08:00
|
|
|
i++;
|
2010-03-03 05:17:15 +08:00
|
|
|
l = l->virt_link_addr;
|
2009-11-20 02:49:17 +08:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_DEBUG_FS
|
|
|
|
|
|
|
|
|
|
#define COH901318_DEBUGFS_ASSIGN(x, y) (x = y)
|
|
|
|
|
|
|
|
|
|
static struct coh901318_base *debugfs_dma_base;
|
|
|
|
|
static struct dentry *dma_dentry;
|
|
|
|
|
|
|
|
|
|
static int coh901318_debugfs_read(struct file *file, char __user *buf,
|
|
|
|
|
size_t count, loff_t *f_pos)
|
|
|
|
|
{
|
|
|
|
|
u64 started_channels = debugfs_dma_base->pm.started_channels;
|
|
|
|
|
int pool_count = debugfs_dma_base->pool.debugfs_pool_counter;
|
|
|
|
|
char *dev_buf;
|
|
|
|
|
char *tmp;
|
2013-07-16 21:58:45 +08:00
|
|
|
int ret;
|
|
|
|
|
int i;
|
2009-11-20 02:49:17 +08:00
|
|
|
|
|
|
|
|
dev_buf = kmalloc(4*1024, GFP_KERNEL);
|
|
|
|
|
if (dev_buf == NULL)
|
2013-07-16 21:58:45 +08:00
|
|
|
return -ENOMEM;
|
2009-11-20 02:49:17 +08:00
|
|
|
tmp = dev_buf;
|
|
|
|
|
|
2010-03-03 05:17:15 +08:00
|
|
|
tmp += sprintf(tmp, "DMA -- enabled dma channels\n");
|
2009-11-20 02:49:17 +08:00
|
|
|
|
2013-01-07 06:36:14 +08:00
|
|
|
for (i = 0; i < U300_DMA_CHANNELS; i++)
|
2009-11-20 02:49:17 +08:00
|
|
|
if (started_channels & (1 << i))
|
|
|
|
|
tmp += sprintf(tmp, "channel %d\n", i);
|
|
|
|
|
|
|
|
|
|
tmp += sprintf(tmp, "Pool alloc nbr %d\n", pool_count);
|
|
|
|
|
|
2013-07-16 21:58:45 +08:00
|
|
|
ret = simple_read_from_buffer(buf, count, f_pos, dev_buf,
|
|
|
|
|
tmp - dev_buf);
|
2009-11-20 02:49:17 +08:00
|
|
|
kfree(dev_buf);
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static const struct file_operations coh901318_debugfs_status_operations = {
|
|
|
|
|
.owner = THIS_MODULE,
|
2012-04-06 05:25:11 +08:00
|
|
|
.open = simple_open,
|
2009-11-20 02:49:17 +08:00
|
|
|
.read = coh901318_debugfs_read,
|
llseek: automatically add .llseek fop
All file_operations should get a .llseek operation so we can make
nonseekable_open the default for future file operations without a
.llseek pointer.
The three cases that we can automatically detect are no_llseek, seq_lseek
and default_llseek. For cases where we can we can automatically prove that
the file offset is always ignored, we use noop_llseek, which maintains
the current behavior of not returning an error from a seek.
New drivers should normally not use noop_llseek but instead use no_llseek
and call nonseekable_open at open time. Existing drivers can be converted
to do the same when the maintainer knows for certain that no user code
relies on calling seek on the device file.
The generated code is often incorrectly indented and right now contains
comments that clarify for each added line why a specific variant was
chosen. In the version that gets submitted upstream, the comments will
be gone and I will manually fix the indentation, because there does not
seem to be a way to do that using coccinelle.
Some amount of new code is currently sitting in linux-next that should get
the same modifications, which I will do at the end of the merge window.
Many thanks to Julia Lawall for helping me learn to write a semantic
patch that does all this.
===== begin semantic patch =====
// This adds an llseek= method to all file operations,
// as a preparation for making no_llseek the default.
//
// The rules are
// - use no_llseek explicitly if we do nonseekable_open
// - use seq_lseek for sequential files
// - use default_llseek if we know we access f_pos
// - use noop_llseek if we know we don't access f_pos,
// but we still want to allow users to call lseek
//
@ open1 exists @
identifier nested_open;
@@
nested_open(...)
{
<+...
nonseekable_open(...)
...+>
}
@ open exists@
identifier open_f;
identifier i, f;
identifier open1.nested_open;
@@
int open_f(struct inode *i, struct file *f)
{
<+...
(
nonseekable_open(...)
|
nested_open(...)
)
...+>
}
@ read disable optional_qualifier exists @
identifier read_f;
identifier f, p, s, off;
type ssize_t, size_t, loff_t;
expression E;
identifier func;
@@
ssize_t read_f(struct file *f, char *p, size_t s, loff_t *off)
{
<+...
(
*off = E
|
*off += E
|
func(..., off, ...)
|
E = *off
)
...+>
}
@ read_no_fpos disable optional_qualifier exists @
identifier read_f;
identifier f, p, s, off;
type ssize_t, size_t, loff_t;
@@
ssize_t read_f(struct file *f, char *p, size_t s, loff_t *off)
{
... when != off
}
@ write @
identifier write_f;
identifier f, p, s, off;
type ssize_t, size_t, loff_t;
expression E;
identifier func;
@@
ssize_t write_f(struct file *f, const char *p, size_t s, loff_t *off)
{
<+...
(
*off = E
|
*off += E
|
func(..., off, ...)
|
E = *off
)
...+>
}
@ write_no_fpos @
identifier write_f;
identifier f, p, s, off;
type ssize_t, size_t, loff_t;
@@
ssize_t write_f(struct file *f, const char *p, size_t s, loff_t *off)
{
... when != off
}
@ fops0 @
identifier fops;
@@
struct file_operations fops = {
...
};
@ has_llseek depends on fops0 @
identifier fops0.fops;
identifier llseek_f;
@@
struct file_operations fops = {
...
.llseek = llseek_f,
...
};
@ has_read depends on fops0 @
identifier fops0.fops;
identifier read_f;
@@
struct file_operations fops = {
...
.read = read_f,
...
};
@ has_write depends on fops0 @
identifier fops0.fops;
identifier write_f;
@@
struct file_operations fops = {
...
.write = write_f,
...
};
@ has_open depends on fops0 @
identifier fops0.fops;
identifier open_f;
@@
struct file_operations fops = {
...
.open = open_f,
...
};
// use no_llseek if we call nonseekable_open
////////////////////////////////////////////
@ nonseekable1 depends on !has_llseek && has_open @
identifier fops0.fops;
identifier nso ~= "nonseekable_open";
@@
struct file_operations fops = {
... .open = nso, ...
+.llseek = no_llseek, /* nonseekable */
};
@ nonseekable2 depends on !has_llseek @
identifier fops0.fops;
identifier open.open_f;
@@
struct file_operations fops = {
... .open = open_f, ...
+.llseek = no_llseek, /* open uses nonseekable */
};
// use seq_lseek for sequential files
/////////////////////////////////////
@ seq depends on !has_llseek @
identifier fops0.fops;
identifier sr ~= "seq_read";
@@
struct file_operations fops = {
... .read = sr, ...
+.llseek = seq_lseek, /* we have seq_read */
};
// use default_llseek if there is a readdir
///////////////////////////////////////////
@ fops1 depends on !has_llseek && !nonseekable1 && !nonseekable2 && !seq @
identifier fops0.fops;
identifier readdir_e;
@@
// any other fop is used that changes pos
struct file_operations fops = {
... .readdir = readdir_e, ...
+.llseek = default_llseek, /* readdir is present */
};
// use default_llseek if at least one of read/write touches f_pos
/////////////////////////////////////////////////////////////////
@ fops2 depends on !fops1 && !has_llseek && !nonseekable1 && !nonseekable2 && !seq @
identifier fops0.fops;
identifier read.read_f;
@@
// read fops use offset
struct file_operations fops = {
... .read = read_f, ...
+.llseek = default_llseek, /* read accesses f_pos */
};
@ fops3 depends on !fops1 && !fops2 && !has_llseek && !nonseekable1 && !nonseekable2 && !seq @
identifier fops0.fops;
identifier write.write_f;
@@
// write fops use offset
struct file_operations fops = {
... .write = write_f, ...
+ .llseek = default_llseek, /* write accesses f_pos */
};
// Use noop_llseek if neither read nor write accesses f_pos
///////////////////////////////////////////////////////////
@ fops4 depends on !fops1 && !fops2 && !fops3 && !has_llseek && !nonseekable1 && !nonseekable2 && !seq @
identifier fops0.fops;
identifier read_no_fpos.read_f;
identifier write_no_fpos.write_f;
@@
// write fops use offset
struct file_operations fops = {
...
.write = write_f,
.read = read_f,
...
+.llseek = noop_llseek, /* read and write both use no f_pos */
};
@ depends on has_write && !has_read && !fops1 && !fops2 && !has_llseek && !nonseekable1 && !nonseekable2 && !seq @
identifier fops0.fops;
identifier write_no_fpos.write_f;
@@
struct file_operations fops = {
... .write = write_f, ...
+.llseek = noop_llseek, /* write uses no f_pos */
};
@ depends on has_read && !has_write && !fops1 && !fops2 && !has_llseek && !nonseekable1 && !nonseekable2 && !seq @
identifier fops0.fops;
identifier read_no_fpos.read_f;
@@
struct file_operations fops = {
... .read = read_f, ...
+.llseek = noop_llseek, /* read uses no f_pos */
};
@ depends on !has_read && !has_write && !fops1 && !fops2 && !has_llseek && !nonseekable1 && !nonseekable2 && !seq @
identifier fops0.fops;
@@
struct file_operations fops = {
...
+.llseek = noop_llseek, /* no read or write fn */
};
===== End semantic patch =====
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Cc: Julia Lawall <julia@diku.dk>
Cc: Christoph Hellwig <hch@infradead.org>
2010-08-16 00:52:59 +08:00
|
|
|
.llseek = default_llseek,
|
2009-11-20 02:49:17 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
static int __init init_coh901318_debugfs(void)
|
|
|
|
|
{
|
|
|
|
|
|
|
|
|
|
dma_dentry = debugfs_create_dir("dma", NULL);
|
|
|
|
|
|
|
|
|
|
(void) debugfs_create_file("status",
|
|
|
|
|
S_IFREG | S_IRUGO,
|
|
|
|
|
dma_dentry, NULL,
|
|
|
|
|
&coh901318_debugfs_status_operations);
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void __exit exit_coh901318_debugfs(void)
|
|
|
|
|
{
|
|
|
|
|
debugfs_remove_recursive(dma_dentry);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
module_init(init_coh901318_debugfs);
|
|
|
|
|
module_exit(exit_coh901318_debugfs);
|
|
|
|
|
#else
|
|
|
|
|
|
|
|
|
|
#define COH901318_DEBUGFS_ASSIGN(x, y)
|
|
|
|
|
|
|
|
|
|
#endif /* CONFIG_DEBUG_FS */
|
|
|
|
|
|
|
|
|
|
static inline struct coh901318_chan *to_coh901318_chan(struct dma_chan *chan)
|
|
|
|
|
{
|
|
|
|
|
return container_of(chan, struct coh901318_chan, chan);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline const struct coh901318_params *
|
|
|
|
|
cohc_chan_param(struct coh901318_chan *cohc)
|
|
|
|
|
{
|
2013-01-07 06:36:14 +08:00
|
|
|
return &chan_config[cohc->id].param;
|
2009-11-20 02:49:17 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline const struct coh_dma_channel *
|
|
|
|
|
cohc_chan_conf(struct coh901318_chan *cohc)
|
|
|
|
|
{
|
2013-01-07 06:36:14 +08:00
|
|
|
return &chan_config[cohc->id];
|
2009-11-20 02:49:17 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void enable_powersave(struct coh901318_chan *cohc)
|
|
|
|
|
{
|
|
|
|
|
unsigned long flags;
|
|
|
|
|
struct powersave *pm = &cohc->base->pm;
|
|
|
|
|
|
|
|
|
|
spin_lock_irqsave(&pm->lock, flags);
|
|
|
|
|
|
|
|
|
|
pm->started_channels &= ~(1ULL << cohc->id);
|
|
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&pm->lock, flags);
|
|
|
|
|
}
|
|
|
|
|
static void disable_powersave(struct coh901318_chan *cohc)
|
|
|
|
|
{
|
|
|
|
|
unsigned long flags;
|
|
|
|
|
struct powersave *pm = &cohc->base->pm;
|
|
|
|
|
|
|
|
|
|
spin_lock_irqsave(&pm->lock, flags);
|
|
|
|
|
|
|
|
|
|
pm->started_channels |= (1ULL << cohc->id);
|
|
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&pm->lock, flags);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline int coh901318_set_ctrl(struct coh901318_chan *cohc, u32 control)
|
|
|
|
|
{
|
|
|
|
|
int channel = cohc->id;
|
|
|
|
|
void __iomem *virtbase = cohc->base->virtbase;
|
|
|
|
|
|
|
|
|
|
writel(control,
|
|
|
|
|
virtbase + COH901318_CX_CTRL +
|
|
|
|
|
COH901318_CX_CTRL_SPACING * channel);
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline int coh901318_set_conf(struct coh901318_chan *cohc, u32 conf)
|
|
|
|
|
{
|
|
|
|
|
int channel = cohc->id;
|
|
|
|
|
void __iomem *virtbase = cohc->base->virtbase;
|
|
|
|
|
|
|
|
|
|
writel(conf,
|
|
|
|
|
virtbase + COH901318_CX_CFG +
|
|
|
|
|
COH901318_CX_CFG_SPACING*channel);
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
static int coh901318_start(struct coh901318_chan *cohc)
|
|
|
|
|
{
|
|
|
|
|
u32 val;
|
|
|
|
|
int channel = cohc->id;
|
|
|
|
|
void __iomem *virtbase = cohc->base->virtbase;
|
|
|
|
|
|
|
|
|
|
disable_powersave(cohc);
|
|
|
|
|
|
|
|
|
|
val = readl(virtbase + COH901318_CX_CFG +
|
|
|
|
|
COH901318_CX_CFG_SPACING * channel);
|
|
|
|
|
|
|
|
|
|
/* Enable channel */
|
|
|
|
|
val |= COH901318_CX_CFG_CH_ENABLE;
|
|
|
|
|
writel(val, virtbase + COH901318_CX_CFG +
|
|
|
|
|
COH901318_CX_CFG_SPACING * channel);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int coh901318_prep_linked_list(struct coh901318_chan *cohc,
|
2010-03-04 21:31:47 +08:00
|
|
|
struct coh901318_lli *lli)
|
2009-11-20 02:49:17 +08:00
|
|
|
{
|
|
|
|
|
int channel = cohc->id;
|
|
|
|
|
void __iomem *virtbase = cohc->base->virtbase;
|
|
|
|
|
|
|
|
|
|
BUG_ON(readl(virtbase + COH901318_CX_STAT +
|
|
|
|
|
COH901318_CX_STAT_SPACING*channel) &
|
|
|
|
|
COH901318_CX_STAT_ACTIVE);
|
|
|
|
|
|
2010-03-04 21:31:47 +08:00
|
|
|
writel(lli->src_addr,
|
2009-11-20 02:49:17 +08:00
|
|
|
virtbase + COH901318_CX_SRC_ADDR +
|
|
|
|
|
COH901318_CX_SRC_ADDR_SPACING * channel);
|
|
|
|
|
|
2010-03-04 21:31:47 +08:00
|
|
|
writel(lli->dst_addr, virtbase +
|
2009-11-20 02:49:17 +08:00
|
|
|
COH901318_CX_DST_ADDR +
|
|
|
|
|
COH901318_CX_DST_ADDR_SPACING * channel);
|
|
|
|
|
|
2010-03-04 21:31:47 +08:00
|
|
|
writel(lli->link_addr, virtbase + COH901318_CX_LNK_ADDR +
|
2009-11-20 02:49:17 +08:00
|
|
|
COH901318_CX_LNK_ADDR_SPACING * channel);
|
|
|
|
|
|
2010-03-04 21:31:47 +08:00
|
|
|
writel(lli->control, virtbase + COH901318_CX_CTRL +
|
2009-11-20 02:49:17 +08:00
|
|
|
COH901318_CX_CTRL_SPACING * channel);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static struct coh901318_desc *
|
|
|
|
|
coh901318_desc_get(struct coh901318_chan *cohc)
|
|
|
|
|
{
|
|
|
|
|
struct coh901318_desc *desc;
|
|
|
|
|
|
|
|
|
|
if (list_empty(&cohc->free)) {
|
|
|
|
|
/* alloc new desc because we're out of used ones
|
|
|
|
|
* TODO: alloc a pile of descs instead of just one,
|
|
|
|
|
* avoid many small allocations.
|
|
|
|
|
*/
|
2010-03-03 05:17:20 +08:00
|
|
|
desc = kzalloc(sizeof(struct coh901318_desc), GFP_NOWAIT);
|
2009-11-20 02:49:17 +08:00
|
|
|
if (desc == NULL)
|
|
|
|
|
goto out;
|
|
|
|
|
INIT_LIST_HEAD(&desc->node);
|
2010-03-03 05:17:20 +08:00
|
|
|
dma_async_tx_descriptor_init(&desc->desc, &cohc->chan);
|
2009-11-20 02:49:17 +08:00
|
|
|
} else {
|
|
|
|
|
/* Reuse an old desc. */
|
|
|
|
|
desc = list_first_entry(&cohc->free,
|
|
|
|
|
struct coh901318_desc,
|
|
|
|
|
node);
|
|
|
|
|
list_del(&desc->node);
|
2010-03-03 05:17:20 +08:00
|
|
|
/* Initialize it a bit so it's not insane */
|
|
|
|
|
desc->sg = NULL;
|
|
|
|
|
desc->sg_len = 0;
|
|
|
|
|
desc->desc.callback = NULL;
|
|
|
|
|
desc->desc.callback_param = NULL;
|
2009-11-20 02:49:17 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
out:
|
|
|
|
|
return desc;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
coh901318_desc_free(struct coh901318_chan *cohc, struct coh901318_desc *cohd)
|
|
|
|
|
{
|
|
|
|
|
list_add_tail(&cohd->node, &cohc->free);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* call with irq lock held */
|
|
|
|
|
static void
|
|
|
|
|
coh901318_desc_submit(struct coh901318_chan *cohc, struct coh901318_desc *desc)
|
|
|
|
|
{
|
|
|
|
|
list_add_tail(&desc->node, &cohc->active);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static struct coh901318_desc *
|
|
|
|
|
coh901318_first_active_get(struct coh901318_chan *cohc)
|
|
|
|
|
{
|
|
|
|
|
struct coh901318_desc *d;
|
|
|
|
|
|
|
|
|
|
if (list_empty(&cohc->active))
|
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
|
|
d = list_first_entry(&cohc->active,
|
|
|
|
|
struct coh901318_desc,
|
|
|
|
|
node);
|
|
|
|
|
return d;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
coh901318_desc_remove(struct coh901318_desc *cohd)
|
|
|
|
|
{
|
|
|
|
|
list_del(&cohd->node);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
coh901318_desc_queue(struct coh901318_chan *cohc, struct coh901318_desc *desc)
|
|
|
|
|
{
|
|
|
|
|
list_add_tail(&desc->node, &cohc->queue);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static struct coh901318_desc *
|
|
|
|
|
coh901318_first_queued(struct coh901318_chan *cohc)
|
|
|
|
|
{
|
|
|
|
|
struct coh901318_desc *d;
|
|
|
|
|
|
|
|
|
|
if (list_empty(&cohc->queue))
|
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
|
|
d = list_first_entry(&cohc->queue,
|
|
|
|
|
struct coh901318_desc,
|
|
|
|
|
node);
|
|
|
|
|
return d;
|
|
|
|
|
}
|
|
|
|
|
|
2010-03-04 21:40:30 +08:00
|
|
|
static inline u32 coh901318_get_bytes_in_lli(struct coh901318_lli *in_lli)
|
|
|
|
|
{
|
|
|
|
|
struct coh901318_lli *lli = in_lli;
|
|
|
|
|
u32 bytes = 0;
|
|
|
|
|
|
|
|
|
|
while (lli) {
|
|
|
|
|
bytes += lli->control & COH901318_CX_CTRL_TC_VALUE_MASK;
|
|
|
|
|
lli = lli->virt_link_addr;
|
|
|
|
|
}
|
|
|
|
|
return bytes;
|
|
|
|
|
}
|
|
|
|
|
|
2009-11-20 02:49:17 +08:00
|
|
|
/*
|
2010-03-04 21:40:30 +08:00
|
|
|
* Get the number of bytes left to transfer on this channel,
|
|
|
|
|
* it is unwise to call this before stopping the channel for
|
|
|
|
|
* absolute measures, but for a rough guess you can still call
|
|
|
|
|
* it.
|
2009-11-20 02:49:17 +08:00
|
|
|
*/
|
2010-03-27 07:50:49 +08:00
|
|
|
static u32 coh901318_get_bytes_left(struct dma_chan *chan)
|
2009-11-20 02:49:17 +08:00
|
|
|
{
|
|
|
|
|
struct coh901318_chan *cohc = to_coh901318_chan(chan);
|
2010-03-04 21:40:30 +08:00
|
|
|
struct coh901318_desc *cohd;
|
|
|
|
|
struct list_head *pos;
|
|
|
|
|
unsigned long flags;
|
|
|
|
|
u32 left = 0;
|
|
|
|
|
int i = 0;
|
2009-11-20 02:49:17 +08:00
|
|
|
|
|
|
|
|
spin_lock_irqsave(&cohc->lock, flags);
|
|
|
|
|
|
2010-03-04 21:40:30 +08:00
|
|
|
/*
|
|
|
|
|
* If there are many queued jobs, we iterate and add the
|
|
|
|
|
* size of them all. We take a special look on the first
|
|
|
|
|
* job though, since it is probably active.
|
|
|
|
|
*/
|
|
|
|
|
list_for_each(pos, &cohc->active) {
|
|
|
|
|
/*
|
|
|
|
|
* The first job in the list will be working on the
|
|
|
|
|
* hardware. The job can be stopped but still active,
|
|
|
|
|
* so that the transfer counter is somewhere inside
|
|
|
|
|
* the buffer.
|
|
|
|
|
*/
|
|
|
|
|
cohd = list_entry(pos, struct coh901318_desc, node);
|
|
|
|
|
|
|
|
|
|
if (i == 0) {
|
|
|
|
|
struct coh901318_lli *lli;
|
|
|
|
|
dma_addr_t ladd;
|
|
|
|
|
|
|
|
|
|
/* Read current transfer count value */
|
|
|
|
|
left = readl(cohc->base->virtbase +
|
|
|
|
|
COH901318_CX_CTRL +
|
|
|
|
|
COH901318_CX_CTRL_SPACING * cohc->id) &
|
|
|
|
|
COH901318_CX_CTRL_TC_VALUE_MASK;
|
|
|
|
|
|
|
|
|
|
/* See if the transfer is linked... */
|
|
|
|
|
ladd = readl(cohc->base->virtbase +
|
|
|
|
|
COH901318_CX_LNK_ADDR +
|
|
|
|
|
COH901318_CX_LNK_ADDR_SPACING *
|
|
|
|
|
cohc->id) &
|
|
|
|
|
~COH901318_CX_LNK_LINK_IMMEDIATE;
|
|
|
|
|
/* Single transaction */
|
|
|
|
|
if (!ladd)
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Linked transaction, follow the lli, find the
|
|
|
|
|
* currently processing lli, and proceed to the next
|
|
|
|
|
*/
|
|
|
|
|
lli = cohd->lli;
|
|
|
|
|
while (lli && lli->link_addr != ladd)
|
|
|
|
|
lli = lli->virt_link_addr;
|
|
|
|
|
|
|
|
|
|
if (lli)
|
|
|
|
|
lli = lli->virt_link_addr;
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Follow remaining lli links around to count the total
|
|
|
|
|
* number of bytes left
|
|
|
|
|
*/
|
|
|
|
|
left += coh901318_get_bytes_in_lli(lli);
|
|
|
|
|
} else {
|
|
|
|
|
left += coh901318_get_bytes_in_lli(cohd->lli);
|
|
|
|
|
}
|
|
|
|
|
i++;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Also count bytes in the queued jobs */
|
|
|
|
|
list_for_each(pos, &cohc->queue) {
|
|
|
|
|
cohd = list_entry(pos, struct coh901318_desc, node);
|
|
|
|
|
left += coh901318_get_bytes_in_lli(cohd->lli);
|
|
|
|
|
}
|
2009-11-20 02:49:17 +08:00
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&cohc->lock, flags);
|
|
|
|
|
|
2010-03-04 21:40:30 +08:00
|
|
|
return left;
|
2009-11-20 02:49:17 +08:00
|
|
|
}
|
|
|
|
|
|
2010-03-27 07:44:01 +08:00
|
|
|
/*
|
|
|
|
|
* Pauses a transfer without losing data. Enables power save.
|
|
|
|
|
* Use this function in conjunction with coh901318_resume.
|
|
|
|
|
*/
|
|
|
|
|
static void coh901318_pause(struct dma_chan *chan)
|
2009-11-20 02:49:17 +08:00
|
|
|
{
|
|
|
|
|
u32 val;
|
|
|
|
|
unsigned long flags;
|
|
|
|
|
struct coh901318_chan *cohc = to_coh901318_chan(chan);
|
|
|
|
|
int channel = cohc->id;
|
|
|
|
|
void __iomem *virtbase = cohc->base->virtbase;
|
|
|
|
|
|
|
|
|
|
spin_lock_irqsave(&cohc->lock, flags);
|
|
|
|
|
|
|
|
|
|
/* Disable channel in HW */
|
|
|
|
|
val = readl(virtbase + COH901318_CX_CFG +
|
|
|
|
|
COH901318_CX_CFG_SPACING * channel);
|
|
|
|
|
|
2011-03-31 09:57:33 +08:00
|
|
|
/* Stopping infinite transfer */
|
2009-11-20 02:49:17 +08:00
|
|
|
if ((val & COH901318_CX_CTRL_TC_ENABLE) == 0 &&
|
|
|
|
|
(val & COH901318_CX_CFG_CH_ENABLE))
|
|
|
|
|
cohc->stopped = 1;
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
val &= ~COH901318_CX_CFG_CH_ENABLE;
|
|
|
|
|
/* Enable twice, HW bug work around */
|
|
|
|
|
writel(val, virtbase + COH901318_CX_CFG +
|
|
|
|
|
COH901318_CX_CFG_SPACING * channel);
|
|
|
|
|
writel(val, virtbase + COH901318_CX_CFG +
|
|
|
|
|
COH901318_CX_CFG_SPACING * channel);
|
|
|
|
|
|
|
|
|
|
/* Spin-wait for it to actually go inactive */
|
|
|
|
|
while (readl(virtbase + COH901318_CX_STAT+COH901318_CX_STAT_SPACING *
|
|
|
|
|
channel) & COH901318_CX_STAT_ACTIVE)
|
|
|
|
|
cpu_relax();
|
|
|
|
|
|
|
|
|
|
/* Check if we stopped an active job */
|
|
|
|
|
if ((readl(virtbase + COH901318_CX_CTRL+COH901318_CX_CTRL_SPACING *
|
|
|
|
|
channel) & COH901318_CX_CTRL_TC_VALUE_MASK) > 0)
|
|
|
|
|
cohc->stopped = 1;
|
|
|
|
|
|
|
|
|
|
enable_powersave(cohc);
|
|
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&cohc->lock, flags);
|
|
|
|
|
}
|
|
|
|
|
|
2010-03-27 07:44:01 +08:00
|
|
|
/* Resumes a transfer that has been stopped via 300_dma_stop(..).
|
2009-11-20 02:49:17 +08:00
|
|
|
Power save is handled.
|
|
|
|
|
*/
|
2010-03-27 07:44:01 +08:00
|
|
|
static void coh901318_resume(struct dma_chan *chan)
|
2009-11-20 02:49:17 +08:00
|
|
|
{
|
|
|
|
|
u32 val;
|
|
|
|
|
unsigned long flags;
|
|
|
|
|
struct coh901318_chan *cohc = to_coh901318_chan(chan);
|
|
|
|
|
int channel = cohc->id;
|
|
|
|
|
|
|
|
|
|
spin_lock_irqsave(&cohc->lock, flags);
|
|
|
|
|
|
|
|
|
|
disable_powersave(cohc);
|
|
|
|
|
|
|
|
|
|
if (cohc->stopped) {
|
|
|
|
|
/* Enable channel in HW */
|
|
|
|
|
val = readl(cohc->base->virtbase + COH901318_CX_CFG +
|
|
|
|
|
COH901318_CX_CFG_SPACING * channel);
|
|
|
|
|
|
|
|
|
|
val |= COH901318_CX_CFG_CH_ENABLE;
|
|
|
|
|
|
|
|
|
|
writel(val, cohc->base->virtbase + COH901318_CX_CFG +
|
|
|
|
|
COH901318_CX_CFG_SPACING*channel);
|
|
|
|
|
|
|
|
|
|
cohc->stopped = 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&cohc->lock, flags);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
bool coh901318_filter_id(struct dma_chan *chan, void *chan_id)
|
|
|
|
|
{
|
|
|
|
|
unsigned int ch_nr = (unsigned int) chan_id;
|
|
|
|
|
|
|
|
|
|
if (ch_nr == to_coh901318_chan(chan)->id)
|
|
|
|
|
return true;
|
|
|
|
|
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
EXPORT_SYMBOL(coh901318_filter_id);
|
|
|
|
|
|
2013-04-19 19:42:55 +08:00
|
|
|
struct coh901318_filter_args {
|
|
|
|
|
struct coh901318_base *base;
|
|
|
|
|
unsigned int ch_nr;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static bool coh901318_filter_base_and_id(struct dma_chan *chan, void *data)
|
|
|
|
|
{
|
|
|
|
|
struct coh901318_filter_args *args = data;
|
|
|
|
|
|
|
|
|
|
if (&args->base->dma_slave == chan->device &&
|
|
|
|
|
args->ch_nr == to_coh901318_chan(chan)->id)
|
|
|
|
|
return true;
|
|
|
|
|
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static struct dma_chan *coh901318_xlate(struct of_phandle_args *dma_spec,
|
|
|
|
|
struct of_dma *ofdma)
|
|
|
|
|
{
|
|
|
|
|
struct coh901318_filter_args args = {
|
|
|
|
|
.base = ofdma->of_dma_data,
|
|
|
|
|
.ch_nr = dma_spec->args[0],
|
|
|
|
|
};
|
|
|
|
|
dma_cap_mask_t cap;
|
|
|
|
|
dma_cap_zero(cap);
|
|
|
|
|
dma_cap_set(DMA_SLAVE, cap);
|
|
|
|
|
|
|
|
|
|
return dma_request_channel(cap, coh901318_filter_base_and_id, &args);
|
|
|
|
|
}
|
2009-11-20 02:49:17 +08:00
|
|
|
/*
|
|
|
|
|
* DMA channel allocation
|
|
|
|
|
*/
|
|
|
|
|
static int coh901318_config(struct coh901318_chan *cohc,
|
|
|
|
|
struct coh901318_params *param)
|
|
|
|
|
{
|
|
|
|
|
unsigned long flags;
|
|
|
|
|
const struct coh901318_params *p;
|
|
|
|
|
int channel = cohc->id;
|
|
|
|
|
void __iomem *virtbase = cohc->base->virtbase;
|
|
|
|
|
|
|
|
|
|
spin_lock_irqsave(&cohc->lock, flags);
|
|
|
|
|
|
|
|
|
|
if (param)
|
|
|
|
|
p = param;
|
|
|
|
|
else
|
2013-01-07 06:36:14 +08:00
|
|
|
p = cohc_chan_param(cohc);
|
2009-11-20 02:49:17 +08:00
|
|
|
|
|
|
|
|
/* Clear any pending BE or TC interrupt */
|
|
|
|
|
if (channel < 32) {
|
|
|
|
|
writel(1 << channel, virtbase + COH901318_BE_INT_CLEAR1);
|
|
|
|
|
writel(1 << channel, virtbase + COH901318_TC_INT_CLEAR1);
|
|
|
|
|
} else {
|
|
|
|
|
writel(1 << (channel - 32), virtbase +
|
|
|
|
|
COH901318_BE_INT_CLEAR2);
|
|
|
|
|
writel(1 << (channel - 32), virtbase +
|
|
|
|
|
COH901318_TC_INT_CLEAR2);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
coh901318_set_conf(cohc, p->config);
|
|
|
|
|
coh901318_set_ctrl(cohc, p->ctrl_lli_last);
|
|
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&cohc->lock, flags);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* must lock when calling this function
|
|
|
|
|
* start queued jobs, if any
|
|
|
|
|
* TODO: start all queued jobs in one go
|
|
|
|
|
*
|
|
|
|
|
* Returns descriptor if queued job is started otherwise NULL.
|
|
|
|
|
* If the queue is empty NULL is returned.
|
|
|
|
|
*/
|
|
|
|
|
static struct coh901318_desc *coh901318_queue_start(struct coh901318_chan *cohc)
|
|
|
|
|
{
|
2010-03-04 21:31:47 +08:00
|
|
|
struct coh901318_desc *cohd;
|
2009-11-20 02:49:17 +08:00
|
|
|
|
2010-03-04 21:31:47 +08:00
|
|
|
/*
|
|
|
|
|
* start queued jobs, if any
|
2009-11-20 02:49:17 +08:00
|
|
|
* TODO: transmit all queued jobs in one go
|
|
|
|
|
*/
|
2010-03-04 21:31:47 +08:00
|
|
|
cohd = coh901318_first_queued(cohc);
|
2009-11-20 02:49:17 +08:00
|
|
|
|
2010-03-04 21:31:47 +08:00
|
|
|
if (cohd != NULL) {
|
2009-11-20 02:49:17 +08:00
|
|
|
/* Remove from queue */
|
2010-03-04 21:31:47 +08:00
|
|
|
coh901318_desc_remove(cohd);
|
2009-11-20 02:49:17 +08:00
|
|
|
/* initiate DMA job */
|
|
|
|
|
cohc->busy = 1;
|
|
|
|
|
|
2010-03-04 21:31:47 +08:00
|
|
|
coh901318_desc_submit(cohc, cohd);
|
2009-11-20 02:49:17 +08:00
|
|
|
|
2011-07-01 22:47:28 +08:00
|
|
|
/* Program the transaction head */
|
|
|
|
|
coh901318_set_conf(cohc, cohd->head_config);
|
|
|
|
|
coh901318_set_ctrl(cohc, cohd->head_ctrl);
|
2010-03-04 21:31:47 +08:00
|
|
|
coh901318_prep_linked_list(cohc, cohd->lli);
|
2009-11-20 02:49:17 +08:00
|
|
|
|
2010-03-04 21:31:47 +08:00
|
|
|
/* start dma job on this channel */
|
2009-11-20 02:49:17 +08:00
|
|
|
coh901318_start(cohc);
|
|
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
2010-03-04 21:31:47 +08:00
|
|
|
return cohd;
|
2009-11-20 02:49:17 +08:00
|
|
|
}
|
|
|
|
|
|
2010-03-03 05:17:15 +08:00
|
|
|
/*
|
|
|
|
|
* This tasklet is called from the interrupt handler to
|
|
|
|
|
* handle each descriptor (DMA job) that is sent to a channel.
|
|
|
|
|
*/
|
2009-11-20 02:49:17 +08:00
|
|
|
static void dma_tasklet(unsigned long data)
|
|
|
|
|
{
|
|
|
|
|
struct coh901318_chan *cohc = (struct coh901318_chan *) data;
|
|
|
|
|
struct coh901318_desc *cohd_fin;
|
|
|
|
|
unsigned long flags;
|
|
|
|
|
dma_async_tx_callback callback;
|
|
|
|
|
void *callback_param;
|
|
|
|
|
|
2010-03-03 05:17:15 +08:00
|
|
|
dev_vdbg(COHC_2_DEV(cohc), "[%s] chan_id %d"
|
|
|
|
|
" nbr_active_done %ld\n", __func__,
|
|
|
|
|
cohc->id, cohc->nbr_active_done);
|
|
|
|
|
|
2009-11-20 02:49:17 +08:00
|
|
|
spin_lock_irqsave(&cohc->lock, flags);
|
|
|
|
|
|
2010-03-03 05:17:15 +08:00
|
|
|
/* get first active descriptor entry from list */
|
2009-11-20 02:49:17 +08:00
|
|
|
cohd_fin = coh901318_first_active_get(cohc);
|
|
|
|
|
|
|
|
|
|
if (cohd_fin == NULL)
|
|
|
|
|
goto err;
|
|
|
|
|
|
2010-03-03 05:17:44 +08:00
|
|
|
/* locate callback to client */
|
|
|
|
|
callback = cohd_fin->desc.callback;
|
|
|
|
|
callback_param = cohd_fin->desc.callback_param;
|
2009-11-20 02:49:17 +08:00
|
|
|
|
2010-03-03 05:17:44 +08:00
|
|
|
/* sign this job as completed on the channel */
|
2012-03-07 06:35:07 +08:00
|
|
|
dma_cookie_complete(&cohd_fin->desc);
|
2009-11-20 02:49:17 +08:00
|
|
|
|
2010-03-03 05:17:44 +08:00
|
|
|
/* release the lli allocation and remove the descriptor */
|
2010-03-04 21:31:47 +08:00
|
|
|
coh901318_lli_free(&cohc->base->pool, &cohd_fin->lli);
|
2009-11-20 02:49:17 +08:00
|
|
|
|
2010-03-03 05:17:44 +08:00
|
|
|
/* return desc to free-list */
|
|
|
|
|
coh901318_desc_remove(cohd_fin);
|
|
|
|
|
coh901318_desc_free(cohc, cohd_fin);
|
2009-11-20 02:49:17 +08:00
|
|
|
|
2010-03-03 05:17:44 +08:00
|
|
|
spin_unlock_irqrestore(&cohc->lock, flags);
|
2009-11-20 02:49:17 +08:00
|
|
|
|
2010-03-03 05:17:44 +08:00
|
|
|
/* Call the callback when we're done */
|
|
|
|
|
if (callback)
|
|
|
|
|
callback(callback_param);
|
2009-11-20 02:49:17 +08:00
|
|
|
|
2010-03-03 05:17:44 +08:00
|
|
|
spin_lock_irqsave(&cohc->lock, flags);
|
2009-11-20 02:49:17 +08:00
|
|
|
|
2010-03-03 05:17:15 +08:00
|
|
|
/*
|
|
|
|
|
* If another interrupt fired while the tasklet was scheduling,
|
|
|
|
|
* we don't get called twice, so we have this number of active
|
|
|
|
|
* counter that keep track of the number of IRQs expected to
|
|
|
|
|
* be handled for this channel. If there happen to be more than
|
|
|
|
|
* one IRQ to be ack:ed, we simply schedule this tasklet again.
|
|
|
|
|
*/
|
2010-03-03 05:17:44 +08:00
|
|
|
cohc->nbr_active_done--;
|
2009-11-20 02:49:17 +08:00
|
|
|
if (cohc->nbr_active_done) {
|
2010-03-03 05:17:15 +08:00
|
|
|
dev_dbg(COHC_2_DEV(cohc), "scheduling tasklet again, new IRQs "
|
|
|
|
|
"came in while we were scheduling this tasklet\n");
|
2009-11-20 02:49:17 +08:00
|
|
|
if (cohc_chan_conf(cohc)->priority_high)
|
|
|
|
|
tasklet_hi_schedule(&cohc->tasklet);
|
|
|
|
|
else
|
|
|
|
|
tasklet_schedule(&cohc->tasklet);
|
|
|
|
|
}
|
|
|
|
|
|
2010-03-03 05:17:44 +08:00
|
|
|
spin_unlock_irqrestore(&cohc->lock, flags);
|
2009-11-20 02:49:17 +08:00
|
|
|
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
err:
|
|
|
|
|
spin_unlock_irqrestore(&cohc->lock, flags);
|
|
|
|
|
dev_err(COHC_2_DEV(cohc), "[%s] No active dma desc\n", __func__);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/* called from interrupt context */
|
|
|
|
|
static void dma_tc_handle(struct coh901318_chan *cohc)
|
|
|
|
|
{
|
2010-03-04 21:31:47 +08:00
|
|
|
/*
|
|
|
|
|
* If the channel is not allocated, then we shouldn't have
|
|
|
|
|
* any TC interrupts on it.
|
|
|
|
|
*/
|
|
|
|
|
if (!cohc->allocated) {
|
|
|
|
|
dev_err(COHC_2_DEV(cohc), "spurious interrupt from "
|
|
|
|
|
"unallocated channel\n");
|
2009-11-20 02:49:17 +08:00
|
|
|
return;
|
2010-03-04 21:31:47 +08:00
|
|
|
}
|
2009-11-20 02:49:17 +08:00
|
|
|
|
2010-03-03 05:17:44 +08:00
|
|
|
spin_lock(&cohc->lock);
|
2009-11-20 02:49:17 +08:00
|
|
|
|
2010-03-04 21:31:47 +08:00
|
|
|
/*
|
|
|
|
|
* When we reach this point, at least one queue item
|
|
|
|
|
* should have been moved over from cohc->queue to
|
|
|
|
|
* cohc->active and run to completion, that is why we're
|
|
|
|
|
* getting a terminal count interrupt is it not?
|
|
|
|
|
* If you get this BUG() the most probable cause is that
|
|
|
|
|
* the individual nodes in the lli chain have IRQ enabled,
|
|
|
|
|
* so check your platform config for lli chain ctrl.
|
|
|
|
|
*/
|
|
|
|
|
BUG_ON(list_empty(&cohc->active));
|
|
|
|
|
|
2009-11-20 02:49:17 +08:00
|
|
|
cohc->nbr_active_done++;
|
|
|
|
|
|
2010-03-04 21:31:47 +08:00
|
|
|
/*
|
|
|
|
|
* This attempt to take a job from cohc->queue, put it
|
|
|
|
|
* into cohc->active and start it.
|
|
|
|
|
*/
|
2010-03-03 05:17:44 +08:00
|
|
|
if (coh901318_queue_start(cohc) == NULL)
|
2009-11-20 02:49:17 +08:00
|
|
|
cohc->busy = 0;
|
|
|
|
|
|
2010-03-03 05:17:44 +08:00
|
|
|
spin_unlock(&cohc->lock);
|
|
|
|
|
|
2010-03-04 21:31:47 +08:00
|
|
|
/*
|
|
|
|
|
* This tasklet will remove items from cohc->active
|
|
|
|
|
* and thus terminates them.
|
|
|
|
|
*/
|
2009-11-20 02:49:17 +08:00
|
|
|
if (cohc_chan_conf(cohc)->priority_high)
|
|
|
|
|
tasklet_hi_schedule(&cohc->tasklet);
|
|
|
|
|
else
|
|
|
|
|
tasklet_schedule(&cohc->tasklet);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
static irqreturn_t dma_irq_handler(int irq, void *dev_id)
|
|
|
|
|
{
|
|
|
|
|
u32 status1;
|
|
|
|
|
u32 status2;
|
|
|
|
|
int i;
|
|
|
|
|
int ch;
|
|
|
|
|
struct coh901318_base *base = dev_id;
|
|
|
|
|
struct coh901318_chan *cohc;
|
|
|
|
|
void __iomem *virtbase = base->virtbase;
|
|
|
|
|
|
|
|
|
|
status1 = readl(virtbase + COH901318_INT_STATUS1);
|
|
|
|
|
status2 = readl(virtbase + COH901318_INT_STATUS2);
|
|
|
|
|
|
|
|
|
|
if (unlikely(status1 == 0 && status2 == 0)) {
|
|
|
|
|
dev_warn(base->dev, "spurious DMA IRQ from no channel!\n");
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* TODO: consider handle IRQ in tasklet here to
|
|
|
|
|
* minimize interrupt latency */
|
|
|
|
|
|
|
|
|
|
/* Check the first 32 DMA channels for IRQ */
|
|
|
|
|
while (status1) {
|
|
|
|
|
/* Find first bit set, return as a number. */
|
|
|
|
|
i = ffs(status1) - 1;
|
|
|
|
|
ch = i;
|
|
|
|
|
|
|
|
|
|
cohc = &base->chans[ch];
|
|
|
|
|
spin_lock(&cohc->lock);
|
|
|
|
|
|
|
|
|
|
/* Mask off this bit */
|
|
|
|
|
status1 &= ~(1 << i);
|
|
|
|
|
/* Check the individual channel bits */
|
|
|
|
|
if (test_bit(i, virtbase + COH901318_BE_INT_STATUS1)) {
|
|
|
|
|
dev_crit(COHC_2_DEV(cohc),
|
|
|
|
|
"DMA bus error on channel %d!\n", ch);
|
|
|
|
|
BUG_ON(1);
|
|
|
|
|
/* Clear BE interrupt */
|
|
|
|
|
__set_bit(i, virtbase + COH901318_BE_INT_CLEAR1);
|
|
|
|
|
} else {
|
|
|
|
|
/* Caused by TC, really? */
|
|
|
|
|
if (unlikely(!test_bit(i, virtbase +
|
|
|
|
|
COH901318_TC_INT_STATUS1))) {
|
|
|
|
|
dev_warn(COHC_2_DEV(cohc),
|
|
|
|
|
"ignoring interrupt not caused by terminal count on channel %d\n", ch);
|
|
|
|
|
/* Clear TC interrupt */
|
|
|
|
|
BUG_ON(1);
|
|
|
|
|
__set_bit(i, virtbase + COH901318_TC_INT_CLEAR1);
|
|
|
|
|
} else {
|
|
|
|
|
/* Enable powersave if transfer has finished */
|
|
|
|
|
if (!(readl(virtbase + COH901318_CX_STAT +
|
|
|
|
|
COH901318_CX_STAT_SPACING*ch) &
|
|
|
|
|
COH901318_CX_STAT_ENABLED)) {
|
|
|
|
|
enable_powersave(cohc);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Must clear TC interrupt before calling
|
|
|
|
|
* dma_tc_handle
|
2011-01-29 03:48:18 +08:00
|
|
|
* in case tc_handle initiate a new dma job
|
2009-11-20 02:49:17 +08:00
|
|
|
*/
|
|
|
|
|
__set_bit(i, virtbase + COH901318_TC_INT_CLEAR1);
|
|
|
|
|
|
|
|
|
|
dma_tc_handle(cohc);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
spin_unlock(&cohc->lock);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Check the remaining 32 DMA channels for IRQ */
|
|
|
|
|
while (status2) {
|
|
|
|
|
/* Find first bit set, return as a number. */
|
|
|
|
|
i = ffs(status2) - 1;
|
|
|
|
|
ch = i + 32;
|
|
|
|
|
cohc = &base->chans[ch];
|
|
|
|
|
spin_lock(&cohc->lock);
|
|
|
|
|
|
|
|
|
|
/* Mask off this bit */
|
|
|
|
|
status2 &= ~(1 << i);
|
|
|
|
|
/* Check the individual channel bits */
|
|
|
|
|
if (test_bit(i, virtbase + COH901318_BE_INT_STATUS2)) {
|
|
|
|
|
dev_crit(COHC_2_DEV(cohc),
|
|
|
|
|
"DMA bus error on channel %d!\n", ch);
|
|
|
|
|
/* Clear BE interrupt */
|
|
|
|
|
BUG_ON(1);
|
|
|
|
|
__set_bit(i, virtbase + COH901318_BE_INT_CLEAR2);
|
|
|
|
|
} else {
|
|
|
|
|
/* Caused by TC, really? */
|
|
|
|
|
if (unlikely(!test_bit(i, virtbase +
|
|
|
|
|
COH901318_TC_INT_STATUS2))) {
|
|
|
|
|
dev_warn(COHC_2_DEV(cohc),
|
|
|
|
|
"ignoring interrupt not caused by terminal count on channel %d\n", ch);
|
|
|
|
|
/* Clear TC interrupt */
|
|
|
|
|
__set_bit(i, virtbase + COH901318_TC_INT_CLEAR2);
|
|
|
|
|
BUG_ON(1);
|
|
|
|
|
} else {
|
|
|
|
|
/* Enable powersave if transfer has finished */
|
|
|
|
|
if (!(readl(virtbase + COH901318_CX_STAT +
|
|
|
|
|
COH901318_CX_STAT_SPACING*ch) &
|
|
|
|
|
COH901318_CX_STAT_ENABLED)) {
|
|
|
|
|
enable_powersave(cohc);
|
|
|
|
|
}
|
|
|
|
|
/* Must clear TC interrupt before calling
|
|
|
|
|
* dma_tc_handle
|
2011-01-29 03:48:18 +08:00
|
|
|
* in case tc_handle initiate a new dma job
|
2009-11-20 02:49:17 +08:00
|
|
|
*/
|
|
|
|
|
__set_bit(i, virtbase + COH901318_TC_INT_CLEAR2);
|
|
|
|
|
|
|
|
|
|
dma_tc_handle(cohc);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
spin_unlock(&cohc->lock);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int coh901318_alloc_chan_resources(struct dma_chan *chan)
|
|
|
|
|
{
|
|
|
|
|
struct coh901318_chan *cohc = to_coh901318_chan(chan);
|
2010-03-04 21:40:30 +08:00
|
|
|
unsigned long flags;
|
2009-11-20 02:49:17 +08:00
|
|
|
|
|
|
|
|
dev_vdbg(COHC_2_DEV(cohc), "[%s] DMA channel %d\n",
|
|
|
|
|
__func__, cohc->id);
|
|
|
|
|
|
|
|
|
|
if (chan->client_count > 1)
|
|
|
|
|
return -EBUSY;
|
|
|
|
|
|
2010-03-04 21:40:30 +08:00
|
|
|
spin_lock_irqsave(&cohc->lock, flags);
|
|
|
|
|
|
2009-11-20 02:49:17 +08:00
|
|
|
coh901318_config(cohc, NULL);
|
|
|
|
|
|
|
|
|
|
cohc->allocated = 1;
|
2012-03-07 06:35:47 +08:00
|
|
|
dma_cookie_init(chan);
|
2009-11-20 02:49:17 +08:00
|
|
|
|
2010-03-04 21:40:30 +08:00
|
|
|
spin_unlock_irqrestore(&cohc->lock, flags);
|
|
|
|
|
|
2009-11-20 02:49:17 +08:00
|
|
|
return 1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
coh901318_free_chan_resources(struct dma_chan *chan)
|
|
|
|
|
{
|
|
|
|
|
struct coh901318_chan *cohc = to_coh901318_chan(chan);
|
|
|
|
|
int channel = cohc->id;
|
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
|
|
spin_lock_irqsave(&cohc->lock, flags);
|
|
|
|
|
|
|
|
|
|
/* Disable HW */
|
|
|
|
|
writel(0x00000000U, cohc->base->virtbase + COH901318_CX_CFG +
|
|
|
|
|
COH901318_CX_CFG_SPACING*channel);
|
|
|
|
|
writel(0x00000000U, cohc->base->virtbase + COH901318_CX_CTRL +
|
|
|
|
|
COH901318_CX_CTRL_SPACING*channel);
|
|
|
|
|
|
|
|
|
|
cohc->allocated = 0;
|
|
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&cohc->lock, flags);
|
|
|
|
|
|
2010-05-18 07:30:42 +08:00
|
|
|
chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
|
2009-11-20 02:49:17 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
static dma_cookie_t
|
|
|
|
|
coh901318_tx_submit(struct dma_async_tx_descriptor *tx)
|
|
|
|
|
{
|
|
|
|
|
struct coh901318_desc *cohd = container_of(tx, struct coh901318_desc,
|
|
|
|
|
desc);
|
|
|
|
|
struct coh901318_chan *cohc = to_coh901318_chan(tx->chan);
|
|
|
|
|
unsigned long flags;
|
2012-03-07 06:34:46 +08:00
|
|
|
dma_cookie_t cookie;
|
2009-11-20 02:49:17 +08:00
|
|
|
|
|
|
|
|
spin_lock_irqsave(&cohc->lock, flags);
|
2012-03-07 06:34:46 +08:00
|
|
|
cookie = dma_cookie_assign(tx);
|
2009-11-20 02:49:17 +08:00
|
|
|
|
|
|
|
|
coh901318_desc_queue(cohc, cohd);
|
|
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&cohc->lock, flags);
|
|
|
|
|
|
2012-03-07 06:34:46 +08:00
|
|
|
return cookie;
|
2009-11-20 02:49:17 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static struct dma_async_tx_descriptor *
|
|
|
|
|
coh901318_prep_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
|
|
|
|
|
size_t size, unsigned long flags)
|
|
|
|
|
{
|
2010-03-04 21:31:47 +08:00
|
|
|
struct coh901318_lli *lli;
|
2009-11-20 02:49:17 +08:00
|
|
|
struct coh901318_desc *cohd;
|
|
|
|
|
unsigned long flg;
|
|
|
|
|
struct coh901318_chan *cohc = to_coh901318_chan(chan);
|
|
|
|
|
int lli_len;
|
|
|
|
|
u32 ctrl_last = cohc_chan_param(cohc)->ctrl_lli_last;
|
2010-03-03 05:17:20 +08:00
|
|
|
int ret;
|
2009-11-20 02:49:17 +08:00
|
|
|
|
|
|
|
|
spin_lock_irqsave(&cohc->lock, flg);
|
|
|
|
|
|
|
|
|
|
dev_vdbg(COHC_2_DEV(cohc),
|
|
|
|
|
"[%s] channel %d src 0x%x dest 0x%x size %d\n",
|
|
|
|
|
__func__, cohc->id, src, dest, size);
|
|
|
|
|
|
|
|
|
|
if (flags & DMA_PREP_INTERRUPT)
|
|
|
|
|
/* Trigger interrupt after last lli */
|
|
|
|
|
ctrl_last |= COH901318_CX_CTRL_TC_IRQ_ENABLE;
|
|
|
|
|
|
|
|
|
|
lli_len = size >> MAX_DMA_PACKET_SIZE_SHIFT;
|
|
|
|
|
if ((lli_len << MAX_DMA_PACKET_SIZE_SHIFT) < size)
|
|
|
|
|
lli_len++;
|
|
|
|
|
|
2010-03-04 21:31:47 +08:00
|
|
|
lli = coh901318_lli_alloc(&cohc->base->pool, lli_len);
|
2009-11-20 02:49:17 +08:00
|
|
|
|
2010-03-04 21:31:47 +08:00
|
|
|
if (lli == NULL)
|
2009-11-20 02:49:17 +08:00
|
|
|
goto err;
|
|
|
|
|
|
2010-03-03 05:17:20 +08:00
|
|
|
ret = coh901318_lli_fill_memcpy(
|
2010-03-04 21:31:47 +08:00
|
|
|
&cohc->base->pool, lli, src, size, dest,
|
2010-03-03 05:17:20 +08:00
|
|
|
cohc_chan_param(cohc)->ctrl_lli_chained,
|
|
|
|
|
ctrl_last);
|
|
|
|
|
if (ret)
|
|
|
|
|
goto err;
|
2009-11-20 02:49:17 +08:00
|
|
|
|
2010-03-04 21:31:47 +08:00
|
|
|
COH_DBG(coh901318_list_print(cohc, lli));
|
2009-11-20 02:49:17 +08:00
|
|
|
|
2010-03-03 05:17:20 +08:00
|
|
|
/* Pick a descriptor to handle this transfer */
|
|
|
|
|
cohd = coh901318_desc_get(cohc);
|
2010-03-04 21:31:47 +08:00
|
|
|
cohd->lli = lli;
|
2010-03-03 05:17:20 +08:00
|
|
|
cohd->flags = flags;
|
2009-11-20 02:49:17 +08:00
|
|
|
cohd->desc.tx_submit = coh901318_tx_submit;
|
|
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&cohc->lock, flg);
|
|
|
|
|
|
|
|
|
|
return &cohd->desc;
|
|
|
|
|
err:
|
|
|
|
|
spin_unlock_irqrestore(&cohc->lock, flg);
|
|
|
|
|
return NULL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static struct dma_async_tx_descriptor *
|
|
|
|
|
coh901318_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
|
2011-10-14 01:04:23 +08:00
|
|
|
unsigned int sg_len, enum dma_transfer_direction direction,
|
2012-03-09 04:35:13 +08:00
|
|
|
unsigned long flags, void *context)
|
2009-11-20 02:49:17 +08:00
|
|
|
{
|
|
|
|
|
struct coh901318_chan *cohc = to_coh901318_chan(chan);
|
2010-03-04 21:31:47 +08:00
|
|
|
struct coh901318_lli *lli;
|
2009-11-20 02:49:17 +08:00
|
|
|
struct coh901318_desc *cohd;
|
2010-03-03 03:12:46 +08:00
|
|
|
const struct coh901318_params *params;
|
2009-11-20 02:49:17 +08:00
|
|
|
struct scatterlist *sg;
|
|
|
|
|
int len = 0;
|
|
|
|
|
int size;
|
|
|
|
|
int i;
|
|
|
|
|
u32 ctrl_chained = cohc_chan_param(cohc)->ctrl_lli_chained;
|
|
|
|
|
u32 ctrl = cohc_chan_param(cohc)->ctrl_lli;
|
|
|
|
|
u32 ctrl_last = cohc_chan_param(cohc)->ctrl_lli_last;
|
2010-03-03 03:12:46 +08:00
|
|
|
u32 config;
|
2009-11-20 02:49:17 +08:00
|
|
|
unsigned long flg;
|
2010-03-03 05:17:44 +08:00
|
|
|
int ret;
|
2009-11-20 02:49:17 +08:00
|
|
|
|
|
|
|
|
if (!sgl)
|
|
|
|
|
goto out;
|
2012-04-26 02:50:52 +08:00
|
|
|
if (sg_dma_len(sgl) == 0)
|
2009-11-20 02:49:17 +08:00
|
|
|
goto out;
|
|
|
|
|
|
|
|
|
|
spin_lock_irqsave(&cohc->lock, flg);
|
|
|
|
|
|
|
|
|
|
dev_vdbg(COHC_2_DEV(cohc), "[%s] sg_len %d dir %d\n",
|
|
|
|
|
__func__, sg_len, direction);
|
|
|
|
|
|
|
|
|
|
if (flags & DMA_PREP_INTERRUPT)
|
|
|
|
|
/* Trigger interrupt after last lli */
|
|
|
|
|
ctrl_last |= COH901318_CX_CTRL_TC_IRQ_ENABLE;
|
|
|
|
|
|
2010-03-03 03:12:46 +08:00
|
|
|
params = cohc_chan_param(cohc);
|
|
|
|
|
config = params->config;
|
2010-08-04 19:37:53 +08:00
|
|
|
/*
|
|
|
|
|
* Add runtime-specific control on top, make
|
|
|
|
|
* sure the bits you set per peripheral channel are
|
|
|
|
|
* cleared in the default config from the platform.
|
|
|
|
|
*/
|
2013-01-04 20:50:49 +08:00
|
|
|
ctrl_chained |= cohc->ctrl;
|
|
|
|
|
ctrl_last |= cohc->ctrl;
|
|
|
|
|
ctrl |= cohc->ctrl;
|
2010-03-03 03:12:46 +08:00
|
|
|
|
2011-10-14 01:04:23 +08:00
|
|
|
if (direction == DMA_MEM_TO_DEV) {
|
2009-11-20 02:49:17 +08:00
|
|
|
u32 tx_flags = COH901318_CX_CTRL_PRDD_SOURCE |
|
|
|
|
|
COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE;
|
|
|
|
|
|
2010-03-03 03:12:46 +08:00
|
|
|
config |= COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY;
|
2009-11-20 02:49:17 +08:00
|
|
|
ctrl_chained |= tx_flags;
|
|
|
|
|
ctrl_last |= tx_flags;
|
|
|
|
|
ctrl |= tx_flags;
|
2011-10-14 01:04:23 +08:00
|
|
|
} else if (direction == DMA_DEV_TO_MEM) {
|
2009-11-20 02:49:17 +08:00
|
|
|
u32 rx_flags = COH901318_CX_CTRL_PRDD_DEST |
|
|
|
|
|
COH901318_CX_CTRL_DST_ADDR_INC_ENABLE;
|
|
|
|
|
|
2010-03-03 03:12:46 +08:00
|
|
|
config |= COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY;
|
2009-11-20 02:49:17 +08:00
|
|
|
ctrl_chained |= rx_flags;
|
|
|
|
|
ctrl_last |= rx_flags;
|
|
|
|
|
ctrl |= rx_flags;
|
|
|
|
|
} else
|
|
|
|
|
goto err_direction;
|
|
|
|
|
|
|
|
|
|
/* The dma only supports transmitting packages up to
|
|
|
|
|
* MAX_DMA_PACKET_SIZE. Calculate to total number of
|
|
|
|
|
* dma elemts required to send the entire sg list
|
|
|
|
|
*/
|
|
|
|
|
for_each_sg(sgl, sg, sg_len, i) {
|
|
|
|
|
unsigned int factor;
|
|
|
|
|
size = sg_dma_len(sg);
|
|
|
|
|
|
|
|
|
|
if (size <= MAX_DMA_PACKET_SIZE) {
|
|
|
|
|
len++;
|
|
|
|
|
continue;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
factor = size >> MAX_DMA_PACKET_SIZE_SHIFT;
|
|
|
|
|
if ((factor << MAX_DMA_PACKET_SIZE_SHIFT) < size)
|
|
|
|
|
factor++;
|
|
|
|
|
|
|
|
|
|
len += factor;
|
|
|
|
|
}
|
|
|
|
|
|
2010-03-03 05:17:15 +08:00
|
|
|
pr_debug("Allocate %d lli:s for this transfer\n", len);
|
2010-03-04 21:31:47 +08:00
|
|
|
lli = coh901318_lli_alloc(&cohc->base->pool, len);
|
2009-11-20 02:49:17 +08:00
|
|
|
|
2010-03-04 21:31:47 +08:00
|
|
|
if (lli == NULL)
|
2009-11-20 02:49:17 +08:00
|
|
|
goto err_dma_alloc;
|
|
|
|
|
|
2010-03-04 21:31:47 +08:00
|
|
|
/* initiate allocated lli list */
|
|
|
|
|
ret = coh901318_lli_fill_sg(&cohc->base->pool, lli, sgl, sg_len,
|
2013-01-04 20:50:49 +08:00
|
|
|
cohc->addr,
|
2010-03-03 05:17:44 +08:00
|
|
|
ctrl_chained,
|
|
|
|
|
ctrl,
|
|
|
|
|
ctrl_last,
|
|
|
|
|
direction, COH901318_CX_CTRL_TC_IRQ_ENABLE);
|
|
|
|
|
if (ret)
|
|
|
|
|
goto err_lli_fill;
|
2009-11-20 02:49:17 +08:00
|
|
|
|
2010-08-04 19:37:53 +08:00
|
|
|
|
2010-03-04 21:31:47 +08:00
|
|
|
COH_DBG(coh901318_list_print(cohc, lli));
|
2009-11-20 02:49:17 +08:00
|
|
|
|
2010-03-03 05:17:20 +08:00
|
|
|
/* Pick a descriptor to handle this transfer */
|
|
|
|
|
cohd = coh901318_desc_get(cohc);
|
2011-07-01 22:47:28 +08:00
|
|
|
cohd->head_config = config;
|
|
|
|
|
/*
|
|
|
|
|
* Set the default head ctrl for the channel to the one from the
|
|
|
|
|
* lli, things may have changed due to odd buffer alignment
|
|
|
|
|
* etc.
|
|
|
|
|
*/
|
|
|
|
|
cohd->head_ctrl = lli->control;
|
2010-03-03 05:17:20 +08:00
|
|
|
cohd->dir = direction;
|
|
|
|
|
cohd->flags = flags;
|
|
|
|
|
cohd->desc.tx_submit = coh901318_tx_submit;
|
2010-03-04 21:31:47 +08:00
|
|
|
cohd->lli = lli;
|
2010-03-03 05:17:20 +08:00
|
|
|
|
2009-11-20 02:49:17 +08:00
|
|
|
spin_unlock_irqrestore(&cohc->lock, flg);
|
|
|
|
|
|
|
|
|
|
return &cohd->desc;
|
2010-03-03 05:17:44 +08:00
|
|
|
err_lli_fill:
|
2009-11-20 02:49:17 +08:00
|
|
|
err_dma_alloc:
|
|
|
|
|
err_direction:
|
|
|
|
|
spin_unlock_irqrestore(&cohc->lock, flg);
|
|
|
|
|
out:
|
|
|
|
|
return NULL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static enum dma_status
|
2010-03-27 07:50:49 +08:00
|
|
|
coh901318_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
|
|
|
|
|
struct dma_tx_state *txstate)
|
2009-11-20 02:49:17 +08:00
|
|
|
{
|
|
|
|
|
struct coh901318_chan *cohc = to_coh901318_chan(chan);
|
2012-03-07 06:35:27 +08:00
|
|
|
enum dma_status ret;
|
2009-11-20 02:49:17 +08:00
|
|
|
|
2012-03-07 06:35:27 +08:00
|
|
|
ret = dma_cookie_status(chan, cookie, txstate);
|
2013-10-16 16:05:45 +08:00
|
|
|
if (ret == DMA_COMPLETE)
|
2013-02-14 17:00:18 +08:00
|
|
|
return ret;
|
|
|
|
|
|
2012-03-07 06:35:27 +08:00
|
|
|
dma_set_residue(txstate, coh901318_get_bytes_left(chan));
|
2009-11-20 02:49:17 +08:00
|
|
|
|
2010-03-27 07:50:49 +08:00
|
|
|
if (ret == DMA_IN_PROGRESS && cohc->stopped)
|
|
|
|
|
ret = DMA_PAUSED;
|
2009-11-20 02:49:17 +08:00
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
coh901318_issue_pending(struct dma_chan *chan)
|
|
|
|
|
{
|
|
|
|
|
struct coh901318_chan *cohc = to_coh901318_chan(chan);
|
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
|
|
spin_lock_irqsave(&cohc->lock, flags);
|
|
|
|
|
|
2010-03-04 21:31:47 +08:00
|
|
|
/*
|
|
|
|
|
* Busy means that pending jobs are already being processed,
|
|
|
|
|
* and then there is no point in starting the queue: the
|
|
|
|
|
* terminal count interrupt on the channel will take the next
|
|
|
|
|
* job on the queue and execute it anyway.
|
|
|
|
|
*/
|
2009-11-20 02:49:17 +08:00
|
|
|
if (!cohc->busy)
|
|
|
|
|
coh901318_queue_start(cohc);
|
|
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&cohc->lock, flags);
|
|
|
|
|
}
|
|
|
|
|
|
2010-08-04 19:37:53 +08:00
|
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/*
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* Here we wrap in the runtime dma control interface
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*/
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struct burst_table {
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int burst_8bit;
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int burst_16bit;
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int burst_32bit;
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u32 reg;
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};
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static const struct burst_table burst_sizes[] = {
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{
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.burst_8bit = 64,
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.burst_16bit = 32,
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.burst_32bit = 16,
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.reg = COH901318_CX_CTRL_BURST_COUNT_64_BYTES,
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},
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{
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.burst_8bit = 48,
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.burst_16bit = 24,
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.burst_32bit = 12,
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.reg = COH901318_CX_CTRL_BURST_COUNT_48_BYTES,
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},
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{
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.burst_8bit = 32,
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.burst_16bit = 16,
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.burst_32bit = 8,
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.reg = COH901318_CX_CTRL_BURST_COUNT_32_BYTES,
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},
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{
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.burst_8bit = 16,
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.burst_16bit = 8,
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.burst_32bit = 4,
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.reg = COH901318_CX_CTRL_BURST_COUNT_16_BYTES,
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},
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{
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.burst_8bit = 8,
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.burst_16bit = 4,
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.burst_32bit = 2,
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.reg = COH901318_CX_CTRL_BURST_COUNT_8_BYTES,
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},
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{
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.burst_8bit = 4,
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.burst_16bit = 2,
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.burst_32bit = 1,
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.reg = COH901318_CX_CTRL_BURST_COUNT_4_BYTES,
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},
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{
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.burst_8bit = 2,
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.burst_16bit = 1,
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.burst_32bit = 0,
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.reg = COH901318_CX_CTRL_BURST_COUNT_2_BYTES,
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},
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{
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.burst_8bit = 1,
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.burst_16bit = 0,
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.burst_32bit = 0,
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.reg = COH901318_CX_CTRL_BURST_COUNT_1_BYTE,
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},
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};
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static void coh901318_dma_set_runtimeconfig(struct dma_chan *chan,
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struct dma_slave_config *config)
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{
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struct coh901318_chan *cohc = to_coh901318_chan(chan);
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dma_addr_t addr;
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enum dma_slave_buswidth addr_width;
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u32 maxburst;
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2013-01-04 20:50:49 +08:00
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u32 ctrl = 0;
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2010-08-04 19:37:53 +08:00
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int i = 0;
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/* We only support mem to per or per to mem transfers */
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2011-10-14 01:04:23 +08:00
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if (config->direction == DMA_DEV_TO_MEM) {
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2010-08-04 19:37:53 +08:00
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addr = config->src_addr;
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addr_width = config->src_addr_width;
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maxburst = config->src_maxburst;
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2011-10-14 01:04:23 +08:00
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} else if (config->direction == DMA_MEM_TO_DEV) {
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2010-08-04 19:37:53 +08:00
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addr = config->dst_addr;
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addr_width = config->dst_addr_width;
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maxburst = config->dst_maxburst;
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} else {
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dev_err(COHC_2_DEV(cohc), "illegal channel mode\n");
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return;
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}
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dev_dbg(COHC_2_DEV(cohc), "configure channel for %d byte transfers\n",
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addr_width);
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switch (addr_width) {
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case DMA_SLAVE_BUSWIDTH_1_BYTE:
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2013-01-04 20:50:49 +08:00
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ctrl |=
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2010-08-04 19:37:53 +08:00
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COH901318_CX_CTRL_SRC_BUS_SIZE_8_BITS |
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COH901318_CX_CTRL_DST_BUS_SIZE_8_BITS;
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while (i < ARRAY_SIZE(burst_sizes)) {
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if (burst_sizes[i].burst_8bit <= maxburst)
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break;
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i++;
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}
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break;
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case DMA_SLAVE_BUSWIDTH_2_BYTES:
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2013-01-04 20:50:49 +08:00
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ctrl |=
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2010-08-04 19:37:53 +08:00
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COH901318_CX_CTRL_SRC_BUS_SIZE_16_BITS |
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COH901318_CX_CTRL_DST_BUS_SIZE_16_BITS;
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while (i < ARRAY_SIZE(burst_sizes)) {
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if (burst_sizes[i].burst_16bit <= maxburst)
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break;
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i++;
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}
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break;
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case DMA_SLAVE_BUSWIDTH_4_BYTES:
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/* Direction doesn't matter here, it's 32/32 bits */
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2013-01-04 20:50:49 +08:00
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ctrl |=
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2010-08-04 19:37:53 +08:00
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COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
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COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS;
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while (i < ARRAY_SIZE(burst_sizes)) {
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if (burst_sizes[i].burst_32bit <= maxburst)
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break;
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i++;
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}
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break;
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default:
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dev_err(COHC_2_DEV(cohc),
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"bad runtimeconfig: alien address width\n");
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return;
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}
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2013-01-04 20:50:49 +08:00
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ctrl |= burst_sizes[i].reg;
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2010-08-04 19:37:53 +08:00
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dev_dbg(COHC_2_DEV(cohc),
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"selected burst size %d bytes for address width %d bytes, maxburst %d\n",
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burst_sizes[i].burst_8bit, addr_width, maxburst);
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2013-01-04 20:50:49 +08:00
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cohc->addr = addr;
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cohc->ctrl = ctrl;
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2010-08-04 19:37:53 +08:00
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}
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2010-03-27 07:44:01 +08:00
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static int
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2010-05-18 07:30:42 +08:00
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coh901318_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
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unsigned long arg)
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2009-11-20 02:49:17 +08:00
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{
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unsigned long flags;
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struct coh901318_chan *cohc = to_coh901318_chan(chan);
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struct coh901318_desc *cohd;
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void __iomem *virtbase = cohc->base->virtbase;
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2010-08-04 19:37:53 +08:00
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if (cmd == DMA_SLAVE_CONFIG) {
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struct dma_slave_config *config =
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(struct dma_slave_config *) arg;
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coh901318_dma_set_runtimeconfig(chan, config);
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return 0;
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}
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2010-03-27 07:44:01 +08:00
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if (cmd == DMA_PAUSE) {
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coh901318_pause(chan);
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return 0;
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}
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if (cmd == DMA_RESUME) {
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coh901318_resume(chan);
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return 0;
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}
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if (cmd != DMA_TERMINATE_ALL)
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return -ENXIO;
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2009-11-20 02:49:17 +08:00
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2010-03-27 07:44:01 +08:00
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/* The remainder of this function terminates the transfer */
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coh901318_pause(chan);
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2009-11-20 02:49:17 +08:00
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spin_lock_irqsave(&cohc->lock, flags);
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/* Clear any pending BE or TC interrupt */
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if (cohc->id < 32) {
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writel(1 << cohc->id, virtbase + COH901318_BE_INT_CLEAR1);
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writel(1 << cohc->id, virtbase + COH901318_TC_INT_CLEAR1);
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} else {
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writel(1 << (cohc->id - 32), virtbase +
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COH901318_BE_INT_CLEAR2);
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writel(1 << (cohc->id - 32), virtbase +
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COH901318_TC_INT_CLEAR2);
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}
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enable_powersave(cohc);
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while ((cohd = coh901318_first_active_get(cohc))) {
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/* release the lli allocation*/
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2010-03-04 21:31:47 +08:00
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coh901318_lli_free(&cohc->base->pool, &cohd->lli);
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2009-11-20 02:49:17 +08:00
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/* return desc to free-list */
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2010-03-03 05:17:15 +08:00
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coh901318_desc_remove(cohd);
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2009-11-20 02:49:17 +08:00
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coh901318_desc_free(cohc, cohd);
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}
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while ((cohd = coh901318_first_queued(cohc))) {
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/* release the lli allocation*/
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2010-03-04 21:31:47 +08:00
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coh901318_lli_free(&cohc->base->pool, &cohd->lli);
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2009-11-20 02:49:17 +08:00
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/* return desc to free-list */
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2010-03-03 05:17:15 +08:00
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coh901318_desc_remove(cohd);
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2009-11-20 02:49:17 +08:00
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coh901318_desc_free(cohc, cohd);
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}
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cohc->nbr_active_done = 0;
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cohc->busy = 0;
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spin_unlock_irqrestore(&cohc->lock, flags);
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2010-03-27 07:44:01 +08:00
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return 0;
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2009-11-20 02:49:17 +08:00
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}
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2010-08-04 19:37:53 +08:00
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2009-11-20 02:49:17 +08:00
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void coh901318_base_init(struct dma_device *dma, const int *pick_chans,
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struct coh901318_base *base)
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{
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int chans_i;
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int i = 0;
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struct coh901318_chan *cohc;
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INIT_LIST_HEAD(&dma->channels);
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for (chans_i = 0; pick_chans[chans_i] != -1; chans_i += 2) {
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for (i = pick_chans[chans_i]; i <= pick_chans[chans_i+1]; i++) {
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cohc = &base->chans[i];
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cohc->base = base;
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cohc->chan.device = dma;
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cohc->id = i;
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/* TODO: do we really need this lock if only one
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* client is connected to each channel?
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*/
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spin_lock_init(&cohc->lock);
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cohc->nbr_active_done = 0;
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cohc->busy = 0;
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INIT_LIST_HEAD(&cohc->free);
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INIT_LIST_HEAD(&cohc->active);
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INIT_LIST_HEAD(&cohc->queue);
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tasklet_init(&cohc->tasklet, dma_tasklet,
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(unsigned long) cohc);
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list_add_tail(&cohc->chan.device_node,
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&dma->channels);
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}
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}
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}
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static int __init coh901318_probe(struct platform_device *pdev)
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{
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int err = 0;
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struct coh901318_base *base;
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int irq;
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struct resource *io;
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io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!io)
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2012-06-13 02:19:24 +08:00
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return -ENODEV;
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2009-11-20 02:49:17 +08:00
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/* Map DMA controller registers to virtual memory */
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2012-06-13 02:19:24 +08:00
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if (devm_request_mem_region(&pdev->dev,
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io->start,
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resource_size(io),
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pdev->dev.driver->name) == NULL)
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return -ENOMEM;
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2009-11-20 02:49:17 +08:00
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2012-06-13 02:19:24 +08:00
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base = devm_kzalloc(&pdev->dev,
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ALIGN(sizeof(struct coh901318_base), 4) +
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2013-01-07 06:36:14 +08:00
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U300_DMA_CHANNELS *
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2012-06-13 02:19:24 +08:00
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sizeof(struct coh901318_chan),
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GFP_KERNEL);
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2009-11-20 02:49:17 +08:00
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if (!base)
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2012-06-13 02:19:24 +08:00
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return -ENOMEM;
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2009-11-20 02:49:17 +08:00
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base->chans = ((void *)base) + ALIGN(sizeof(struct coh901318_base), 4);
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2012-06-13 02:19:24 +08:00
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base->virtbase = devm_ioremap(&pdev->dev, io->start, resource_size(io));
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if (!base->virtbase)
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return -ENOMEM;
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2009-11-20 02:49:17 +08:00
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base->dev = &pdev->dev;
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spin_lock_init(&base->pm.lock);
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base->pm.started_channels = 0;
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COH901318_DEBUGFS_ASSIGN(debugfs_dma_base, base);
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irq = platform_get_irq(pdev, 0);
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if (irq < 0)
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2012-06-13 02:19:24 +08:00
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return irq;
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2013-10-13 13:00:00 +08:00
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err = devm_request_irq(&pdev->dev, irq, dma_irq_handler, 0,
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2012-06-13 02:19:24 +08:00
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"coh901318", base);
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if (err)
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return err;
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2009-11-20 02:49:17 +08:00
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err = coh901318_pool_create(&base->pool, &pdev->dev,
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sizeof(struct coh901318_lli),
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32);
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if (err)
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2012-06-13 02:19:24 +08:00
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return err;
|
2009-11-20 02:49:17 +08:00
|
|
|
|
|
|
|
|
/* init channels for device transfers */
|
2013-01-07 06:36:14 +08:00
|
|
|
coh901318_base_init(&base->dma_slave, dma_slave_channels,
|
2009-11-20 02:49:17 +08:00
|
|
|
base);
|
|
|
|
|
|
|
|
|
|
dma_cap_zero(base->dma_slave.cap_mask);
|
|
|
|
|
dma_cap_set(DMA_SLAVE, base->dma_slave.cap_mask);
|
|
|
|
|
|
|
|
|
|
base->dma_slave.device_alloc_chan_resources = coh901318_alloc_chan_resources;
|
|
|
|
|
base->dma_slave.device_free_chan_resources = coh901318_free_chan_resources;
|
|
|
|
|
base->dma_slave.device_prep_slave_sg = coh901318_prep_slave_sg;
|
2010-03-27 07:50:49 +08:00
|
|
|
base->dma_slave.device_tx_status = coh901318_tx_status;
|
2009-11-20 02:49:17 +08:00
|
|
|
base->dma_slave.device_issue_pending = coh901318_issue_pending;
|
2010-03-27 07:44:01 +08:00
|
|
|
base->dma_slave.device_control = coh901318_control;
|
2009-11-20 02:49:17 +08:00
|
|
|
base->dma_slave.dev = &pdev->dev;
|
|
|
|
|
|
|
|
|
|
err = dma_async_device_register(&base->dma_slave);
|
|
|
|
|
|
|
|
|
|
if (err)
|
|
|
|
|
goto err_register_slave;
|
|
|
|
|
|
|
|
|
|
/* init channels for memcpy */
|
2013-01-07 06:36:14 +08:00
|
|
|
coh901318_base_init(&base->dma_memcpy, dma_memcpy_channels,
|
2009-11-20 02:49:17 +08:00
|
|
|
base);
|
|
|
|
|
|
|
|
|
|
dma_cap_zero(base->dma_memcpy.cap_mask);
|
|
|
|
|
dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask);
|
|
|
|
|
|
|
|
|
|
base->dma_memcpy.device_alloc_chan_resources = coh901318_alloc_chan_resources;
|
|
|
|
|
base->dma_memcpy.device_free_chan_resources = coh901318_free_chan_resources;
|
|
|
|
|
base->dma_memcpy.device_prep_dma_memcpy = coh901318_prep_memcpy;
|
2010-03-27 07:50:49 +08:00
|
|
|
base->dma_memcpy.device_tx_status = coh901318_tx_status;
|
2009-11-20 02:49:17 +08:00
|
|
|
base->dma_memcpy.device_issue_pending = coh901318_issue_pending;
|
2010-03-27 07:44:01 +08:00
|
|
|
base->dma_memcpy.device_control = coh901318_control;
|
2009-11-20 02:49:17 +08:00
|
|
|
base->dma_memcpy.dev = &pdev->dev;
|
2010-03-03 03:12:46 +08:00
|
|
|
/*
|
|
|
|
|
* This controller can only access address at even 32bit boundaries,
|
|
|
|
|
* i.e. 2^2
|
|
|
|
|
*/
|
|
|
|
|
base->dma_memcpy.copy_align = 2;
|
2009-11-20 02:49:17 +08:00
|
|
|
err = dma_async_device_register(&base->dma_memcpy);
|
|
|
|
|
|
|
|
|
|
if (err)
|
|
|
|
|
goto err_register_memcpy;
|
|
|
|
|
|
2013-04-19 19:42:55 +08:00
|
|
|
err = of_dma_controller_register(pdev->dev.of_node, coh901318_xlate,
|
|
|
|
|
base);
|
|
|
|
|
if (err)
|
|
|
|
|
goto err_register_of_dma;
|
|
|
|
|
|
2012-06-13 02:19:24 +08:00
|
|
|
platform_set_drvdata(pdev, base);
|
2010-03-03 05:17:15 +08:00
|
|
|
dev_info(&pdev->dev, "Initialized COH901318 DMA on virtual base 0x%08x\n",
|
2009-11-20 02:49:17 +08:00
|
|
|
(u32) base->virtbase);
|
|
|
|
|
|
|
|
|
|
return err;
|
|
|
|
|
|
2013-04-19 19:42:55 +08:00
|
|
|
err_register_of_dma:
|
|
|
|
|
dma_async_device_unregister(&base->dma_memcpy);
|
2009-11-20 02:49:17 +08:00
|
|
|
err_register_memcpy:
|
|
|
|
|
dma_async_device_unregister(&base->dma_slave);
|
|
|
|
|
err_register_slave:
|
|
|
|
|
coh901318_pool_destroy(&base->pool);
|
|
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
|
2013-02-20 08:07:04 +08:00
|
|
|
static int coh901318_remove(struct platform_device *pdev)
|
2009-11-20 02:49:17 +08:00
|
|
|
{
|
|
|
|
|
struct coh901318_base *base = platform_get_drvdata(pdev);
|
|
|
|
|
|
2013-04-19 19:42:55 +08:00
|
|
|
of_dma_controller_free(pdev->dev.of_node);
|
2009-11-20 02:49:17 +08:00
|
|
|
dma_async_device_unregister(&base->dma_memcpy);
|
|
|
|
|
dma_async_device_unregister(&base->dma_slave);
|
|
|
|
|
coh901318_pool_destroy(&base->pool);
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2013-04-19 19:42:55 +08:00
|
|
|
static const struct of_device_id coh901318_dt_match[] = {
|
|
|
|
|
{ .compatible = "stericsson,coh901318" },
|
|
|
|
|
{},
|
|
|
|
|
};
|
2009-11-20 02:49:17 +08:00
|
|
|
|
|
|
|
|
static struct platform_driver coh901318_driver = {
|
2013-02-20 08:07:04 +08:00
|
|
|
.remove = coh901318_remove,
|
2009-11-20 02:49:17 +08:00
|
|
|
.driver = {
|
|
|
|
|
.name = "coh901318",
|
2013-04-19 19:42:55 +08:00
|
|
|
.of_match_table = coh901318_dt_match,
|
2009-11-20 02:49:17 +08:00
|
|
|
},
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
int __init coh901318_init(void)
|
|
|
|
|
{
|
|
|
|
|
return platform_driver_probe(&coh901318_driver, coh901318_probe);
|
|
|
|
|
}
|
2011-05-18 20:18:57 +08:00
|
|
|
subsys_initcall(coh901318_init);
|
2009-11-20 02:49:17 +08:00
|
|
|
|
|
|
|
|
void __exit coh901318_exit(void)
|
|
|
|
|
{
|
|
|
|
|
platform_driver_unregister(&coh901318_driver);
|
|
|
|
|
}
|
|
|
|
|
module_exit(coh901318_exit);
|
|
|
|
|
|
|
|
|
|
MODULE_LICENSE("GPL");
|
|
|
|
|
MODULE_AUTHOR("Per Friden");
|
