2021-08-03 01:30:05 +08:00
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// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright(c) 2020 Intel Corporation. */
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#include <linux/device.h>
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#include <linux/slab.h>
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#include <linux/idr.h>
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#include <linux/pci.h>
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#include <cxlmem.h>
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2023-04-19 11:26:28 +08:00
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#include "trace.h"
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2021-08-03 01:30:05 +08:00
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#include "core.h"
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2021-09-09 13:12:32 +08:00
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static DECLARE_RWSEM(cxl_memdev_rwsem);
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2021-08-03 01:30:05 +08:00
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/*
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* An entire PCI topology full of devices should be enough for any
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* config
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*/
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#define CXL_MEM_MAX_DEVS 65536
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static int cxl_mem_major;
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static DEFINE_IDA(cxl_memdev_ida);
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static void cxl_memdev_release(struct device *dev)
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{
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struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
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ida_free(&cxl_memdev_ida, cxlmd->id);
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kfree(cxlmd);
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}
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2023-01-11 19:30:08 +08:00
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static char *cxl_memdev_devnode(const struct device *dev, umode_t *mode, kuid_t *uid,
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2021-08-03 01:30:05 +08:00
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kgid_t *gid)
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{
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return kasprintf(GFP_KERNEL, "cxl/%s", dev_name(dev));
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}
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static ssize_t firmware_version_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
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2021-11-03 04:29:01 +08:00
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struct cxl_dev_state *cxlds = cxlmd->cxlds;
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2021-08-03 01:30:05 +08:00
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2021-11-03 04:29:01 +08:00
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return sysfs_emit(buf, "%.16s\n", cxlds->firmware_version);
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2021-08-03 01:30:05 +08:00
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}
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static DEVICE_ATTR_RO(firmware_version);
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static ssize_t payload_max_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
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2021-11-03 04:29:01 +08:00
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struct cxl_dev_state *cxlds = cxlmd->cxlds;
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2021-08-03 01:30:05 +08:00
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2021-11-03 04:29:01 +08:00
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return sysfs_emit(buf, "%zu\n", cxlds->payload_size);
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2021-08-03 01:30:05 +08:00
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}
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static DEVICE_ATTR_RO(payload_max);
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static ssize_t label_storage_size_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
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2021-11-03 04:29:01 +08:00
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struct cxl_dev_state *cxlds = cxlmd->cxlds;
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2021-08-03 01:30:05 +08:00
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2021-11-03 04:29:01 +08:00
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return sysfs_emit(buf, "%zu\n", cxlds->lsa_size);
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2021-08-03 01:30:05 +08:00
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}
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static DEVICE_ATTR_RO(label_storage_size);
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static ssize_t ram_size_show(struct device *dev, struct device_attribute *attr,
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char *buf)
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{
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struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
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2021-11-03 04:29:01 +08:00
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struct cxl_dev_state *cxlds = cxlmd->cxlds;
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2022-05-22 06:35:29 +08:00
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unsigned long long len = resource_size(&cxlds->ram_res);
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2021-08-03 01:30:05 +08:00
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return sysfs_emit(buf, "%#llx\n", len);
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}
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static struct device_attribute dev_attr_ram_size =
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__ATTR(size, 0444, ram_size_show, NULL);
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static ssize_t pmem_size_show(struct device *dev, struct device_attribute *attr,
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char *buf)
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{
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struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
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2021-11-03 04:29:01 +08:00
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struct cxl_dev_state *cxlds = cxlmd->cxlds;
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2022-05-22 06:35:29 +08:00
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unsigned long long len = resource_size(&cxlds->pmem_res);
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2021-08-03 01:30:05 +08:00
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return sysfs_emit(buf, "%#llx\n", len);
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}
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static struct device_attribute dev_attr_pmem_size =
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__ATTR(size, 0444, pmem_size_show, NULL);
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2022-02-01 05:56:11 +08:00
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static ssize_t serial_show(struct device *dev, struct device_attribute *attr,
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char *buf)
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{
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struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
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struct cxl_dev_state *cxlds = cxlmd->cxlds;
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return sysfs_emit(buf, "%#llx\n", cxlds->serial);
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}
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static DEVICE_ATTR_RO(serial);
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2022-01-24 08:31:24 +08:00
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static ssize_t numa_node_show(struct device *dev, struct device_attribute *attr,
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char *buf)
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{
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return sprintf(buf, "%d\n", dev_to_node(dev));
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}
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static DEVICE_ATTR_RO(numa_node);
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2023-04-19 01:39:06 +08:00
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static int cxl_get_poison_by_memdev(struct cxl_memdev *cxlmd)
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{
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struct cxl_dev_state *cxlds = cxlmd->cxlds;
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u64 offset, length;
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int rc = 0;
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/* CXL 3.0 Spec 8.2.9.8.4.1 Separate pmem and ram poison requests */
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if (resource_size(&cxlds->pmem_res)) {
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offset = cxlds->pmem_res.start;
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length = resource_size(&cxlds->pmem_res);
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rc = cxl_mem_get_poison(cxlmd, offset, length, NULL);
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if (rc)
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return rc;
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}
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if (resource_size(&cxlds->ram_res)) {
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offset = cxlds->ram_res.start;
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length = resource_size(&cxlds->ram_res);
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rc = cxl_mem_get_poison(cxlmd, offset, length, NULL);
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/*
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* Invalid Physical Address is not an error for
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* volatile addresses. Device support is optional.
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*/
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if (rc == -EFAULT)
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rc = 0;
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}
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return rc;
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}
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int cxl_trigger_poison_list(struct cxl_memdev *cxlmd)
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{
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2023-04-19 01:39:07 +08:00
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struct cxl_port *port;
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2023-04-19 01:39:06 +08:00
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int rc;
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2023-04-19 01:39:07 +08:00
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port = dev_get_drvdata(&cxlmd->dev);
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if (!port || !is_cxl_endpoint(port))
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return -EINVAL;
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2023-04-19 01:39:06 +08:00
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rc = down_read_interruptible(&cxl_dpa_rwsem);
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if (rc)
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return rc;
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2023-04-19 01:39:07 +08:00
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if (port->commit_end == -1) {
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/* No regions mapped to this memdev */
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rc = cxl_get_poison_by_memdev(cxlmd);
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} else {
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/* Regions mapped, collect poison by endpoint */
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rc = cxl_get_poison_by_endpoint(port);
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}
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2023-04-19 01:39:06 +08:00
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up_read(&cxl_dpa_rwsem);
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return rc;
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}
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EXPORT_SYMBOL_NS_GPL(cxl_trigger_poison_list, CXL);
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2023-04-19 11:26:27 +08:00
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struct cxl_dpa_to_region_context {
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struct cxl_region *cxlr;
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u64 dpa;
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};
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static int __cxl_dpa_to_region(struct device *dev, void *arg)
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{
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struct cxl_dpa_to_region_context *ctx = arg;
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struct cxl_endpoint_decoder *cxled;
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u64 dpa = ctx->dpa;
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if (!is_endpoint_decoder(dev))
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return 0;
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cxled = to_cxl_endpoint_decoder(dev);
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if (!cxled->dpa_res || !resource_size(cxled->dpa_res))
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return 0;
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if (dpa > cxled->dpa_res->end || dpa < cxled->dpa_res->start)
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return 0;
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dev_dbg(dev, "dpa:0x%llx mapped in region:%s\n", dpa,
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dev_name(&cxled->cxld.region->dev));
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ctx->cxlr = cxled->cxld.region;
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return 1;
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}
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static struct cxl_region *cxl_dpa_to_region(struct cxl_memdev *cxlmd, u64 dpa)
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{
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struct cxl_dpa_to_region_context ctx;
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struct cxl_port *port;
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ctx = (struct cxl_dpa_to_region_context) {
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.dpa = dpa,
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};
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port = dev_get_drvdata(&cxlmd->dev);
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if (port && is_cxl_endpoint(port) && port->commit_end != -1)
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device_for_each_child(&port->dev, &ctx, __cxl_dpa_to_region);
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return ctx.cxlr;
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}
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cxl/memdev: Add support for the Inject Poison mailbox command
CXL devices optionally support the INJECT POISON mailbox command. Add
memdev driver support for the mailbox command.
Per the CXL Specification (3.0 8.2.9.8.4.2), after receiving a valid
inject poison request, the device will return poison when the address
is accessed through the CXL.mem driver. Injecting poison adds the address
to the device's Poison List and the error source is set to Injected.
In addition, the device adds a poison creation event to its internal
Informational Event log, updates the Event Status register, and if
configured, interrupts the host.
Also, per the CXL Specification, it is not an error to inject poison
into an address that already has poison present and no error is
returned from the device.
If the address is not contained in the device's dpa resource, or is
not 64 byte aligned, return -EINVAL without issuing the mbox command.
Poison injection is intended for debug only and will be exposed to
userspace through debugfs. Restrict compilation to CONFIG_DEBUG_FS.
Signed-off-by: Alison Schofield <alison.schofield@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Link: https://lore.kernel.org/r/241c64115e6bd2effed9c7a20b08b3908dd7be8f.1681874357.git.alison.schofield@intel.com
Tested-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2023-04-19 11:26:25 +08:00
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static int cxl_validate_poison_dpa(struct cxl_memdev *cxlmd, u64 dpa)
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{
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struct cxl_dev_state *cxlds = cxlmd->cxlds;
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if (!IS_ENABLED(CONFIG_DEBUG_FS))
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return 0;
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if (!resource_size(&cxlds->dpa_res)) {
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dev_dbg(cxlds->dev, "device has no dpa resource\n");
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return -EINVAL;
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}
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if (dpa < cxlds->dpa_res.start || dpa > cxlds->dpa_res.end) {
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dev_dbg(cxlds->dev, "dpa:0x%llx not in resource:%pR\n",
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dpa, &cxlds->dpa_res);
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return -EINVAL;
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}
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if (!IS_ALIGNED(dpa, 64)) {
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dev_dbg(cxlds->dev, "dpa:0x%llx is not 64-byte aligned\n", dpa);
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return -EINVAL;
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}
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return 0;
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}
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int cxl_inject_poison(struct cxl_memdev *cxlmd, u64 dpa)
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{
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struct cxl_dev_state *cxlds = cxlmd->cxlds;
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struct cxl_mbox_inject_poison inject;
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2023-04-19 11:26:28 +08:00
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struct cxl_poison_record record;
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cxl/memdev: Add support for the Inject Poison mailbox command
CXL devices optionally support the INJECT POISON mailbox command. Add
memdev driver support for the mailbox command.
Per the CXL Specification (3.0 8.2.9.8.4.2), after receiving a valid
inject poison request, the device will return poison when the address
is accessed through the CXL.mem driver. Injecting poison adds the address
to the device's Poison List and the error source is set to Injected.
In addition, the device adds a poison creation event to its internal
Informational Event log, updates the Event Status register, and if
configured, interrupts the host.
Also, per the CXL Specification, it is not an error to inject poison
into an address that already has poison present and no error is
returned from the device.
If the address is not contained in the device's dpa resource, or is
not 64 byte aligned, return -EINVAL without issuing the mbox command.
Poison injection is intended for debug only and will be exposed to
userspace through debugfs. Restrict compilation to CONFIG_DEBUG_FS.
Signed-off-by: Alison Schofield <alison.schofield@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Link: https://lore.kernel.org/r/241c64115e6bd2effed9c7a20b08b3908dd7be8f.1681874357.git.alison.schofield@intel.com
Tested-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2023-04-19 11:26:25 +08:00
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struct cxl_mbox_cmd mbox_cmd;
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2023-04-19 11:26:27 +08:00
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struct cxl_region *cxlr;
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cxl/memdev: Add support for the Inject Poison mailbox command
CXL devices optionally support the INJECT POISON mailbox command. Add
memdev driver support for the mailbox command.
Per the CXL Specification (3.0 8.2.9.8.4.2), after receiving a valid
inject poison request, the device will return poison when the address
is accessed through the CXL.mem driver. Injecting poison adds the address
to the device's Poison List and the error source is set to Injected.
In addition, the device adds a poison creation event to its internal
Informational Event log, updates the Event Status register, and if
configured, interrupts the host.
Also, per the CXL Specification, it is not an error to inject poison
into an address that already has poison present and no error is
returned from the device.
If the address is not contained in the device's dpa resource, or is
not 64 byte aligned, return -EINVAL without issuing the mbox command.
Poison injection is intended for debug only and will be exposed to
userspace through debugfs. Restrict compilation to CONFIG_DEBUG_FS.
Signed-off-by: Alison Schofield <alison.schofield@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Link: https://lore.kernel.org/r/241c64115e6bd2effed9c7a20b08b3908dd7be8f.1681874357.git.alison.schofield@intel.com
Tested-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2023-04-19 11:26:25 +08:00
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int rc;
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if (!IS_ENABLED(CONFIG_DEBUG_FS))
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return 0;
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rc = down_read_interruptible(&cxl_dpa_rwsem);
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if (rc)
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return rc;
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rc = cxl_validate_poison_dpa(cxlmd, dpa);
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if (rc)
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goto out;
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inject.address = cpu_to_le64(dpa);
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mbox_cmd = (struct cxl_mbox_cmd) {
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.opcode = CXL_MBOX_OP_INJECT_POISON,
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.size_in = sizeof(inject),
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.payload_in = &inject,
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};
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rc = cxl_internal_send_cmd(cxlds, &mbox_cmd);
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2023-04-19 11:26:27 +08:00
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if (rc)
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goto out;
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cxlr = cxl_dpa_to_region(cxlmd, dpa);
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if (cxlr)
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dev_warn_once(cxlds->dev,
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"poison inject dpa:%#llx region: %s\n", dpa,
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dev_name(&cxlr->dev));
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2023-04-19 11:26:28 +08:00
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record = (struct cxl_poison_record) {
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.address = cpu_to_le64(dpa),
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|
|
.length = cpu_to_le32(1),
|
|
|
|
};
|
|
|
|
trace_cxl_poison(cxlmd, cxlr, &record, 0, 0, CXL_POISON_TRACE_INJECT);
|
cxl/memdev: Add support for the Inject Poison mailbox command
CXL devices optionally support the INJECT POISON mailbox command. Add
memdev driver support for the mailbox command.
Per the CXL Specification (3.0 8.2.9.8.4.2), after receiving a valid
inject poison request, the device will return poison when the address
is accessed through the CXL.mem driver. Injecting poison adds the address
to the device's Poison List and the error source is set to Injected.
In addition, the device adds a poison creation event to its internal
Informational Event log, updates the Event Status register, and if
configured, interrupts the host.
Also, per the CXL Specification, it is not an error to inject poison
into an address that already has poison present and no error is
returned from the device.
If the address is not contained in the device's dpa resource, or is
not 64 byte aligned, return -EINVAL without issuing the mbox command.
Poison injection is intended for debug only and will be exposed to
userspace through debugfs. Restrict compilation to CONFIG_DEBUG_FS.
Signed-off-by: Alison Schofield <alison.schofield@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Link: https://lore.kernel.org/r/241c64115e6bd2effed9c7a20b08b3908dd7be8f.1681874357.git.alison.schofield@intel.com
Tested-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2023-04-19 11:26:25 +08:00
|
|
|
out:
|
|
|
|
up_read(&cxl_dpa_rwsem);
|
|
|
|
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_NS_GPL(cxl_inject_poison, CXL);
|
|
|
|
|
2023-04-19 11:26:26 +08:00
|
|
|
int cxl_clear_poison(struct cxl_memdev *cxlmd, u64 dpa)
|
|
|
|
{
|
|
|
|
struct cxl_dev_state *cxlds = cxlmd->cxlds;
|
|
|
|
struct cxl_mbox_clear_poison clear;
|
2023-04-19 11:26:28 +08:00
|
|
|
struct cxl_poison_record record;
|
2023-04-19 11:26:26 +08:00
|
|
|
struct cxl_mbox_cmd mbox_cmd;
|
2023-04-19 11:26:27 +08:00
|
|
|
struct cxl_region *cxlr;
|
2023-04-19 11:26:26 +08:00
|
|
|
int rc;
|
|
|
|
|
|
|
|
if (!IS_ENABLED(CONFIG_DEBUG_FS))
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
rc = down_read_interruptible(&cxl_dpa_rwsem);
|
|
|
|
if (rc)
|
|
|
|
return rc;
|
|
|
|
|
|
|
|
rc = cxl_validate_poison_dpa(cxlmd, dpa);
|
|
|
|
if (rc)
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* In CXL 3.0 Spec 8.2.9.8.4.3, the Clear Poison mailbox command
|
|
|
|
* is defined to accept 64 bytes of write-data, along with the
|
|
|
|
* address to clear. This driver uses zeroes as write-data.
|
|
|
|
*/
|
|
|
|
clear = (struct cxl_mbox_clear_poison) {
|
|
|
|
.address = cpu_to_le64(dpa)
|
|
|
|
};
|
|
|
|
|
|
|
|
mbox_cmd = (struct cxl_mbox_cmd) {
|
|
|
|
.opcode = CXL_MBOX_OP_CLEAR_POISON,
|
|
|
|
.size_in = sizeof(clear),
|
|
|
|
.payload_in = &clear,
|
|
|
|
};
|
|
|
|
|
|
|
|
rc = cxl_internal_send_cmd(cxlds, &mbox_cmd);
|
|
|
|
if (rc)
|
|
|
|
goto out;
|
2023-04-19 11:26:27 +08:00
|
|
|
|
|
|
|
cxlr = cxl_dpa_to_region(cxlmd, dpa);
|
|
|
|
if (cxlr)
|
|
|
|
dev_warn_once(cxlds->dev, "poison clear dpa:%#llx region: %s\n",
|
|
|
|
dpa, dev_name(&cxlr->dev));
|
2023-04-19 11:26:28 +08:00
|
|
|
|
|
|
|
record = (struct cxl_poison_record) {
|
|
|
|
.address = cpu_to_le64(dpa),
|
|
|
|
.length = cpu_to_le32(1),
|
|
|
|
};
|
|
|
|
trace_cxl_poison(cxlmd, cxlr, &record, 0, 0, CXL_POISON_TRACE_CLEAR);
|
2023-04-19 11:26:26 +08:00
|
|
|
out:
|
|
|
|
up_read(&cxl_dpa_rwsem);
|
|
|
|
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_NS_GPL(cxl_clear_poison, CXL);
|
|
|
|
|
2021-08-03 01:30:05 +08:00
|
|
|
static struct attribute *cxl_memdev_attributes[] = {
|
2022-02-01 05:56:11 +08:00
|
|
|
&dev_attr_serial.attr,
|
2021-08-03 01:30:05 +08:00
|
|
|
&dev_attr_firmware_version.attr,
|
|
|
|
&dev_attr_payload_max.attr,
|
|
|
|
&dev_attr_label_storage_size.attr,
|
2022-01-24 08:31:24 +08:00
|
|
|
&dev_attr_numa_node.attr,
|
2021-08-03 01:30:05 +08:00
|
|
|
NULL,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct attribute *cxl_memdev_pmem_attributes[] = {
|
|
|
|
&dev_attr_pmem_size.attr,
|
|
|
|
NULL,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct attribute *cxl_memdev_ram_attributes[] = {
|
|
|
|
&dev_attr_ram_size.attr,
|
|
|
|
NULL,
|
|
|
|
};
|
|
|
|
|
2022-01-24 08:31:24 +08:00
|
|
|
static umode_t cxl_memdev_visible(struct kobject *kobj, struct attribute *a,
|
|
|
|
int n)
|
|
|
|
{
|
|
|
|
if (!IS_ENABLED(CONFIG_NUMA) && a == &dev_attr_numa_node.attr)
|
|
|
|
return 0;
|
|
|
|
return a->mode;
|
|
|
|
}
|
|
|
|
|
2021-08-03 01:30:05 +08:00
|
|
|
static struct attribute_group cxl_memdev_attribute_group = {
|
|
|
|
.attrs = cxl_memdev_attributes,
|
2022-01-24 08:31:24 +08:00
|
|
|
.is_visible = cxl_memdev_visible,
|
2021-08-03 01:30:05 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct attribute_group cxl_memdev_ram_attribute_group = {
|
|
|
|
.name = "ram",
|
|
|
|
.attrs = cxl_memdev_ram_attributes,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct attribute_group cxl_memdev_pmem_attribute_group = {
|
|
|
|
.name = "pmem",
|
|
|
|
.attrs = cxl_memdev_pmem_attributes,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct attribute_group *cxl_memdev_attribute_groups[] = {
|
|
|
|
&cxl_memdev_attribute_group,
|
|
|
|
&cxl_memdev_ram_attribute_group,
|
|
|
|
&cxl_memdev_pmem_attribute_group,
|
|
|
|
NULL,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct device_type cxl_memdev_type = {
|
|
|
|
.name = "cxl_memdev",
|
|
|
|
.release = cxl_memdev_release,
|
|
|
|
.devnode = cxl_memdev_devnode,
|
|
|
|
.groups = cxl_memdev_attribute_groups,
|
|
|
|
};
|
|
|
|
|
2023-01-11 19:30:17 +08:00
|
|
|
bool is_cxl_memdev(const struct device *dev)
|
2022-02-04 23:18:31 +08:00
|
|
|
{
|
|
|
|
return dev->type == &cxl_memdev_type;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_NS_GPL(is_cxl_memdev, CXL);
|
|
|
|
|
2021-09-15 03:03:04 +08:00
|
|
|
/**
|
|
|
|
* set_exclusive_cxl_commands() - atomically disable user cxl commands
|
2021-11-03 04:29:01 +08:00
|
|
|
* @cxlds: The device state to operate on
|
2021-09-15 03:03:04 +08:00
|
|
|
* @cmds: bitmap of commands to mark exclusive
|
|
|
|
*
|
|
|
|
* Grab the cxl_memdev_rwsem in write mode to flush in-flight
|
|
|
|
* invocations of the ioctl path and then disable future execution of
|
|
|
|
* commands with the command ids set in @cmds.
|
|
|
|
*/
|
2021-11-03 04:29:01 +08:00
|
|
|
void set_exclusive_cxl_commands(struct cxl_dev_state *cxlds, unsigned long *cmds)
|
2021-09-15 03:03:04 +08:00
|
|
|
{
|
|
|
|
down_write(&cxl_memdev_rwsem);
|
2021-11-03 04:29:01 +08:00
|
|
|
bitmap_or(cxlds->exclusive_cmds, cxlds->exclusive_cmds, cmds,
|
2021-09-15 03:03:04 +08:00
|
|
|
CXL_MEM_COMMAND_ID_MAX);
|
|
|
|
up_write(&cxl_memdev_rwsem);
|
|
|
|
}
|
2021-11-13 08:32:58 +08:00
|
|
|
EXPORT_SYMBOL_NS_GPL(set_exclusive_cxl_commands, CXL);
|
2021-09-15 03:03:04 +08:00
|
|
|
|
|
|
|
/**
|
|
|
|
* clear_exclusive_cxl_commands() - atomically enable user cxl commands
|
2021-11-03 04:29:01 +08:00
|
|
|
* @cxlds: The device state to modify
|
2021-09-15 03:03:04 +08:00
|
|
|
* @cmds: bitmap of commands to mark available for userspace
|
|
|
|
*/
|
2021-11-03 04:29:01 +08:00
|
|
|
void clear_exclusive_cxl_commands(struct cxl_dev_state *cxlds, unsigned long *cmds)
|
2021-09-15 03:03:04 +08:00
|
|
|
{
|
|
|
|
down_write(&cxl_memdev_rwsem);
|
2021-11-03 04:29:01 +08:00
|
|
|
bitmap_andnot(cxlds->exclusive_cmds, cxlds->exclusive_cmds, cmds,
|
2021-09-15 03:03:04 +08:00
|
|
|
CXL_MEM_COMMAND_ID_MAX);
|
|
|
|
up_write(&cxl_memdev_rwsem);
|
|
|
|
}
|
2021-11-13 08:32:58 +08:00
|
|
|
EXPORT_SYMBOL_NS_GPL(clear_exclusive_cxl_commands, CXL);
|
2021-09-15 03:03:04 +08:00
|
|
|
|
2021-09-09 13:12:32 +08:00
|
|
|
static void cxl_memdev_shutdown(struct device *dev)
|
|
|
|
{
|
|
|
|
struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
|
|
|
|
|
|
|
|
down_write(&cxl_memdev_rwsem);
|
2021-11-03 04:29:01 +08:00
|
|
|
cxlmd->cxlds = NULL;
|
2021-09-09 13:12:32 +08:00
|
|
|
up_write(&cxl_memdev_rwsem);
|
|
|
|
}
|
|
|
|
|
2021-08-03 01:30:05 +08:00
|
|
|
static void cxl_memdev_unregister(void *_cxlmd)
|
|
|
|
{
|
|
|
|
struct cxl_memdev *cxlmd = _cxlmd;
|
|
|
|
struct device *dev = &cxlmd->dev;
|
|
|
|
|
2021-09-09 13:12:32 +08:00
|
|
|
cxl_memdev_shutdown(dev);
|
2021-08-03 01:30:05 +08:00
|
|
|
cdev_device_del(&cxlmd->cdev, dev);
|
|
|
|
put_device(dev);
|
|
|
|
}
|
|
|
|
|
2022-02-04 23:18:31 +08:00
|
|
|
static void detach_memdev(struct work_struct *work)
|
|
|
|
{
|
|
|
|
struct cxl_memdev *cxlmd;
|
|
|
|
|
|
|
|
cxlmd = container_of(work, typeof(*cxlmd), detach_work);
|
|
|
|
device_release_driver(&cxlmd->dev);
|
|
|
|
put_device(&cxlmd->dev);
|
|
|
|
}
|
|
|
|
|
2022-04-21 23:33:13 +08:00
|
|
|
static struct lock_class_key cxl_memdev_key;
|
|
|
|
|
2021-11-03 04:29:01 +08:00
|
|
|
static struct cxl_memdev *cxl_memdev_alloc(struct cxl_dev_state *cxlds,
|
2021-08-03 01:30:05 +08:00
|
|
|
const struct file_operations *fops)
|
|
|
|
{
|
|
|
|
struct cxl_memdev *cxlmd;
|
|
|
|
struct device *dev;
|
|
|
|
struct cdev *cdev;
|
|
|
|
int rc;
|
|
|
|
|
|
|
|
cxlmd = kzalloc(sizeof(*cxlmd), GFP_KERNEL);
|
|
|
|
if (!cxlmd)
|
|
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
|
2023-02-09 02:19:44 +08:00
|
|
|
rc = ida_alloc_max(&cxl_memdev_ida, CXL_MEM_MAX_DEVS - 1, GFP_KERNEL);
|
2021-08-03 01:30:05 +08:00
|
|
|
if (rc < 0)
|
|
|
|
goto err;
|
|
|
|
cxlmd->id = rc;
|
2023-02-11 09:29:09 +08:00
|
|
|
cxlmd->depth = -1;
|
2021-08-03 01:30:05 +08:00
|
|
|
|
|
|
|
dev = &cxlmd->dev;
|
|
|
|
device_initialize(dev);
|
2022-04-21 23:33:13 +08:00
|
|
|
lockdep_set_class(&dev->mutex, &cxl_memdev_key);
|
2021-11-03 04:29:01 +08:00
|
|
|
dev->parent = cxlds->dev;
|
2021-08-03 01:30:05 +08:00
|
|
|
dev->bus = &cxl_bus_type;
|
|
|
|
dev->devt = MKDEV(cxl_mem_major, cxlmd->id);
|
|
|
|
dev->type = &cxl_memdev_type;
|
|
|
|
device_set_pm_not_required(dev);
|
2022-02-04 23:18:31 +08:00
|
|
|
INIT_WORK(&cxlmd->detach_work, detach_memdev);
|
2021-08-03 01:30:05 +08:00
|
|
|
|
|
|
|
cdev = &cxlmd->cdev;
|
|
|
|
cdev_init(cdev, fops);
|
|
|
|
return cxlmd;
|
|
|
|
|
|
|
|
err:
|
|
|
|
kfree(cxlmd);
|
|
|
|
return ERR_PTR(rc);
|
|
|
|
}
|
|
|
|
|
2021-09-09 13:12:32 +08:00
|
|
|
static long __cxl_memdev_ioctl(struct cxl_memdev *cxlmd, unsigned int cmd,
|
|
|
|
unsigned long arg)
|
|
|
|
{
|
|
|
|
switch (cmd) {
|
|
|
|
case CXL_MEM_QUERY_COMMANDS:
|
|
|
|
return cxl_query_cmd(cxlmd, (void __user *)arg);
|
|
|
|
case CXL_MEM_SEND_COMMAND:
|
|
|
|
return cxl_send_cmd(cxlmd, (void __user *)arg);
|
|
|
|
default:
|
|
|
|
return -ENOTTY;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static long cxl_memdev_ioctl(struct file *file, unsigned int cmd,
|
|
|
|
unsigned long arg)
|
|
|
|
{
|
|
|
|
struct cxl_memdev *cxlmd = file->private_data;
|
|
|
|
int rc = -ENXIO;
|
|
|
|
|
|
|
|
down_read(&cxl_memdev_rwsem);
|
2021-11-03 04:29:01 +08:00
|
|
|
if (cxlmd->cxlds)
|
2021-09-09 13:12:32 +08:00
|
|
|
rc = __cxl_memdev_ioctl(cxlmd, cmd, arg);
|
|
|
|
up_read(&cxl_memdev_rwsem);
|
|
|
|
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int cxl_memdev_open(struct inode *inode, struct file *file)
|
|
|
|
{
|
|
|
|
struct cxl_memdev *cxlmd =
|
|
|
|
container_of(inode->i_cdev, typeof(*cxlmd), cdev);
|
|
|
|
|
|
|
|
get_device(&cxlmd->dev);
|
|
|
|
file->private_data = cxlmd;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int cxl_memdev_release_file(struct inode *inode, struct file *file)
|
|
|
|
{
|
|
|
|
struct cxl_memdev *cxlmd =
|
|
|
|
container_of(inode->i_cdev, typeof(*cxlmd), cdev);
|
|
|
|
|
|
|
|
put_device(&cxlmd->dev);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct file_operations cxl_memdev_fops = {
|
|
|
|
.owner = THIS_MODULE,
|
|
|
|
.unlocked_ioctl = cxl_memdev_ioctl,
|
|
|
|
.open = cxl_memdev_open,
|
|
|
|
.release = cxl_memdev_release_file,
|
|
|
|
.compat_ioctl = compat_ptr_ioctl,
|
|
|
|
.llseek = noop_llseek,
|
|
|
|
};
|
|
|
|
|
2021-11-03 04:29:01 +08:00
|
|
|
struct cxl_memdev *devm_cxl_add_memdev(struct cxl_dev_state *cxlds)
|
2021-08-03 01:30:05 +08:00
|
|
|
{
|
|
|
|
struct cxl_memdev *cxlmd;
|
|
|
|
struct device *dev;
|
|
|
|
struct cdev *cdev;
|
|
|
|
int rc;
|
|
|
|
|
2021-11-03 04:29:01 +08:00
|
|
|
cxlmd = cxl_memdev_alloc(cxlds, &cxl_memdev_fops);
|
2021-08-03 01:30:05 +08:00
|
|
|
if (IS_ERR(cxlmd))
|
|
|
|
return cxlmd;
|
|
|
|
|
|
|
|
dev = &cxlmd->dev;
|
|
|
|
rc = dev_set_name(dev, "mem%d", cxlmd->id);
|
|
|
|
if (rc)
|
|
|
|
goto err;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Activate ioctl operations, no cxl_memdev_rwsem manipulation
|
|
|
|
* needed as this is ordered with cdev_add() publishing the device.
|
|
|
|
*/
|
2021-11-03 04:29:01 +08:00
|
|
|
cxlmd->cxlds = cxlds;
|
2022-11-30 01:48:59 +08:00
|
|
|
cxlds->cxlmd = cxlmd;
|
2021-08-03 01:30:05 +08:00
|
|
|
|
|
|
|
cdev = &cxlmd->cdev;
|
|
|
|
rc = cdev_device_add(cdev, dev);
|
|
|
|
if (rc)
|
|
|
|
goto err;
|
|
|
|
|
2021-11-03 04:29:01 +08:00
|
|
|
rc = devm_add_action_or_reset(cxlds->dev, cxl_memdev_unregister, cxlmd);
|
2021-08-03 01:30:05 +08:00
|
|
|
if (rc)
|
|
|
|
return ERR_PTR(rc);
|
|
|
|
return cxlmd;
|
|
|
|
|
|
|
|
err:
|
|
|
|
/*
|
|
|
|
* The cdev was briefly live, shutdown any ioctl operations that
|
|
|
|
* saw that state.
|
|
|
|
*/
|
2021-09-09 13:12:32 +08:00
|
|
|
cxl_memdev_shutdown(dev);
|
2021-08-03 01:30:05 +08:00
|
|
|
put_device(dev);
|
|
|
|
return ERR_PTR(rc);
|
|
|
|
}
|
2021-11-13 08:32:58 +08:00
|
|
|
EXPORT_SYMBOL_NS_GPL(devm_cxl_add_memdev, CXL);
|
2021-08-03 01:30:05 +08:00
|
|
|
|
|
|
|
__init int cxl_memdev_init(void)
|
|
|
|
{
|
|
|
|
dev_t devt;
|
|
|
|
int rc;
|
|
|
|
|
|
|
|
rc = alloc_chrdev_region(&devt, 0, CXL_MEM_MAX_DEVS, "cxl");
|
|
|
|
if (rc)
|
|
|
|
return rc;
|
|
|
|
|
|
|
|
cxl_mem_major = MAJOR(devt);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
void cxl_memdev_exit(void)
|
|
|
|
{
|
|
|
|
unregister_chrdev_region(MKDEV(cxl_mem_major, 0), CXL_MEM_MAX_DEVS);
|
|
|
|
}
|