irqchip: add basic infrastructure
With the recent creation of the drivers/irqchip/ directory, it is
desirable to move irq controller drivers here. At the moment, the only
driver here is irq-bcm2835, the driver for the irq controller found in
the ARM BCM2835 SoC, present in Rasberry Pi systems. This irq
controller driver was exporting its initialization function and its
irq handling function through a header file in
<linux/irqchip/bcm2835.h>.
When proposing to also move another irq controller driver in
drivers/irqchip, Rob Herring raised the very valid point that moving
things to drivers/irqchip was good in order to remove more stuff from
arch/arm, but if it means adding gazillions of headers files in
include/linux/irqchip/, it would not be very nice.
So, upon the suggestion of Rob Herring and Arnd Bergmann, this commit
introduces a small infrastructure that defines a central
irqchip_init() function in drivers/irqchip/irqchip.c, which is meant
to be called as the ->init_irq() callback of ARM platforms. This
function calls of_irq_init() with an array of match strings and init
functions generated from a special linker section.
Note that the irq controller driver initialization function is
responsible for setting the global handle_arch_irq() variable, so that
ARM platforms no longer have to define the ->handle_irq field in their
DT_MACHINE structure.
A global header, <linux/irqchip.h> is also added to expose the single
irqchip_init() function to the reset of the kernel.
A further commit moves the BCM2835 irq controller driver to this new
small infrastructure, therefore removing the include/linux/irqchip/
directory.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Stephen Warren <swarren@wwwdotorg.org>
Reviewed-by: Rob Herring <rob.herring@calxeda.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
[rob.herring: reword commit message to reflect use of linker sections.]
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
2012-11-21 06:00:52 +08:00
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config IRQCHIP
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def_bool y
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depends on OF_IRQ
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2012-11-21 11:21:40 +08:00
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config ARM_GIC
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bool
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select IRQ_DOMAIN
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2014-11-25 16:04:19 +08:00
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select IRQ_DOMAIN_HIERARCHY
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2012-11-21 11:21:40 +08:00
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select MULTI_IRQ_HANDLER
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2015-12-18 17:44:53 +08:00
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config ARM_GIC_MAX_NR
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int
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default 2 if ARCH_REALVIEW
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default 1
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2014-11-26 02:47:22 +08:00
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config ARM_GIC_V2M
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bool
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depends on ARM_GIC
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depends on PCI && PCI_MSI
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select PCI_MSI_IRQ_DOMAIN
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2012-11-21 11:21:40 +08:00
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config GIC_NON_BANKED
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bool
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2014-06-30 23:01:31 +08:00
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config ARM_GIC_V3
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bool
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select IRQ_DOMAIN
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select MULTI_IRQ_HANDLER
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2014-11-24 22:35:09 +08:00
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select IRQ_DOMAIN_HIERARCHY
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2016-04-11 16:57:54 +08:00
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select PARTITION_PERCPU
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2014-06-30 23:01:31 +08:00
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2014-11-24 22:35:19 +08:00
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config ARM_GIC_V3_ITS
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bool
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select PCI_MSI_IRQ_DOMAIN
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2014-06-30 23:01:31 +08:00
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2013-06-26 15:18:48 +08:00
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config ARM_NVIC
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bool
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select IRQ_DOMAIN
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2015-05-16 17:44:16 +08:00
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select IRQ_DOMAIN_HIERARCHY
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2013-06-26 15:18:48 +08:00
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select GENERIC_IRQ_CHIP
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2012-10-28 06:25:26 +08:00
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config ARM_VIC
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bool
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select IRQ_DOMAIN
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select MULTI_IRQ_HANDLER
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config ARM_VIC_NR
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int
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default 4 if ARCH_S5PV210
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default 2
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depends on ARM_VIC
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help
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The maximum number of VICs available in the system, for
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power management.
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2016-02-10 22:46:56 +08:00
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config ARMADA_370_XP_IRQ
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bool
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select GENERIC_IRQ_CHIP
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2016-02-10 22:46:57 +08:00
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select PCI_MSI_IRQ_DOMAIN if PCI_MSI
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2016-02-10 22:46:56 +08:00
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2016-02-19 23:22:44 +08:00
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config ALPINE_MSI
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bool
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depends on PCI && PCI_MSI
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select GENERIC_IRQ_CHIP
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select PCI_MSI_IRQ_DOMAIN
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2014-07-11 01:14:18 +08:00
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config ATMEL_AIC_IRQ
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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select MULTI_IRQ_HANDLER
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select SPARSE_IRQ
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config ATMEL_AIC5_IRQ
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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select MULTI_IRQ_HANDLER
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select SPARSE_IRQ
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2015-07-08 20:46:08 +08:00
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config I8259
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bool
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select IRQ_DOMAIN
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2015-11-22 22:30:14 +08:00
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config BCM6345_L1_IRQ
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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IRQCHIP: Add new driver for BCM7038-style level 1 interrupt controllers
This is the main peripheral IRQ controller on the BCM7xxx MIPS chips;
it has the following characteristics:
- 64 to 160+ level IRQs
- Atomic set/clear registers
- Reasonably predictable register layout (N status words, then N
mask status words, then N mask set words, then N mask clear words)
- SMP affinity supported on most systems
- Typically connected to MIPS IRQ 2,3,2,3 on CPUs 0,1,2,3
This driver registers one IRQ domain and one IRQ chip to cover all
instances of the block. Up to 4 instances of the block may appear, as
it supports 4-way IRQ affinity on BCM7435.
The same block exists on the ARM BCM7xxx chips, but typically the ARM GIC
is used instead. So this driver is primarily intended for MIPS STB chips.
Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: jaedon.shin@gmail.com
Cc: abrestic@chromium.org
Cc: tglx@linutronix.de
Cc: jason@lakedaemon.net
Cc: jogo@openwrt.org
Cc: arnd@arndb.de
Cc: computersforpeace@gmail.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8844/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-12-26 01:49:06 +08:00
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config BCM7038_L1_IRQ
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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2014-11-07 14:44:27 +08:00
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config BCM7120_L2_IRQ
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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2014-05-24 08:40:53 +08:00
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config BRCMSTB_L2_IRQ
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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2013-09-09 20:01:20 +08:00
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config DW_APB_ICTL
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bool
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2014-10-22 20:59:10 +08:00
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select GENERIC_IRQ_CHIP
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2013-09-09 20:01:20 +08:00
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select IRQ_DOMAIN
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2016-03-23 17:06:33 +08:00
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config HISILICON_IRQ_MBIGEN
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bool
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select ARM_GIC_V3
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select ARM_GIC_V3_ITS
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select GENERIC_MSI_IRQ_DOMAIN
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2013-04-22 22:43:50 +08:00
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config IMGPDC_IRQ
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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2015-05-27 00:20:06 +08:00
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config IRQ_MIPS_CPU
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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2014-02-02 16:07:46 +08:00
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config CLPS711X_IRQCHIP
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bool
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depends on ARCH_CLPS711X
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select IRQ_DOMAIN
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select MULTI_IRQ_HANDLER
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select SPARSE_IRQ
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default y
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2014-05-27 04:31:42 +08:00
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config OR1K_PIC
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bool
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select IRQ_DOMAIN
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2014-09-16 05:15:02 +08:00
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config OMAP_IRQCHIP
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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2013-06-07 00:27:09 +08:00
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config ORION_IRQCHIP
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bool
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select IRQ_DOMAIN
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select MULTI_IRQ_HANDLER
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2016-01-14 09:15:35 +08:00
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config PIC32_EVIC
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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2013-02-18 22:28:34 +08:00
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config RENESAS_INTC_IRQPIN
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bool
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select IRQ_DOMAIN
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2013-02-27 16:15:01 +08:00
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config RENESAS_IRQC
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bool
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2015-09-28 17:42:37 +08:00
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select GENERIC_IRQ_CHIP
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2013-02-27 16:15:01 +08:00
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select IRQ_DOMAIN
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2015-02-18 23:13:58 +08:00
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config ST_IRQCHIP
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bool
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select REGMAP
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select MFD_SYSCON
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help
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Enables SysCfg Controlled IRQs on STi based platforms.
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2016-01-21 02:07:17 +08:00
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config TANGO_IRQ
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bool
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select IRQ_DOMAIN
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select GENERIC_IRQ_CHIP
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2013-06-26 00:29:57 +08:00
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config TB10X_IRQC
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bool
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select IRQ_DOMAIN
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select GENERIC_IRQ_CHIP
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2015-12-22 04:11:23 +08:00
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config TS4800_IRQ
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tristate "TS-4800 IRQ controller"
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select IRQ_DOMAIN
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2016-01-26 06:24:17 +08:00
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depends on HAS_IOMEM
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2016-02-09 18:19:20 +08:00
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depends on SOC_IMX51 || COMPILE_TEST
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2015-12-22 04:11:23 +08:00
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help
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Support for the TS-4800 FPGA IRQ controller
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2012-11-01 05:04:31 +08:00
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config VERSATILE_FPGA_IRQ
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bool
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select IRQ_DOMAIN
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config VERSATILE_FPGA_IRQ_NR
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int
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default 4
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depends on VERSATILE_FPGA_IRQ
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2013-12-01 16:04:57 +08:00
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config XTENSA_MX
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bool
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select IRQ_DOMAIN
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2013-12-03 18:27:23 +08:00
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config IRQ_CROSSBAR
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bool
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help
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2014-09-18 11:09:42 +08:00
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Support for a CROSSBAR ip that precedes the main interrupt controller.
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2013-12-03 18:27:23 +08:00
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The primary irqchip invokes the crossbar's callback which inturn allocates
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a free irq and configures the IP. Thus the peripheral interrupts are
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routed to one of the free irqchip interrupt lines.
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2014-07-23 22:40:30 +08:00
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config KEYSTONE_IRQ
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tristate "Keystone 2 IRQ controller IP"
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depends on ARCH_KEYSTONE
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help
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Support for Texas Instruments Keystone 2 IRQ controller IP which
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is part of the Keystone 2 IPC mechanism
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2014-09-19 05:47:19 +08:00
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config MIPS_GIC
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bool
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2015-12-08 21:20:28 +08:00
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select GENERIC_IRQ_IPI
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2015-12-08 21:20:23 +08:00
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select IRQ_DOMAIN_HIERARCHY
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2014-09-19 05:47:19 +08:00
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select MIPS_CM
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2015-05-10 01:30:47 +08:00
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2015-05-24 23:11:31 +08:00
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config INGENIC_IRQ
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bool
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depends on MACH_INGENIC
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default y
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2015-06-28 03:44:34 +08:00
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2015-05-10 01:30:47 +08:00
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config RENESAS_H8300H_INTC
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bool
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select IRQ_DOMAIN
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config RENESAS_H8S_INTC
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bool
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2015-06-28 03:44:34 +08:00
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select IRQ_DOMAIN
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2015-08-25 03:04:15 +08:00
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config IMX_GPCV2
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bool
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select IRQ_DOMAIN
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help
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Enables the wakeup IRQs for IMX platforms with GPCv2 block
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2015-10-13 03:15:34 +08:00
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config IRQ_MXS
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def_bool y if MACH_ASM9260 || ARCH_MXS
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select IRQ_DOMAIN
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select STMP_DEVICE
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2016-02-19 21:34:43 +08:00
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config MVEBU_ODMI
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bool
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select GENERIC_MSI_IRQ_DOMAIN
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irqchip: Add per-cpu interrupt partitioning library
We've unfortunately started seeing a situation where percpu interrupts
are partitioned in the system: one arbitrary set of CPUs has an
interrupt connected to a type of device, while another disjoint
set of CPUs has the same interrupt connected to another type of device.
This makes it impossible to have a device driver requesting this interrupt
using the current percpu-interrupt abstraction, as the same interrupt number
is now potentially claimed by at least two drivers, and we forbid interrupt
sharing on per-cpu interrupt.
A solution to this is to turn things upside down. Let's assume that our
system describes all the possible partitions for a given interrupt, and
give each of them a unique identifier. It is then possible to create
a namespace where the affinity identifier itself is a form of interrupt
number. At this point, it becomes easy to implement a set of partitions
as a cascaded irqchip, each affinity identifier being the HW irq.
This allows us to keep a number of nice properties:
- Each partition results in a separate percpu-interrupt (with a restrictied
affinity), which keeps drivers happy.
- Because the underlying interrupt is still per-cpu, the overhead of
the indirection can be kept pretty minimal.
- The core code can ignore most of that crap.
For that purpose, we implement a small library that deals with some of
the boilerplate code, relying on platform-specific drivers to provide
a description of the affinity sets and a set of callbacks.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Rob Herring <robh+dt@kernel.org>
Link: http://lkml.kernel.org/r/1460365075-7316-4-git-send-email-marc.zyngier@arm.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2016-04-11 16:57:53 +08:00
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2016-03-23 19:08:20 +08:00
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|
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config LS_SCFG_MSI
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def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
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depends on PCI && PCI_MSI
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select PCI_MSI_IRQ_DOMAIN
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irqchip: Add per-cpu interrupt partitioning library
We've unfortunately started seeing a situation where percpu interrupts
are partitioned in the system: one arbitrary set of CPUs has an
interrupt connected to a type of device, while another disjoint
set of CPUs has the same interrupt connected to another type of device.
This makes it impossible to have a device driver requesting this interrupt
using the current percpu-interrupt abstraction, as the same interrupt number
is now potentially claimed by at least two drivers, and we forbid interrupt
sharing on per-cpu interrupt.
A solution to this is to turn things upside down. Let's assume that our
system describes all the possible partitions for a given interrupt, and
give each of them a unique identifier. It is then possible to create
a namespace where the affinity identifier itself is a form of interrupt
number. At this point, it becomes easy to implement a set of partitions
as a cascaded irqchip, each affinity identifier being the HW irq.
This allows us to keep a number of nice properties:
- Each partition results in a separate percpu-interrupt (with a restrictied
affinity), which keeps drivers happy.
- Because the underlying interrupt is still per-cpu, the overhead of
the indirection can be kept pretty minimal.
- The core code can ignore most of that crap.
For that purpose, we implement a small library that deals with some of
the boilerplate code, relying on platform-specific drivers to provide
a description of the affinity sets and a set of callbacks.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Rob Herring <robh+dt@kernel.org>
Link: http://lkml.kernel.org/r/1460365075-7316-4-git-send-email-marc.zyngier@arm.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2016-04-11 16:57:53 +08:00
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config PARTITION_PERCPU
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bool
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2016-05-20 00:46:18 +08:00
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2015-10-29 06:26:22 +08:00
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config EZNPS_GIC
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bool "NPS400 Global Interrupt Manager (GIM)"
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2016-05-13 05:03:35 +08:00
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depends on ARC || (COMPILE_TEST && !64BIT)
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2015-10-29 06:26:22 +08:00
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select IRQ_DOMAIN
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help
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Support the EZchip NPS400 global interrupt controller
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