2020-06-22 20:41:10 +08:00
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// SPDX-License-Identifier: GPL-2.0-only
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// Copyright (c) 2020, The Linux Foundation. All rights reserved.
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#include <linux/module.h>
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#include <linux/of_irq.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/regulator/driver.h>
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#include <linux/regulator/of_regulator.h>
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#define REG_PERPH_TYPE 0x04
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#define QCOM_LAB_TYPE 0x24
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#define QCOM_IBB_TYPE 0x20
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#define PMI8998_LAB_REG_BASE 0xde00
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#define PMI8998_IBB_REG_BASE 0xdc00
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#define REG_LABIBB_STATUS1 0x08
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2021-01-14 03:42:08 +08:00
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#define REG_LABIBB_VOLTAGE 0x41
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#define LABIBB_VOLTAGE_OVERRIDE_EN BIT(7)
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#define LAB_VOLTAGE_SET_MASK GENMASK(3, 0)
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#define IBB_VOLTAGE_SET_MASK GENMASK(5, 0)
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2020-06-22 20:41:10 +08:00
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#define REG_LABIBB_ENABLE_CTL 0x46
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#define LABIBB_STATUS1_VREG_OK_BIT BIT(7)
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#define LABIBB_CONTROL_ENABLE BIT(7)
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2021-01-20 01:44:17 +08:00
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#define REG_LABIBB_PD_CTL 0x47
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#define LAB_PD_CTL_MASK GENMASK(1, 0)
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#define IBB_PD_CTL_MASK (BIT(0) | BIT(7))
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#define LAB_PD_CTL_STRONG_PULL BIT(0)
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#define IBB_PD_CTL_HALF_STRENGTH BIT(0)
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#define IBB_PD_CTL_EN BIT(7)
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2021-01-20 01:44:16 +08:00
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#define REG_LABIBB_CURRENT_LIMIT 0x4b
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#define LAB_CURRENT_LIMIT_MASK GENMASK(2, 0)
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#define IBB_CURRENT_LIMIT_MASK GENMASK(4, 0)
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#define LAB_CURRENT_LIMIT_OVERRIDE_EN BIT(3)
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#define LABIBB_CURRENT_LIMIT_EN BIT(7)
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2021-01-20 01:44:17 +08:00
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#define REG_IBB_PWRUP_PWRDN_CTL_1 0x58
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#define IBB_CTL_1_DISCHARGE_EN BIT(2)
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#define REG_LABIBB_SOFT_START_CTL 0x5f
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#define REG_LABIBB_SEC_ACCESS 0xd0
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#define LABIBB_SEC_UNLOCK_CODE 0xa5
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2020-06-22 20:41:10 +08:00
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#define LAB_ENABLE_CTL_MASK BIT(7)
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#define IBB_ENABLE_CTL_MASK (BIT(7) | BIT(6))
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#define LABIBB_OFF_ON_DELAY 1000
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#define LAB_ENABLE_TIME (LABIBB_OFF_ON_DELAY * 2)
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#define IBB_ENABLE_TIME (LABIBB_OFF_ON_DELAY * 10)
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#define LABIBB_POLL_ENABLED_TIME 1000
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2021-01-20 01:44:16 +08:00
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struct labibb_current_limits {
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u32 uA_min;
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u32 uA_step;
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u8 ovr_val;
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};
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2020-06-22 20:41:10 +08:00
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struct labibb_regulator {
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struct regulator_desc desc;
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struct device *dev;
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struct regmap *regmap;
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struct regulator_dev *rdev;
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struct labibb_current_limits uA_limits;
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u16 base;
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u8 type;
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u8 dischg_sel;
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u8 soft_start_sel;
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2020-06-22 20:41:10 +08:00
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};
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struct labibb_regulator_data {
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const char *name;
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u8 type;
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u16 base;
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const struct regulator_desc *desc;
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};
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2021-01-20 01:44:16 +08:00
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static int qcom_labibb_set_current_limit(struct regulator_dev *rdev,
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int min_uA, int max_uA)
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{
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struct labibb_regulator *vreg = rdev_get_drvdata(rdev);
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struct regulator_desc *desc = &vreg->desc;
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struct labibb_current_limits *lim = &vreg->uA_limits;
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u32 mask, val;
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int i, ret, sel = -1;
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if (min_uA < lim->uA_min || max_uA < lim->uA_min)
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return -EINVAL;
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for (i = 0; i < desc->n_current_limits; i++) {
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int uA_limit = (lim->uA_step * i) + lim->uA_min;
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if (max_uA >= uA_limit && min_uA <= uA_limit)
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sel = i;
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}
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if (sel < 0)
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return -EINVAL;
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/* Current limit setting needs secure access */
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ret = regmap_write(vreg->regmap, vreg->base + REG_LABIBB_SEC_ACCESS,
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LABIBB_SEC_UNLOCK_CODE);
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if (ret)
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return ret;
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mask = desc->csel_mask | lim->ovr_val;
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mask |= LABIBB_CURRENT_LIMIT_EN;
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val = (u32)sel | lim->ovr_val;
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val |= LABIBB_CURRENT_LIMIT_EN;
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return regmap_update_bits(vreg->regmap, desc->csel_reg, mask, val);
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}
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static int qcom_labibb_get_current_limit(struct regulator_dev *rdev)
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{
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struct labibb_regulator *vreg = rdev_get_drvdata(rdev);
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struct regulator_desc *desc = &vreg->desc;
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struct labibb_current_limits *lim = &vreg->uA_limits;
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unsigned int cur_step;
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int ret;
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ret = regmap_read(vreg->regmap, desc->csel_reg, &cur_step);
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if (ret)
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return ret;
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cur_step &= desc->csel_mask;
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return (cur_step * lim->uA_step) + lim->uA_min;
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}
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2021-01-20 01:44:17 +08:00
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static int qcom_labibb_set_soft_start(struct regulator_dev *rdev)
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{
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struct labibb_regulator *vreg = rdev_get_drvdata(rdev);
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u32 val = 0;
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if (vreg->type == QCOM_IBB_TYPE)
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val = vreg->dischg_sel;
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else
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val = vreg->soft_start_sel;
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return regmap_write(rdev->regmap, rdev->desc->soft_start_reg, val);
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}
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static int qcom_labibb_get_table_sel(const int *table, int sz, u32 value)
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{
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int i;
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for (i = 0; i < sz; i++)
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if (table[i] == value)
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return i;
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return -EINVAL;
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}
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/* IBB discharge resistor values in KOhms */
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static const int dischg_resistor_values[] = { 300, 64, 32, 16 };
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/* Soft start time in microseconds */
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static const int soft_start_values[] = { 200, 400, 600, 800 };
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static int qcom_labibb_of_parse_cb(struct device_node *np,
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const struct regulator_desc *desc,
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struct regulator_config *config)
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{
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struct labibb_regulator *vreg = config->driver_data;
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u32 dischg_kohms, soft_start_time;
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int ret;
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ret = of_property_read_u32(np, "qcom,discharge-resistor-kohms",
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&dischg_kohms);
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if (ret)
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dischg_kohms = 300;
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ret = qcom_labibb_get_table_sel(dischg_resistor_values,
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ARRAY_SIZE(dischg_resistor_values),
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dischg_kohms);
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if (ret < 0)
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return ret;
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vreg->dischg_sel = (u8)ret;
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ret = of_property_read_u32(np, "qcom,soft-start-us",
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&soft_start_time);
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if (ret)
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soft_start_time = 200;
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ret = qcom_labibb_get_table_sel(soft_start_values,
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ARRAY_SIZE(soft_start_values),
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soft_start_time);
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if (ret < 0)
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return ret;
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vreg->soft_start_sel = (u8)ret;
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return 0;
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}
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2020-10-01 00:26:02 +08:00
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static const struct regulator_ops qcom_labibb_ops = {
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.enable = regulator_enable_regmap,
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.disable = regulator_disable_regmap,
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.is_enabled = regulator_is_enabled_regmap,
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.set_voltage_sel = regulator_set_voltage_sel_regmap,
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.get_voltage_sel = regulator_get_voltage_sel_regmap,
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.list_voltage = regulator_list_voltage_linear,
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.map_voltage = regulator_map_voltage_linear,
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2021-01-20 01:44:17 +08:00
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.set_active_discharge = regulator_set_active_discharge_regmap,
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.set_pull_down = regulator_set_pull_down_regmap,
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.set_current_limit = qcom_labibb_set_current_limit,
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.get_current_limit = qcom_labibb_get_current_limit,
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.set_soft_start = qcom_labibb_set_soft_start,
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2020-06-22 20:41:10 +08:00
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};
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2020-10-01 00:26:02 +08:00
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static const struct regulator_desc pmi8998_lab_desc = {
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2020-06-22 20:41:10 +08:00
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.enable_mask = LAB_ENABLE_CTL_MASK,
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.enable_reg = (PMI8998_LAB_REG_BASE + REG_LABIBB_ENABLE_CTL),
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.enable_val = LABIBB_CONTROL_ENABLE,
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.enable_time = LAB_ENABLE_TIME,
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.poll_enabled_time = LABIBB_POLL_ENABLED_TIME,
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.soft_start_reg = (PMI8998_LAB_REG_BASE + REG_LABIBB_SOFT_START_CTL),
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.pull_down_reg = (PMI8998_LAB_REG_BASE + REG_LABIBB_PD_CTL),
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.pull_down_mask = LAB_PD_CTL_MASK,
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.pull_down_val_on = LAB_PD_CTL_STRONG_PULL,
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.vsel_reg = (PMI8998_LAB_REG_BASE + REG_LABIBB_VOLTAGE),
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.vsel_mask = LAB_VOLTAGE_SET_MASK,
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.apply_reg = (PMI8998_LAB_REG_BASE + REG_LABIBB_VOLTAGE),
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.apply_bit = LABIBB_VOLTAGE_OVERRIDE_EN,
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.csel_reg = (PMI8998_LAB_REG_BASE + REG_LABIBB_CURRENT_LIMIT),
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.csel_mask = LAB_CURRENT_LIMIT_MASK,
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.n_current_limits = 8,
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.off_on_delay = LABIBB_OFF_ON_DELAY,
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.owner = THIS_MODULE,
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.type = REGULATOR_VOLTAGE,
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.min_uV = 4600000,
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.uV_step = 100000,
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.n_voltages = 16,
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.ops = &qcom_labibb_ops,
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.of_parse_cb = qcom_labibb_of_parse_cb,
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2020-06-22 20:41:10 +08:00
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};
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2020-10-01 00:26:02 +08:00
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static const struct regulator_desc pmi8998_ibb_desc = {
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2020-06-22 20:41:10 +08:00
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.enable_mask = IBB_ENABLE_CTL_MASK,
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.enable_reg = (PMI8998_IBB_REG_BASE + REG_LABIBB_ENABLE_CTL),
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.enable_val = LABIBB_CONTROL_ENABLE,
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.enable_time = IBB_ENABLE_TIME,
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.poll_enabled_time = LABIBB_POLL_ENABLED_TIME,
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.soft_start_reg = (PMI8998_IBB_REG_BASE + REG_LABIBB_SOFT_START_CTL),
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.active_discharge_off = 0,
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.active_discharge_on = IBB_CTL_1_DISCHARGE_EN,
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.active_discharge_mask = IBB_CTL_1_DISCHARGE_EN,
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.active_discharge_reg = (PMI8998_IBB_REG_BASE + REG_IBB_PWRUP_PWRDN_CTL_1),
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.pull_down_reg = (PMI8998_IBB_REG_BASE + REG_LABIBB_PD_CTL),
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.pull_down_mask = IBB_PD_CTL_MASK,
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.pull_down_val_on = IBB_PD_CTL_HALF_STRENGTH | IBB_PD_CTL_EN,
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.vsel_reg = (PMI8998_IBB_REG_BASE + REG_LABIBB_VOLTAGE),
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.vsel_mask = IBB_VOLTAGE_SET_MASK,
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.apply_reg = (PMI8998_IBB_REG_BASE + REG_LABIBB_VOLTAGE),
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.apply_bit = LABIBB_VOLTAGE_OVERRIDE_EN,
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2021-01-20 01:44:16 +08:00
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.csel_reg = (PMI8998_IBB_REG_BASE + REG_LABIBB_CURRENT_LIMIT),
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.csel_mask = IBB_CURRENT_LIMIT_MASK,
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.n_current_limits = 32,
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2020-06-22 20:41:10 +08:00
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.off_on_delay = LABIBB_OFF_ON_DELAY,
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.owner = THIS_MODULE,
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.type = REGULATOR_VOLTAGE,
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.min_uV = 1400000,
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.uV_step = 100000,
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.n_voltages = 64,
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2020-06-22 20:41:10 +08:00
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.ops = &qcom_labibb_ops,
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2021-01-20 01:44:17 +08:00
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.of_parse_cb = qcom_labibb_of_parse_cb,
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2020-06-22 20:41:10 +08:00
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};
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static const struct labibb_regulator_data pmi8998_labibb_data[] = {
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{"lab", QCOM_LAB_TYPE, PMI8998_LAB_REG_BASE, &pmi8998_lab_desc},
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{"ibb", QCOM_IBB_TYPE, PMI8998_IBB_REG_BASE, &pmi8998_ibb_desc},
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{ },
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};
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static const struct of_device_id qcom_labibb_match[] = {
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{ .compatible = "qcom,pmi8998-lab-ibb", .data = &pmi8998_labibb_data},
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{ },
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};
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MODULE_DEVICE_TABLE(of, qcom_labibb_match);
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static int qcom_labibb_regulator_probe(struct platform_device *pdev)
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{
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struct labibb_regulator *vreg;
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struct device *dev = &pdev->dev;
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struct regulator_config cfg = {};
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const struct of_device_id *match;
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const struct labibb_regulator_data *reg_data;
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struct regmap *reg_regmap;
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unsigned int type;
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int ret;
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reg_regmap = dev_get_regmap(pdev->dev.parent, NULL);
|
|
|
|
if (!reg_regmap) {
|
|
|
|
dev_err(&pdev->dev, "Couldn't get parent's regmap\n");
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
|
|
|
|
match = of_match_device(qcom_labibb_match, &pdev->dev);
|
|
|
|
if (!match)
|
|
|
|
return -ENODEV;
|
|
|
|
|
|
|
|
for (reg_data = match->data; reg_data->name; reg_data++) {
|
|
|
|
|
|
|
|
/* Validate if the type of regulator is indeed
|
|
|
|
* what's mentioned in DT.
|
|
|
|
*/
|
|
|
|
ret = regmap_read(reg_regmap, reg_data->base + REG_PERPH_TYPE,
|
|
|
|
&type);
|
|
|
|
if (ret < 0) {
|
|
|
|
dev_err(dev,
|
|
|
|
"Peripheral type read failed ret=%d\n",
|
|
|
|
ret);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (WARN_ON((type != QCOM_LAB_TYPE) && (type != QCOM_IBB_TYPE)) ||
|
|
|
|
WARN_ON(type != reg_data->type))
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
vreg = devm_kzalloc(&pdev->dev, sizeof(*vreg),
|
|
|
|
GFP_KERNEL);
|
|
|
|
if (!vreg)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
vreg->regmap = reg_regmap;
|
|
|
|
vreg->dev = dev;
|
|
|
|
vreg->base = reg_data->base;
|
|
|
|
vreg->type = reg_data->type;
|
|
|
|
|
2021-01-20 01:44:16 +08:00
|
|
|
switch (vreg->type) {
|
|
|
|
case QCOM_LAB_TYPE:
|
|
|
|
/* LAB Limits: 200-1600mA */
|
|
|
|
vreg->uA_limits.uA_min = 200000;
|
|
|
|
vreg->uA_limits.uA_step = 200000;
|
|
|
|
vreg->uA_limits.ovr_val = LAB_CURRENT_LIMIT_OVERRIDE_EN;
|
|
|
|
break;
|
|
|
|
case QCOM_IBB_TYPE:
|
|
|
|
/* IBB Limits: 0-1550mA */
|
|
|
|
vreg->uA_limits.uA_min = 0;
|
|
|
|
vreg->uA_limits.uA_step = 50000;
|
|
|
|
vreg->uA_limits.ovr_val = 0; /* No override bit */
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2020-06-22 20:41:10 +08:00
|
|
|
memcpy(&vreg->desc, reg_data->desc, sizeof(vreg->desc));
|
|
|
|
vreg->desc.of_match = reg_data->name;
|
|
|
|
vreg->desc.name = reg_data->name;
|
|
|
|
|
|
|
|
cfg.dev = vreg->dev;
|
|
|
|
cfg.driver_data = vreg;
|
|
|
|
cfg.regmap = vreg->regmap;
|
|
|
|
|
|
|
|
vreg->rdev = devm_regulator_register(vreg->dev, &vreg->desc,
|
|
|
|
&cfg);
|
|
|
|
|
|
|
|
if (IS_ERR(vreg->rdev)) {
|
|
|
|
dev_err(dev, "qcom_labibb: error registering %s : %d\n",
|
|
|
|
reg_data->name, ret);
|
|
|
|
return PTR_ERR(vreg->rdev);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct platform_driver qcom_labibb_regulator_driver = {
|
|
|
|
.driver = {
|
|
|
|
.name = "qcom-lab-ibb-regulator",
|
|
|
|
.of_match_table = qcom_labibb_match,
|
|
|
|
},
|
|
|
|
.probe = qcom_labibb_regulator_probe,
|
|
|
|
};
|
|
|
|
module_platform_driver(qcom_labibb_regulator_driver);
|
|
|
|
|
|
|
|
MODULE_DESCRIPTION("Qualcomm labibb driver");
|
|
|
|
MODULE_AUTHOR("Nisha Kumari <nishakumari@codeaurora.org>");
|
|
|
|
MODULE_AUTHOR("Sumit Semwal <sumit.semwal@linaro.org>");
|
|
|
|
MODULE_LICENSE("GPL v2");
|