2021-03-29 19:17:46 +08:00
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.. SPDX-License-Identifier: GPL-2.0
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===========================================================================
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Driver for Synopsys DesignWare PCIe traffic generator (also known as xData)
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===========================================================================
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2021-04-10 22:52:59 +08:00
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Supported chips:
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Synopsys DesignWare PCIe prototype solution
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Datasheet:
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Not freely available
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Author:
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Gustavo Pimentel <gustavo.pimentel@synopsys.com>
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Description
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-----------
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2021-03-29 19:17:46 +08:00
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This driver should be used as a host-side (Root Complex) driver and Synopsys
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DesignWare prototype that includes this IP.
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2021-04-10 22:52:59 +08:00
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The dw-xdata-pcie driver can be used to enable/disable PCIe traffic
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2021-03-29 19:17:46 +08:00
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generator in either direction (mutual exclusion) besides allowing the
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PCIe link performance analysis.
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The interaction with this driver is done through the module parameter and
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can be changed in runtime. The driver outputs the requested command state
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2021-04-10 22:52:59 +08:00
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information to ``/var/log/kern.log`` or dmesg.
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Example
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-------
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Write TLPs traffic generation - Root Complex to Endpoint direction
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Generate traffic::
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# echo 1 > /sys/class/misc/dw-xdata-pcie.0/write
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Get link throughput in MB/s::
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# cat /sys/class/misc/dw-xdata-pcie.0/write
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204
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Stop traffic in any direction::
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# echo 0 > /sys/class/misc/dw-xdata-pcie.0/write
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Read TLPs traffic generation - Endpoint to Root Complex direction
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Generate traffic::
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# echo 1 > /sys/class/misc/dw-xdata-pcie.0/read
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Get link throughput in MB/s::
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# cat /sys/class/misc/dw-xdata-pcie.0/read
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199
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Stop traffic in any direction::
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# echo 0 > /sys/class/misc/dw-xdata-pcie.0/read
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