2019-02-21 11:16:19 +08:00
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// SPDX-License-Identifier: GPL-2.0
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/*
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* PCIe controller EP driver for Freescale Layerscape SoCs
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*
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* Copyright (C) 2018 NXP Semiconductor.
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*
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* Author: Xiaowei Bao <xiaowei.bao@nxp.com>
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/of_pci.h>
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#include <linux/of_platform.h>
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#include <linux/of_address.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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#include <linux/resource.h>
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#include "pcie-designware.h"
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2020-09-18 16:00:21 +08:00
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#define to_ls_pcie_ep(x) dev_get_drvdata((x)->dev)
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struct ls_pcie_ep_drvdata {
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u32 func_offset;
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const struct dw_pcie_ep_ops *ops;
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const struct dw_pcie_ops *dw_pcie_ops;
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2019-02-21 11:16:19 +08:00
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};
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2020-09-18 16:00:21 +08:00
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struct ls_pcie_ep {
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struct dw_pcie *pci;
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struct pci_epc_features *ls_epc;
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const struct ls_pcie_ep_drvdata *drvdata;
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};
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2019-02-21 11:16:19 +08:00
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static const struct pci_epc_features*
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ls_pcie_ep_get_features(struct dw_pcie_ep *ep)
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{
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2020-09-18 16:00:19 +08:00
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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struct ls_pcie_ep *pcie = to_ls_pcie_ep(pci);
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return pcie->ls_epc;
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2019-02-21 11:16:19 +08:00
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}
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static void ls_pcie_ep_init(struct dw_pcie_ep *ep)
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{
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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2020-09-18 16:00:19 +08:00
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struct ls_pcie_ep *pcie = to_ls_pcie_ep(pci);
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struct dw_pcie_ep_func *ep_func;
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2019-02-21 11:16:19 +08:00
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enum pci_barno bar;
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2020-09-18 16:00:19 +08:00
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ep_func = dw_pcie_ep_get_func_from_ep(ep, 0);
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if (!ep_func)
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return;
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2019-09-28 07:43:08 +08:00
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for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)
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2019-02-21 11:16:19 +08:00
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dw_pcie_ep_reset_bar(pci, bar);
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2020-09-18 16:00:19 +08:00
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pcie->ls_epc->msi_capable = ep_func->msi_cap ? true : false;
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pcie->ls_epc->msix_capable = ep_func->msix_cap ? true : false;
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2019-02-21 11:16:19 +08:00
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}
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static int ls_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
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2020-09-18 16:00:18 +08:00
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enum pci_epc_irq_type type, u16 interrupt_num)
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2019-02-21 11:16:19 +08:00
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{
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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switch (type) {
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case PCI_EPC_IRQ_LEGACY:
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return dw_pcie_ep_raise_legacy_irq(ep, func_no);
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case PCI_EPC_IRQ_MSI:
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return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
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case PCI_EPC_IRQ_MSIX:
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2020-09-18 16:00:20 +08:00
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return dw_pcie_ep_raise_msix_irq_doorbell(ep, func_no,
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interrupt_num);
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2019-02-21 11:16:19 +08:00
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default:
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dev_err(pci->dev, "UNKNOWN IRQ type\n");
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return -EINVAL;
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}
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}
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2020-09-18 16:00:21 +08:00
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static unsigned int ls_pcie_ep_func_conf_select(struct dw_pcie_ep *ep,
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u8 func_no)
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{
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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struct ls_pcie_ep *pcie = to_ls_pcie_ep(pci);
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WARN_ON(func_no && !pcie->drvdata->func_offset);
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return pcie->drvdata->func_offset * func_no;
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}
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static const struct dw_pcie_ep_ops ls_pcie_ep_ops = {
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2019-02-21 11:16:19 +08:00
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.ep_init = ls_pcie_ep_init,
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.raise_irq = ls_pcie_ep_raise_irq,
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.get_features = ls_pcie_ep_get_features,
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2020-09-18 16:00:21 +08:00
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.func_conf_select = ls_pcie_ep_func_conf_select,
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};
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static const struct ls_pcie_ep_drvdata ls1_ep_drvdata = {
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.ops = &ls_pcie_ep_ops,
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};
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static const struct ls_pcie_ep_drvdata ls2_ep_drvdata = {
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.func_offset = 0x20000,
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.ops = &ls_pcie_ep_ops,
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};
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2020-10-26 13:14:48 +08:00
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static const struct ls_pcie_ep_drvdata lx2_ep_drvdata = {
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.func_offset = 0x8000,
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.ops = &ls_pcie_ep_ops,
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};
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2020-09-18 16:00:21 +08:00
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static const struct of_device_id ls_pcie_ep_of_match[] = {
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{ .compatible = "fsl,ls1046a-pcie-ep", .data = &ls1_ep_drvdata },
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{ .compatible = "fsl,ls1088a-pcie-ep", .data = &ls2_ep_drvdata },
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{ .compatible = "fsl,ls2088a-pcie-ep", .data = &ls2_ep_drvdata },
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2020-10-26 13:14:48 +08:00
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{ .compatible = "fsl,lx2160ar2-pcie-ep", .data = &lx2_ep_drvdata },
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2020-09-18 16:00:21 +08:00
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{ },
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2019-02-21 11:16:19 +08:00
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};
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static int __init ls_pcie_ep_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct dw_pcie *pci;
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struct ls_pcie_ep *pcie;
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2020-09-18 16:00:19 +08:00
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struct pci_epc_features *ls_epc;
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2019-02-21 11:16:19 +08:00
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struct resource *dbi_base;
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pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
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if (!pcie)
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return -ENOMEM;
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pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
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if (!pci)
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return -ENOMEM;
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2020-09-18 16:00:19 +08:00
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ls_epc = devm_kzalloc(dev, sizeof(*ls_epc), GFP_KERNEL);
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if (!ls_epc)
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return -ENOMEM;
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2020-09-18 16:00:21 +08:00
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pcie->drvdata = of_device_get_match_data(dev);
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2019-02-21 11:16:19 +08:00
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pci->dev = dev;
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2020-09-18 16:00:21 +08:00
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pci->ops = pcie->drvdata->dw_pcie_ops;
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2019-02-21 11:16:19 +08:00
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2021-03-11 11:37:45 +08:00
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ls_epc->bar_fixed_64bit = (1 << BAR_2) | (1 << BAR_4);
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2020-09-18 16:00:19 +08:00
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2020-09-18 16:00:21 +08:00
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pcie->pci = pci;
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2020-09-18 16:00:19 +08:00
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pcie->ls_epc = ls_epc;
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2020-09-18 16:00:21 +08:00
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dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
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pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_base);
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if (IS_ERR(pci->dbi_base))
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return PTR_ERR(pci->dbi_base);
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2020-11-06 05:11:46 +08:00
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pci->ep.ops = &ls_pcie_ep_ops;
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2020-09-18 16:00:21 +08:00
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2019-02-21 11:16:19 +08:00
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platform_set_drvdata(pdev, pcie);
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2020-11-06 05:11:46 +08:00
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return dw_pcie_ep_init(&pci->ep);
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2019-02-21 11:16:19 +08:00
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}
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static struct platform_driver ls_pcie_ep_driver = {
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.driver = {
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.name = "layerscape-pcie-ep",
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.of_match_table = ls_pcie_ep_of_match,
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.suppress_bind_attrs = true,
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},
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};
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builtin_platform_driver_probe(ls_pcie_ep_driver, ls_pcie_ep_probe);
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