2022-06-07 22:11:32 +08:00
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// SPDX-License-Identifier: GPL-2.0-only
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2010-12-09 23:13:46 +08:00
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/*
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* OMAP3 OPP table definitions.
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*
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2020-07-19 18:30:33 +08:00
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* Copyright (C) 2009-2010 Texas Instruments Incorporated - https://www.ti.com/
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2010-12-09 23:13:46 +08:00
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* Nishanth Menon
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* Kevin Hilman
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2011-03-11 13:17:45 +08:00
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* Copyright (C) 2010-2011 Nokia Corporation.
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2010-12-09 23:13:46 +08:00
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* Eduardo Valentin
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2011-03-11 13:17:45 +08:00
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* Paul Walmsley
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2010-12-09 23:13:46 +08:00
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*/
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#include <linux/module.h>
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2012-10-06 04:25:59 +08:00
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#include "soc.h"
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2011-03-11 13:17:45 +08:00
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#include "control.h"
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2010-12-09 23:13:46 +08:00
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#include "omap_opp_data.h"
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2011-01-06 04:49:35 +08:00
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#include "pm.h"
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2010-12-09 23:13:46 +08:00
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2011-03-11 13:17:45 +08:00
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/* 34xx */
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/* VDD1 */
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#define OMAP3430_VDD_MPU_OPP1_UV 975000
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#define OMAP3430_VDD_MPU_OPP2_UV 1075000
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#define OMAP3430_VDD_MPU_OPP3_UV 1200000
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#define OMAP3430_VDD_MPU_OPP4_UV 1270000
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#define OMAP3430_VDD_MPU_OPP5_UV 1350000
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struct omap_volt_data omap34xx_vddmpu_volt_data[] = {
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VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP1_UV, OMAP343X_CONTROL_FUSE_OPP1_VDD1, 0xf4, 0x0c),
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VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP2_UV, OMAP343X_CONTROL_FUSE_OPP2_VDD1, 0xf4, 0x0c),
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VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP3_UV, OMAP343X_CONTROL_FUSE_OPP3_VDD1, 0xf9, 0x18),
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VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP4_UV, OMAP343X_CONTROL_FUSE_OPP4_VDD1, 0xf9, 0x18),
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VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP5_UV, OMAP343X_CONTROL_FUSE_OPP5_VDD1, 0xf9, 0x18),
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VOLT_DATA_DEFINE(0, 0, 0, 0),
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};
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/* VDD2 */
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#define OMAP3430_VDD_CORE_OPP1_UV 975000
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#define OMAP3430_VDD_CORE_OPP2_UV 1050000
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#define OMAP3430_VDD_CORE_OPP3_UV 1150000
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struct omap_volt_data omap34xx_vddcore_volt_data[] = {
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VOLT_DATA_DEFINE(OMAP3430_VDD_CORE_OPP1_UV, OMAP343X_CONTROL_FUSE_OPP1_VDD2, 0xf4, 0x0c),
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VOLT_DATA_DEFINE(OMAP3430_VDD_CORE_OPP2_UV, OMAP343X_CONTROL_FUSE_OPP2_VDD2, 0xf4, 0x0c),
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VOLT_DATA_DEFINE(OMAP3430_VDD_CORE_OPP3_UV, OMAP343X_CONTROL_FUSE_OPP3_VDD2, 0xf9, 0x18),
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VOLT_DATA_DEFINE(0, 0, 0, 0),
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};
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/* 36xx */
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/* VDD1 */
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#define OMAP3630_VDD_MPU_OPP50_UV 1012500
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#define OMAP3630_VDD_MPU_OPP100_UV 1200000
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#define OMAP3630_VDD_MPU_OPP120_UV 1325000
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#define OMAP3630_VDD_MPU_OPP1G_UV 1375000
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struct omap_volt_data omap36xx_vddmpu_volt_data[] = {
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VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP50_UV, OMAP3630_CONTROL_FUSE_OPP50_VDD1, 0xf4, 0x0c),
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VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP100_UV, OMAP3630_CONTROL_FUSE_OPP100_VDD1, 0xf9, 0x16),
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VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP120_UV, OMAP3630_CONTROL_FUSE_OPP120_VDD1, 0xfa, 0x23),
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VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP1G_UV, OMAP3630_CONTROL_FUSE_OPP1G_VDD1, 0xfa, 0x27),
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VOLT_DATA_DEFINE(0, 0, 0, 0),
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};
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/* VDD2 */
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#define OMAP3630_VDD_CORE_OPP50_UV 1000000
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#define OMAP3630_VDD_CORE_OPP100_UV 1200000
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struct omap_volt_data omap36xx_vddcore_volt_data[] = {
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VOLT_DATA_DEFINE(OMAP3630_VDD_CORE_OPP50_UV, OMAP3630_CONTROL_FUSE_OPP50_VDD2, 0xf4, 0x0c),
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VOLT_DATA_DEFINE(OMAP3630_VDD_CORE_OPP100_UV, OMAP3630_CONTROL_FUSE_OPP100_VDD2, 0xf9, 0x16),
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VOLT_DATA_DEFINE(0, 0, 0, 0),
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};
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