2019-06-04 16:11:33 +08:00
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/* SPDX-License-Identifier: GPL-2.0-only */
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2014-07-16 20:01:44 +08:00
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/*
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* Copyright (C) 2014 NVIDIA Corporation
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*/
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#ifndef __SOC_TEGRA_COMMON_H__
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#define __SOC_TEGRA_COMMON_H__
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2021-05-28 07:54:03 +08:00
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#include <linux/errno.h>
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2021-05-28 07:54:02 +08:00
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#include <linux/types.h>
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2021-05-28 07:54:03 +08:00
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struct device;
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/**
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* Tegra SoC core device OPP table configuration
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*
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* @init_state: pre-initialize OPP state of a device
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*/
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struct tegra_core_opp_params {
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bool init_state;
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};
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2021-05-28 07:54:02 +08:00
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#ifdef CONFIG_ARCH_TEGRA
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2014-07-16 20:01:44 +08:00
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bool soc_is_tegra(void);
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2021-05-28 07:54:03 +08:00
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int devm_tegra_core_dev_init_opp_table(struct device *dev,
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struct tegra_core_opp_params *params);
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2021-05-28 07:54:02 +08:00
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#else
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static inline bool soc_is_tegra(void)
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{
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return false;
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}
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2021-05-28 07:54:03 +08:00
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static inline int
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devm_tegra_core_dev_init_opp_table(struct device *dev,
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struct tegra_core_opp_params *params)
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{
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return -ENODEV;
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}
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2021-05-28 07:54:02 +08:00
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#endif
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2014-07-16 20:01:44 +08:00
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2021-12-01 07:23:09 +08:00
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static inline int
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devm_tegra_core_dev_init_opp_table_common(struct device *dev)
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{
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struct tegra_core_opp_params opp_params = {};
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int err;
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opp_params.init_state = true;
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err = devm_tegra_core_dev_init_opp_table(dev, &opp_params);
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if (err != -ENODEV)
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return err;
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return 0;
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}
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2014-07-16 20:01:44 +08:00
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#endif /* __SOC_TEGRA_COMMON_H__ */
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