korg/linux
0
0
Fork 0
mirror of https://mirrors.bfsu.edu.cn/git/linux.git synced 2024-11-11 12:28:41 +08:00
Code Issues Packages Projects Releases Wiki Activity
287372fa39
linux/drivers/clk/samsung/clk-exynos4.c

1411 lines
56 KiB
C
Raw Normal View History

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500 Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Enrico Weigelt <info@metux.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-06-04 16:11:33 +08:00
// SPDX-License-Identifier: GPL-2.0-only
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
/*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* Copyright (c) 2013 Linaro Ltd.
* Author: Thomas Abraham <thomas.ab@samsung.com>
*
* Common Clock Framework support for all Exynos4 SoCs.
*/
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
#include <dt-bindings/clock/exynos4.h>
clk: samsung: Properly include clk.h and clkdev.h Clock provider drivers generally shouldn't include clk.h because it's the consumer API. Only include clk.h in files that are using it. The clkdev.h header isn't always used either, so remove it and add in slab.h where files were relying on it to include slab for them. Cc: Chanwoo Choi <cw00.choi@samsung.com> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Cc: Krzysztof Kozlowski <k.kozlowski@samsung.com> Cc: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-06-20 06:00:46 +08:00
#include <linux/slab.h>
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
#include <linux/clk.h>
#include <linux/clk-provider.h>
clk: Remove io.h from clk-provider.h Now that we've gotten rid of clk_readl() we can remove io.h from the clk-provider header and push out the io.h include to any code that isn't already including the io.h header but using things like readl/writel, etc. Found with this grep: git grep -l clk-provider.h | grep '.c$' | xargs git grep -L 'linux/io.h' | \ xargs git grep -l \ -e '\<__iowrite32_copy\>' --or \ -e '\<__ioread32_copy\>' --or \ -e '\<__iowrite64_copy\>' --or \ -e '\<ioremap_page_range\>' --or \ -e '\<ioremap_huge_init\>' --or \ -e '\<arch_ioremap_pud_supported\>' --or \ -e '\<arch_ioremap_pmd_supported\>' --or \ -e '\<devm_ioport_map\>' --or \ -e '\<devm_ioport_unmap\>' --or \ -e '\<IOMEM_ERR_PTR\>' --or \ -e '\<devm_ioremap\>' --or \ -e '\<devm_ioremap_nocache\>' --or \ -e '\<devm_ioremap_wc\>' --or \ -e '\<devm_iounmap\>' --or \ -e '\<devm_ioremap_release\>' --or \ -e '\<devm_memremap\>' --or \ -e '\<devm_memunmap\>' --or \ -e '\<__devm_memremap_pages\>' --or \ -e '\<pci_remap_cfgspace\>' --or \ -e '\<arch_has_dev_port\>' --or \ -e '\<arch_phys_wc_add\>' --or \ -e '\<arch_phys_wc_del\>' --or \ -e '\<memremap\>' --or \ -e '\<memunmap\>' --or \ -e '\<arch_io_reserve_memtype_wc\>' --or \ -e '\<arch_io_free_memtype_wc\>' --or \ -e '\<__io_aw\>' --or \ -e '\<__io_pbw\>' --or \ -e '\<__io_paw\>' --or \ -e '\<__io_pbr\>' --or \ -e '\<__io_par\>' --or \ -e '\<__raw_readb\>' --or \ -e '\<__raw_readw\>' --or \ -e '\<__raw_readl\>' --or \ -e '\<__raw_readq\>' --or \ -e '\<__raw_writeb\>' --or \ -e '\<__raw_writew\>' --or \ -e '\<__raw_writel\>' --or \ -e '\<__raw_writeq\>' --or \ -e '\<readb\>' --or \ -e '\<readw\>' --or \ -e '\<readl\>' --or \ -e '\<readq\>' --or \ -e '\<writeb\>' --or \ -e '\<writew\>' --or \ -e '\<writel\>' --or \ -e '\<writeq\>' --or \ -e '\<readb_relaxed\>' --or \ -e '\<readw_relaxed\>' --or \ -e '\<readl_relaxed\>' --or \ -e '\<readq_relaxed\>' --or \ -e '\<writeb_relaxed\>' --or \ -e '\<writew_relaxed\>' --or \ -e '\<writel_relaxed\>' --or \ -e '\<writeq_relaxed\>' --or \ -e '\<readsb\>' --or \ -e '\<readsw\>' --or \ -e '\<readsl\>' --or \ -e '\<readsq\>' --or \ -e '\<writesb\>' --or \ -e '\<writesw\>' --or \ -e '\<writesl\>' --or \ -e '\<writesq\>' --or \ -e '\<inb\>' --or \ -e '\<inw\>' --or \ -e '\<inl\>' --or \ -e '\<outb\>' --or \ -e '\<outw\>' --or \ -e '\<outl\>' --or \ -e '\<inb_p\>' --or \ -e '\<inw_p\>' --or \ -e '\<inl_p\>' --or \ -e '\<outb_p\>' --or \ -e '\<outw_p\>' --or \ -e '\<outl_p\>' --or \ -e '\<insb\>' --or \ -e '\<insw\>' --or \ -e '\<insl\>' --or \ -e '\<outsb\>' --or \ -e '\<outsw\>' --or \ -e '\<outsl\>' --or \ -e '\<insb_p\>' --or \ -e '\<insw_p\>' --or \ -e '\<insl_p\>' --or \ -e '\<outsb_p\>' --or \ -e '\<outsw_p\>' --or \ -e '\<outsl_p\>' --or \ -e '\<ioread8\>' --or \ -e '\<ioread16\>' --or \ -e '\<ioread32\>' --or \ -e '\<ioread64\>' --or \ -e '\<iowrite8\>' --or \ -e '\<iowrite16\>' --or \ -e '\<iowrite32\>' --or \ -e '\<iowrite64\>' --or \ -e '\<ioread16be\>' --or \ -e '\<ioread32be\>' --or \ -e '\<ioread64be\>' --or \ -e '\<iowrite16be\>' --or \ -e '\<iowrite32be\>' --or \ -e '\<iowrite64be\>' --or \ -e '\<ioread8_rep\>' --or \ -e '\<ioread16_rep\>' --or \ -e '\<ioread32_rep\>' --or \ -e '\<ioread64_rep\>' --or \ -e '\<iowrite8_rep\>' --or \ -e '\<iowrite16_rep\>' --or \ -e '\<iowrite32_rep\>' --or \ -e '\<iowrite64_rep\>' --or \ -e '\<__io_virt\>' --or \ -e '\<pci_iounmap\>' --or \ -e '\<virt_to_phys\>' --or \ -e '\<phys_to_virt\>' --or \ -e '\<ioremap_uc\>' --or \ -e '\<ioremap\>' --or \ -e '\<__ioremap\>' --or \ -e '\<iounmap\>' --or \ -e '\<ioremap\>' --or \ -e '\<ioremap_nocache\>' --or \ -e '\<ioremap_uc\>' --or \ -e '\<ioremap_wc\>' --or \ -e '\<ioremap_wc\>' --or \ -e '\<ioremap_wt\>' --or \ -e '\<ioport_map\>' --or \ -e '\<ioport_unmap\>' --or \ -e '\<ioport_map\>' --or \ -e '\<ioport_unmap\>' --or \ -e '\<xlate_dev_kmem_ptr\>' --or \ -e '\<xlate_dev_mem_ptr\>' --or \ -e '\<unxlate_dev_mem_ptr\>' --or \ -e '\<virt_to_bus\>' --or \ -e '\<bus_to_virt\>' --or \ -e '\<memset_io\>' --or \ -e '\<memcpy_fromio\>' --or \ -e '\<memcpy_toio\>' I also reordered a couple includes when they weren't alphabetical and removed clk.h from kona, replacing it with clk-provider.h because that driver doesn't use clk consumer APIs. Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Tero Kristo <t-kristo@ti.com> Acked-by: Sekhar Nori <nsekhar@ti.com> Cc: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Mark Brown <broonie@kernel.org> Cc: Chris Zankel <chris@zankel.net> Acked-by: Max Filippov <jcmvbkbc@gmail.com> Acked-by: John Crispin <john@phrozen.org> Acked-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-04-19 06:20:22 +08:00
#include <linux/io.h>
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
#include <linux/of.h>
#include <linux/of_address.h>
#include "clk.h"
clk: samsung: exynos4: add cpu clock configuration data and instantiate cpu clock With the addition of the new Samsung specific cpu-clock type, the arm clock can be represented as a cpu-clock type. Add the CPU clock configuration data and instantiate the CPU clock type for Exynos4210. Changes by Bartlomiej: - fixed issue with wrong dividers being setup by Common Clock Framework (by an addition of CLK_RECALC_NEW_RATES clock flag to mout_apll clock, without this change cpufreq-dt driver showed ~10 mA larger energy consumption when compared to cpufreq-exynos one when "performance" cpufreq governor was used on Exynos4210 SoC based Origen board), this was probably meant to be workarounded by use of CLK_GET_RATE_NOCACHE and CLK_DIVIDER_READ_ONLY clock flags in the original patchset (in "[PATCH v12 6/6] clk: samsung: remove unused clock aliases and update clock flags") but using these flags is not sufficient to fix the issue observed - removed Exynos5250 and Exynos5420 support for now Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Mike Turquette <mturquette@linaro.org> Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-04-04 00:43:46 +08:00
#include "clk-cpu.h"
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
/* Exynos4 clock controller register offsets */
#define SRC_LEFTBUS 0x4200
clk: exynos4: Add missing registers to suspend save list This patch adds missing clock control registers to the list of registers that should be saved across system suspend. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04 12:35:32 +08:00
#define DIV_LEFTBUS 0x4500
#define GATE_IP_LEFTBUS 0x4800
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
#define E4X12_GATE_IP_IMAGE 0x4930
clk: samsung: exynos4: Add CLKOUT clock hierarchy This patch adds definitions of clocks that are used to drive clock output signals of particular CMU sub-blocks that are then fed to PMU and handled by Exynos CLKOUT driver added in further patch. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-06-25 00:08:25 +08:00
#define CLKOUT_CMU_LEFTBUS 0x4a00
clk: exynos4: Add missing registers to suspend save list This patch adds missing clock control registers to the list of registers that should be saved across system suspend. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04 12:35:32 +08:00
#define SRC_RIGHTBUS 0x8200
#define DIV_RIGHTBUS 0x8500
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
#define GATE_IP_RIGHTBUS 0x8800
#define E4X12_GATE_IP_PERIR 0x8960
clk: samsung: exynos4: Add CLKOUT clock hierarchy This patch adds definitions of clocks that are used to drive clock output signals of particular CMU sub-blocks that are then fed to PMU and handled by Exynos CLKOUT driver added in further patch. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-06-25 00:08:25 +08:00
#define CLKOUT_CMU_RIGHTBUS 0x8a00
clk: exynos4: Define {E,V}PLL registers This patch adds preprocessor definitions of EPLL and VPLL registers and replaces all occurences of offsets of related registers with new definitions. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04 12:33:30 +08:00
#define EPLL_LOCK 0xc010
#define VPLL_LOCK 0xc020
#define EPLL_CON0 0xc110
#define EPLL_CON1 0xc114
#define EPLL_CON2 0xc118
#define VPLL_CON0 0xc120
#define VPLL_CON1 0xc124
#define VPLL_CON2 0xc128
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
#define SRC_TOP0 0xc210
#define SRC_TOP1 0xc214
#define SRC_CAM 0xc220
#define SRC_TV 0xc224
clk: samsung: exynos4: Correct SRC_MFC register The SRC_MFC register offset was incorrect, which could cause have caused wrong calculation of rate of sclk_mfc clock, that could in turn lead to incorrect operation of MFC. This patch corrects it. Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> [t.figa: Updated patch description] Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2013-11-22 13:21:08 +08:00
#define SRC_MFC 0xc228
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
#define SRC_G3D 0xc22c
#define E4210_SRC_IMAGE 0xc230
#define SRC_LCD0 0xc234
clk: exynos4: Add E4210 prefix to LCD1 clock registers This patch adds E4210 prefix to all registers related to LCD1 clock domain, because they are present only on Exynos4210. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04 12:35:18 +08:00
#define E4210_SRC_LCD1 0xc238
clk: exynos4: Add missing CMU_TOP and ISP clocks The patch adds missing clocks to TOP and ISP clock domains. It also adds clock gates for ISP sub-blocks. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04 12:33:22 +08:00
#define E4X12_SRC_ISP 0xc238
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
#define SRC_MAUDIO 0xc23c
#define SRC_FSYS 0xc240
#define SRC_PERIL0 0xc250
#define SRC_PERIL1 0xc254
#define E4X12_SRC_CAM1 0xc258
clk: exynos4: Add missing registers to suspend save list This patch adds missing clock control registers to the list of registers that should be saved across system suspend. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04 12:35:32 +08:00
#define SRC_MASK_TOP 0xc310
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
#define SRC_MASK_CAM 0xc320
#define SRC_MASK_TV 0xc324
#define SRC_MASK_LCD0 0xc334
clk: exynos4: Add E4210 prefix to LCD1 clock registers This patch adds E4210 prefix to all registers related to LCD1 clock domain, because they are present only on Exynos4210. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04 12:35:18 +08:00
#define E4210_SRC_MASK_LCD1 0xc338
clk: exynos4: Add missing CMU_TOP and ISP clocks The patch adds missing clocks to TOP and ISP clock domains. It also adds clock gates for ISP sub-blocks. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04 12:33:22 +08:00
#define E4X12_SRC_MASK_ISP 0xc338
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
#define SRC_MASK_MAUDIO 0xc33c
#define SRC_MASK_FSYS 0xc340
#define SRC_MASK_PERIL0 0xc350
#define SRC_MASK_PERIL1 0xc354
#define DIV_TOP 0xc510
#define DIV_CAM 0xc520
#define DIV_TV 0xc524
#define DIV_MFC 0xc528
#define DIV_G3D 0xc52c
#define DIV_IMAGE 0xc530
#define DIV_LCD0 0xc534
#define E4210_DIV_LCD1 0xc538
#define E4X12_DIV_ISP 0xc538
#define DIV_MAUDIO 0xc53c
#define DIV_FSYS0 0xc540
#define DIV_FSYS1 0xc544
#define DIV_FSYS2 0xc548
#define DIV_FSYS3 0xc54c
#define DIV_PERIL0 0xc550
#define DIV_PERIL1 0xc554
#define DIV_PERIL2 0xc558
#define DIV_PERIL3 0xc55c
#define DIV_PERIL4 0xc560
#define DIV_PERIL5 0xc564
#define E4X12_DIV_CAM1 0xc568
clk: exynos4: Fix wrong clock for Exynos4x12 ADC The TSADC gate clock was used in Exynos4x12 DTSI for exynos-adc driver. However TSADC is present only on Exynos4210 so on Trats2 board (with Exynos4412 SoC) the exynos-adc driver could not be probed: ERROR: could not get clock /adc@126C0000:adc(0) exynos-adc 126c0000.adc: failed getting clock, err = -2 exynos-adc: probe of 126c0000.adc failed with error -2 Instead on Exynos4x12 SoCs the main clock used by Analog to Digital Converter is located in different register and it is named in datasheet as PCLK_ADC. Regardless of the name the purpose of this PCLK_ADC clock is the same as purpose of TSADC from Exynos4210. The patch adds gate clock for Exynos4x12 using the proper register so backward compatibility is preserved. This fixes the probe of exynos-adc driver on Exynos4x12 boards and allows accessing sensors connected to it on Trats2 board (ntc,ncp15wb473 AP and battery thermistors). Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Cc: <stable@vger.kernel.org> Fixes: c63c57433003 ("ARM: dts: Add ADC's dt data to read raw data for exynos4x12") Reviewed-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Acked-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-06-12 09:53:25 +08:00
#define E4X12_GATE_BUS_FSYS1 0xc744
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
#define GATE_SCLK_CAM 0xc820
#define GATE_IP_CAM 0xc920
#define GATE_IP_TV 0xc924
#define GATE_IP_MFC 0xc928
#define GATE_IP_G3D 0xc92c
#define E4210_GATE_IP_IMAGE 0xc930
#define GATE_IP_LCD0 0xc934
clk: exynos4: Add E4210 prefix to LCD1 clock registers This patch adds E4210 prefix to all registers related to LCD1 clock domain, because they are present only on Exynos4210. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04 12:35:18 +08:00
#define E4210_GATE_IP_LCD1 0xc938
clk: exynos4: Add missing CMU_TOP and ISP clocks The patch adds missing clocks to TOP and ISP clock domains. It also adds clock gates for ISP sub-blocks. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04 12:33:22 +08:00
#define E4X12_GATE_IP_ISP 0xc938
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
#define E4X12_GATE_IP_MAUDIO 0xc93c
#define GATE_IP_FSYS 0xc940
#define GATE_IP_GPS 0xc94c
#define GATE_IP_PERIL 0xc950
clk: exynos4: Add E4210 prefix to GATE_IP_PERIR register This definition is specific for Exynos4210 (which has another location than the same register on Exynos4x12 SoCs) and so needs appropriate prefix. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04 12:35:22 +08:00
#define E4210_GATE_IP_PERIR 0xc960
clk: exynos4: Add missing registers to suspend save list This patch adds missing clock control registers to the list of registers that should be saved across system suspend. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04 12:35:32 +08:00
#define GATE_BLOCK 0xc970
clk: samsung: exynos4: Add CLKOUT clock hierarchy This patch adds definitions of clocks that are used to drive clock output signals of particular CMU sub-blocks that are then fed to PMU and handled by Exynos CLKOUT driver added in further patch. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-06-25 00:08:25 +08:00
#define CLKOUT_CMU_TOP 0xca00
clk: samsung: Migrate exynos4 to use common samsung_clk_register_pll() This patch migrates exynos4 pll registeration to use common samsung_clk_register_pll() by intialising table of PLLs. Signed-off-by: Yadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: Vikas Sajjan <vikas.sajjan@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-11 17:31:09 +08:00
#define E4X12_MPLL_LOCK 0x10008
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
#define E4X12_MPLL_CON0 0x10108
clk: exynos4: Remove E4X12 prefix from SRC_DMC register This register is present on all Exynos4 SoCs and so the prefix is misleading. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04 12:35:27 +08:00
#define SRC_DMC 0x10200
clk: exynos4: Add missing registers to suspend save list This patch adds missing clock control registers to the list of registers that should be saved across system suspend. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04 12:35:32 +08:00
#define SRC_MASK_DMC 0x10300
#define DIV_DMC0 0x10500
#define DIV_DMC1 0x10504
#define GATE_IP_DMC 0x10900
clk: samsung: exynos4: Add CLKOUT clock hierarchy This patch adds definitions of clocks that are used to drive clock output signals of particular CMU sub-blocks that are then fed to PMU and handled by Exynos CLKOUT driver added in further patch. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-06-25 00:08:25 +08:00
#define CLKOUT_CMU_DMC 0x10a00
clk: samsung: Migrate exynos4 to use common samsung_clk_register_pll() This patch migrates exynos4 pll registeration to use common samsung_clk_register_pll() by intialising table of PLLs. Signed-off-by: Yadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: Vikas Sajjan <vikas.sajjan@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-11 17:31:09 +08:00
#define APLL_LOCK 0x14000
clk: samsung: pll: Use new registration method for PLL45xx This patch modifies PLL45xx support code and its users to use the recently introduced common PLL registration helper. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:04 +08:00
#define E4210_MPLL_LOCK 0x14008
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
#define APLL_CON0 0x14100
#define E4210_MPLL_CON0 0x14108
#define SRC_CPU 0x14200
#define DIV_CPU0 0x14500
clk: exynos4: Add missing registers to suspend save list This patch adds missing clock control registers to the list of registers that should be saved across system suspend. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04 12:35:32 +08:00
#define DIV_CPU1 0x14504
#define GATE_SCLK_CPU 0x14800
#define GATE_IP_CPU 0x14900
clk: samsung: exynos4: Add CLKOUT clock hierarchy This patch adds definitions of clocks that are used to drive clock output signals of particular CMU sub-blocks that are then fed to PMU and handled by Exynos CLKOUT driver added in further patch. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-06-25 00:08:25 +08:00
#define CLKOUT_CMU_CPU 0x14a00
clk: samsung: exynos4: Enable ARMCLK down feature Enable ARMCLK down feature on all Exynos4 SoCs. The frequency of ARMCLK will be reduced upon entering idle mode (WFI or WFE). The feature behaves like very fast cpufreq ondemand governor. In idle mode this reduces energy consumption on full frequency chosen by cpufreq governor by approximately: - Trats2: 6.5% (153 mA -> 143 mA) - Trats: 33.0% (180 mA -> 120 mA) - Gear1: 27.0% (180 mA -> 130 mA) The patch uses simillar settings as Exynos5250 (clk-exynos5250.c), except it disables clock up feature and on Exynos4412 ARMCLK down is enabled for all 4 cores. Tested on Trats board (Exynos4210), Trats2 board (Exynos4412) and Samsung Gear 1 (Exynos4212). Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Tested-by: Daniel Drake <drake@endlessm.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-07-18 22:36:32 +08:00
#define PWR_CTRL1 0x15020
#define E4X12_PWR_CTRL2 0x15024
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
clk: samsung: exynos4: Enable ARMCLK down feature Enable ARMCLK down feature on all Exynos4 SoCs. The frequency of ARMCLK will be reduced upon entering idle mode (WFI or WFE). The feature behaves like very fast cpufreq ondemand governor. In idle mode this reduces energy consumption on full frequency chosen by cpufreq governor by approximately: - Trats2: 6.5% (153 mA -> 143 mA) - Trats: 33.0% (180 mA -> 120 mA) - Gear1: 27.0% (180 mA -> 130 mA) The patch uses simillar settings as Exynos5250 (clk-exynos5250.c), except it disables clock up feature and on Exynos4412 ARMCLK down is enabled for all 4 cores. Tested on Trats board (Exynos4210), Trats2 board (Exynos4412) and Samsung Gear 1 (Exynos4212). Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Tested-by: Daniel Drake <drake@endlessm.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-07-18 22:36:32 +08:00
/* Below definitions are used for PWR_CTRL settings */
#define PWR_CTRL1_CORE2_DOWN_RATIO(x) (((x) & 0x7) << 28)
#define PWR_CTRL1_CORE1_DOWN_RATIO(x) (((x) & 0x7) << 16)
#define PWR_CTRL1_DIV2_DOWN_EN (1 << 9)
#define PWR_CTRL1_DIV1_DOWN_EN (1 << 8)
#define PWR_CTRL1_USE_CORE3_WFE (1 << 7)
#define PWR_CTRL1_USE_CORE2_WFE (1 << 6)
#define PWR_CTRL1_USE_CORE1_WFE (1 << 5)
#define PWR_CTRL1_USE_CORE0_WFE (1 << 4)
#define PWR_CTRL1_USE_CORE3_WFI (1 << 3)
#define PWR_CTRL1_USE_CORE2_WFI (1 << 2)
#define PWR_CTRL1_USE_CORE1_WFI (1 << 1)
#define PWR_CTRL1_USE_CORE0_WFI (1 << 0)
clk: samsung: exynos4: do not define number of clocks in bindings Number of clocks supported by Linux drivers might vary - sometimes we add new clocks, not exposed previously. Therefore these numbers of clocks should not be in the bindings, as that prevents changing them. Define number of clocks per each clock controller inside the driver directly. Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Link: https://lore.kernel.org/r/20230808082738.122804-3-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2023-08-08 16:27:29 +08:00
/* NOTE: Must be equal to the last clock ID increased by one */
#define CLKS_NR (CLK_DIV_CORE2 + 1)
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
/* the exynos4 soc type */
enum exynos4_soc {
EXYNOS4210,
clk: samsung: Re-add support for Exynos4212 CPU clock Support for the Exynos4212 SoC was originally dropped as there were no boards using it. We will be adding a device that uses it, so add it back. This reverts commit c9194fb623b0158029a268376df09fe28a2a2b05. Signed-off-by: Artur Weber <aweber.kernel@gmail.com> Link: https://lore.kernel.org/r/20230501195525.6268-7-aweber.kernel@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2023-05-02 03:55:18 +08:00
EXYNOS4212,
EXYNOS4412,
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
};
clk: samsung: Migrate exynos4 to use common samsung_clk_register_pll() This patch migrates exynos4 pll registeration to use common samsung_clk_register_pll() by intialising table of PLLs. Signed-off-by: Yadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: Vikas Sajjan <vikas.sajjan@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-11 17:31:09 +08:00
/* list of PLLs to be registered */
enum exynos4_plls {
apll, mpll, epll, vpll,
nr_plls /* number of PLLs */
};
clk: samsung: exynos4: Move suspend/resume handling to SoC driver Since there are multiple differences in how suspend/resume of particular Exynos SoCs must be handled, SoC driver is better place for suspend/resume handlers and so this patch moves them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.ab@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-02-14 07:16:00 +08:00
static void __iomem *reg_base;
static enum exynos4_soc exynos4_soc;
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
/*
* list of controller registers to be saved and restored during a
* suspend/resume cycle.
*/
clk: samsung: exynos4: Constify all clock initializers All of initialization data can be made const. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2016-05-11 20:02:01 +08:00
static const unsigned long exynos4210_clk_save[] __initconst = {
clk: exynos4: Add support for SoC-specific register save list This patch extends suspend/resume support for SoC-specific registers to handle differences in register sets on particular SoCs. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04 12:35:35 +08:00
E4210_SRC_IMAGE,
E4210_SRC_LCD1,
E4210_SRC_MASK_LCD1,
E4210_DIV_LCD1,
E4210_GATE_IP_IMAGE,
E4210_GATE_IP_LCD1,
E4210_GATE_IP_PERIR,
E4210_MPLL_CON0,
clk: samsung: exynos4: Enable ARMCLK down feature Enable ARMCLK down feature on all Exynos4 SoCs. The frequency of ARMCLK will be reduced upon entering idle mode (WFI or WFE). The feature behaves like very fast cpufreq ondemand governor. In idle mode this reduces energy consumption on full frequency chosen by cpufreq governor by approximately: - Trats2: 6.5% (153 mA -> 143 mA) - Trats: 33.0% (180 mA -> 120 mA) - Gear1: 27.0% (180 mA -> 130 mA) The patch uses simillar settings as Exynos5250 (clk-exynos5250.c), except it disables clock up feature and on Exynos4412 ARMCLK down is enabled for all 4 cores. Tested on Trats board (Exynos4210), Trats2 board (Exynos4412) and Samsung Gear 1 (Exynos4212). Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Tested-by: Daniel Drake <drake@endlessm.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-07-18 22:36:32 +08:00
PWR_CTRL1,
clk: exynos4: Add support for SoC-specific register save list This patch extends suspend/resume support for SoC-specific registers to handle differences in register sets on particular SoCs. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04 12:35:35 +08:00
};
clk: samsung: exynos4: Constify all clock initializers All of initialization data can be made const. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2016-05-11 20:02:01 +08:00
static const unsigned long exynos4x12_clk_save[] __initconst = {
clk: exynos4: Add support for SoC-specific register save list This patch extends suspend/resume support for SoC-specific registers to handle differences in register sets on particular SoCs. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04 12:35:35 +08:00
E4X12_GATE_IP_IMAGE,
E4X12_GATE_IP_PERIR,
E4X12_SRC_CAM1,
E4X12_DIV_ISP,
E4X12_DIV_CAM1,
E4X12_MPLL_CON0,
clk: samsung: exynos4: Enable ARMCLK down feature Enable ARMCLK down feature on all Exynos4 SoCs. The frequency of ARMCLK will be reduced upon entering idle mode (WFI or WFE). The feature behaves like very fast cpufreq ondemand governor. In idle mode this reduces energy consumption on full frequency chosen by cpufreq governor by approximately: - Trats2: 6.5% (153 mA -> 143 mA) - Trats: 33.0% (180 mA -> 120 mA) - Gear1: 27.0% (180 mA -> 130 mA) The patch uses simillar settings as Exynos5250 (clk-exynos5250.c), except it disables clock up feature and on Exynos4412 ARMCLK down is enabled for all 4 cores. Tested on Trats board (Exynos4210), Trats2 board (Exynos4412) and Samsung Gear 1 (Exynos4212). Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Tested-by: Daniel Drake <drake@endlessm.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-07-18 22:36:32 +08:00
PWR_CTRL1,
E4X12_PWR_CTRL2,
clk: exynos4: Add support for SoC-specific register save list This patch extends suspend/resume support for SoC-specific registers to handle differences in register sets on particular SoCs. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04 12:35:35 +08:00
};
clk: samsung: exynos4: Use generic helper for handling suspend/resume Replace common suspend/resume handling code by generic helper. Handling of PLLs is a bit different in generic code, as they are handled in the same way as other clock registers. Such approach was already used on later Exynos SoCs and worked fine. Tests have shown that it works also on Exynos4 SoCs and significantly simplifies the code. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Sylwester Nawrocki <snawrocki@kernel.org>
2018-09-06 23:55:31 +08:00
static const unsigned long exynos4_clk_regs[] __initconst = {
clk: samsung: exynos4: Add remaining suspend/resume handling As of now, part of Exynos4 clock suspend/resume handling is located in mach-exynos/pm.c, which is not where code accessing CMU registers should reside. This patch implements all the necessary suspend/resume handling code in Exynos4 clock driver to allow dropping that old code. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.ab@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-02-14 07:16:01 +08:00
EPLL_LOCK,
VPLL_LOCK,
EPLL_CON0,
EPLL_CON1,
EPLL_CON2,
VPLL_CON0,
VPLL_CON1,
VPLL_CON2,
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
SRC_LEFTBUS,
clk: exynos4: Add missing registers to suspend save list This patch adds missing clock control registers to the list of registers that should be saved across system suspend. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04 12:35:32 +08:00
DIV_LEFTBUS,
GATE_IP_LEFTBUS,
SRC_RIGHTBUS,
DIV_RIGHTBUS,
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
GATE_IP_RIGHTBUS,
SRC_TOP0,
SRC_TOP1,
SRC_CAM,
SRC_TV,
SRC_MFC,
SRC_G3D,
SRC_LCD0,
SRC_MAUDIO,
SRC_FSYS,
SRC_PERIL0,
SRC_PERIL1,
clk: exynos4: Add missing registers to suspend save list This patch adds missing clock control registers to the list of registers that should be saved across system suspend. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04 12:35:32 +08:00
SRC_MASK_TOP,
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
SRC_MASK_CAM,
SRC_MASK_TV,
SRC_MASK_LCD0,
SRC_MASK_MAUDIO,
SRC_MASK_FSYS,
SRC_MASK_PERIL0,
SRC_MASK_PERIL1,
DIV_TOP,
DIV_CAM,
DIV_TV,
DIV_MFC,
DIV_G3D,
DIV_IMAGE,
DIV_LCD0,
DIV_MAUDIO,
DIV_FSYS0,
DIV_FSYS1,
DIV_FSYS2,
DIV_FSYS3,
DIV_PERIL0,
DIV_PERIL1,
DIV_PERIL2,
DIV_PERIL3,
DIV_PERIL4,
DIV_PERIL5,
GATE_SCLK_CAM,
GATE_IP_CAM,
GATE_IP_TV,
GATE_IP_MFC,
GATE_IP_G3D,
GATE_IP_LCD0,
GATE_IP_FSYS,
GATE_IP_GPS,
GATE_IP_PERIL,
clk: exynos4: Add missing registers to suspend save list This patch adds missing clock control registers to the list of registers that should be saved across system suspend. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04 12:35:32 +08:00
GATE_BLOCK,
SRC_MASK_DMC,
SRC_DMC,
DIV_DMC0,
DIV_DMC1,
GATE_IP_DMC,
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
APLL_CON0,
SRC_CPU,
DIV_CPU0,
clk: exynos4: Add missing registers to suspend save list This patch adds missing clock control registers to the list of registers that should be saved across system suspend. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04 12:35:32 +08:00
DIV_CPU1,
GATE_SCLK_CPU,
GATE_IP_CPU,
clk: samsung: exynos4: Add CLKOUT clock hierarchy This patch adds definitions of clocks that are used to drive clock output signals of particular CMU sub-blocks that are then fed to PMU and handled by Exynos CLKOUT driver added in further patch. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-06-25 00:08:25 +08:00
CLKOUT_CMU_LEFTBUS,
CLKOUT_CMU_RIGHTBUS,
CLKOUT_CMU_TOP,
CLKOUT_CMU_DMC,
CLKOUT_CMU_CPU,
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
};
clk: samsung: exynos4: Add remaining suspend/resume handling As of now, part of Exynos4 clock suspend/resume handling is located in mach-exynos/pm.c, which is not where code accessing CMU registers should reside. This patch implements all the necessary suspend/resume handling code in Exynos4 clock driver to allow dropping that old code. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.ab@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-02-14 07:16:01 +08:00
static const struct samsung_clk_reg_dump src_mask_suspend[] = {
clk: samsung: exynos4: Use generic helper for handling suspend/resume Replace common suspend/resume handling code by generic helper. Handling of PLLs is a bit different in generic code, as they are handled in the same way as other clock registers. Such approach was already used on later Exynos SoCs and worked fine. Tests have shown that it works also on Exynos4 SoCs and significantly simplifies the code. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Sylwester Nawrocki <snawrocki@kernel.org>
2018-09-06 23:55:31 +08:00
{ .offset = VPLL_CON0, .value = 0x80600302, },
{ .offset = EPLL_CON0, .value = 0x806F0302, },
clk: samsung: exynos4: Add remaining suspend/resume handling As of now, part of Exynos4 clock suspend/resume handling is located in mach-exynos/pm.c, which is not where code accessing CMU registers should reside. This patch implements all the necessary suspend/resume handling code in Exynos4 clock driver to allow dropping that old code. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.ab@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-02-14 07:16:01 +08:00
{ .offset = SRC_MASK_TOP, .value = 0x00000001, },
{ .offset = SRC_MASK_CAM, .value = 0x11111111, },
{ .offset = SRC_MASK_TV, .value = 0x00000111, },
{ .offset = SRC_MASK_LCD0, .value = 0x00001111, },
{ .offset = SRC_MASK_MAUDIO, .value = 0x00000001, },
{ .offset = SRC_MASK_FSYS, .value = 0x01011111, },
{ .offset = SRC_MASK_PERIL0, .value = 0x01111111, },
{ .offset = SRC_MASK_PERIL1, .value = 0x01110111, },
{ .offset = SRC_MASK_DMC, .value = 0x00010000, },
};
static const struct samsung_clk_reg_dump src_mask_suspend_e4210[] = {
{ .offset = E4210_SRC_MASK_LCD1, .value = 0x00001111, },
};
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
/* list of all parent clock list */
PNAME(mout_apll_p) = { "fin_pll", "fout_apll", };
PNAME(mout_mpll_p) = { "fin_pll", "fout_mpll", };
PNAME(mout_epll_p) = { "fin_pll", "fout_epll", };
PNAME(mout_vpllsrc_p) = { "fin_pll", "sclk_hdmi24m", };
PNAME(mout_vpll_p) = { "fin_pll", "fout_vpll", };
PNAME(sclk_evpll_p) = { "sclk_epll", "sclk_vpll", };
PNAME(mout_mfc_p) = { "mout_mfc0", "mout_mfc1", };
PNAME(mout_g3d_p) = { "mout_g3d0", "mout_g3d1", };
PNAME(mout_g2d_p) = { "mout_g2d0", "mout_g2d1", };
PNAME(mout_hdmi_p) = { "sclk_pixel", "sclk_hdmiphy", };
PNAME(mout_jpeg_p) = { "mout_jpeg0", "mout_jpeg1", };
PNAME(mout_spdif_p) = { "sclk_audio0", "sclk_audio1", "sclk_audio2",
"spdif_extclk", };
clk: exynos4: Add missing CMU_TOP and ISP clocks The patch adds missing clocks to TOP and ISP clock domains. It also adds clock gates for ISP sub-blocks. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04 12:33:22 +08:00
PNAME(mout_onenand_p) = {"aclk133", "aclk160", };
PNAME(mout_onenand1_p) = {"mout_onenand", "sclk_vpll", };
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
clk: exynos4: Use mout_mpll_user_* on Exynos4x12 Many clock muxes of Exynos 4x12 uses mout_mpll_user_* clocks instead of sclk_mpll as one of their parents. This patch moves such clocks from common array into SoC-specific arrays and adjusts their parent lists respectively. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04 12:32:37 +08:00
/* Exynos 4210-specific parent groups */
PNAME(sclk_vpll_p4210) = { "mout_vpllsrc", "fout_vpll", };
PNAME(mout_core_p4210) = { "mout_apll", "sclk_mpll", };
PNAME(sclk_ampll_p4210) = { "sclk_mpll", "sclk_apll", };
PNAME(group1_p4210) = { "xxti", "xusbxti", "sclk_hdmi24m",
"sclk_usbphy0", "none", "sclk_hdmiphy",
"sclk_mpll", "sclk_epll", "sclk_vpll", };
PNAME(mout_audio0_p4210) = { "cdclk0", "none", "sclk_hdmi24m",
"sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll",
"sclk_epll", "sclk_vpll" };
PNAME(mout_audio1_p4210) = { "cdclk1", "none", "sclk_hdmi24m",
"sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll",
"sclk_epll", "sclk_vpll", };
PNAME(mout_audio2_p4210) = { "cdclk2", "none", "sclk_hdmi24m",
"sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll",
"sclk_epll", "sclk_vpll", };
PNAME(mout_mixer_p4210) = { "sclk_dac", "sclk_hdmi", };
PNAME(mout_dac_p4210) = { "sclk_vpll", "sclk_hdmiphy", };
clk: samsung: exynos4: Add missing CPU/DMC clock hierarchy This patch adds missing definitions of clocks from CPU and DMC clock domains, which are necessary to properly represent CLKOUT clock hierarchy added in further patch. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-06-25 00:08:24 +08:00
PNAME(mout_pwi_p4210) = { "xxti", "xusbxti", "sclk_hdmi24m", "sclk_usbphy0",
"sclk_usbphy1", "sclk_hdmiphy", "none",
"sclk_epll", "sclk_vpll" };
clk: samsung: exynos4: Add CLKOUT clock hierarchy This patch adds definitions of clocks that are used to drive clock output signals of particular CMU sub-blocks that are then fed to PMU and handled by Exynos CLKOUT driver added in further patch. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-06-25 00:08:25 +08:00
PNAME(clkout_left_p4210) = { "sclk_mpll_div_2", "sclk_apll_div_2",
"div_gdl", "div_gpl" };
PNAME(clkout_right_p4210) = { "sclk_mpll_div_2", "sclk_apll_div_2",
"div_gdr", "div_gpr" };
PNAME(clkout_top_p4210) = { "fout_epll", "fout_vpll", "sclk_hdmi24m",
"sclk_usbphy0", "sclk_usbphy1", "sclk_hdmiphy",
"cdclk0", "cdclk1", "cdclk2", "spdif_extclk",
"aclk160", "aclk133", "aclk200", "aclk100",
"sclk_mfc", "sclk_g3d", "sclk_g2d",
"cam_a_pclk", "cam_b_pclk", "s_rxbyteclkhs0_2l",
"s_rxbyteclkhs0_4l" };
PNAME(clkout_dmc_p4210) = { "div_dmcd", "div_dmcp", "div_acp_pclk", "div_dmc",
"div_dphy", "none", "div_pwi" };
PNAME(clkout_cpu_p4210) = { "fout_apll_div_2", "none", "fout_mpll_div_2",
"none", "arm_clk_div_2", "div_corem0",
"div_corem1", "div_corem0", "div_atb",
"div_periph", "div_pclk_dbg", "div_hpm" };
clk: exynos4: Use mout_mpll_user_* on Exynos4x12 Many clock muxes of Exynos 4x12 uses mout_mpll_user_* clocks instead of sclk_mpll as one of their parents. This patch moves such clocks from common array into SoC-specific arrays and adjusts their parent lists respectively. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04 12:32:37 +08:00
/* Exynos 4x12-specific parent groups */
PNAME(mout_mpll_user_p4x12) = { "fin_pll", "sclk_mpll", };
PNAME(mout_core_p4x12) = { "mout_apll", "mout_mpll_user_c", };
clk: samsung: exynos4: Add missing CPU/DMC clock hierarchy This patch adds missing definitions of clocks from CPU and DMC clock domains, which are necessary to properly represent CLKOUT clock hierarchy added in further patch. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-06-25 00:08:24 +08:00
PNAME(mout_gdl_p4x12) = { "mout_mpll_user_l", "sclk_apll", };
PNAME(mout_gdr_p4x12) = { "mout_mpll_user_r", "sclk_apll", };
clk: exynos4: Use mout_mpll_user_* on Exynos4x12 Many clock muxes of Exynos 4x12 uses mout_mpll_user_* clocks instead of sclk_mpll as one of their parents. This patch moves such clocks from common array into SoC-specific arrays and adjusts their parent lists respectively. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04 12:32:37 +08:00
PNAME(sclk_ampll_p4x12) = { "mout_mpll_user_t", "sclk_apll", };
PNAME(group1_p4x12) = { "xxti", "xusbxti", "sclk_hdmi24m", "sclk_usbphy0",
"none", "sclk_hdmiphy", "mout_mpll_user_t",
"sclk_epll", "sclk_vpll", };
PNAME(mout_audio0_p4x12) = { "cdclk0", "none", "sclk_hdmi24m",
"sclk_usbphy0", "xxti", "xusbxti",
"mout_mpll_user_t", "sclk_epll", "sclk_vpll" };
PNAME(mout_audio1_p4x12) = { "cdclk1", "none", "sclk_hdmi24m",
"sclk_usbphy0", "xxti", "xusbxti",
"mout_mpll_user_t", "sclk_epll", "sclk_vpll", };
PNAME(mout_audio2_p4x12) = { "cdclk2", "none", "sclk_hdmi24m",
"sclk_usbphy0", "xxti", "xusbxti",
"mout_mpll_user_t", "sclk_epll", "sclk_vpll", };
PNAME(aclk_p4412) = { "mout_mpll_user_t", "sclk_apll", };
clk: exynos4: Add missing CMU_TOP and ISP clocks The patch adds missing clocks to TOP and ISP clock domains. It also adds clock gates for ISP sub-blocks. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04 12:33:22 +08:00
PNAME(mout_user_aclk400_mcuisp_p4x12) = {"fin_pll", "div_aclk400_mcuisp", };
PNAME(mout_user_aclk200_p4x12) = {"fin_pll", "div_aclk200", };
PNAME(mout_user_aclk266_gps_p4x12) = {"fin_pll", "div_aclk266_gps", };
clk: samsung: exynos4: Add missing CPU/DMC clock hierarchy This patch adds missing definitions of clocks from CPU and DMC clock domains, which are necessary to properly represent CLKOUT clock hierarchy added in further patch. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-06-25 00:08:24 +08:00
PNAME(mout_pwi_p4x12) = { "xxti", "xusbxti", "sclk_hdmi24m", "sclk_usbphy0",
"none", "sclk_hdmiphy", "sclk_mpll",
"sclk_epll", "sclk_vpll" };
clk: samsung: exynos4: Add CLKOUT clock hierarchy This patch adds definitions of clocks that are used to drive clock output signals of particular CMU sub-blocks that are then fed to PMU and handled by Exynos CLKOUT driver added in further patch. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-06-25 00:08:25 +08:00
PNAME(clkout_left_p4x12) = { "sclk_mpll_user_l_div_2", "sclk_apll_div_2",
"div_gdl", "div_gpl" };
PNAME(clkout_right_p4x12) = { "sclk_mpll_user_r_div_2", "sclk_apll_div_2",
"div_gdr", "div_gpr" };
PNAME(clkout_top_p4x12) = { "fout_epll", "fout_vpll", "sclk_hdmi24m",
"sclk_usbphy0", "none", "sclk_hdmiphy",
"cdclk0", "cdclk1", "cdclk2", "spdif_extclk",
"aclk160", "aclk133", "aclk200", "aclk100",
"sclk_mfc", "sclk_g3d", "aclk400_mcuisp",
"cam_a_pclk", "cam_b_pclk", "s_rxbyteclkhs0_2l",
"s_rxbyteclkhs0_4l", "rx_half_byte_clk_csis0",
"rx_half_byte_clk_csis1", "div_jpeg",
"sclk_pwm_isp", "sclk_spi0_isp",
"sclk_spi1_isp", "sclk_uart_isp",
"sclk_mipihsi", "sclk_hdmi", "sclk_fimd0",
"sclk_pcm0" };
PNAME(clkout_dmc_p4x12) = { "div_dmcd", "div_dmcp", "aclk_acp", "div_acp_pclk",
"div_dmc", "div_dphy", "fout_mpll_div_2",
"div_pwi", "none", "div_c2c", "div_c2c_aclk" };
PNAME(clkout_cpu_p4x12) = { "fout_apll_div_2", "none", "none", "none",
"arm_clk_div_2", "div_corem0", "div_corem1",
"div_cores", "div_atb", "div_periph",
"div_pclk_dbg", "div_hpm" };
clk: exynos4: Use mout_mpll_user_* on Exynos4x12 Many clock muxes of Exynos 4x12 uses mout_mpll_user_* clocks instead of sclk_mpll as one of their parents. This patch moves such clocks from common array into SoC-specific arrays and adjusts their parent lists respectively. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04 12:32:37 +08:00
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
/* fixed rate clocks generated outside the soc */
clk: exynos4: Staticize local symbols Symbols referenced only in this file are made static. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-07-18 18:01:17 +08:00
static struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata = {
clk: samsung: Remove CLK_IS_ROOT This flag is a no-op now. Remove usage of the flag. Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-02 02:59:58 +08:00
FRATE(CLK_XXTI, "xxti", NULL, 0, 0),
FRATE(CLK_XUSBXTI, "xusbxti", NULL, 0, 0),
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
};
/* fixed rate clocks generated inside the soc */
clk: samsung: exynos4: Constify all clock initializers All of initialization data can be made const. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2016-05-11 20:02:01 +08:00
static const struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initconst = {
clk: samsung: Remove CLK_IS_ROOT This flag is a no-op now. Remove usage of the flag. Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-02 02:59:58 +08:00
FRATE(0, "sclk_hdmi24m", NULL, 0, 24000000),
clk: samsung: exynos4: set parent of sclk_hdmiphy to hdmi sclk_hdmiphy clock is generated by HDMI-PHY and depends on hdmi gate clock. The patch models this dependency using parent/child hirerarchy. The patch fixes issue with system hangs during mixer device access, mixer uses sclk_hdmiphy descendant clock. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2014-11-24 15:30:50 +08:00
FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", "hdmi", 0, 27000000),
clk: samsung: Remove CLK_IS_ROOT This flag is a no-op now. Remove usage of the flag. Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-02 02:59:58 +08:00
FRATE(0, "sclk_usbphy0", NULL, 0, 48000000),
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
};
clk: samsung: exynos4: Constify all clock initializers All of initialization data can be made const. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2016-05-11 20:02:01 +08:00
static const struct samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initconst = {
clk: samsung: Remove CLK_IS_ROOT This flag is a no-op now. Remove usage of the flag. Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-02 02:59:58 +08:00
FRATE(0, "sclk_usbphy1", NULL, 0, 48000000),
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
};
clk: samsung: exynos4: Constify all clock initializers All of initialization data can be made const. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2016-05-11 20:02:01 +08:00
static const struct samsung_fixed_factor_clock exynos4_fixed_factor_clks[] __initconst = {
clk: samsung: exynos4: Add CLKOUT clock hierarchy This patch adds definitions of clocks that are used to drive clock output signals of particular CMU sub-blocks that are then fed to PMU and handled by Exynos CLKOUT driver added in further patch. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-06-25 00:08:25 +08:00
FFACTOR(0, "sclk_apll_div_2", "sclk_apll", 1, 2, 0),
FFACTOR(0, "fout_mpll_div_2", "fout_mpll", 1, 2, 0),
FFACTOR(0, "fout_apll_div_2", "fout_apll", 1, 2, 0),
clk: samsung: exynos4: remove duplicate div_core2 divider clock instantiation The 'div_core2' clock and the 'arm_clk' divider clocks are instances of the same divider clock. So remove the 'arm_clk' clock instance. Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> [tomasz.figa@gmail.com: Fixed remaining occurences of 'arm_clk'.] Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
2014-07-30 15:55:32 +08:00
FFACTOR(0, "arm_clk_div_2", "div_core2", 1, 2, 0),
clk: samsung: exynos4: Add CLKOUT clock hierarchy This patch adds definitions of clocks that are used to drive clock output signals of particular CMU sub-blocks that are then fed to PMU and handled by Exynos CLKOUT driver added in further patch. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-06-25 00:08:25 +08:00
};
clk: samsung: exynos4: Constify all clock initializers All of initialization data can be made const. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2016-05-11 20:02:01 +08:00
static const struct samsung_fixed_factor_clock exynos4210_fixed_factor_clks[] __initconst = {
clk: samsung: exynos4: Add CLKOUT clock hierarchy This patch adds definitions of clocks that are used to drive clock output signals of particular CMU sub-blocks that are then fed to PMU and handled by Exynos CLKOUT driver added in further patch. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-06-25 00:08:25 +08:00
FFACTOR(0, "sclk_mpll_div_2", "sclk_mpll", 1, 2, 0),
};
clk: samsung: exynos4: Constify all clock initializers All of initialization data can be made const. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2016-05-11 20:02:01 +08:00
static const struct samsung_fixed_factor_clock exynos4x12_fixed_factor_clks[] __initconst = {
clk: samsung: exynos4: Add CLKOUT clock hierarchy This patch adds definitions of clocks that are used to drive clock output signals of particular CMU sub-blocks that are then fed to PMU and handled by Exynos CLKOUT driver added in further patch. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-06-25 00:08:25 +08:00
FFACTOR(0, "sclk_mpll_user_l_div_2", "mout_mpll_user_l", 1, 2, 0),
FFACTOR(0, "sclk_mpll_user_r_div_2", "mout_mpll_user_r", 1, 2, 0),
FFACTOR(0, "sclk_mpll_user_t_div_2", "mout_mpll_user_t", 1, 2, 0),
FFACTOR(0, "sclk_mpll_user_c_div_2", "mout_mpll_user_c", 1, 2, 0),
};
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
/* list of mux clocks supported in all exynos4 soc's */
clk: samsung: exynos4: Constify all clock initializers All of initialization data can be made const. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2016-05-11 20:02:01 +08:00
static const struct samsung_mux_clock exynos4_mux_clks[] __initconst = {
clk: samsung: Remove clkdev alias support in Exynos4 clk driver All Exynos4 boards have been fully converted to device-tree and use generic dt-based CPUfreq driver, so there is no need to create any clkdev aliases for the clocks. Drop all the code related to aliases handling. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2017-10-03 18:00:09 +08:00
MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
clk: samsung: exynos4: add support for MOUT_HDMI and MOUT_MIXER clocks This patch adds support for exporting mout_hdmi and mout_mixer to device tree. Access to those clocks is required to correctly setup HDMI module on Exynos 4210 and 4x12 SoCs. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> CC: Mike Turquette <mturquette@linaro.org> CC: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
2014-07-01 16:10:05 +08:00
MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_TV, 0, 1),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
MUX(0, "mout_mfc1", sclk_evpll_p, SRC_MFC, 4, 1),
MUX(0, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1),
MUX_F(CLK_MOUT_G3D1, "mout_g3d1", sclk_evpll_p, SRC_G3D, 4, 1,
clk: exynos4: Add G3D clocks This patch adds clocks needed for G3D block present on Exynos 4 SoCs. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04 12:33:17 +08:00
CLK_SET_RATE_PARENT, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
MUX_F(CLK_MOUT_G3D, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1,
clk: exynos4: Add G3D clocks This patch adds clocks needed for G3D block present on Exynos 4 SoCs. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04 12:33:17 +08:00
CLK_SET_RATE_PARENT, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIL1, 8, 2),
MUX(0, "mout_onenand1", mout_onenand1_p, SRC_TOP0, 0, 1),
MUX(CLK_SCLK_EPLL, "sclk_epll", mout_epll_p, SRC_TOP0, 4, 1),
MUX(0, "mout_onenand", mout_onenand_p, SRC_TOP0, 28, 1),
clk: samsung: exynos4: Add missing CPU/DMC clock hierarchy This patch adds missing definitions of clocks from CPU and DMC clock domains, which are necessary to properly represent CLKOUT clock hierarchy added in further patch. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-06-25 00:08:24 +08:00
MUX(0, "mout_dmc_bus", sclk_ampll_p4210, SRC_DMC, 4, 1),
MUX(0, "mout_dphy", sclk_ampll_p4210, SRC_DMC, 8, 1),
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
};
/* list of mux clocks supported in exynos4210 soc */
clk: samsung: exynos4: Constify all clock initializers All of initialization data can be made const. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2016-05-11 20:02:01 +08:00
static const struct samsung_mux_clock exynos4210_mux_early[] __initconst = {
clk: samsung: remove __clk_lookup() usage __clk_lookup() interface is obsolete, so remove it from the Samsung clock drivers. This has been achieved by getting rid of custom _get_rate() helper and replacing it with clk_hw_get_rate(). Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Link: https://lore.kernel.org/r/20211018125456.8292-2-m.szyprowski@samsung.com Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2021-10-18 20:54:56 +08:00
MUX(CLK_MOUT_VPLLSRC, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1),
clk: samsung: exynos4: Reorder registration of mout_vpllsrc Since PLL input frequency must be known before PLL registration, mout_vpllsrc clock which is a reference clock of VPLL must be registered before VPLL. This patch reorders clock registration to register mout_vpllsrc before VPLL. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:08 +08:00
};
clk: samsung: exynos4: Constify all clock initializers All of initialization data can be made const. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2016-05-11 20:02:01 +08:00
static const struct samsung_mux_clock exynos4210_mux_clks[] __initconst = {
clk: samsung: exynos4: Add missing CPU/DMC clock hierarchy This patch adds missing definitions of clocks from CPU and DMC clock domains, which are necessary to properly represent CLKOUT clock hierarchy added in further patch. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-06-25 00:08:24 +08:00
MUX(0, "mout_gdl", sclk_ampll_p4210, SRC_LEFTBUS, 0, 1),
clk: samsung: exynos4: Add CLKOUT clock hierarchy This patch adds definitions of clocks that are used to drive clock output signals of particular CMU sub-blocks that are then fed to PMU and handled by Exynos CLKOUT driver added in further patch. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-06-25 00:08:25 +08:00
MUX(0, "mout_clkout_leftbus", clkout_left_p4210,
CLKOUT_CMU_LEFTBUS, 0, 5),
clk: samsung: exynos4: Add missing CPU/DMC clock hierarchy This patch adds missing definitions of clocks from CPU and DMC clock domains, which are necessary to properly represent CLKOUT clock hierarchy added in further patch. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-06-25 00:08:24 +08:00
MUX(0, "mout_gdr", sclk_ampll_p4210, SRC_RIGHTBUS, 0, 1),
clk: samsung: exynos4: Add CLKOUT clock hierarchy This patch adds definitions of clocks that are used to drive clock output signals of particular CMU sub-blocks that are then fed to PMU and handled by Exynos CLKOUT driver added in further patch. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-06-25 00:08:25 +08:00
MUX(0, "mout_clkout_rightbus", clkout_right_p4210,
CLKOUT_CMU_RIGHTBUS, 0, 5),
clk: samsung: exynos4: Add missing CPU/DMC clock hierarchy This patch adds missing definitions of clocks from CPU and DMC clock domains, which are necessary to properly represent CLKOUT clock hierarchy added in further patch. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-06-25 00:08:24 +08:00
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
MUX(0, "mout_aclk200", sclk_ampll_p4210, SRC_TOP0, 12, 1),
MUX(0, "mout_aclk100", sclk_ampll_p4210, SRC_TOP0, 16, 1),
MUX(0, "mout_aclk160", sclk_ampll_p4210, SRC_TOP0, 20, 1),
MUX(0, "mout_aclk133", sclk_ampll_p4210, SRC_TOP0, 24, 1),
clk: samsung: exynos4: add support for MOUT_HDMI and MOUT_MIXER clocks This patch adds support for exporting mout_hdmi and mout_mixer to device tree. Access to those clocks is required to correctly setup HDMI module on Exynos 4210 and 4x12 SoCs. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> CC: Mike Turquette <mturquette@linaro.org> CC: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
2014-07-01 16:10:05 +08:00
MUX(CLK_MOUT_MIXER, "mout_mixer", mout_mixer_p4210, SRC_TV, 4, 1),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
MUX(0, "mout_dac", mout_dac_p4210, SRC_TV, 8, 1),
MUX(0, "mout_g2d0", sclk_ampll_p4210, E4210_SRC_IMAGE, 0, 1),
MUX(0, "mout_g2d1", sclk_evpll_p, E4210_SRC_IMAGE, 4, 1),
MUX(0, "mout_g2d", mout_g2d_p, E4210_SRC_IMAGE, 8, 1),
MUX(0, "mout_fimd1", group1_p4210, E4210_SRC_LCD1, 0, 4),
MUX(0, "mout_mipi1", group1_p4210, E4210_SRC_LCD1, 12, 4),
MUX(CLK_SCLK_MPLL, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1),
MUX(CLK_MOUT_CORE, "mout_core", mout_core_p4210, SRC_CPU, 16, 1),
clk: samsung: exynos4: Add missing CPU/DMC clock hierarchy This patch adds missing definitions of clocks from CPU and DMC clock domains, which are necessary to properly represent CLKOUT clock hierarchy added in further patch. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-06-25 00:08:24 +08:00
MUX(0, "mout_hpm", mout_core_p4210, SRC_CPU, 20, 1),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
MUX(CLK_SCLK_VPLL, "sclk_vpll", sclk_vpll_p4210, SRC_TOP0, 8, 1),
MUX(CLK_MOUT_FIMC0, "mout_fimc0", group1_p4210, SRC_CAM, 0, 4),
MUX(CLK_MOUT_FIMC1, "mout_fimc1", group1_p4210, SRC_CAM, 4, 4),
MUX(CLK_MOUT_FIMC2, "mout_fimc2", group1_p4210, SRC_CAM, 8, 4),
MUX(CLK_MOUT_FIMC3, "mout_fimc3", group1_p4210, SRC_CAM, 12, 4),
MUX(CLK_MOUT_CAM0, "mout_cam0", group1_p4210, SRC_CAM, 16, 4),
MUX(CLK_MOUT_CAM1, "mout_cam1", group1_p4210, SRC_CAM, 20, 4),
MUX(CLK_MOUT_CSIS0, "mout_csis0", group1_p4210, SRC_CAM, 24, 4),
MUX(CLK_MOUT_CSIS1, "mout_csis1", group1_p4210, SRC_CAM, 28, 4),
MUX(0, "mout_mfc0", sclk_ampll_p4210, SRC_MFC, 0, 1),
MUX_F(CLK_MOUT_G3D0, "mout_g3d0", sclk_ampll_p4210, SRC_G3D, 0, 1,
clk: exynos4: Add G3D clocks This patch adds clocks needed for G3D block present on Exynos 4 SoCs. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04 12:33:17 +08:00
CLK_SET_RATE_PARENT, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
MUX(0, "mout_fimd0", group1_p4210, SRC_LCD0, 0, 4),
MUX(0, "mout_mipi0", group1_p4210, SRC_LCD0, 12, 4),
MUX(0, "mout_audio0", mout_audio0_p4210, SRC_MAUDIO, 0, 4),
MUX(0, "mout_mmc0", group1_p4210, SRC_FSYS, 0, 4),
MUX(0, "mout_mmc1", group1_p4210, SRC_FSYS, 4, 4),
MUX(0, "mout_mmc2", group1_p4210, SRC_FSYS, 8, 4),
MUX(0, "mout_mmc3", group1_p4210, SRC_FSYS, 12, 4),
MUX(0, "mout_mmc4", group1_p4210, SRC_FSYS, 16, 4),
MUX(0, "mout_sata", sclk_ampll_p4210, SRC_FSYS, 24, 1),
MUX(0, "mout_uart0", group1_p4210, SRC_PERIL0, 0, 4),
MUX(0, "mout_uart1", group1_p4210, SRC_PERIL0, 4, 4),
MUX(0, "mout_uart2", group1_p4210, SRC_PERIL0, 8, 4),
MUX(0, "mout_uart3", group1_p4210, SRC_PERIL0, 12, 4),
MUX(0, "mout_uart4", group1_p4210, SRC_PERIL0, 16, 4),
MUX(0, "mout_audio1", mout_audio1_p4210, SRC_PERIL1, 0, 4),
MUX(0, "mout_audio2", mout_audio2_p4210, SRC_PERIL1, 4, 4),
MUX(0, "mout_spi0", group1_p4210, SRC_PERIL1, 16, 4),
MUX(0, "mout_spi1", group1_p4210, SRC_PERIL1, 20, 4),
MUX(0, "mout_spi2", group1_p4210, SRC_PERIL1, 24, 4),
clk: samsung: exynos4: Add CLKOUT clock hierarchy This patch adds definitions of clocks that are used to drive clock output signals of particular CMU sub-blocks that are then fed to PMU and handled by Exynos CLKOUT driver added in further patch. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-06-25 00:08:25 +08:00
MUX(0, "mout_clkout_top", clkout_top_p4210, CLKOUT_CMU_TOP, 0, 5),
clk: samsung: exynos4: Add missing CPU/DMC clock hierarchy This patch adds missing definitions of clocks from CPU and DMC clock domains, which are necessary to properly represent CLKOUT clock hierarchy added in further patch. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-06-25 00:08:24 +08:00
MUX(0, "mout_pwi", mout_pwi_p4210, SRC_DMC, 16, 4),
clk: samsung: exynos4: Add CLKOUT clock hierarchy This patch adds definitions of clocks that are used to drive clock output signals of particular CMU sub-blocks that are then fed to PMU and handled by Exynos CLKOUT driver added in further patch. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-06-25 00:08:25 +08:00
MUX(0, "mout_clkout_dmc", clkout_dmc_p4210, CLKOUT_CMU_DMC, 0, 5),
MUX(0, "mout_clkout_cpu", clkout_cpu_p4210, CLKOUT_CMU_CPU, 0, 5),
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
};
/* list of mux clocks supported in exynos4x12 soc */
clk: samsung: exynos4: Constify all clock initializers All of initialization data can be made const. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2016-05-11 20:02:01 +08:00
static const struct samsung_mux_clock exynos4x12_mux_clks[] __initconst = {
clk: samsung: exynos4: Add missing CPU/DMC clock hierarchy This patch adds missing definitions of clocks from CPU and DMC clock domains, which are necessary to properly represent CLKOUT clock hierarchy added in further patch. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-06-25 00:08:24 +08:00
MUX(0, "mout_mpll_user_l", mout_mpll_p, SRC_LEFTBUS, 4, 1),
MUX(0, "mout_gdl", mout_gdl_p4x12, SRC_LEFTBUS, 0, 1),
clk: samsung: exynos4: Add CLKOUT clock hierarchy This patch adds definitions of clocks that are used to drive clock output signals of particular CMU sub-blocks that are then fed to PMU and handled by Exynos CLKOUT driver added in further patch. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-06-25 00:08:25 +08:00
MUX(0, "mout_clkout_leftbus", clkout_left_p4x12,
CLKOUT_CMU_LEFTBUS, 0, 5),
clk: samsung: exynos4: Add missing CPU/DMC clock hierarchy This patch adds missing definitions of clocks from CPU and DMC clock domains, which are necessary to properly represent CLKOUT clock hierarchy added in further patch. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-06-25 00:08:24 +08:00
MUX(0, "mout_mpll_user_r", mout_mpll_p, SRC_RIGHTBUS, 4, 1),
MUX(0, "mout_gdr", mout_gdr_p4x12, SRC_RIGHTBUS, 0, 1),
clk: samsung: exynos4: Add CLKOUT clock hierarchy This patch adds definitions of clocks that are used to drive clock output signals of particular CMU sub-blocks that are then fed to PMU and handled by Exynos CLKOUT driver added in further patch. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-06-25 00:08:25 +08:00
MUX(0, "mout_clkout_rightbus", clkout_right_p4x12,
CLKOUT_CMU_RIGHTBUS, 0, 5),
clk: samsung: exynos4: Add missing CPU/DMC clock hierarchy This patch adds missing definitions of clocks from CPU and DMC clock domains, which are necessary to properly represent CLKOUT clock hierarchy added in further patch. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-06-25 00:08:24 +08:00
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
MUX(CLK_MOUT_MPLL_USER_C, "mout_mpll_user_c", mout_mpll_user_p4x12,
clk: samsung: exynos4: Use separate aliases for cpufreq related clocks Exynos cpufreq driver is the only remaining piece of code that needs static clkdev aliases for operation, because it can not do device tree based clock lookups yet. This patch moves clock alias definitions for those clocks to separate arrays that can be used with samsung_clk_register_alias() helper. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:08:59 +08:00
SRC_CPU, 24, 1),
clk: samsung: exynos4: Add CLKOUT clock hierarchy This patch adds definitions of clocks that are used to drive clock output signals of particular CMU sub-blocks that are then fed to PMU and handled by Exynos CLKOUT driver added in further patch. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-06-25 00:08:25 +08:00
MUX(0, "mout_clkout_cpu", clkout_cpu_p4x12, CLKOUT_CMU_CPU, 0, 5),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
MUX(0, "mout_aclk266_gps", aclk_p4412, SRC_TOP1, 4, 1),
MUX(0, "mout_aclk400_mcuisp", aclk_p4412, SRC_TOP1, 8, 1),
MUX(CLK_MOUT_MPLL_USER_T, "mout_mpll_user_t", mout_mpll_user_p4x12,
clk: exynos4: Use mout_mpll_user_* on Exynos4x12 Many clock muxes of Exynos 4x12 uses mout_mpll_user_* clocks instead of sclk_mpll as one of their parents. This patch moves such clocks from common array into SoC-specific arrays and adjusts their parent lists respectively. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04 12:32:37 +08:00
SRC_TOP1, 12, 1),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
MUX(0, "mout_user_aclk266_gps", mout_user_aclk266_gps_p4x12,
clk: exynos4: Add missing CMU_TOP and ISP clocks The patch adds missing clocks to TOP and ISP clock domains. It also adds clock gates for ISP sub-blocks. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04 12:33:22 +08:00
SRC_TOP1, 16, 1),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
MUX(CLK_ACLK200, "aclk200", mout_user_aclk200_p4x12, SRC_TOP1, 20, 1),
MUX(CLK_ACLK400_MCUISP, "aclk400_mcuisp",
mout_user_aclk400_mcuisp_p4x12, SRC_TOP1, 24, 1),
MUX(0, "mout_aclk200", aclk_p4412, SRC_TOP0, 12, 1),
MUX(0, "mout_aclk100", aclk_p4412, SRC_TOP0, 16, 1),
MUX(0, "mout_aclk160", aclk_p4412, SRC_TOP0, 20, 1),
MUX(0, "mout_aclk133", aclk_p4412, SRC_TOP0, 24, 1),
MUX(0, "mout_mdnie0", group1_p4x12, SRC_LCD0, 4, 4),
MUX(0, "mout_mdnie_pwm0", group1_p4x12, SRC_LCD0, 8, 4),
MUX(0, "mout_sata", sclk_ampll_p4x12, SRC_FSYS, 24, 1),
MUX(0, "mout_jpeg0", sclk_ampll_p4x12, E4X12_SRC_CAM1, 0, 1),
MUX(0, "mout_jpeg1", sclk_evpll_p, E4X12_SRC_CAM1, 4, 1),
MUX(0, "mout_jpeg", mout_jpeg_p, E4X12_SRC_CAM1, 8, 1),
MUX(CLK_SCLK_MPLL, "sclk_mpll", mout_mpll_p, SRC_DMC, 12, 1),
MUX(CLK_SCLK_VPLL, "sclk_vpll", mout_vpll_p, SRC_TOP0, 8, 1),
MUX(CLK_MOUT_CORE, "mout_core", mout_core_p4x12, SRC_CPU, 16, 1),
clk: samsung: exynos4: Add missing CPU/DMC clock hierarchy This patch adds missing definitions of clocks from CPU and DMC clock domains, which are necessary to properly represent CLKOUT clock hierarchy added in further patch. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-06-25 00:08:24 +08:00
MUX(0, "mout_hpm", mout_core_p4x12, SRC_CPU, 20, 1),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
MUX(CLK_MOUT_FIMC0, "mout_fimc0", group1_p4x12, SRC_CAM, 0, 4),
MUX(CLK_MOUT_FIMC1, "mout_fimc1", group1_p4x12, SRC_CAM, 4, 4),
MUX(CLK_MOUT_FIMC2, "mout_fimc2", group1_p4x12, SRC_CAM, 8, 4),
MUX(CLK_MOUT_FIMC3, "mout_fimc3", group1_p4x12, SRC_CAM, 12, 4),
MUX(CLK_MOUT_CAM0, "mout_cam0", group1_p4x12, SRC_CAM, 16, 4),
MUX(CLK_MOUT_CAM1, "mout_cam1", group1_p4x12, SRC_CAM, 20, 4),
MUX(CLK_MOUT_CSIS0, "mout_csis0", group1_p4x12, SRC_CAM, 24, 4),
MUX(CLK_MOUT_CSIS1, "mout_csis1", group1_p4x12, SRC_CAM, 28, 4),
MUX(0, "mout_mfc0", sclk_ampll_p4x12, SRC_MFC, 0, 1),
MUX_F(CLK_MOUT_G3D0, "mout_g3d0", sclk_ampll_p4x12, SRC_G3D, 0, 1,
clk: exynos4: Add G3D clocks This patch adds clocks needed for G3D block present on Exynos 4 SoCs. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04 12:33:17 +08:00
CLK_SET_RATE_PARENT, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
MUX(0, "mout_fimd0", group1_p4x12, SRC_LCD0, 0, 4),
MUX(0, "mout_mipi0", group1_p4x12, SRC_LCD0, 12, 4),
MUX(0, "mout_audio0", mout_audio0_p4x12, SRC_MAUDIO, 0, 4),
MUX(0, "mout_mmc0", group1_p4x12, SRC_FSYS, 0, 4),
MUX(0, "mout_mmc1", group1_p4x12, SRC_FSYS, 4, 4),
MUX(0, "mout_mmc2", group1_p4x12, SRC_FSYS, 8, 4),
MUX(0, "mout_mmc3", group1_p4x12, SRC_FSYS, 12, 4),
MUX(0, "mout_mmc4", group1_p4x12, SRC_FSYS, 16, 4),
MUX(0, "mout_mipihsi", aclk_p4412, SRC_FSYS, 24, 1),
MUX(0, "mout_uart0", group1_p4x12, SRC_PERIL0, 0, 4),
MUX(0, "mout_uart1", group1_p4x12, SRC_PERIL0, 4, 4),
MUX(0, "mout_uart2", group1_p4x12, SRC_PERIL0, 8, 4),
MUX(0, "mout_uart3", group1_p4x12, SRC_PERIL0, 12, 4),
MUX(0, "mout_uart4", group1_p4x12, SRC_PERIL0, 16, 4),
MUX(0, "mout_audio1", mout_audio1_p4x12, SRC_PERIL1, 0, 4),
MUX(0, "mout_audio2", mout_audio2_p4x12, SRC_PERIL1, 4, 4),
MUX(0, "mout_spi0", group1_p4x12, SRC_PERIL1, 16, 4),
MUX(0, "mout_spi1", group1_p4x12, SRC_PERIL1, 20, 4),
MUX(0, "mout_spi2", group1_p4x12, SRC_PERIL1, 24, 4),
MUX(0, "mout_pwm_isp", group1_p4x12, E4X12_SRC_ISP, 0, 4),
MUX(0, "mout_spi0_isp", group1_p4x12, E4X12_SRC_ISP, 4, 4),
MUX(0, "mout_spi1_isp", group1_p4x12, E4X12_SRC_ISP, 8, 4),
MUX(0, "mout_uart_isp", group1_p4x12, E4X12_SRC_ISP, 12, 4),
clk: samsung: exynos4: Add CLKOUT clock hierarchy This patch adds definitions of clocks that are used to drive clock output signals of particular CMU sub-blocks that are then fed to PMU and handled by Exynos CLKOUT driver added in further patch. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-06-25 00:08:25 +08:00
MUX(0, "mout_clkout_top", clkout_top_p4x12, CLKOUT_CMU_TOP, 0, 5),
clk: samsung: exynos4: Add missing CPU/DMC clock hierarchy This patch adds missing definitions of clocks from CPU and DMC clock domains, which are necessary to properly represent CLKOUT clock hierarchy added in further patch. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-06-25 00:08:24 +08:00
MUX(0, "mout_c2c", sclk_ampll_p4210, SRC_DMC, 0, 1),
MUX(0, "mout_pwi", mout_pwi_p4x12, SRC_DMC, 16, 4),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
MUX(0, "mout_g2d0", sclk_ampll_p4210, SRC_DMC, 20, 1),
MUX(0, "mout_g2d1", sclk_evpll_p, SRC_DMC, 24, 1),
MUX(0, "mout_g2d", mout_g2d_p, SRC_DMC, 28, 1),
clk: samsung: exynos4: Add CLKOUT clock hierarchy This patch adds definitions of clocks that are used to drive clock output signals of particular CMU sub-blocks that are then fed to PMU and handled by Exynos CLKOUT driver added in further patch. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-06-25 00:08:25 +08:00
MUX(0, "mout_clkout_dmc", clkout_dmc_p4x12, CLKOUT_CMU_DMC, 0, 5),
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
};
/* list of divider clocks supported in all exynos4 soc's */
clk: samsung: exynos4: Constify all clock initializers All of initialization data can be made const. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2016-05-11 20:02:01 +08:00
static const struct samsung_div_clock exynos4_div_clks[] __initconst = {
clk: samsung: exynos4: Add divider clock id for memory bus frequency This patch adds the divider clock id for Exynos4 memory bus frequency. The clock id is used for DVFS (Dynamic Voltage/Frequency Scaling) feature of the exynos memory bus. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: MyungJoo Ham <myungjoo.ham@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2015-01-15 09:50:52 +08:00
DIV(CLK_DIV_GDL, "div_gdl", "mout_gdl", DIV_LEFTBUS, 0, 3),
clk: samsung: exynos4: Add missing CPU/DMC clock hierarchy This patch adds missing definitions of clocks from CPU and DMC clock domains, which are necessary to properly represent CLKOUT clock hierarchy added in further patch. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-06-25 00:08:24 +08:00
DIV(0, "div_gpl", "div_gdl", DIV_LEFTBUS, 4, 3),
clk: samsung: exynos4: Add CLKOUT clock hierarchy This patch adds definitions of clocks that are used to drive clock output signals of particular CMU sub-blocks that are then fed to PMU and handled by Exynos CLKOUT driver added in further patch. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-06-25 00:08:25 +08:00
DIV(0, "div_clkout_leftbus", "mout_clkout_leftbus",
CLKOUT_CMU_LEFTBUS, 8, 6),
clk: samsung: exynos4: Add missing CPU/DMC clock hierarchy This patch adds missing definitions of clocks from CPU and DMC clock domains, which are necessary to properly represent CLKOUT clock hierarchy added in further patch. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-06-25 00:08:24 +08:00
clk: samsung: exynos4: Add divider clock id for memory bus frequency This patch adds the divider clock id for Exynos4 memory bus frequency. The clock id is used for DVFS (Dynamic Voltage/Frequency Scaling) feature of the exynos memory bus. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: MyungJoo Ham <myungjoo.ham@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2015-01-15 09:50:52 +08:00
DIV(CLK_DIV_GDR, "div_gdr", "mout_gdr", DIV_RIGHTBUS, 0, 3),
clk: samsung: exynos4: Add missing CPU/DMC clock hierarchy This patch adds missing definitions of clocks from CPU and DMC clock domains, which are necessary to properly represent CLKOUT clock hierarchy added in further patch. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-06-25 00:08:24 +08:00
DIV(0, "div_gpr", "div_gdr", DIV_RIGHTBUS, 4, 3),
clk: samsung: exynos4: Add CLKOUT clock hierarchy This patch adds definitions of clocks that are used to drive clock output signals of particular CMU sub-blocks that are then fed to PMU and handled by Exynos CLKOUT driver added in further patch. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-06-25 00:08:25 +08:00
DIV(0, "div_clkout_rightbus", "mout_clkout_rightbus",
CLKOUT_CMU_RIGHTBUS, 8, 6),
clk: samsung: exynos4: Add missing CPU/DMC clock hierarchy This patch adds missing definitions of clocks from CPU and DMC clock domains, which are necessary to properly represent CLKOUT clock hierarchy added in further patch. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-06-25 00:08:24 +08:00
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
DIV(0, "div_core", "mout_core", DIV_CPU0, 0, 3),
clk: samsung: exynos4: Add missing CPU/DMC clock hierarchy This patch adds missing definitions of clocks from CPU and DMC clock domains, which are necessary to properly represent CLKOUT clock hierarchy added in further patch. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-06-25 00:08:24 +08:00
DIV(0, "div_corem0", "div_core2", DIV_CPU0, 4, 3),
DIV(0, "div_corem1", "div_core2", DIV_CPU0, 8, 3),
DIV(0, "div_periph", "div_core2", DIV_CPU0, 12, 3),
DIV(0, "div_atb", "mout_core", DIV_CPU0, 16, 3),
DIV(0, "div_pclk_dbg", "div_atb", DIV_CPU0, 20, 3),
clk: samsung: remove __clk_lookup() usage __clk_lookup() interface is obsolete, so remove it from the Samsung clock drivers. This has been achieved by getting rid of custom _get_rate() helper and replacing it with clk_hw_get_rate(). Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Link: https://lore.kernel.org/r/20211018125456.8292-2-m.szyprowski@samsung.com Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2021-10-18 20:54:56 +08:00
DIV(CLK_DIV_CORE2, "div_core2", "div_core", DIV_CPU0, 28, 3),
clk: samsung: exynos4: Add missing CPU/DMC clock hierarchy This patch adds missing definitions of clocks from CPU and DMC clock domains, which are necessary to properly represent CLKOUT clock hierarchy added in further patch. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-06-25 00:08:24 +08:00
DIV(0, "div_copy", "mout_hpm", DIV_CPU1, 0, 3),
DIV(0, "div_hpm", "div_copy", DIV_CPU1, 4, 3),
clk: samsung: exynos4: Add CLKOUT clock hierarchy This patch adds definitions of clocks that are used to drive clock output signals of particular CMU sub-blocks that are then fed to PMU and handled by Exynos CLKOUT driver added in further patch. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-06-25 00:08:25 +08:00
DIV(0, "div_clkout_cpu", "mout_clkout_cpu", CLKOUT_CMU_CPU, 8, 6),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
DIV(0, "div_fimc0", "mout_fimc0", DIV_CAM, 0, 4),
DIV(0, "div_fimc1", "mout_fimc1", DIV_CAM, 4, 4),
DIV(0, "div_fimc2", "mout_fimc2", DIV_CAM, 8, 4),
DIV(0, "div_fimc3", "mout_fimc3", DIV_CAM, 12, 4),
DIV(0, "div_cam0", "mout_cam0", DIV_CAM, 16, 4),
DIV(0, "div_cam1", "mout_cam1", DIV_CAM, 20, 4),
DIV(0, "div_csis0", "mout_csis0", DIV_CAM, 24, 4),
DIV(0, "div_csis1", "mout_csis1", DIV_CAM, 28, 4),
DIV(CLK_SCLK_MFC, "sclk_mfc", "mout_mfc", DIV_MFC, 0, 4),
clk: samsung: exynos4: fix g3d clocks sclk_g3d clock doesn't have enable/disable bits, but the driver hijacked g3d gate clock bits for this purpose and didn't provide real g3d clock at all. This patch fixes this issue by adding proper definition for g3d clock and removing incorrect access to GATE_IP_G3D register in sclk_g3d. In addition CLK_SET_RATE_PARENT flag is dropped from sclk_g3d, because it does not make any sense and most likely has been added by mistake. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> [tomasz.figa@gmail.com: Adjusted commit message.] Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
2014-09-22 20:17:12 +08:00
DIV(CLK_SCLK_G3D, "sclk_g3d", "mout_g3d", DIV_G3D, 0, 4),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
DIV(0, "div_fimd0", "mout_fimd0", DIV_LCD0, 0, 4),
DIV(0, "div_mipi0", "mout_mipi0", DIV_LCD0, 16, 4),
DIV(0, "div_audio0", "mout_audio0", DIV_MAUDIO, 0, 4),
DIV(CLK_SCLK_PCM0, "sclk_pcm0", "sclk_audio0", DIV_MAUDIO, 4, 8),
DIV(0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
DIV(0, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
DIV(0, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
DIV(0, "div_mmc3", "mout_mmc3", DIV_FSYS2, 16, 4),
DIV(CLK_SCLK_PIXEL, "sclk_pixel", "sclk_vpll", DIV_TV, 0, 4),
DIV(CLK_ACLK100, "aclk100", "mout_aclk100", DIV_TOP, 4, 4),
DIV(CLK_ACLK160, "aclk160", "mout_aclk160", DIV_TOP, 8, 3),
DIV(CLK_ACLK133, "aclk133", "mout_aclk133", DIV_TOP, 12, 3),
DIV(0, "div_onenand", "mout_onenand1", DIV_TOP, 16, 3),
DIV(CLK_SCLK_SLIMBUS, "sclk_slimbus", "sclk_epll", DIV_PERIL3, 4, 4),
DIV(CLK_SCLK_PCM1, "sclk_pcm1", "sclk_audio1", DIV_PERIL4, 4, 8),
DIV(CLK_SCLK_PCM2, "sclk_pcm2", "sclk_audio2", DIV_PERIL4, 20, 8),
DIV(CLK_SCLK_I2S1, "sclk_i2s1", "sclk_audio1", DIV_PERIL5, 0, 6),
DIV(CLK_SCLK_I2S2, "sclk_i2s2", "sclk_audio2", DIV_PERIL5, 8, 6),
DIV(0, "div_mmc4", "mout_mmc4", DIV_FSYS3, 0, 4),
The first half of the clk framework pull request is made up almost entirely of new platform/driver support. There are some conversions of existing drivers to the common-clock Device Tree binding, and a few non-critical fixes to the framework. Due to an entirely unnecessary cyclical dependency with the arm-soc tree this pull request is broken into two pieces. The second piece will be sent out after arm-soc sends you the pull request that merged in core support for the HiSilicon 3620 platform. That same pull request from arm-soc depends on this pull request to merge in those HiSilicon bits without causing build failures. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.14 (GNU/Linux) iQIcBAABAgAGBQJS4WZPAAoJEDqPOy9afJhJVz4QAL63xispjEVuABUjgskR1fyo 7QljpqUJCOViqiVqNi1sPtM0irvfrApNwTpK3mGm20/kbNIBSdqGc/fI5CbWxXAU scRqplTTLY6F7nXJXGgiM/e5b31Tb+KmY9Su5chq1Yv6py4/yb6SzoohcBlQJ5in JKIxgLqe1VqUkCY2EFlqLwYqUtgr/Zm6ZJDt4LTwxc43apwgG7USMAS8ppx7nTgd oGgcsU4dNur1L4+ahvwqC+ntfoZNmVKJm+eY+JrHXJ2sga4PLaJcorgK2NXFpgln nwZQzRfbZLg7vNg/ODIDvP94mhc266xq2TCWzD/kMOBwmhsM0lySpzI/IM8qv1U2 Tdy9EHAj2iHoU+s1yPEUtNRV4h2+BGUUy54690XO30+VCLVEJUCC2KopDAk0G3ua qxSCb1mJto8EEq3jCJwKZSOUI7gcizDjHAaqfLlnDytMlsFJR7AJVj5IcRdgC/9s Vg975Xklkn33fWEuYQzdQdcmJ8ZCnydo92R2S0CaMgxMZqp2eoYZXJWvgCAvfQYC HjAtnBpHxNsZQeASvclb9bQrEisAUjIrxvuzLenQhg88WhBuyUDgBdretCzHFhP4 i62QGAhSYiNJJQzs+U9EndG6fRr/p98Pmw2pBAAn8UYOT2wWMj8wpR+IVT50Bmdi j6LsDpvc7CE2a4f+KoCa =Hh66 -----END PGP SIGNATURE----- Merge tag 'clk-for-linus-3.14-part1' of git://git.linaro.org/people/mike.turquette/linux Pull clk framework changes from Mike Turquette: "The first half of the clk framework pull request is made up almost entirely of new platform/driver support. There are some conversions of existing drivers to the common-clock Device Tree binding, and a few non-critical fixes to the framework. Due to an entirely unnecessary cyclical dependency with the arm-soc tree this pull request is broken into two pieces. The second piece will be sent out after arm-soc sends you the pull request that merged in core support for the HiSilicon 3620 platform. That same pull request from arm-soc depends on this pull request to merge in those HiSilicon bits without causing build failures" [ Just did the ARM SoC merges, so getting ready for the second clk tree pull request - Linus ] * tag 'clk-for-linus-3.14-part1' of git://git.linaro.org/people/mike.turquette/linux: (97 commits) devicetree: bindings: Document qcom,mmcc devicetree: bindings: Document qcom,gcc clk: qcom: Add support for MSM8660's global clock controller (GCC) clk: qcom: Add support for MSM8974's multimedia clock controller (MMCC) clk: qcom: Add support for MSM8974's global clock controller (GCC) clk: qcom: Add support for MSM8960's multimedia clock controller (MMCC) clk: qcom: Add support for MSM8960's global clock controller (GCC) clk: qcom: Add reset controller support clk: qcom: Add support for branches/gate clocks clk: qcom: Add support for root clock generators (RCGs) clk: qcom: Add support for phase locked loops (PLLs) clk: qcom: Add a regmap type clock struct clk: Add set_rate_and_parent() op reset: Silence warning in reset-controller.h clk: sirf: re-arch to make the codes support both prima2 and atlas6 clk: composite: pass mux_hw into determine_rate clk: shmobile: Fix MSTP clock array initialization clk: shmobile: Fix MSTP clock index ARM: dts: Add clock provider specific properties to max77686 node clk: max77686: Register OF clock provider ...
2014-01-24 10:56:08 +08:00
DIV_F(0, "div_mmc_pre4", "div_mmc4", DIV_FSYS3, 8, 8,
clk: samsung: exynos4: Fix definition of div_mmc_pre4 divider The clock was missing CLK_SET_RATE_PARENT flag, which caused rate setting failures due to inability of reconfiguration of second divider behind it. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-12-21 06:58:38 +08:00
CLK_SET_RATE_PARENT, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
DIV(0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
DIV(0, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
DIV(0, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),
DIV(0, "div_uart3", "mout_uart3", DIV_PERIL0, 12, 4),
DIV(0, "div_uart4", "mout_uart4", DIV_PERIL0, 16, 4),
DIV(0, "div_spi0", "mout_spi0", DIV_PERIL1, 0, 4),
DIV(0, "div_spi_pre0", "div_spi0", DIV_PERIL1, 8, 8),
DIV(0, "div_spi1", "mout_spi1", DIV_PERIL1, 16, 4),
DIV(0, "div_spi_pre1", "div_spi1", DIV_PERIL1, 24, 8),
DIV(0, "div_spi2", "mout_spi2", DIV_PERIL2, 0, 4),
DIV(0, "div_spi_pre2", "div_spi2", DIV_PERIL2, 8, 8),
DIV(0, "div_audio1", "mout_audio1", DIV_PERIL4, 0, 4),
DIV(0, "div_audio2", "mout_audio2", DIV_PERIL4, 16, 4),
DIV(CLK_SCLK_APLL, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
DIV_F(0, "div_mipi_pre0", "div_mipi0", DIV_LCD0, 20, 4,
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
CLK_SET_RATE_PARENT, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
DIV_F(0, "div_mmc_pre0", "div_mmc0", DIV_FSYS1, 8, 8,
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
CLK_SET_RATE_PARENT, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
DIV_F(0, "div_mmc_pre1", "div_mmc1", DIV_FSYS1, 24, 8,
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
CLK_SET_RATE_PARENT, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
DIV_F(0, "div_mmc_pre2", "div_mmc2", DIV_FSYS2, 8, 8,
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
CLK_SET_RATE_PARENT, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
DIV_F(0, "div_mmc_pre3", "div_mmc3", DIV_FSYS2, 24, 8,
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
CLK_SET_RATE_PARENT, 0),
clk: samsung: exynos4: Add CLKOUT clock hierarchy This patch adds definitions of clocks that are used to drive clock output signals of particular CMU sub-blocks that are then fed to PMU and handled by Exynos CLKOUT driver added in further patch. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-06-25 00:08:25 +08:00
DIV(0, "div_clkout_top", "mout_clkout_top", CLKOUT_CMU_TOP, 8, 6),
clk: samsung: exynos4: Add missing CPU/DMC clock hierarchy This patch adds missing definitions of clocks from CPU and DMC clock domains, which are necessary to properly represent CLKOUT clock hierarchy added in further patch. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-06-25 00:08:24 +08:00
clk: samsung: exynos4: Add divider clock id for memory bus frequency This patch adds the divider clock id for Exynos4 memory bus frequency. The clock id is used for DVFS (Dynamic Voltage/Frequency Scaling) feature of the exynos memory bus. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: MyungJoo Ham <myungjoo.ham@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2015-01-15 09:50:52 +08:00
DIV(CLK_DIV_ACP, "div_acp", "mout_dmc_bus", DIV_DMC0, 0, 3),
clk: samsung: exynos4: Add missing CPU/DMC clock hierarchy This patch adds missing definitions of clocks from CPU and DMC clock domains, which are necessary to properly represent CLKOUT clock hierarchy added in further patch. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-06-25 00:08:24 +08:00
DIV(0, "div_acp_pclk", "div_acp", DIV_DMC0, 4, 3),
DIV(0, "div_dphy", "mout_dphy", DIV_DMC0, 8, 3),
clk: samsung: exynos4: Add divider clock id for memory bus frequency This patch adds the divider clock id for Exynos4 memory bus frequency. The clock id is used for DVFS (Dynamic Voltage/Frequency Scaling) feature of the exynos memory bus. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: MyungJoo Ham <myungjoo.ham@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2015-01-15 09:50:52 +08:00
DIV(CLK_DIV_DMC, "div_dmc", "mout_dmc_bus", DIV_DMC0, 12, 3),
clk: samsung: exynos4: Add missing CPU/DMC clock hierarchy This patch adds missing definitions of clocks from CPU and DMC clock domains, which are necessary to properly represent CLKOUT clock hierarchy added in further patch. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-06-25 00:08:24 +08:00
DIV(0, "div_dmcd", "div_dmc", DIV_DMC0, 16, 3),
DIV(0, "div_dmcp", "div_dmcd", DIV_DMC0, 20, 3),
DIV(0, "div_pwi", "mout_pwi", DIV_DMC1, 8, 4),
clk: samsung: exynos4: Add CLKOUT clock hierarchy This patch adds definitions of clocks that are used to drive clock output signals of particular CMU sub-blocks that are then fed to PMU and handled by Exynos CLKOUT driver added in further patch. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-06-25 00:08:25 +08:00
DIV(0, "div_clkout_dmc", "mout_clkout_dmc", CLKOUT_CMU_DMC, 8, 6),
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
};
/* list of divider clocks supported in exynos4210 soc */
clk: samsung: exynos4: Constify all clock initializers All of initialization data can be made const. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2016-05-11 20:02:01 +08:00
static const struct samsung_div_clock exynos4210_div_clks[] __initconst = {
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
DIV(CLK_ACLK200, "aclk200", "mout_aclk200", DIV_TOP, 0, 3),
DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_IMAGE, 0, 4),
DIV(0, "div_fimd1", "mout_fimd1", E4210_DIV_LCD1, 0, 4),
DIV(0, "div_mipi1", "mout_mipi1", E4210_DIV_LCD1, 16, 4),
DIV(0, "div_sata", "mout_sata", DIV_FSYS0, 20, 4),
DIV_F(0, "div_mipi_pre1", "div_mipi1", E4210_DIV_LCD1, 20, 4,
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
CLK_SET_RATE_PARENT, 0),
};
/* list of divider clocks supported in exynos4x12 soc */
clk: samsung: exynos4: Constify all clock initializers All of initialization data can be made const. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2016-05-11 20:02:01 +08:00
static const struct samsung_div_clock exynos4x12_div_clks[] __initconst = {
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
DIV(0, "div_mdnie0", "mout_mdnie0", DIV_LCD0, 4, 4),
DIV(0, "div_mdnie_pwm0", "mout_mdnie_pwm0", DIV_LCD0, 8, 4),
DIV(0, "div_mdnie_pwm_pre0", "div_mdnie_pwm0", DIV_LCD0, 12, 4),
DIV(0, "div_mipihsi", "mout_mipihsi", DIV_FSYS0, 20, 4),
DIV(0, "div_jpeg", "mout_jpeg", E4X12_DIV_CAM1, 0, 4),
DIV(CLK_DIV_ACLK200, "div_aclk200", "mout_aclk200", DIV_TOP, 0, 3),
DIV(0, "div_aclk266_gps", "mout_aclk266_gps", DIV_TOP, 20, 3),
DIV(CLK_DIV_ACLK400_MCUISP, "div_aclk400_mcuisp", "mout_aclk400_mcuisp",
clk: exynos4: export clocks required for fimc-is This patch adds clock indexes for ACLK_DIV0, ACLK_DIV1, ACLK_400_MCUISP, ACLK_MCUISP_DIV0, ACLK_MCUISP_DIV1, DIVACLK_400_MCUISP and DIVACLK_200 so these clocks are available to the consumers (Exynos4x12 FIMC-IS subsystem). While at it, indentation of the mux clocks table is corrected. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-08 14:24:47 +08:00
DIV_TOP, 24, 3),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
DIV(0, "div_pwm_isp", "mout_pwm_isp", E4X12_DIV_ISP, 0, 4),
DIV(0, "div_spi0_isp", "mout_spi0_isp", E4X12_DIV_ISP, 4, 4),
DIV(0, "div_spi0_isp_pre", "div_spi0_isp", E4X12_DIV_ISP, 8, 8),
DIV(0, "div_spi1_isp", "mout_spi1_isp", E4X12_DIV_ISP, 16, 4),
DIV(0, "div_spi1_isp_pre", "div_spi1_isp", E4X12_DIV_ISP, 20, 8),
DIV(0, "div_uart_isp", "mout_uart_isp", E4X12_DIV_ISP, 28, 4),
clk: samsung: Instantiate Exynos4412 ISP clocks only when available Some registers for the Exynos 4412 ISP (Camera subsystem) clocks are located in the ISP power domain. Instantiate those clocks only when provided clock registers resource covers those registers. This is a preparation for adding a separate clock driver for ISP clocks, which will be integrated with power domain using runtime PM feature. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2017-10-11 17:25:11 +08:00
DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_DMC1, 0, 4),
DIV(CLK_DIV_C2C, "div_c2c", "mout_c2c", DIV_DMC1, 4, 3),
DIV(0, "div_c2c_aclk", "div_c2c", DIV_DMC1, 12, 3),
};
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
/* list of gate clocks supported in all exynos4 soc's */
clk: samsung: exynos4: Constify all clock initializers All of initialization data can be made const. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2016-05-11 20:02:01 +08:00
static const struct samsung_gate_clock exynos4_gate_clks[] __initconst = {
clk: exynos4: Add PPMU IP block source clocks. Exynos4 has saveral PPMUs and each of them has operation clock which can be gated through CMU's SFR control. New clocks are listed below. All clocks are added as a gate-typed clock. CLK_PPMULEFT, CLK_PPMURIGHT, CLK_PPMUCAMIF, CLK_PPMUTV, CLK_PPMUMFC_L, CLK_PPMUMFC_R, CLK_G3D, CLK_PPMUIMAGE, CLK_PPMULCD0, CLK_PPMULCD1, CLK_PPMUFILE, CLK_PPMUGPS, CLK_PPMUDMC0, CLK_PPMUDMC1, CLK_PPMUCPU, CLK_PPMUACP, Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Myungjoo Ham <myungjoo.ham@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-05-27 19:27:08 +08:00
GATE(CLK_PPMULEFT, "ppmuleft", "aclk200", GATE_IP_LEFTBUS, 1, 0, 0),
GATE(CLK_PPMURIGHT, "ppmuright", "aclk200", GATE_IP_RIGHTBUS, 1, 0, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi", SRC_MASK_TV, 0, 0, 0),
GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif", SRC_MASK_PERIL1, 8, 0,
0),
GATE(CLK_JPEG, "jpeg", "aclk160", GATE_IP_CAM, 6, 0, 0),
GATE(CLK_MIE0, "mie0", "aclk160", GATE_IP_LCD0, 1, 0, 0),
GATE(CLK_DSIM0, "dsim0", "aclk160", GATE_IP_LCD0, 3, 0, 0),
GATE(CLK_FIMD1, "fimd1", "aclk160", E4210_GATE_IP_LCD1, 0, 0, 0),
GATE(CLK_MIE1, "mie1", "aclk160", E4210_GATE_IP_LCD1, 1, 0, 0),
GATE(CLK_DSIM1, "dsim1", "aclk160", E4210_GATE_IP_LCD1, 3, 0, 0),
GATE(CLK_SMMU_FIMD1, "smmu_fimd1", "aclk160", E4210_GATE_IP_LCD1, 4, 0,
0),
GATE(CLK_TSI, "tsi", "aclk133", GATE_IP_FSYS, 4, 0, 0),
GATE(CLK_SROMC, "sromc", "aclk133", GATE_IP_FSYS, 11, 0, 0),
clk: samsung: exynos4: fix g3d clocks sclk_g3d clock doesn't have enable/disable bits, but the driver hijacked g3d gate clock bits for this purpose and didn't provide real g3d clock at all. This patch fixes this issue by adding proper definition for g3d clock and removing incorrect access to GATE_IP_G3D register in sclk_g3d. In addition CLK_SET_RATE_PARENT flag is dropped from sclk_g3d, because it does not make any sense and most likely has been added by mistake. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> [tomasz.figa@gmail.com: Adjusted commit message.] Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
2014-09-22 20:17:12 +08:00
GATE(CLK_G3D, "g3d", "aclk200", GATE_IP_G3D, 0, 0, 0),
clk: exynos4: Add PPMU IP block source clocks. Exynos4 has saveral PPMUs and each of them has operation clock which can be gated through CMU's SFR control. New clocks are listed below. All clocks are added as a gate-typed clock. CLK_PPMULEFT, CLK_PPMURIGHT, CLK_PPMUCAMIF, CLK_PPMUTV, CLK_PPMUMFC_L, CLK_PPMUMFC_R, CLK_G3D, CLK_PPMUIMAGE, CLK_PPMULCD0, CLK_PPMULCD1, CLK_PPMUFILE, CLK_PPMUGPS, CLK_PPMUDMC0, CLK_PPMUDMC1, CLK_PPMUCPU, CLK_PPMUACP, Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Myungjoo Ham <myungjoo.ham@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-05-27 19:27:08 +08:00
GATE(CLK_PPMUG3D, "ppmug3d", "aclk200", GATE_IP_G3D, 1, 0, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_USB_DEVICE, "usb_device", "aclk133", GATE_IP_FSYS, 13, 0, 0),
GATE(CLK_ONENAND, "onenand", "aclk133", GATE_IP_FSYS, 15, 0, 0),
GATE(CLK_NFCON, "nfcon", "aclk133", GATE_IP_FSYS, 16, 0, 0),
GATE(CLK_GPS, "gps", "aclk133", GATE_IP_GPS, 0, 0, 0),
GATE(CLK_SMMU_GPS, "smmu_gps", "aclk133", GATE_IP_GPS, 1, 0, 0),
clk: exynos4: Add PPMU IP block source clocks. Exynos4 has saveral PPMUs and each of them has operation clock which can be gated through CMU's SFR control. New clocks are listed below. All clocks are added as a gate-typed clock. CLK_PPMULEFT, CLK_PPMURIGHT, CLK_PPMUCAMIF, CLK_PPMUTV, CLK_PPMUMFC_L, CLK_PPMUMFC_R, CLK_G3D, CLK_PPMUIMAGE, CLK_PPMULCD0, CLK_PPMULCD1, CLK_PPMUFILE, CLK_PPMUGPS, CLK_PPMUDMC0, CLK_PPMUDMC1, CLK_PPMUCPU, CLK_PPMUACP, Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Myungjoo Ham <myungjoo.ham@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-05-27 19:27:08 +08:00
GATE(CLK_PPMUGPS, "ppmugps", "aclk200", GATE_IP_GPS, 2, 0, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_SLIMBUS, "slimbus", "aclk100", GATE_IP_PERIL, 25, 0, 0),
GATE(CLK_SCLK_CAM0, "sclk_cam0", "div_cam0", GATE_SCLK_CAM, 4,
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
CLK_SET_RATE_PARENT, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_SCLK_CAM1, "sclk_cam1", "div_cam1", GATE_SCLK_CAM, 5,
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
CLK_SET_RATE_PARENT, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_SCLK_MIPI0, "sclk_mipi0", "div_mipi_pre0",
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
SRC_MASK_LCD0, 12, CLK_SET_RATE_PARENT, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_audio0", SRC_MASK_MAUDIO, 0,
clk: exynos4: Add missing sclk_audio0 clock This clock is a parent of mout_spdif and sclk_pcm0. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04 12:32:47 +08:00
CLK_SET_RATE_PARENT, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_audio1", SRC_MASK_PERIL1, 0,
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
CLK_SET_RATE_PARENT, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_VP, "vp", "aclk160", GATE_IP_TV, 0, 0, 0),
GATE(CLK_MIXER, "mixer", "aclk160", GATE_IP_TV, 1, 0, 0),
GATE(CLK_HDMI, "hdmi", "aclk160", GATE_IP_TV, 3, 0, 0),
GATE(CLK_PWM, "pwm", "aclk100", GATE_IP_PERIL, 24, 0, 0),
GATE(CLK_SDMMC4, "sdmmc4", "aclk133", GATE_IP_FSYS, 9, 0, 0),
GATE(CLK_USB_HOST, "usb_host", "aclk133", GATE_IP_FSYS, 12, 0, 0),
GATE(CLK_SCLK_FIMC0, "sclk_fimc0", "div_fimc0", SRC_MASK_CAM, 0,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
CLK_SET_RATE_PARENT, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_SCLK_FIMC1, "sclk_fimc1", "div_fimc1", SRC_MASK_CAM, 4,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
CLK_SET_RATE_PARENT, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_SCLK_FIMC2, "sclk_fimc2", "div_fimc2", SRC_MASK_CAM, 8,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
CLK_SET_RATE_PARENT, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_SCLK_FIMC3, "sclk_fimc3", "div_fimc3", SRC_MASK_CAM, 12,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
CLK_SET_RATE_PARENT, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_SCLK_CSIS0, "sclk_csis0", "div_csis0", SRC_MASK_CAM, 24,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
CLK_SET_RATE_PARENT, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_SCLK_CSIS1, "sclk_csis1", "div_csis1", SRC_MASK_CAM, 28,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
CLK_SET_RATE_PARENT, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_SCLK_FIMD0, "sclk_fimd0", "div_fimd0", SRC_MASK_LCD0, 0,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
CLK_SET_RATE_PARENT, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0", SRC_MASK_FSYS, 0,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
CLK_SET_RATE_PARENT, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc_pre1", SRC_MASK_FSYS, 4,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
CLK_SET_RATE_PARENT, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc_pre2", SRC_MASK_FSYS, 8,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
CLK_SET_RATE_PARENT, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_SCLK_MMC3, "sclk_mmc3", "div_mmc_pre3", SRC_MASK_FSYS, 12,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
CLK_SET_RATE_PARENT, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_SCLK_MMC4, "sclk_mmc4", "div_mmc_pre4", SRC_MASK_FSYS, 16,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
CLK_SET_RATE_PARENT, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_SCLK_UART0, "uclk0", "div_uart0", SRC_MASK_PERIL0, 0,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
CLK_SET_RATE_PARENT, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_SCLK_UART1, "uclk1", "div_uart1", SRC_MASK_PERIL0, 4,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
CLK_SET_RATE_PARENT, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_SCLK_UART2, "uclk2", "div_uart2", SRC_MASK_PERIL0, 8,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
CLK_SET_RATE_PARENT, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_SCLK_UART3, "uclk3", "div_uart3", SRC_MASK_PERIL0, 12,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
CLK_SET_RATE_PARENT, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_SCLK_UART4, "uclk4", "div_uart4", SRC_MASK_PERIL0, 16,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
CLK_SET_RATE_PARENT, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_SCLK_AUDIO2, "sclk_audio2", "div_audio2", SRC_MASK_PERIL1, 4,
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
CLK_SET_RATE_PARENT, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi_pre0", SRC_MASK_PERIL1, 16,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
CLK_SET_RATE_PARENT, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_SCLK_SPI1, "sclk_spi1", "div_spi_pre1", SRC_MASK_PERIL1, 20,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
CLK_SET_RATE_PARENT, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_SCLK_SPI2, "sclk_spi2", "div_spi_pre2", SRC_MASK_PERIL1, 24,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
CLK_SET_RATE_PARENT, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_FIMC0, "fimc0", "aclk160", GATE_IP_CAM, 0,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
0, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_FIMC1, "fimc1", "aclk160", GATE_IP_CAM, 1,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
0, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_FIMC2, "fimc2", "aclk160", GATE_IP_CAM, 2,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
0, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_FIMC3, "fimc3", "aclk160", GATE_IP_CAM, 3,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
0, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_CSIS0, "csis0", "aclk160", GATE_IP_CAM, 4,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
0, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_CSIS1, "csis1", "aclk160", GATE_IP_CAM, 5,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
0, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_SMMU_FIMC0, "smmu_fimc0", "aclk160", GATE_IP_CAM, 7,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
0, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_SMMU_FIMC1, "smmu_fimc1", "aclk160", GATE_IP_CAM, 8,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
0, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_SMMU_FIMC2, "smmu_fimc2", "aclk160", GATE_IP_CAM, 9,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
0, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_SMMU_FIMC3, "smmu_fimc3", "aclk160", GATE_IP_CAM, 10,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
0, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_SMMU_JPEG, "smmu_jpeg", "aclk160", GATE_IP_CAM, 11,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
0, 0),
clk: exynos4: Add PPMU IP block source clocks. Exynos4 has saveral PPMUs and each of them has operation clock which can be gated through CMU's SFR control. New clocks are listed below. All clocks are added as a gate-typed clock. CLK_PPMULEFT, CLK_PPMURIGHT, CLK_PPMUCAMIF, CLK_PPMUTV, CLK_PPMUMFC_L, CLK_PPMUMFC_R, CLK_G3D, CLK_PPMUIMAGE, CLK_PPMULCD0, CLK_PPMULCD1, CLK_PPMUFILE, CLK_PPMUGPS, CLK_PPMUDMC0, CLK_PPMUDMC1, CLK_PPMUCPU, CLK_PPMUACP, Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Myungjoo Ham <myungjoo.ham@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-05-27 19:27:08 +08:00
GATE(CLK_PPMUCAMIF, "ppmucamif", "aclk160", GATE_IP_CAM, 16, 0, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_PIXELASYNCM0, "pxl_async0", "aclk160", GATE_IP_CAM, 17, 0, 0),
GATE(CLK_PIXELASYNCM1, "pxl_async1", "aclk160", GATE_IP_CAM, 18, 0, 0),
GATE(CLK_SMMU_TV, "smmu_tv", "aclk160", GATE_IP_TV, 4,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
0, 0),
clk: exynos4: Add PPMU IP block source clocks. Exynos4 has saveral PPMUs and each of them has operation clock which can be gated through CMU's SFR control. New clocks are listed below. All clocks are added as a gate-typed clock. CLK_PPMULEFT, CLK_PPMURIGHT, CLK_PPMUCAMIF, CLK_PPMUTV, CLK_PPMUMFC_L, CLK_PPMUMFC_R, CLK_G3D, CLK_PPMUIMAGE, CLK_PPMULCD0, CLK_PPMULCD1, CLK_PPMUFILE, CLK_PPMUGPS, CLK_PPMUDMC0, CLK_PPMUDMC1, CLK_PPMUCPU, CLK_PPMUACP, Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Myungjoo Ham <myungjoo.ham@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-05-27 19:27:08 +08:00
GATE(CLK_PPMUTV, "ppmutv", "aclk160", GATE_IP_TV, 5, 0, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_MFC, "mfc", "aclk100", GATE_IP_MFC, 0, 0, 0),
GATE(CLK_SMMU_MFCL, "smmu_mfcl", "aclk100", GATE_IP_MFC, 1,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
0, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_SMMU_MFCR, "smmu_mfcr", "aclk100", GATE_IP_MFC, 2,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
0, 0),
clk: exynos4: Add PPMU IP block source clocks. Exynos4 has saveral PPMUs and each of them has operation clock which can be gated through CMU's SFR control. New clocks are listed below. All clocks are added as a gate-typed clock. CLK_PPMULEFT, CLK_PPMURIGHT, CLK_PPMUCAMIF, CLK_PPMUTV, CLK_PPMUMFC_L, CLK_PPMUMFC_R, CLK_G3D, CLK_PPMUIMAGE, CLK_PPMULCD0, CLK_PPMULCD1, CLK_PPMUFILE, CLK_PPMUGPS, CLK_PPMUDMC0, CLK_PPMUDMC1, CLK_PPMUCPU, CLK_PPMUACP, Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Myungjoo Ham <myungjoo.ham@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-05-27 19:27:08 +08:00
GATE(CLK_PPMUMFC_L, "ppmumfc_l", "aclk100", GATE_IP_MFC, 3, 0, 0),
GATE(CLK_PPMUMFC_R, "ppmumfc_r", "aclk100", GATE_IP_MFC, 4, 0, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_FIMD0, "fimd0", "aclk160", GATE_IP_LCD0, 0,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
0, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_SMMU_FIMD0, "smmu_fimd0", "aclk160", GATE_IP_LCD0, 4,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
0, 0),
clk: exynos4: Add PPMU IP block source clocks. Exynos4 has saveral PPMUs and each of them has operation clock which can be gated through CMU's SFR control. New clocks are listed below. All clocks are added as a gate-typed clock. CLK_PPMULEFT, CLK_PPMURIGHT, CLK_PPMUCAMIF, CLK_PPMUTV, CLK_PPMUMFC_L, CLK_PPMUMFC_R, CLK_G3D, CLK_PPMUIMAGE, CLK_PPMULCD0, CLK_PPMULCD1, CLK_PPMUFILE, CLK_PPMUGPS, CLK_PPMUDMC0, CLK_PPMUDMC1, CLK_PPMUCPU, CLK_PPMUACP, Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Myungjoo Ham <myungjoo.ham@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-05-27 19:27:08 +08:00
GATE(CLK_PPMULCD0, "ppmulcd0", "aclk160", GATE_IP_LCD0, 5, 0, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_PDMA0, "pdma0", "aclk133", GATE_IP_FSYS, 0,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
0, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_PDMA1, "pdma1", "aclk133", GATE_IP_FSYS, 1,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
0, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_SDMMC0, "sdmmc0", "aclk133", GATE_IP_FSYS, 5,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
0, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_SDMMC1, "sdmmc1", "aclk133", GATE_IP_FSYS, 6,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
0, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_SDMMC2, "sdmmc2", "aclk133", GATE_IP_FSYS, 7,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
0, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_SDMMC3, "sdmmc3", "aclk133", GATE_IP_FSYS, 8,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
0, 0),
clk: exynos4: Add PPMU IP block source clocks. Exynos4 has saveral PPMUs and each of them has operation clock which can be gated through CMU's SFR control. New clocks are listed below. All clocks are added as a gate-typed clock. CLK_PPMULEFT, CLK_PPMURIGHT, CLK_PPMUCAMIF, CLK_PPMUTV, CLK_PPMUMFC_L, CLK_PPMUMFC_R, CLK_G3D, CLK_PPMUIMAGE, CLK_PPMULCD0, CLK_PPMULCD1, CLK_PPMUFILE, CLK_PPMUGPS, CLK_PPMUDMC0, CLK_PPMUDMC1, CLK_PPMUCPU, CLK_PPMUACP, Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Myungjoo Ham <myungjoo.ham@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-05-27 19:27:08 +08:00
GATE(CLK_PPMUFILE, "ppmufile", "aclk133", GATE_IP_FSYS, 17, 0, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_UART0, "uart0", "aclk100", GATE_IP_PERIL, 0,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
0, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_UART1, "uart1", "aclk100", GATE_IP_PERIL, 1,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
0, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_UART2, "uart2", "aclk100", GATE_IP_PERIL, 2,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
0, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_UART3, "uart3", "aclk100", GATE_IP_PERIL, 3,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
0, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_UART4, "uart4", "aclk100", GATE_IP_PERIL, 4,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
0, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_I2C0, "i2c0", "aclk100", GATE_IP_PERIL, 6,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
0, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_I2C1, "i2c1", "aclk100", GATE_IP_PERIL, 7,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
0, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_I2C2, "i2c2", "aclk100", GATE_IP_PERIL, 8,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
0, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_I2C3, "i2c3", "aclk100", GATE_IP_PERIL, 9,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
0, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_I2C4, "i2c4", "aclk100", GATE_IP_PERIL, 10,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
0, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_I2C5, "i2c5", "aclk100", GATE_IP_PERIL, 11,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
0, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_I2C6, "i2c6", "aclk100", GATE_IP_PERIL, 12,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
0, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_I2C7, "i2c7", "aclk100", GATE_IP_PERIL, 13,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
0, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_I2C_HDMI, "i2c-hdmi", "aclk100", GATE_IP_PERIL, 14,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
0, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_SPI0, "spi0", "aclk100", GATE_IP_PERIL, 16,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
0, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_SPI1, "spi1", "aclk100", GATE_IP_PERIL, 17,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
0, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_SPI2, "spi2", "aclk100", GATE_IP_PERIL, 18,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
0, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_I2S1, "i2s1", "aclk100", GATE_IP_PERIL, 20,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
0, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_I2S2, "i2s2", "aclk100", GATE_IP_PERIL, 21,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
0, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_PCM1, "pcm1", "aclk100", GATE_IP_PERIL, 22,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
0, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_PCM2, "pcm2", "aclk100", GATE_IP_PERIL, 23,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
0, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_SPDIF, "spdif", "aclk100", GATE_IP_PERIL, 26,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
0, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_AC97, "ac97", "aclk100", GATE_IP_PERIL, 27,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
0, 0),
clk: samsung: exynos4: Add SSS gate clock Add a gate clock for controlling all clocks of Security Sub System (SSS). Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
2015-10-19 13:00:32 +08:00
GATE(CLK_SSS, "sss", "aclk133", GATE_IP_DMC, 4, 0, 0),
clk: exynos4: Add PPMU IP block source clocks. Exynos4 has saveral PPMUs and each of them has operation clock which can be gated through CMU's SFR control. New clocks are listed below. All clocks are added as a gate-typed clock. CLK_PPMULEFT, CLK_PPMURIGHT, CLK_PPMUCAMIF, CLK_PPMUTV, CLK_PPMUMFC_L, CLK_PPMUMFC_R, CLK_G3D, CLK_PPMUIMAGE, CLK_PPMULCD0, CLK_PPMULCD1, CLK_PPMUFILE, CLK_PPMUGPS, CLK_PPMUDMC0, CLK_PPMUDMC1, CLK_PPMUCPU, CLK_PPMUACP, Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Myungjoo Ham <myungjoo.ham@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-05-27 19:27:08 +08:00
GATE(CLK_PPMUDMC0, "ppmudmc0", "aclk133", GATE_IP_DMC, 8, 0, 0),
GATE(CLK_PPMUDMC1, "ppmudmc1", "aclk133", GATE_IP_DMC, 9, 0, 0),
GATE(CLK_PPMUCPU, "ppmucpu", "aclk133", GATE_IP_DMC, 10, 0, 0),
GATE(CLK_PPMUACP, "ppmuacp", "aclk133", GATE_IP_DMC, 16, 0, 0),
clk: samsung: exynos4: Add CLKOUT clock hierarchy This patch adds definitions of clocks that are used to drive clock output signals of particular CMU sub-blocks that are then fed to PMU and handled by Exynos CLKOUT driver added in further patch. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-06-25 00:08:25 +08:00
GATE(CLK_OUT_LEFTBUS, "clkout_leftbus", "div_clkout_leftbus",
CLKOUT_CMU_LEFTBUS, 16, CLK_SET_RATE_PARENT, 0),
GATE(CLK_OUT_RIGHTBUS, "clkout_rightbus", "div_clkout_rightbus",
CLKOUT_CMU_RIGHTBUS, 16, CLK_SET_RATE_PARENT, 0),
GATE(CLK_OUT_TOP, "clkout_top", "div_clkout_top",
CLKOUT_CMU_TOP, 16, CLK_SET_RATE_PARENT, 0),
GATE(CLK_OUT_DMC, "clkout_dmc", "div_clkout_dmc",
CLKOUT_CMU_DMC, 16, CLK_SET_RATE_PARENT, 0),
GATE(CLK_OUT_CPU, "clkout_cpu", "div_clkout_cpu",
CLKOUT_CMU_CPU, 16, CLK_SET_RATE_PARENT, 0),
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
};
/* list of gate clocks supported in exynos4210 soc */
clk: samsung: exynos4: Constify all clock initializers All of initialization data can be made const. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2016-05-11 20:02:01 +08:00
static const struct samsung_gate_clock exynos4210_gate_clks[] __initconst = {
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_TVENC, "tvenc", "aclk160", GATE_IP_TV, 2, 0, 0),
GATE(CLK_G2D, "g2d", "aclk200", E4210_GATE_IP_IMAGE, 0, 0, 0),
GATE(CLK_ROTATOR, "rotator", "aclk200", E4210_GATE_IP_IMAGE, 1, 0, 0),
GATE(CLK_MDMA, "mdma", "aclk200", E4210_GATE_IP_IMAGE, 2, 0, 0),
GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk200", E4210_GATE_IP_IMAGE, 3, 0, 0),
GATE(CLK_SMMU_MDMA, "smmu_mdma", "aclk200", E4210_GATE_IP_IMAGE, 5, 0,
0),
clk: exynos4: Add PPMU IP block source clocks. Exynos4 has saveral PPMUs and each of them has operation clock which can be gated through CMU's SFR control. New clocks are listed below. All clocks are added as a gate-typed clock. CLK_PPMULEFT, CLK_PPMURIGHT, CLK_PPMUCAMIF, CLK_PPMUTV, CLK_PPMUMFC_L, CLK_PPMUMFC_R, CLK_G3D, CLK_PPMUIMAGE, CLK_PPMULCD0, CLK_PPMULCD1, CLK_PPMUFILE, CLK_PPMUGPS, CLK_PPMUDMC0, CLK_PPMUDMC1, CLK_PPMUCPU, CLK_PPMUACP, Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Myungjoo Ham <myungjoo.ham@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-05-27 19:27:08 +08:00
GATE(CLK_PPMUIMAGE, "ppmuimage", "aclk200", E4210_GATE_IP_IMAGE, 9, 0,
0),
GATE(CLK_PPMULCD1, "ppmulcd1", "aclk160", E4210_GATE_IP_LCD1, 5, 0, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_PCIE_PHY, "pcie_phy", "aclk133", GATE_IP_FSYS, 2, 0, 0),
GATE(CLK_SATA_PHY, "sata_phy", "aclk133", GATE_IP_FSYS, 3, 0, 0),
GATE(CLK_SATA, "sata", "aclk133", GATE_IP_FSYS, 10, 0, 0),
GATE(CLK_PCIE, "pcie", "aclk133", GATE_IP_FSYS, 14, 0, 0),
GATE(CLK_SMMU_PCIE, "smmu_pcie", "aclk133", GATE_IP_FSYS, 18, 0, 0),
GATE(CLK_MODEMIF, "modemif", "aclk100", GATE_IP_PERIL, 28, 0, 0),
clk: samsung: exynos4: mark 'chipid' clock as CLK_IGNORE_UNUSED The ChipID IO region has it's own clock, which is being disabled while scanning for unused clocks. It turned out that some CPU hotplug, CPU idle or even SOC firmware code depends on the reads from that area. Fix the mysterious hang caused by entering deep CPU idle state by ignoring the 'chipid' clock during unused clocks scan, as there are no direct clients for it which will keep it enabled. Fixes: e062b571777f ("clk: exynos4: register clocks using common clock framework") Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Link: https://lore.kernel.org/r/20200922124046.10496-1-m.szyprowski@samsung.com Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-09-22 20:40:46 +08:00
GATE(CLK_CHIPID, "chipid", "aclk100", E4210_GATE_IP_PERIR, 0, CLK_IGNORE_UNUSED, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_SYSREG, "sysreg", "aclk100", E4210_GATE_IP_PERIR, 0,
clk: samsung: Add CLK_IGNORE_UNUSED flag for the sysreg clocks Currently no driver *) handles the sysreg clock, with an assumption that this clock is always left in its default state (enabled). Before commit 6e6aac7590f902d14d90bace3fd499 ARM: EXYNOS: Migrate clock support to common clock framework the sysreg clock was not even defined and hence wasn't handled explicitly in the kernel. To restore the previous behaviour disable masking the sysreg clock off in the clock core by default. *) Except the Exynos4x12 FIMC-IS driver, which will be modified to not touch the sysreg clock. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-05-11 00:38:09 +08:00
CLK_IGNORE_UNUSED, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk100", E4210_GATE_IP_PERIR, 11, 0,
0),
GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "aclk200",
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
E4210_GATE_IP_IMAGE, 4, 0, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "div_mipi_pre1",
clk: exynos4: Add E4210 prefix to LCD1 clock registers This patch adds E4210 prefix to all registers related to LCD1 clock domain, because they are present only on Exynos4210. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04 12:35:18 +08:00
E4210_SRC_MASK_LCD1, 12, CLK_SET_RATE_PARENT, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_SCLK_SATA, "sclk_sata", "div_sata",
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_SCLK_MIXER, "sclk_mixer", "mout_mixer", SRC_MASK_TV, 4, 0, 0),
GATE(CLK_SCLK_DAC, "sclk_dac", "mout_dac", SRC_MASK_TV, 8, 0, 0),
GATE(CLK_TSADC, "tsadc", "aclk100", GATE_IP_PERIL, 15,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
0, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_MCT, "mct", "aclk100", E4210_GATE_IP_PERIR, 13,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
0, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_WDT, "watchdog", "aclk100", E4210_GATE_IP_PERIR, 14,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
0, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_RTC, "rtc", "aclk100", E4210_GATE_IP_PERIR, 15,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
0, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_KEYIF, "keyif", "aclk100", E4210_GATE_IP_PERIR, 16,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
0, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "div_fimd1", E4210_SRC_MASK_LCD1, 0,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
CLK_SET_RATE_PARENT, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_TMU_APBIF, "tmu_apbif", "aclk100", E4210_GATE_IP_PERIR, 17, 0,
0),
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
};
/* list of gate clocks supported in exynos4x12 soc */
clk: samsung: exynos4: Constify all clock initializers All of initialization data can be made const. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2016-05-11 20:02:01 +08:00
static const struct samsung_gate_clock exynos4x12_gate_clks[] __initconst = {
clk: samsung: Add bus clock for GPU/G3D on Exynos4412 Add ID and gate for bus clock for GPU (Mali 400) on Exynos4412. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2019-06-19 03:05:26 +08:00
GATE(CLK_ASYNC_G3D, "async_g3d", "aclk200", GATE_IP_LEFTBUS, 6, 0, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_AUDSS, "audss", "sclk_epll", E4X12_GATE_IP_MAUDIO, 0, 0, 0),
GATE(CLK_MDNIE0, "mdnie0", "aclk160", GATE_IP_LCD0, 2, 0, 0),
GATE(CLK_ROTATOR, "rotator", "aclk200", E4X12_GATE_IP_IMAGE, 1, 0, 0),
clk: samsung: exynos4: Use single clock ID for CLK_MDMA gate clocks Exynos4210 and Exynos4x12 SoCs have the PL330 MDMA IP block clock defined exactly in same way in documentation. Using different names for these clocks is a bit misleading. Since there is no users of CLK_MDMA2 in existing dts files this patch drops CLK_MDMA2 and replaces it with CLK_MDMA in the driver. This ensures PL330 MDMA has correct clock assigned on Exynos4x12 SoCs. Suggested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-04-16 00:30:20 +08:00
GATE(CLK_MDMA, "mdma", "aclk200", E4X12_GATE_IP_IMAGE, 2, 0, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_SMMU_MDMA, "smmu_mdma", "aclk200", E4X12_GATE_IP_IMAGE, 5, 0,
0),
clk: exynos4: Add PPMU IP block source clocks. Exynos4 has saveral PPMUs and each of them has operation clock which can be gated through CMU's SFR control. New clocks are listed below. All clocks are added as a gate-typed clock. CLK_PPMULEFT, CLK_PPMURIGHT, CLK_PPMUCAMIF, CLK_PPMUTV, CLK_PPMUMFC_L, CLK_PPMUMFC_R, CLK_G3D, CLK_PPMUIMAGE, CLK_PPMULCD0, CLK_PPMULCD1, CLK_PPMUFILE, CLK_PPMUGPS, CLK_PPMUDMC0, CLK_PPMUDMC1, CLK_PPMUCPU, CLK_PPMUACP, Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Myungjoo Ham <myungjoo.ham@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-05-27 19:27:08 +08:00
GATE(CLK_PPMUIMAGE, "ppmuimage", "aclk200", E4X12_GATE_IP_IMAGE, 9, 0,
0),
clk: exynos4: Fix wrong clock for Exynos4x12 ADC The TSADC gate clock was used in Exynos4x12 DTSI for exynos-adc driver. However TSADC is present only on Exynos4210 so on Trats2 board (with Exynos4412 SoC) the exynos-adc driver could not be probed: ERROR: could not get clock /adc@126C0000:adc(0) exynos-adc 126c0000.adc: failed getting clock, err = -2 exynos-adc: probe of 126c0000.adc failed with error -2 Instead on Exynos4x12 SoCs the main clock used by Analog to Digital Converter is located in different register and it is named in datasheet as PCLK_ADC. Regardless of the name the purpose of this PCLK_ADC clock is the same as purpose of TSADC from Exynos4210. The patch adds gate clock for Exynos4x12 using the proper register so backward compatibility is preserved. This fixes the probe of exynos-adc driver on Exynos4x12 boards and allows accessing sensors connected to it on Trats2 board (ntc,ncp15wb473 AP and battery thermistors). Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Cc: <stable@vger.kernel.org> Fixes: c63c57433003 ("ARM: dts: Add ADC's dt data to read raw data for exynos4x12") Reviewed-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Acked-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-06-12 09:53:25 +08:00
GATE(CLK_TSADC, "tsadc", "aclk133", E4X12_GATE_BUS_FSYS1, 16, 0, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_MIPI_HSI, "mipi_hsi", "aclk133", GATE_IP_FSYS, 10, 0, 0),
clk: samsung: exynos4: mark 'chipid' clock as CLK_IGNORE_UNUSED The ChipID IO region has it's own clock, which is being disabled while scanning for unused clocks. It turned out that some CPU hotplug, CPU idle or even SOC firmware code depends on the reads from that area. Fix the mysterious hang caused by entering deep CPU idle state by ignoring the 'chipid' clock during unused clocks scan, as there are no direct clients for it which will keep it enabled. Fixes: e062b571777f ("clk: exynos4: register clocks using common clock framework") Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Link: https://lore.kernel.org/r/20200922124046.10496-1-m.szyprowski@samsung.com Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-09-22 20:40:46 +08:00
GATE(CLK_CHIPID, "chipid", "aclk100", E4X12_GATE_IP_PERIR, 0, CLK_IGNORE_UNUSED, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_SYSREG, "sysreg", "aclk100", E4X12_GATE_IP_PERIR, 1,
clk: samsung: Add CLK_IGNORE_UNUSED flag for the sysreg clocks Currently no driver *) handles the sysreg clock, with an assumption that this clock is always left in its default state (enabled). Before commit 6e6aac7590f902d14d90bace3fd499 ARM: EXYNOS: Migrate clock support to common clock framework the sysreg clock was not even defined and hence wasn't handled explicitly in the kernel. To restore the previous behaviour disable masking the sysreg clock off in the clock core by default. *) Except the Exynos4x12 FIMC-IS driver, which will be modified to not touch the sysreg clock. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-05-11 00:38:09 +08:00
CLK_IGNORE_UNUSED, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk100", E4X12_GATE_IP_PERIR, 11, 0,
0),
GATE(CLK_SCLK_MDNIE0, "sclk_mdnie0", "div_mdnie0",
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
SRC_MASK_LCD0, 4, CLK_SET_RATE_PARENT, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_SCLK_MDNIE_PWM0, "sclk_mdnie_pwm0", "div_mdnie_pwm_pre0",
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
SRC_MASK_LCD0, 8, CLK_SET_RATE_PARENT, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_SCLK_MIPIHSI, "sclk_mipihsi", "div_mipihsi",
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "aclk200",
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
E4X12_GATE_IP_IMAGE, 4, 0, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_MCT, "mct", "aclk100", E4X12_GATE_IP_PERIR, 13,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
0, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_RTC, "rtc", "aclk100", E4X12_GATE_IP_PERIR, 15,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
0, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_KEYIF, "keyif", "aclk100", E4X12_GATE_IP_PERIR, 16, 0, 0),
clk: samsung: exynos4: Remove SRC_MASK_ISP gates ISP special clocks have dedicated gating registers and so MUX SRC_MASK register should not be used. This patch fixes the problem of Exynos4x12-based boards freezing on system suspend, because those mux outputs need not to be masked while suspending. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Cc: Mike Turquette <mturquette@linaro.org>
2014-06-24 21:57:12 +08:00
GATE(CLK_PWM_ISP_SCLK, "pwm_isp_sclk", "div_pwm_isp",
clk: exynos4: Add missing CMU_TOP and ISP clocks The patch adds missing clocks to TOP and ISP clock domains. It also adds clock gates for ISP sub-blocks. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04 12:33:22 +08:00
E4X12_GATE_IP_ISP, 0, 0, 0),
clk: samsung: exynos4: Remove SRC_MASK_ISP gates ISP special clocks have dedicated gating registers and so MUX SRC_MASK register should not be used. This patch fixes the problem of Exynos4x12-based boards freezing on system suspend, because those mux outputs need not to be masked while suspending. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Cc: Mike Turquette <mturquette@linaro.org>
2014-06-24 21:57:12 +08:00
GATE(CLK_SPI0_ISP_SCLK, "spi0_isp_sclk", "div_spi0_isp_pre",
clk: exynos4: Add missing CMU_TOP and ISP clocks The patch adds missing clocks to TOP and ISP clock domains. It also adds clock gates for ISP sub-blocks. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04 12:33:22 +08:00
E4X12_GATE_IP_ISP, 1, 0, 0),
clk: samsung: exynos4: Remove SRC_MASK_ISP gates ISP special clocks have dedicated gating registers and so MUX SRC_MASK register should not be used. This patch fixes the problem of Exynos4x12-based boards freezing on system suspend, because those mux outputs need not to be masked while suspending. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Cc: Mike Turquette <mturquette@linaro.org>
2014-06-24 21:57:12 +08:00
GATE(CLK_SPI1_ISP_SCLK, "spi1_isp_sclk", "div_spi1_isp_pre",
clk: exynos4: Add missing CMU_TOP and ISP clocks The patch adds missing clocks to TOP and ISP clock domains. It also adds clock gates for ISP sub-blocks. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04 12:33:22 +08:00
E4X12_GATE_IP_ISP, 2, 0, 0),
clk: samsung: exynos4: Remove SRC_MASK_ISP gates ISP special clocks have dedicated gating registers and so MUX SRC_MASK register should not be used. This patch fixes the problem of Exynos4x12-based boards freezing on system suspend, because those mux outputs need not to be masked while suspending. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Cc: Mike Turquette <mturquette@linaro.org>
2014-06-24 21:57:12 +08:00
GATE(CLK_UART_ISP_SCLK, "uart_isp_sclk", "div_uart_isp",
clk: exynos4: Add missing CMU_TOP and ISP clocks The patch adds missing clocks to TOP and ISP clock domains. It also adds clock gates for ISP sub-blocks. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04 12:33:22 +08:00
E4X12_GATE_IP_ISP, 3, 0, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_WDT, "watchdog", "aclk100", E4X12_GATE_IP_PERIR, 14, 0, 0),
GATE(CLK_PCM0, "pcm0", "aclk100", E4X12_GATE_IP_MAUDIO, 2,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
0, 0),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
GATE(CLK_I2S0, "i2s0", "aclk100", E4X12_GATE_IP_MAUDIO, 3,
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
0, 0),
clk: samsung: Instantiate Exynos4412 ISP clocks only when available Some registers for the Exynos 4412 ISP (Camera subsystem) clocks are located in the ISP power domain. Instantiate those clocks only when provided clock registers resource covers those registers. This is a preparation for adding a separate clock driver for ISP clocks, which will be integrated with power domain using runtime PM feature. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2017-10-11 17:25:11 +08:00
GATE(CLK_G2D, "g2d", "aclk200", GATE_IP_DMC, 23, 0, 0),
GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk200", GATE_IP_DMC, 24, 0, 0),
GATE(CLK_TMU_APBIF, "tmu_apbif", "aclk100", E4X12_GATE_IP_PERIR, 17, 0,
0),
};
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
/*
* The parent of the fin_pll clock is selected by the XOM[0] bit. This bit
* resides in chipid register space, outside of the clock controller memory
* mapped space. So to determine the parent of fin_pll clock, the chipid
* controller is first remapped and the value of XOM[0] bit is read to
* determine the parent clock.
*/
clk: samsung: exynos4: Move local function to init section The local exynos4_get_xom() function is referenced only from other init-level functions. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2016-05-11 20:02:00 +08:00
static unsigned long __init exynos4_get_xom(void)
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
{
clk: exynos: prepare for multiplatform The new common clock drivers for exynos are using compile time constants and soc_is_exynos* macros to provide backwards compatibility for pre-DT systems, which is not possible with multiplatform kernels. This moves all the necessary information back into platform code and removes the mach/* header inclusions. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Cc: Mike Turquette <mturquette@linaro.org>
2013-04-10 17:31:44 +08:00
unsigned long xom = 0;
void __iomem *chipid_base;
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
struct device_node *np;
np = of_find_compatible_node(NULL, NULL, "samsung,exynos4210-chipid");
clk: exynos: prepare for multiplatform The new common clock drivers for exynos are using compile time constants and soc_is_exynos* macros to provide backwards compatibility for pre-DT systems, which is not possible with multiplatform kernels. This moves all the necessary information back into platform code and removes the mach/* header inclusions. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Cc: Mike Turquette <mturquette@linaro.org>
2013-04-10 17:31:44 +08:00
if (np) {
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
chipid_base = of_iomap(np, 0);
clk: exynos: prepare for multiplatform The new common clock drivers for exynos are using compile time constants and soc_is_exynos* macros to provide backwards compatibility for pre-DT systems, which is not possible with multiplatform kernels. This moves all the necessary information back into platform code and removes the mach/* header inclusions. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Cc: Mike Turquette <mturquette@linaro.org>
2013-04-10 17:31:44 +08:00
if (chipid_base)
xom = readl(chipid_base + 8);
iounmap(chipid_base);
clk: samsung: exynos4: fix refcount leak in exynos4_get_xom() The of_find_compatible_node() returns a node pointer with refcount incremented, but there is the lack of use of the of_node_put() when done. Add the missing of_node_put() to release the refcount. Signed-off-by: Yangtao Li <tiny.windzz@gmail.com> Fixes: e062b571777f ("clk: exynos4: register clocks using common clock framework") Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-26 21:32:15 +08:00
of_node_put(np);
clk: exynos: prepare for multiplatform The new common clock drivers for exynos are using compile time constants and soc_is_exynos* macros to provide backwards compatibility for pre-DT systems, which is not possible with multiplatform kernels. This moves all the necessary information back into platform code and removes the mach/* header inclusions. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Cc: Mike Turquette <mturquette@linaro.org>
2013-04-10 17:31:44 +08:00
}
return xom;
}
clk/samsung: add support for multiple clock providers Samsung CCF helper functions do not provide support to register multiple Clock Providers for a given SoC. Due to this limitation, SoC platforms are not able to use these helpers for registering multiple clock providers and are forced to bypass this layer. This layer is modified accordingly to enable the support for multiple clock providers. Clock file for exynos4, exynos5250, exynos5420, exynos5440, S3c64xx, S3c24xx are also modified as per changed helper functions. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> [t.figa: Modified s3c2410 clock driver as well] Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-03-12 22:56:44 +08:00
static void __init exynos4_clk_register_finpll(struct samsung_clk_provider *ctx)
clk: exynos: prepare for multiplatform The new common clock drivers for exynos are using compile time constants and soc_is_exynos* macros to provide backwards compatibility for pre-DT systems, which is not possible with multiplatform kernels. This moves all the necessary information back into platform code and removes the mach/* header inclusions. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Cc: Mike Turquette <mturquette@linaro.org>
2013-04-10 17:31:44 +08:00
{
struct samsung_fixed_rate_clock fclk;
struct clk *clk;
unsigned long finpll_f = 24000000;
char *parent_name;
clk: exynos4: Remove remnants of non-DT support This patch simplifies a bit clock initialization code by removing remnants of non-DT clock initialization, such as reg_base and xom values passed in function parameters. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.ab@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-02-14 07:16:00 +08:00
unsigned int xom = exynos4_get_xom();
clk: exynos: prepare for multiplatform The new common clock drivers for exynos are using compile time constants and soc_is_exynos* macros to provide backwards compatibility for pre-DT systems, which is not possible with multiplatform kernels. This moves all the necessary information back into platform code and removes the mach/* header inclusions. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Cc: Mike Turquette <mturquette@linaro.org>
2013-04-10 17:31:44 +08:00
parent_name = xom & 1 ? "xusbxti" : "xxti";
clk = clk_get(NULL, parent_name);
if (IS_ERR(clk)) {
pr_err("%s: failed to lookup parent clock %s, assuming "
"fin_pll clock frequency is 24MHz\n", __func__,
parent_name);
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
} else {
clk: exynos: prepare for multiplatform The new common clock drivers for exynos are using compile time constants and soc_is_exynos* macros to provide backwards compatibility for pre-DT systems, which is not possible with multiplatform kernels. This moves all the necessary information back into platform code and removes the mach/* header inclusions. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Cc: Mike Turquette <mturquette@linaro.org>
2013-04-10 17:31:44 +08:00
finpll_f = clk_get_rate(clk);
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
}
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
fclk.id = CLK_FIN_PLL;
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
fclk.name = "fin_pll";
fclk.parent_name = NULL;
clk: samsung: Remove CLK_IS_ROOT This flag is a no-op now. Remove usage of the flag. Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-02 02:59:58 +08:00
fclk.flags = 0;
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
fclk.fixed_rate = finpll_f;
clk/samsung: add support for multiple clock providers Samsung CCF helper functions do not provide support to register multiple Clock Providers for a given SoC. Due to this limitation, SoC platforms are not able to use these helpers for registering multiple clock providers and are forced to bypass this layer. This layer is modified accordingly to enable the support for multiple clock providers. Clock file for exynos4, exynos5250, exynos5420, exynos5440, S3c64xx, S3c24xx are also modified as per changed helper functions. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> [t.figa: Modified s3c2410 clock driver as well] Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-03-12 22:56:44 +08:00
samsung_clk_register_fixed_rate(ctx, &fclk, 1);
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
}
clk: samsung: Make of_device_id array const Array of struct of_device_id may be be const as expected by of_match_table field and of_find_matching_node_and_match() function. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Reviewed-by: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-06-26 20:00:06 +08:00
static const struct of_device_id ext_clk_match[] __initconst = {
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
{ .compatible = "samsung,clock-xxti", .data = (void *)0, },
{ .compatible = "samsung,clock-xusbxti", .data = (void *)1, },
{},
};
clk: samsung: exynos4: Register PLL rate tables for Exynos4210 This patch adds rate tables for PLLs that can be reconfigured at runtime for Exynos4210 SoCs. Provided tables contain PLL coefficients for input clock of 24 MHz and so are registered only in this case. MPLL does not need runtime reconfiguration and so table for it is not provided. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:09 +08:00
/* PLLs PMS values */
clk: samsung: exynos4: Constify all clock initializers All of initialization data can be made const. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2016-05-11 20:02:01 +08:00
static const struct samsung_pll_rate_table exynos4210_apll_rates[] __initconst = {
clk: samsung: Add compile time PLL rate validators Rates declared in PLL rate tables should match exactly rates calculated from PLL coefficients. To avoid possible mistakes we can use compile time validation. The patch introduces such validators and expands all initializers with additional input frequency parameter, required to validate rates. Since S3C24xx PLLs requires different validators two new macros have been introduced to deal with it. Also, since PLLs 4502 and 4508 have different formulas PLL_45XX_RATE has been replaced with PLL_4508_RATE. As the patch adds only compile time validators it should not have impact on compiled code. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Tomasz Figa <tomasz.figa@gmail.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2018-02-20 15:05:39 +08:00
PLL_4508_RATE(24 * MHZ, 1200000000, 150, 3, 1, 28),
PLL_4508_RATE(24 * MHZ, 1000000000, 250, 6, 1, 28),
PLL_4508_RATE(24 * MHZ, 800000000, 200, 6, 1, 28),
PLL_4508_RATE(24 * MHZ, 666857142, 389, 14, 1, 13),
PLL_4508_RATE(24 * MHZ, 600000000, 100, 4, 1, 13),
PLL_4508_RATE(24 * MHZ, 533000000, 533, 24, 1, 5),
PLL_4508_RATE(24 * MHZ, 500000000, 250, 6, 2, 28),
PLL_4508_RATE(24 * MHZ, 400000000, 200, 6, 2, 28),
PLL_4508_RATE(24 * MHZ, 200000000, 200, 6, 3, 28),
clk: samsung: exynos4: Register PLL rate tables for Exynos4210 This patch adds rate tables for PLLs that can be reconfigured at runtime for Exynos4210 SoCs. Provided tables contain PLL coefficients for input clock of 24 MHz and so are registered only in this case. MPLL does not need runtime reconfiguration and so table for it is not provided. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:09 +08:00
{ /* sentinel */ }
};
clk: samsung: exynos4: Constify all clock initializers All of initialization data can be made const. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2016-05-11 20:02:01 +08:00
static const struct samsung_pll_rate_table exynos4210_epll_rates[] __initconst = {
clk: samsung: Add compile time PLL rate validators Rates declared in PLL rate tables should match exactly rates calculated from PLL coefficients. To avoid possible mistakes we can use compile time validation. The patch introduces such validators and expands all initializers with additional input frequency parameter, required to validate rates. Since S3C24xx PLLs requires different validators two new macros have been introduced to deal with it. Also, since PLLs 4502 and 4508 have different formulas PLL_45XX_RATE has been replaced with PLL_4508_RATE. As the patch adds only compile time validators it should not have impact on compiled code. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Tomasz Figa <tomasz.figa@gmail.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2018-02-20 15:05:39 +08:00
PLL_4600_RATE(24 * MHZ, 192000000, 48, 3, 1, 0, 0),
PLL_4600_RATE(24 * MHZ, 180633605, 45, 3, 1, 10381, 0),
PLL_4600_RATE(24 * MHZ, 180000000, 45, 3, 1, 0, 0),
PLL_4600_RATE(24 * MHZ, 73727996, 73, 3, 3, 47710, 1),
PLL_4600_RATE(24 * MHZ, 67737602, 90, 4, 3, 20762, 1),
PLL_4600_RATE(24 * MHZ, 49151992, 49, 3, 3, 9961, 0),
PLL_4600_RATE(24 * MHZ, 45158401, 45, 3, 3, 10381, 0),
clk: samsung: exynos4: Register PLL rate tables for Exynos4210 This patch adds rate tables for PLLs that can be reconfigured at runtime for Exynos4210 SoCs. Provided tables contain PLL coefficients for input clock of 24 MHz and so are registered only in this case. MPLL does not need runtime reconfiguration and so table for it is not provided. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:09 +08:00
{ /* sentinel */ }
};
clk: samsung: exynos4: Constify all clock initializers All of initialization data can be made const. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2016-05-11 20:02:01 +08:00
static const struct samsung_pll_rate_table exynos4210_vpll_rates[] __initconst = {
clk: samsung: Add compile time PLL rate validators Rates declared in PLL rate tables should match exactly rates calculated from PLL coefficients. To avoid possible mistakes we can use compile time validation. The patch introduces such validators and expands all initializers with additional input frequency parameter, required to validate rates. Since S3C24xx PLLs requires different validators two new macros have been introduced to deal with it. Also, since PLLs 4502 and 4508 have different formulas PLL_45XX_RATE has been replaced with PLL_4508_RATE. As the patch adds only compile time validators it should not have impact on compiled code. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Tomasz Figa <tomasz.figa@gmail.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2018-02-20 15:05:39 +08:00
PLL_4650_RATE(24 * MHZ, 360000000, 44, 3, 0, 1024, 0, 14, 0),
PLL_4650_RATE(24 * MHZ, 324000000, 53, 2, 1, 1024, 1, 1, 1),
PLL_4650_RATE(24 * MHZ, 259617187, 63, 3, 1, 1950, 0, 20, 1),
PLL_4650_RATE(24 * MHZ, 110000000, 53, 3, 2, 2048, 0, 17, 0),
PLL_4650_RATE(24 * MHZ, 55360351, 53, 3, 3, 2417, 0, 17, 0),
clk: samsung: exynos4: Register PLL rate tables for Exynos4210 This patch adds rate tables for PLLs that can be reconfigured at runtime for Exynos4210 SoCs. Provided tables contain PLL coefficients for input clock of 24 MHz and so are registered only in this case. MPLL does not need runtime reconfiguration and so table for it is not provided. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:09 +08:00
{ /* sentinel */ }
};
clk: samsung: exynos4: Constify all clock initializers All of initialization data can be made const. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2016-05-11 20:02:01 +08:00
static const struct samsung_pll_rate_table exynos4x12_apll_rates[] __initconst = {
clk: samsung: Add compile time PLL rate validators Rates declared in PLL rate tables should match exactly rates calculated from PLL coefficients. To avoid possible mistakes we can use compile time validation. The patch introduces such validators and expands all initializers with additional input frequency parameter, required to validate rates. Since S3C24xx PLLs requires different validators two new macros have been introduced to deal with it. Also, since PLLs 4502 and 4508 have different formulas PLL_45XX_RATE has been replaced with PLL_4508_RATE. As the patch adds only compile time validators it should not have impact on compiled code. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Tomasz Figa <tomasz.figa@gmail.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2018-02-20 15:05:39 +08:00
PLL_35XX_RATE(24 * MHZ, 1704000000, 213, 3, 0),
PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0),
PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0),
PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0),
PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0),
PLL_35XX_RATE(24 * MHZ, 1200000000, 200, 4, 0),
PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 6, 0),
PLL_35XX_RATE(24 * MHZ, 1000000000, 125, 3, 0),
PLL_35XX_RATE(24 * MHZ, 900000000, 150, 4, 0),
PLL_35XX_RATE(24 * MHZ, 800000000, 100, 3, 0),
PLL_35XX_RATE(24 * MHZ, 700000000, 175, 3, 1),
PLL_35XX_RATE(24 * MHZ, 600000000, 200, 4, 1),
PLL_35XX_RATE(24 * MHZ, 500000000, 125, 3, 1),
PLL_35XX_RATE(24 * MHZ, 400000000, 100, 3, 1),
PLL_35XX_RATE(24 * MHZ, 300000000, 200, 4, 2),
PLL_35XX_RATE(24 * MHZ, 200000000, 100, 3, 2),
clk: samsung: exynos4: Register PLL rate tables for Exynos4x12 This patch adds rate tables for PLLs that can be reconfigured at runtime for Exynos4x12 SoCs. Provided tables contain PLL coefficients for input clock of 24 MHz and so are registered only in this case. MPLL does not need runtime reconfiguration and so table for it is not provided. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:10 +08:00
{ /* sentinel */ }
};
clk: samsung: exynos4: Constify all clock initializers All of initialization data can be made const. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2016-05-11 20:02:01 +08:00
static const struct samsung_pll_rate_table exynos4x12_epll_rates[] __initconst = {
clk: samsung: Add fout=196608001 Hz EPLL rate entry for exynos4412 This additional frequency is required for HDMI audio support on Odroid U3 board. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2018-03-14 19:32:26 +08:00
PLL_36XX_RATE(24 * MHZ, 196608001, 197, 3, 3, -25690),
clk: samsung: Add compile time PLL rate validators Rates declared in PLL rate tables should match exactly rates calculated from PLL coefficients. To avoid possible mistakes we can use compile time validation. The patch introduces such validators and expands all initializers with additional input frequency parameter, required to validate rates. Since S3C24xx PLLs requires different validators two new macros have been introduced to deal with it. Also, since PLLs 4502 and 4508 have different formulas PLL_45XX_RATE has been replaced with PLL_4508_RATE. As the patch adds only compile time validators it should not have impact on compiled code. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Tomasz Figa <tomasz.figa@gmail.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2018-02-20 15:05:39 +08:00
PLL_36XX_RATE(24 * MHZ, 192000000, 48, 3, 1, 0),
PLL_36XX_RATE(24 * MHZ, 180633605, 45, 3, 1, 10381),
PLL_36XX_RATE(24 * MHZ, 180000000, 45, 3, 1, 0),
PLL_36XX_RATE(24 * MHZ, 73727996, 73, 3, 3, 47710),
PLL_36XX_RATE(24 * MHZ, 67737602, 90, 4, 3, 20762),
PLL_36XX_RATE(24 * MHZ, 49151992, 49, 3, 3, 9961),
PLL_36XX_RATE(24 * MHZ, 45158401, 45, 3, 3, 10381),
clk: samsung: exynos4: Register PLL rate tables for Exynos4x12 This patch adds rate tables for PLLs that can be reconfigured at runtime for Exynos4x12 SoCs. Provided tables contain PLL coefficients for input clock of 24 MHz and so are registered only in this case. MPLL does not need runtime reconfiguration and so table for it is not provided. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:10 +08:00
{ /* sentinel */ }
};
clk: samsung: exynos4: Constify all clock initializers All of initialization data can be made const. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2016-05-11 20:02:01 +08:00
static const struct samsung_pll_rate_table exynos4x12_vpll_rates[] __initconst = {
clk: samsung: Add compile time PLL rate validators Rates declared in PLL rate tables should match exactly rates calculated from PLL coefficients. To avoid possible mistakes we can use compile time validation. The patch introduces such validators and expands all initializers with additional input frequency parameter, required to validate rates. Since S3C24xx PLLs requires different validators two new macros have been introduced to deal with it. Also, since PLLs 4502 and 4508 have different formulas PLL_45XX_RATE has been replaced with PLL_4508_RATE. As the patch adds only compile time validators it should not have impact on compiled code. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Tomasz Figa <tomasz.figa@gmail.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2018-02-20 15:05:39 +08:00
PLL_36XX_RATE(24 * MHZ, 533000000, 133, 3, 1, 16384),
PLL_36XX_RATE(24 * MHZ, 440000000, 110, 3, 1, 0),
PLL_36XX_RATE(24 * MHZ, 350000000, 175, 3, 2, 0),
PLL_36XX_RATE(24 * MHZ, 266000000, 133, 3, 2, 0),
PLL_36XX_RATE(24 * MHZ, 160000000, 160, 3, 3, 0),
PLL_36XX_RATE(24 * MHZ, 106031250, 53, 3, 2, 1024),
PLL_36XX_RATE(24 * MHZ, 53015625, 53, 3, 3, 1024),
clk: samsung: exynos4: Register PLL rate tables for Exynos4x12 This patch adds rate tables for PLLs that can be reconfigured at runtime for Exynos4x12 SoCs. Provided tables contain PLL coefficients for input clock of 24 MHz and so are registered only in this case. MPLL does not need runtime reconfiguration and so table for it is not provided. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:10 +08:00
{ /* sentinel */ }
};
clk: samsung: pll: Use new registration method for PLL46xx This patch modifies PLL46xx support code and its users to use the recently introduced common PLL registration helper. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:06 +08:00
static struct samsung_pll_clock exynos4210_plls[nr_plls] __initdata = {
clk: samsung: Remove clkdev alias support in Exynos4 clk driver All Exynos4 boards have been fully converted to device-tree and use generic dt-based CPUfreq driver, so there is no need to create any clkdev aliases for the clocks. Drop all the code related to aliases handling. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2017-10-03 18:00:09 +08:00
[apll] = PLL(pll_4508, CLK_FOUT_APLL, "fout_apll", "fin_pll",
APLL_LOCK, APLL_CON0, NULL),
[mpll] = PLL(pll_4508, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
E4210_MPLL_LOCK, E4210_MPLL_CON0, NULL),
[epll] = PLL(pll_4600, CLK_FOUT_EPLL, "fout_epll", "fin_pll",
EPLL_LOCK, EPLL_CON0, NULL),
[vpll] = PLL(pll_4650c, CLK_FOUT_VPLL, "fout_vpll", "mout_vpllsrc",
VPLL_LOCK, VPLL_CON0, NULL),
clk: samsung: pll: Use new registration method for PLL45xx This patch modifies PLL45xx support code and its users to use the recently introduced common PLL registration helper. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:04 +08:00
};
clk: samsung: exynos4: Rename exynos4_plls to exynos4x12_plls This array defines PLLs specific to Exynos 4x12 SoCs and not for all Exynos 4 SoCs, so the name should represent that. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:03 +08:00
static struct samsung_pll_clock exynos4x12_plls[nr_plls] __initdata = {
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
[apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll",
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
APLL_LOCK, APLL_CON0, NULL),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
[mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
E4X12_MPLL_LOCK, E4X12_MPLL_CON0, NULL),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
[epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll",
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
EPLL_LOCK, EPLL_CON0, NULL),
clk: exynos4: replace clock ID private enums with IDs from DT header The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-07 22:47:31 +08:00
[vpll] = PLL(pll_36xx, CLK_FOUT_VPLL, "fout_vpll", "fin_pll",
clk: samsung: exynos4: Remove unused static clkdev aliases Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:01 +08:00
VPLL_LOCK, VPLL_CON0, NULL),
clk: samsung: Migrate exynos4 to use common samsung_clk_register_pll() This patch migrates exynos4 pll registeration to use common samsung_clk_register_pll() by intialising table of PLLs. Signed-off-by: Yadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: Vikas Sajjan <vikas.sajjan@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-11 17:31:09 +08:00
};
clk: samsung: exynos4: Disable ARMCLK down feature on Exynos4210 SoC Commit 42773b28e71d ("clk: samsung: exynos4: Enable ARMCLK down feature") enabled ARMCLK down feature on all Exynos4 SoCs. Unfortunately on Exynos4210 SoC ARMCLK down feature causes a lockup when ondemand cpufreq governor is used. Fix it by limiting ARMCLK down feature to Exynos4x12 SoCs. This patch was tested on: - Exynos4210 SoC based Trats board - Exynos4210 SoC based Origen board - Exynos4412 SoC based Trats2 board - Exynos4412 SoC based Odroid-U3 board Cc: Daniel Drake <drake@endlessm.com> Cc: Tomasz Figa <t.figa@samsung.com> Cc: Kukjin Kim <kgene@kernel.org> Fixes: 42773b28e71d ("clk: samsung: exynos4: Enable ARMCLK down feature") Cc: <stable@vger.kernel.org> # v3.17+ Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-03-28 00:27:10 +08:00
static void __init exynos4x12_core_down_clock(void)
clk: samsung: exynos4: Enable ARMCLK down feature Enable ARMCLK down feature on all Exynos4 SoCs. The frequency of ARMCLK will be reduced upon entering idle mode (WFI or WFE). The feature behaves like very fast cpufreq ondemand governor. In idle mode this reduces energy consumption on full frequency chosen by cpufreq governor by approximately: - Trats2: 6.5% (153 mA -> 143 mA) - Trats: 33.0% (180 mA -> 120 mA) - Gear1: 27.0% (180 mA -> 130 mA) The patch uses simillar settings as Exynos5250 (clk-exynos5250.c), except it disables clock up feature and on Exynos4412 ARMCLK down is enabled for all 4 cores. Tested on Trats board (Exynos4210), Trats2 board (Exynos4412) and Samsung Gear 1 (Exynos4212). Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Tested-by: Daniel Drake <drake@endlessm.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-07-18 22:36:32 +08:00
{
unsigned int tmp;
/*
* Enable arm clock down (in idle) and set arm divider
* ratios in WFI/WFE state.
*/
tmp = (PWR_CTRL1_CORE2_DOWN_RATIO(7) | PWR_CTRL1_CORE1_DOWN_RATIO(7) |
PWR_CTRL1_DIV2_DOWN_EN | PWR_CTRL1_DIV1_DOWN_EN |
PWR_CTRL1_USE_CORE1_WFE | PWR_CTRL1_USE_CORE0_WFE |
PWR_CTRL1_USE_CORE1_WFI | PWR_CTRL1_USE_CORE0_WFI);
/* On Exynos4412 enable it also on core 2 and 3 */
if (num_possible_cpus() == 4)
tmp |= PWR_CTRL1_USE_CORE3_WFE | PWR_CTRL1_USE_CORE2_WFE |
PWR_CTRL1_USE_CORE3_WFI | PWR_CTRL1_USE_CORE2_WFI;
clk: samsung: exynos4: fixup reg access on be Use the byte-order aware big endian accessors, allowing for kernels running under big-endian. Signed-off-by: Matthew Leach <matthew@mattleach.net> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2016-06-09 02:30:58 +08:00
writel_relaxed(tmp, reg_base + PWR_CTRL1);
clk: samsung: exynos4: Enable ARMCLK down feature Enable ARMCLK down feature on all Exynos4 SoCs. The frequency of ARMCLK will be reduced upon entering idle mode (WFI or WFE). The feature behaves like very fast cpufreq ondemand governor. In idle mode this reduces energy consumption on full frequency chosen by cpufreq governor by approximately: - Trats2: 6.5% (153 mA -> 143 mA) - Trats: 33.0% (180 mA -> 120 mA) - Gear1: 27.0% (180 mA -> 130 mA) The patch uses simillar settings as Exynos5250 (clk-exynos5250.c), except it disables clock up feature and on Exynos4412 ARMCLK down is enabled for all 4 cores. Tested on Trats board (Exynos4210), Trats2 board (Exynos4412) and Samsung Gear 1 (Exynos4212). Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Tested-by: Daniel Drake <drake@endlessm.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-07-18 22:36:32 +08:00
/*
clk: samsung: exynos4: Disable ARMCLK down feature on Exynos4210 SoC Commit 42773b28e71d ("clk: samsung: exynos4: Enable ARMCLK down feature") enabled ARMCLK down feature on all Exynos4 SoCs. Unfortunately on Exynos4210 SoC ARMCLK down feature causes a lockup when ondemand cpufreq governor is used. Fix it by limiting ARMCLK down feature to Exynos4x12 SoCs. This patch was tested on: - Exynos4210 SoC based Trats board - Exynos4210 SoC based Origen board - Exynos4412 SoC based Trats2 board - Exynos4412 SoC based Odroid-U3 board Cc: Daniel Drake <drake@endlessm.com> Cc: Tomasz Figa <t.figa@samsung.com> Cc: Kukjin Kim <kgene@kernel.org> Fixes: 42773b28e71d ("clk: samsung: exynos4: Enable ARMCLK down feature") Cc: <stable@vger.kernel.org> # v3.17+ Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-03-28 00:27:10 +08:00
* Disable the clock up feature in case it was enabled by bootloader.
clk: samsung: exynos4: Enable ARMCLK down feature Enable ARMCLK down feature on all Exynos4 SoCs. The frequency of ARMCLK will be reduced upon entering idle mode (WFI or WFE). The feature behaves like very fast cpufreq ondemand governor. In idle mode this reduces energy consumption on full frequency chosen by cpufreq governor by approximately: - Trats2: 6.5% (153 mA -> 143 mA) - Trats: 33.0% (180 mA -> 120 mA) - Gear1: 27.0% (180 mA -> 130 mA) The patch uses simillar settings as Exynos5250 (clk-exynos5250.c), except it disables clock up feature and on Exynos4412 ARMCLK down is enabled for all 4 cores. Tested on Trats board (Exynos4210), Trats2 board (Exynos4412) and Samsung Gear 1 (Exynos4212). Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Tested-by: Daniel Drake <drake@endlessm.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-07-18 22:36:32 +08:00
*/
clk: samsung: exynos4: fixup reg access on be Use the byte-order aware big endian accessors, allowing for kernels running under big-endian. Signed-off-by: Matthew Leach <matthew@mattleach.net> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2016-06-09 02:30:58 +08:00
writel_relaxed(0x0, reg_base + E4X12_PWR_CTRL2);
clk: samsung: exynos4: Enable ARMCLK down feature Enable ARMCLK down feature on all Exynos4 SoCs. The frequency of ARMCLK will be reduced upon entering idle mode (WFI or WFE). The feature behaves like very fast cpufreq ondemand governor. In idle mode this reduces energy consumption on full frequency chosen by cpufreq governor by approximately: - Trats2: 6.5% (153 mA -> 143 mA) - Trats: 33.0% (180 mA -> 120 mA) - Gear1: 27.0% (180 mA -> 130 mA) The patch uses simillar settings as Exynos5250 (clk-exynos5250.c), except it disables clock up feature and on Exynos4412 ARMCLK down is enabled for all 4 cores. Tested on Trats board (Exynos4210), Trats2 board (Exynos4412) and Samsung Gear 1 (Exynos4212). Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Tested-by: Daniel Drake <drake@endlessm.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-07-18 22:36:32 +08:00
}
clk: samsung: exynos4: add cpu clock configuration data and instantiate cpu clock With the addition of the new Samsung specific cpu-clock type, the arm clock can be represented as a cpu-clock type. Add the CPU clock configuration data and instantiate the CPU clock type for Exynos4210. Changes by Bartlomiej: - fixed issue with wrong dividers being setup by Common Clock Framework (by an addition of CLK_RECALC_NEW_RATES clock flag to mout_apll clock, without this change cpufreq-dt driver showed ~10 mA larger energy consumption when compared to cpufreq-exynos one when "performance" cpufreq governor was used on Exynos4210 SoC based Origen board), this was probably meant to be workarounded by use of CLK_GET_RATE_NOCACHE and CLK_DIVIDER_READ_ONLY clock flags in the original patchset (in "[PATCH v12 6/6] clk: samsung: remove unused clock aliases and update clock flags") but using these flags is not sufficient to fix the issue observed - removed Exynos5250 and Exynos5420 support for now Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Mike Turquette <mturquette@linaro.org> Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-04-04 00:43:46 +08:00
#define E4210_CPU_DIV0(apll, pclk_dbg, atb, periph, corem1, corem0) \
(((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \
((periph) << 12) | ((corem1) << 8) | ((corem0) << 4))
#define E4210_CPU_DIV1(hpm, copy) \
(((hpm) << 4) | ((copy) << 0))
static const struct exynos_cpuclk_cfg_data e4210_armclk_d[] __initconst = {
{ 1200000, E4210_CPU_DIV0(7, 1, 4, 3, 7, 3), E4210_CPU_DIV1(0, 5), },
{ 1000000, E4210_CPU_DIV0(7, 1, 4, 3, 7, 3), E4210_CPU_DIV1(0, 4), },
{ 800000, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), },
{ 500000, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), },
{ 400000, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), },
{ 200000, E4210_CPU_DIV0(0, 1, 1, 1, 3, 1), E4210_CPU_DIV1(0, 3), },
{ 0 },
};
clk: samsung: Re-add support for Exynos4212 CPU clock Support for the Exynos4212 SoC was originally dropped as there were no boards using it. We will be adding a device that uses it, so add it back. This reverts commit c9194fb623b0158029a268376df09fe28a2a2b05. Signed-off-by: Artur Weber <aweber.kernel@gmail.com> Link: https://lore.kernel.org/r/20230501195525.6268-7-aweber.kernel@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2023-05-02 03:55:18 +08:00
static const struct exynos_cpuclk_cfg_data e4212_armclk_d[] __initconst = {
{ 1500000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4210_CPU_DIV1(2, 6), },
{ 1400000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4210_CPU_DIV1(2, 6), },
{ 1300000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4210_CPU_DIV1(2, 5), },
{ 1200000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4210_CPU_DIV1(2, 5), },
{ 1100000, E4210_CPU_DIV0(2, 1, 4, 0, 6, 3), E4210_CPU_DIV1(2, 4), },
{ 1000000, E4210_CPU_DIV0(1, 1, 4, 0, 5, 2), E4210_CPU_DIV1(2, 4), },
{ 900000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4210_CPU_DIV1(2, 3), },
{ 800000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4210_CPU_DIV1(2, 3), },
{ 700000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
{ 600000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
{ 500000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
{ 400000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
{ 300000, E4210_CPU_DIV0(1, 1, 2, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
{ 200000, E4210_CPU_DIV0(1, 1, 1, 0, 3, 1), E4210_CPU_DIV1(2, 3), },
{ 0 },
};
clk: exynos4x12: add cpu clock configuration data and instantiate cpu clock With the addition of the new Samsung specific cpu-clock type, the arm clock can be represented as a cpu-clock type. Add the CPU clock configuration data and instantiate the CPU clock type for Exynos4x12. Based on the earlier work by Thomas Abraham. Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Thomas Abraham <thomas.ab@samsung.com> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Tested-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Kukjin Kim <kgene@kernel.org>
2015-08-12 06:36:47 +08:00
#define E4412_CPU_DIV1(cores, hpm, copy) \
(((cores) << 8) | ((hpm) << 4) | ((copy) << 0))
static const struct exynos_cpuclk_cfg_data e4412_armclk_d[] __initconst = {
clk: samsung: Add CPU clk configuration data for Exynos4412 Prime Add cpu clock configuration data for Exynos4412 Prime SoC (it supports additional PLL rates & CPU frequencies). Based on Hardkernel's kernel for ODROID-X2/U2/U3 boards. Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2016-12-29 21:36:50 +08:00
{ 1704000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(7, 0, 7), },
{ 1600000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(7, 0, 6), },
clk: exynos4x12: add cpu clock configuration data and instantiate cpu clock With the addition of the new Samsung specific cpu-clock type, the arm clock can be represented as a cpu-clock type. Add the CPU clock configuration data and instantiate the CPU clock type for Exynos4x12. Based on the earlier work by Thomas Abraham. Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Thomas Abraham <thomas.ab@samsung.com> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Tested-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Kukjin Kim <kgene@kernel.org>
2015-08-12 06:36:47 +08:00
{ 1500000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(7, 0, 6), },
{ 1400000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(6, 0, 6), },
{ 1300000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4412_CPU_DIV1(6, 0, 5), },
{ 1200000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4412_CPU_DIV1(5, 0, 5), },
{ 1100000, E4210_CPU_DIV0(2, 1, 4, 0, 6, 3), E4412_CPU_DIV1(5, 0, 4), },
{ 1000000, E4210_CPU_DIV0(1, 1, 4, 0, 5, 2), E4412_CPU_DIV1(4, 0, 4), },
{ 900000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4412_CPU_DIV1(4, 0, 3), },
{ 800000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4412_CPU_DIV1(3, 0, 3), },
{ 700000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(3, 0, 3), },
{ 600000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(2, 0, 3), },
{ 500000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(2, 0, 3), },
{ 400000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(1, 0, 3), },
{ 300000, E4210_CPU_DIV0(1, 1, 2, 0, 4, 2), E4412_CPU_DIV1(1, 0, 3), },
{ 200000, E4210_CPU_DIV0(1, 1, 1, 0, 3, 1), E4412_CPU_DIV1(0, 0, 3), },
{ 0 },
};
clk: samsung: Update CPU clk registration Convert the remaining exynos clock drivers to use samsung_clk_register_cpu() or if possible use samsung_cmu_register_one(). With this we can now make exynos_register_cpu_clock() a static function so that future CPU clock registration changes will use the samsung common clock driver. The main benefit of this change is that it standardizes the CPU clock registration for the samsung clock drivers. Link: https://lore.kernel.org/r/20211015190515.3760577-1-willmcvicker@google.com Signed-off-by: Will McVicker <willmcvicker@google.com> Tested-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> [snawrocki@kernel.org: Fixed build break in clk-exynos4.c, clk-exynos5250.c] Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2021-10-16 03:05:14 +08:00
static const struct samsung_cpu_clock exynos4210_cpu_clks[] __initconst = {
CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_SCLK_MPLL,
clk: samsung: Pass actual CPU clock registers base to CPU_CLK() The documentation for struct exynos_cpuclk says .ctrl_base field should contain the controller base address. There are two different problems with that: 1. All Exynos clock drivers are actually passing CPU_SRC register offset via CPU_CLK() macro, which in turn gets assigned to mentioned .ctrl_base field. Because CPU_SRC register usually already has 0x200 offset from controller's base, all other register offsets in clk-cpu.c (like DIVs and MUXes) are specified as offsets from CPU_SRC offset, and not from controller's base. That makes things confusing and inconsistent with register offsets provided in Exynos clock drivers, also breaking the contract for .ctrl_base field as described in struct exynos_cpuclk doc. 2. Furthermore, some Exynos chips have an additional offset for the start of CPU clock registers block (inside of the CMU). There might be different reasons for that, e.g.: - The CMU contains clocks for two different CPUs (like in Exynos5420) - The CMU contains also non-CPU clocks as well (like in Exynos4) - The CPU CMU exists as a dedicated hardware block in the SoC layout, but is modelled as a part of bigger CMU in the driver (like in case of Exynos3250) That means the .ctrl_base field is actually not a controller's base, but instead it's a start address of the CPU clock registers inside of the CMU. Rework all register offsets in clk-cpu.c to be actual offsets from the CPU clock register block start, and fix offsets provided to CPU_CLK() macro in all Exynos clock drivers. Also clarify the .ctrl_base field documentation and rename it to just .base, because it doesn't really contain the CMU base. No functional change. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20240224202053.25313-8-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-02-25 04:20:45 +08:00
CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1, 0x14000,
clk: samsung: Pass register layout type explicitly to CLK_CPU() Use a dedicated enum field to explicitly specify which register layout should be used for the CPU clock, instead of passing it as a bit flag. This way it would be possible to keep the chip-specific data in some array, where each chip structure could be accessed by its corresponding layout index. It prepares clk-cpu.c for adding new chips support, which might have different data for different CPU clusters. No functional change. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20240224202053.25313-9-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-02-25 04:20:46 +08:00
CPUCLK_LAYOUT_E4210, e4210_armclk_d),
clk: samsung: Update CPU clk registration Convert the remaining exynos clock drivers to use samsung_clk_register_cpu() or if possible use samsung_cmu_register_one(). With this we can now make exynos_register_cpu_clock() a static function so that future CPU clock registration changes will use the samsung common clock driver. The main benefit of this change is that it standardizes the CPU clock registration for the samsung clock drivers. Link: https://lore.kernel.org/r/20211015190515.3760577-1-willmcvicker@google.com Signed-off-by: Will McVicker <willmcvicker@google.com> Tested-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> [snawrocki@kernel.org: Fixed build break in clk-exynos4.c, clk-exynos5250.c] Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2021-10-16 03:05:14 +08:00
};
clk: samsung: Re-add support for Exynos4212 CPU clock Support for the Exynos4212 SoC was originally dropped as there were no boards using it. We will be adding a device that uses it, so add it back. This reverts commit c9194fb623b0158029a268376df09fe28a2a2b05. Signed-off-by: Artur Weber <aweber.kernel@gmail.com> Link: https://lore.kernel.org/r/20230501195525.6268-7-aweber.kernel@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2023-05-02 03:55:18 +08:00
static const struct samsung_cpu_clock exynos4212_cpu_clks[] __initconst = {
CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MPLL_USER_C,
clk: samsung: Pass actual CPU clock registers base to CPU_CLK() The documentation for struct exynos_cpuclk says .ctrl_base field should contain the controller base address. There are two different problems with that: 1. All Exynos clock drivers are actually passing CPU_SRC register offset via CPU_CLK() macro, which in turn gets assigned to mentioned .ctrl_base field. Because CPU_SRC register usually already has 0x200 offset from controller's base, all other register offsets in clk-cpu.c (like DIVs and MUXes) are specified as offsets from CPU_SRC offset, and not from controller's base. That makes things confusing and inconsistent with register offsets provided in Exynos clock drivers, also breaking the contract for .ctrl_base field as described in struct exynos_cpuclk doc. 2. Furthermore, some Exynos chips have an additional offset for the start of CPU clock registers block (inside of the CMU). There might be different reasons for that, e.g.: - The CMU contains clocks for two different CPUs (like in Exynos5420) - The CMU contains also non-CPU clocks as well (like in Exynos4) - The CPU CMU exists as a dedicated hardware block in the SoC layout, but is modelled as a part of bigger CMU in the driver (like in case of Exynos3250) That means the .ctrl_base field is actually not a controller's base, but instead it's a start address of the CPU clock registers inside of the CMU. Rework all register offsets in clk-cpu.c to be actual offsets from the CPU clock register block start, and fix offsets provided to CPU_CLK() macro in all Exynos clock drivers. Also clarify the .ctrl_base field documentation and rename it to just .base, because it doesn't really contain the CMU base. No functional change. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20240224202053.25313-8-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-02-25 04:20:45 +08:00
CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1, 0x14000,
clk: samsung: Pass register layout type explicitly to CLK_CPU() Use a dedicated enum field to explicitly specify which register layout should be used for the CPU clock, instead of passing it as a bit flag. This way it would be possible to keep the chip-specific data in some array, where each chip structure could be accessed by its corresponding layout index. It prepares clk-cpu.c for adding new chips support, which might have different data for different CPU clusters. No functional change. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20240224202053.25313-9-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-02-25 04:20:46 +08:00
CPUCLK_LAYOUT_E4210, e4212_armclk_d),
clk: samsung: Re-add support for Exynos4212 CPU clock Support for the Exynos4212 SoC was originally dropped as there were no boards using it. We will be adding a device that uses it, so add it back. This reverts commit c9194fb623b0158029a268376df09fe28a2a2b05. Signed-off-by: Artur Weber <aweber.kernel@gmail.com> Link: https://lore.kernel.org/r/20230501195525.6268-7-aweber.kernel@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2023-05-02 03:55:18 +08:00
};
clk: samsung: Update CPU clk registration Convert the remaining exynos clock drivers to use samsung_clk_register_cpu() or if possible use samsung_cmu_register_one(). With this we can now make exynos_register_cpu_clock() a static function so that future CPU clock registration changes will use the samsung common clock driver. The main benefit of this change is that it standardizes the CPU clock registration for the samsung clock drivers. Link: https://lore.kernel.org/r/20211015190515.3760577-1-willmcvicker@google.com Signed-off-by: Will McVicker <willmcvicker@google.com> Tested-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> [snawrocki@kernel.org: Fixed build break in clk-exynos4.c, clk-exynos5250.c] Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2021-10-16 03:05:14 +08:00
static const struct samsung_cpu_clock exynos4412_cpu_clks[] __initconst = {
CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MPLL_USER_C,
clk: samsung: Pass actual CPU clock registers base to CPU_CLK() The documentation for struct exynos_cpuclk says .ctrl_base field should contain the controller base address. There are two different problems with that: 1. All Exynos clock drivers are actually passing CPU_SRC register offset via CPU_CLK() macro, which in turn gets assigned to mentioned .ctrl_base field. Because CPU_SRC register usually already has 0x200 offset from controller's base, all other register offsets in clk-cpu.c (like DIVs and MUXes) are specified as offsets from CPU_SRC offset, and not from controller's base. That makes things confusing and inconsistent with register offsets provided in Exynos clock drivers, also breaking the contract for .ctrl_base field as described in struct exynos_cpuclk doc. 2. Furthermore, some Exynos chips have an additional offset for the start of CPU clock registers block (inside of the CMU). There might be different reasons for that, e.g.: - The CMU contains clocks for two different CPUs (like in Exynos5420) - The CMU contains also non-CPU clocks as well (like in Exynos4) - The CPU CMU exists as a dedicated hardware block in the SoC layout, but is modelled as a part of bigger CMU in the driver (like in case of Exynos3250) That means the .ctrl_base field is actually not a controller's base, but instead it's a start address of the CPU clock registers inside of the CMU. Rework all register offsets in clk-cpu.c to be actual offsets from the CPU clock register block start, and fix offsets provided to CPU_CLK() macro in all Exynos clock drivers. Also clarify the .ctrl_base field documentation and rename it to just .base, because it doesn't really contain the CMU base. No functional change. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20240224202053.25313-8-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-02-25 04:20:45 +08:00
CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1, 0x14000,
clk: samsung: Pass register layout type explicitly to CLK_CPU() Use a dedicated enum field to explicitly specify which register layout should be used for the CPU clock, instead of passing it as a bit flag. This way it would be possible to keep the chip-specific data in some array, where each chip structure could be accessed by its corresponding layout index. It prepares clk-cpu.c for adding new chips support, which might have different data for different CPU clusters. No functional change. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20240224202053.25313-9-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-02-25 04:20:46 +08:00
CPUCLK_LAYOUT_E4210, e4412_armclk_d),
clk: samsung: Update CPU clk registration Convert the remaining exynos clock drivers to use samsung_clk_register_cpu() or if possible use samsung_cmu_register_one(). With this we can now make exynos_register_cpu_clock() a static function so that future CPU clock registration changes will use the samsung common clock driver. The main benefit of this change is that it standardizes the CPU clock registration for the samsung clock drivers. Link: https://lore.kernel.org/r/20211015190515.3760577-1-willmcvicker@google.com Signed-off-by: Will McVicker <willmcvicker@google.com> Tested-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> [snawrocki@kernel.org: Fixed build break in clk-exynos4.c, clk-exynos5250.c] Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2021-10-16 03:05:14 +08:00
};
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
/* register exynos4 clocks */
clk: exynos4: Staticize local symbols Symbols referenced only in this file are made static. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-07-18 18:01:17 +08:00
static void __init exynos4_clk_init(struct device_node *np,
clk: samsung: exynos4: Move suspend/resume handling to SoC driver Since there are multiple differences in how suspend/resume of particular Exynos SoCs must be handled, SoC driver is better place for suspend/resume handlers and so this patch moves them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.ab@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-02-14 07:16:00 +08:00
enum exynos4_soc soc)
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
{
clk/samsung: add support for multiple clock providers Samsung CCF helper functions do not provide support to register multiple Clock Providers for a given SoC. Due to this limitation, SoC platforms are not able to use these helpers for registering multiple clock providers and are forced to bypass this layer. This layer is modified accordingly to enable the support for multiple clock providers. Clock file for exynos4, exynos5250, exynos5420, exynos5440, S3c64xx, S3c24xx are also modified as per changed helper functions. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> [t.figa: Modified s3c2410 clock driver as well] Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-03-12 22:56:44 +08:00
struct samsung_clk_provider *ctx;
clk: samsung: Use cached clk_hws instead of __clk_lookup() calls For the CPU clock registration two parent clocks are required, these are now being passed as struct clk_hw pointers, rather than by the global scope names. That allows us to avoid __clk_lookup() calls and simplifies a bit the CPU clock registration function. While at it drop unneeded extern keyword in the function declaration. Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Link: https://lore.kernel.org/r/20200826171529.23618-3-s.nawrocki@samsung.com Reported-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2020-08-27 01:15:29 +08:00
struct clk_hw **hws;
clk: samsung: exynos4: Move suspend/resume handling to SoC driver Since there are multiple differences in how suspend/resume of particular Exynos SoCs must be handled, SoC driver is better place for suspend/resume handlers and so this patch moves them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.ab@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-02-14 07:16:00 +08:00
exynos4_soc = soc;
clk: exynos4: Remove remnants of non-DT support This patch simplifies a bit clock initialization code by removing remnants of non-DT clock initialization, such as reg_base and xom values passed in function parameters. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.ab@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-02-14 07:16:00 +08:00
clk: samsung: exynos4: Remove checks for DT node Exynos 4 supports only DT based bootup, so non-DT cases does not need to be handled anymore. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:02 +08:00
reg_base = of_iomap(np, 0);
if (!reg_base)
panic("%s: failed to map registers\n", __func__);
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
clk: samsung: exynos4: do not define number of clocks in bindings Number of clocks supported by Linux drivers might vary - sometimes we add new clocks, not exposed previously. Therefore these numbers of clocks should not be in the bindings, as that prevents changing them. Define number of clocks per each clock controller inside the driver directly. Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Link: https://lore.kernel.org/r/20230808082738.122804-3-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2023-08-08 16:27:29 +08:00
ctx = samsung_clk_init(NULL, reg_base, CLKS_NR);
clk: samsung: Use cached clk_hws instead of __clk_lookup() calls For the CPU clock registration two parent clocks are required, these are now being passed as struct clk_hw pointers, rather than by the global scope names. That allows us to avoid __clk_lookup() calls and simplifies a bit the CPU clock registration function. While at it drop unneeded extern keyword in the function declaration. Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Link: https://lore.kernel.org/r/20200826171529.23618-3-s.nawrocki@samsung.com Reported-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2020-08-27 01:15:29 +08:00
hws = ctx->clk_data.hws;
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
clk/samsung: add support for multiple clock providers Samsung CCF helper functions do not provide support to register multiple Clock Providers for a given SoC. Due to this limitation, SoC platforms are not able to use these helpers for registering multiple clock providers and are forced to bypass this layer. This layer is modified accordingly to enable the support for multiple clock providers. Clock file for exynos4, exynos5250, exynos5420, exynos5440, S3c64xx, S3c24xx are also modified as per changed helper functions. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> [t.figa: Modified s3c2410 clock driver as well] Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-03-12 22:56:44 +08:00
samsung_clk_of_register_fixed_ext(ctx, exynos4_fixed_rate_ext_clks,
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
ARRAY_SIZE(exynos4_fixed_rate_ext_clks),
ext_clk_match);
clk/samsung: add support for multiple clock providers Samsung CCF helper functions do not provide support to register multiple Clock Providers for a given SoC. Due to this limitation, SoC platforms are not able to use these helpers for registering multiple clock providers and are forced to bypass this layer. This layer is modified accordingly to enable the support for multiple clock providers. Clock file for exynos4, exynos5250, exynos5420, exynos5440, S3c64xx, S3c24xx are also modified as per changed helper functions. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> [t.figa: Modified s3c2410 clock driver as well] Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-03-12 22:56:44 +08:00
exynos4_clk_register_finpll(ctx);
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
if (exynos4_soc == EXYNOS4210) {
clk/samsung: add support for multiple clock providers Samsung CCF helper functions do not provide support to register multiple Clock Providers for a given SoC. Due to this limitation, SoC platforms are not able to use these helpers for registering multiple clock providers and are forced to bypass this layer. This layer is modified accordingly to enable the support for multiple clock providers. Clock file for exynos4, exynos5250, exynos5420, exynos5440, S3c64xx, S3c24xx are also modified as per changed helper functions. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> [t.figa: Modified s3c2410 clock driver as well] Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-03-12 22:56:44 +08:00
samsung_clk_register_mux(ctx, exynos4210_mux_early,
clk: samsung: exynos4: Reorder registration of mout_vpllsrc Since PLL input frequency must be known before PLL registration, mout_vpllsrc clock which is a reference clock of VPLL must be registered before VPLL. This patch reorders clock registration to register mout_vpllsrc before VPLL. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:08 +08:00
ARRAY_SIZE(exynos4210_mux_early));
clk: samsung: remove __clk_lookup() usage __clk_lookup() interface is obsolete, so remove it from the Samsung clock drivers. This has been achieved by getting rid of custom _get_rate() helper and replacing it with clk_hw_get_rate(). Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Link: https://lore.kernel.org/r/20211018125456.8292-2-m.szyprowski@samsung.com Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2021-10-18 20:54:56 +08:00
if (clk_hw_get_rate(hws[CLK_FIN_PLL]) == 24000000) {
clk: samsung: exynos4: Register PLL rate tables for Exynos4210 This patch adds rate tables for PLLs that can be reconfigured at runtime for Exynos4210 SoCs. Provided tables contain PLL coefficients for input clock of 24 MHz and so are registered only in this case. MPLL does not need runtime reconfiguration and so table for it is not provided. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:09 +08:00
exynos4210_plls[apll].rate_table =
exynos4210_apll_rates;
exynos4210_plls[epll].rate_table =
exynos4210_epll_rates;
}
clk: samsung: remove __clk_lookup() usage __clk_lookup() interface is obsolete, so remove it from the Samsung clock drivers. This has been achieved by getting rid of custom _get_rate() helper and replacing it with clk_hw_get_rate(). Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Link: https://lore.kernel.org/r/20211018125456.8292-2-m.szyprowski@samsung.com Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2021-10-18 20:54:56 +08:00
if (clk_hw_get_rate(hws[CLK_MOUT_VPLLSRC]) == 24000000)
clk: samsung: exynos4: Register PLL rate tables for Exynos4210 This patch adds rate tables for PLLs that can be reconfigured at runtime for Exynos4210 SoCs. Provided tables contain PLL coefficients for input clock of 24 MHz and so are registered only in this case. MPLL does not need runtime reconfiguration and so table for it is not provided. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:09 +08:00
exynos4210_plls[vpll].rate_table =
exynos4210_vpll_rates;
clk/samsung: add support for multiple clock providers Samsung CCF helper functions do not provide support to register multiple Clock Providers for a given SoC. Due to this limitation, SoC platforms are not able to use these helpers for registering multiple clock providers and are forced to bypass this layer. This layer is modified accordingly to enable the support for multiple clock providers. Clock file for exynos4, exynos5250, exynos5420, exynos5440, S3c64xx, S3c24xx are also modified as per changed helper functions. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> [t.figa: Modified s3c2410 clock driver as well] Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-03-12 22:56:44 +08:00
samsung_clk_register_pll(ctx, exynos4210_plls,
clk: samsung: Don't pass reg_base to samsung_clk_register_pll() Base address can be derived from context structure. Remove `base' argument from samsung_clk_register_pll() and use `ctx->reg_base' instead, as it's done in other clock registering functions. No functional change. Acked-by: Marek Szyprowski <m.szyprowski@samsung.com> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20230223041938.22732-2-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2023-02-23 12:19:33 +08:00
ARRAY_SIZE(exynos4210_plls));
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
} else {
clk: samsung: remove __clk_lookup() usage __clk_lookup() interface is obsolete, so remove it from the Samsung clock drivers. This has been achieved by getting rid of custom _get_rate() helper and replacing it with clk_hw_get_rate(). Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Link: https://lore.kernel.org/r/20211018125456.8292-2-m.szyprowski@samsung.com Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2021-10-18 20:54:56 +08:00
if (clk_hw_get_rate(hws[CLK_FIN_PLL]) == 24000000) {
clk: samsung: exynos4: Register PLL rate tables for Exynos4x12 This patch adds rate tables for PLLs that can be reconfigured at runtime for Exynos4x12 SoCs. Provided tables contain PLL coefficients for input clock of 24 MHz and so are registered only in this case. MPLL does not need runtime reconfiguration and so table for it is not provided. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-27 01:09:10 +08:00
exynos4x12_plls[apll].rate_table =
exynos4x12_apll_rates;
exynos4x12_plls[epll].rate_table =
exynos4x12_epll_rates;
exynos4x12_plls[vpll].rate_table =
exynos4x12_vpll_rates;
}
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
clk/samsung: add support for multiple clock providers Samsung CCF helper functions do not provide support to register multiple Clock Providers for a given SoC. Due to this limitation, SoC platforms are not able to use these helpers for registering multiple clock providers and are forced to bypass this layer. This layer is modified accordingly to enable the support for multiple clock providers. Clock file for exynos4, exynos5250, exynos5420, exynos5440, S3c64xx, S3c24xx are also modified as per changed helper functions. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> [t.figa: Modified s3c2410 clock driver as well] Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-03-12 22:56:44 +08:00
samsung_clk_register_pll(ctx, exynos4x12_plls,
clk: samsung: Don't pass reg_base to samsung_clk_register_pll() Base address can be derived from context structure. Remove `base' argument from samsung_clk_register_pll() and use `ctx->reg_base' instead, as it's done in other clock registering functions. No functional change. Acked-by: Marek Szyprowski <m.szyprowski@samsung.com> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20230223041938.22732-2-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2023-02-23 12:19:33 +08:00
ARRAY_SIZE(exynos4x12_plls));
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
}
clk/samsung: add support for multiple clock providers Samsung CCF helper functions do not provide support to register multiple Clock Providers for a given SoC. Due to this limitation, SoC platforms are not able to use these helpers for registering multiple clock providers and are forced to bypass this layer. This layer is modified accordingly to enable the support for multiple clock providers. Clock file for exynos4, exynos5250, exynos5420, exynos5440, S3c64xx, S3c24xx are also modified as per changed helper functions. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> [t.figa: Modified s3c2410 clock driver as well] Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-03-12 22:56:44 +08:00
samsung_clk_register_fixed_rate(ctx, exynos4_fixed_rate_clks,
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
ARRAY_SIZE(exynos4_fixed_rate_clks));
clk/samsung: add support for multiple clock providers Samsung CCF helper functions do not provide support to register multiple Clock Providers for a given SoC. Due to this limitation, SoC platforms are not able to use these helpers for registering multiple clock providers and are forced to bypass this layer. This layer is modified accordingly to enable the support for multiple clock providers. Clock file for exynos4, exynos5250, exynos5420, exynos5440, S3c64xx, S3c24xx are also modified as per changed helper functions. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> [t.figa: Modified s3c2410 clock driver as well] Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-03-12 22:56:44 +08:00
samsung_clk_register_mux(ctx, exynos4_mux_clks,
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
ARRAY_SIZE(exynos4_mux_clks));
clk/samsung: add support for multiple clock providers Samsung CCF helper functions do not provide support to register multiple Clock Providers for a given SoC. Due to this limitation, SoC platforms are not able to use these helpers for registering multiple clock providers and are forced to bypass this layer. This layer is modified accordingly to enable the support for multiple clock providers. Clock file for exynos4, exynos5250, exynos5420, exynos5440, S3c64xx, S3c24xx are also modified as per changed helper functions. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> [t.figa: Modified s3c2410 clock driver as well] Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-03-12 22:56:44 +08:00
samsung_clk_register_div(ctx, exynos4_div_clks,
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
ARRAY_SIZE(exynos4_div_clks));
clk/samsung: add support for multiple clock providers Samsung CCF helper functions do not provide support to register multiple Clock Providers for a given SoC. Due to this limitation, SoC platforms are not able to use these helpers for registering multiple clock providers and are forced to bypass this layer. This layer is modified accordingly to enable the support for multiple clock providers. Clock file for exynos4, exynos5250, exynos5420, exynos5440, S3c64xx, S3c24xx are also modified as per changed helper functions. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> [t.figa: Modified s3c2410 clock driver as well] Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-03-12 22:56:44 +08:00
samsung_clk_register_gate(ctx, exynos4_gate_clks,
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
ARRAY_SIZE(exynos4_gate_clks));
clk: samsung: exynos4: Add CLKOUT clock hierarchy This patch adds definitions of clocks that are used to drive clock output signals of particular CMU sub-blocks that are then fed to PMU and handled by Exynos CLKOUT driver added in further patch. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-06-25 00:08:25 +08:00
samsung_clk_register_fixed_factor(ctx, exynos4_fixed_factor_clks,
ARRAY_SIZE(exynos4_fixed_factor_clks));
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
if (exynos4_soc == EXYNOS4210) {
clk/samsung: add support for multiple clock providers Samsung CCF helper functions do not provide support to register multiple Clock Providers for a given SoC. Due to this limitation, SoC platforms are not able to use these helpers for registering multiple clock providers and are forced to bypass this layer. This layer is modified accordingly to enable the support for multiple clock providers. Clock file for exynos4, exynos5250, exynos5420, exynos5440, S3c64xx, S3c24xx are also modified as per changed helper functions. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> [t.figa: Modified s3c2410 clock driver as well] Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-03-12 22:56:44 +08:00
samsung_clk_register_fixed_rate(ctx, exynos4210_fixed_rate_clks,
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
ARRAY_SIZE(exynos4210_fixed_rate_clks));
clk/samsung: add support for multiple clock providers Samsung CCF helper functions do not provide support to register multiple Clock Providers for a given SoC. Due to this limitation, SoC platforms are not able to use these helpers for registering multiple clock providers and are forced to bypass this layer. This layer is modified accordingly to enable the support for multiple clock providers. Clock file for exynos4, exynos5250, exynos5420, exynos5440, S3c64xx, S3c24xx are also modified as per changed helper functions. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> [t.figa: Modified s3c2410 clock driver as well] Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-03-12 22:56:44 +08:00
samsung_clk_register_mux(ctx, exynos4210_mux_clks,
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
ARRAY_SIZE(exynos4210_mux_clks));
clk/samsung: add support for multiple clock providers Samsung CCF helper functions do not provide support to register multiple Clock Providers for a given SoC. Due to this limitation, SoC platforms are not able to use these helpers for registering multiple clock providers and are forced to bypass this layer. This layer is modified accordingly to enable the support for multiple clock providers. Clock file for exynos4, exynos5250, exynos5420, exynos5440, S3c64xx, S3c24xx are also modified as per changed helper functions. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> [t.figa: Modified s3c2410 clock driver as well] Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-03-12 22:56:44 +08:00
samsung_clk_register_div(ctx, exynos4210_div_clks,
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
ARRAY_SIZE(exynos4210_div_clks));
clk/samsung: add support for multiple clock providers Samsung CCF helper functions do not provide support to register multiple Clock Providers for a given SoC. Due to this limitation, SoC platforms are not able to use these helpers for registering multiple clock providers and are forced to bypass this layer. This layer is modified accordingly to enable the support for multiple clock providers. Clock file for exynos4, exynos5250, exynos5420, exynos5440, S3c64xx, S3c24xx are also modified as per changed helper functions. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> [t.figa: Modified s3c2410 clock driver as well] Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-03-12 22:56:44 +08:00
samsung_clk_register_gate(ctx, exynos4210_gate_clks,
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
ARRAY_SIZE(exynos4210_gate_clks));
clk: samsung: exynos4: Add CLKOUT clock hierarchy This patch adds definitions of clocks that are used to drive clock output signals of particular CMU sub-blocks that are then fed to PMU and handled by Exynos CLKOUT driver added in further patch. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-06-25 00:08:25 +08:00
samsung_clk_register_fixed_factor(ctx,
exynos4210_fixed_factor_clks,
ARRAY_SIZE(exynos4210_fixed_factor_clks));
clk: samsung: Update CPU clk registration Convert the remaining exynos clock drivers to use samsung_clk_register_cpu() or if possible use samsung_cmu_register_one(). With this we can now make exynos_register_cpu_clock() a static function so that future CPU clock registration changes will use the samsung common clock driver. The main benefit of this change is that it standardizes the CPU clock registration for the samsung clock drivers. Link: https://lore.kernel.org/r/20211015190515.3760577-1-willmcvicker@google.com Signed-off-by: Will McVicker <willmcvicker@google.com> Tested-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> [snawrocki@kernel.org: Fixed build break in clk-exynos4.c, clk-exynos5250.c] Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2021-10-16 03:05:14 +08:00
samsung_clk_register_cpu(ctx, exynos4210_cpu_clks,
ARRAY_SIZE(exynos4210_cpu_clks));
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
} else {
clk/samsung: add support for multiple clock providers Samsung CCF helper functions do not provide support to register multiple Clock Providers for a given SoC. Due to this limitation, SoC platforms are not able to use these helpers for registering multiple clock providers and are forced to bypass this layer. This layer is modified accordingly to enable the support for multiple clock providers. Clock file for exynos4, exynos5250, exynos5420, exynos5440, S3c64xx, S3c24xx are also modified as per changed helper functions. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> [t.figa: Modified s3c2410 clock driver as well] Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-03-12 22:56:44 +08:00
samsung_clk_register_mux(ctx, exynos4x12_mux_clks,
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
ARRAY_SIZE(exynos4x12_mux_clks));
clk/samsung: add support for multiple clock providers Samsung CCF helper functions do not provide support to register multiple Clock Providers for a given SoC. Due to this limitation, SoC platforms are not able to use these helpers for registering multiple clock providers and are forced to bypass this layer. This layer is modified accordingly to enable the support for multiple clock providers. Clock file for exynos4, exynos5250, exynos5420, exynos5440, S3c64xx, S3c24xx are also modified as per changed helper functions. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> [t.figa: Modified s3c2410 clock driver as well] Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-03-12 22:56:44 +08:00
samsung_clk_register_div(ctx, exynos4x12_div_clks,
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
ARRAY_SIZE(exynos4x12_div_clks));
clk/samsung: add support for multiple clock providers Samsung CCF helper functions do not provide support to register multiple Clock Providers for a given SoC. Due to this limitation, SoC platforms are not able to use these helpers for registering multiple clock providers and are forced to bypass this layer. This layer is modified accordingly to enable the support for multiple clock providers. Clock file for exynos4, exynos5250, exynos5420, exynos5440, S3c64xx, S3c24xx are also modified as per changed helper functions. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> [t.figa: Modified s3c2410 clock driver as well] Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-03-12 22:56:44 +08:00
samsung_clk_register_gate(ctx, exynos4x12_gate_clks,
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
ARRAY_SIZE(exynos4x12_gate_clks));
clk: samsung: exynos4: Add CLKOUT clock hierarchy This patch adds definitions of clocks that are used to drive clock output signals of particular CMU sub-blocks that are then fed to PMU and handled by Exynos CLKOUT driver added in further patch. Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-06-25 00:08:25 +08:00
samsung_clk_register_fixed_factor(ctx,
exynos4x12_fixed_factor_clks,
ARRAY_SIZE(exynos4x12_fixed_factor_clks));
clk: samsung: Re-add support for Exynos4212 CPU clock Support for the Exynos4212 SoC was originally dropped as there were no boards using it. We will be adding a device that uses it, so add it back. This reverts commit c9194fb623b0158029a268376df09fe28a2a2b05. Signed-off-by: Artur Weber <aweber.kernel@gmail.com> Link: https://lore.kernel.org/r/20230501195525.6268-7-aweber.kernel@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2023-05-02 03:55:18 +08:00
if (soc == EXYNOS4412)
samsung_clk_register_cpu(ctx, exynos4412_cpu_clks,
ARRAY_SIZE(exynos4412_cpu_clks));
else
samsung_clk_register_cpu(ctx, exynos4212_cpu_clks,
ARRAY_SIZE(exynos4212_cpu_clks));
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
}
clk: samsung: Re-add support for Exynos4212 CPU clock Support for the Exynos4212 SoC was originally dropped as there were no boards using it. We will be adding a device that uses it, so add it back. This reverts commit c9194fb623b0158029a268376df09fe28a2a2b05. Signed-off-by: Artur Weber <aweber.kernel@gmail.com> Link: https://lore.kernel.org/r/20230501195525.6268-7-aweber.kernel@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2023-05-02 03:55:18 +08:00
if (soc == EXYNOS4212 || soc == EXYNOS4412)
clk: samsung: exynos4: Disable ARMCLK down feature on Exynos4210 SoC Commit 42773b28e71d ("clk: samsung: exynos4: Enable ARMCLK down feature") enabled ARMCLK down feature on all Exynos4 SoCs. Unfortunately on Exynos4210 SoC ARMCLK down feature causes a lockup when ondemand cpufreq governor is used. Fix it by limiting ARMCLK down feature to Exynos4x12 SoCs. This patch was tested on: - Exynos4210 SoC based Trats board - Exynos4210 SoC based Origen board - Exynos4412 SoC based Trats2 board - Exynos4412 SoC based Odroid-U3 board Cc: Daniel Drake <drake@endlessm.com> Cc: Tomasz Figa <t.figa@samsung.com> Cc: Kukjin Kim <kgene@kernel.org> Fixes: 42773b28e71d ("clk: samsung: exynos4: Enable ARMCLK down feature") Cc: <stable@vger.kernel.org> # v3.17+ Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-03-28 00:27:10 +08:00
exynos4x12_core_down_clock();
clk: samsung: exynos4: Use generic helper for handling suspend/resume Replace common suspend/resume handling code by generic helper. Handling of PLLs is a bit different in generic code, as they are handled in the same way as other clock registers. Such approach was already used on later Exynos SoCs and worked fine. Tests have shown that it works also on Exynos4 SoCs and significantly simplifies the code. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Sylwester Nawrocki <snawrocki@kernel.org>
2018-09-06 23:55:31 +08:00
samsung_clk_extended_sleep_init(reg_base,
exynos4_clk_regs, ARRAY_SIZE(exynos4_clk_regs),
src_mask_suspend, ARRAY_SIZE(src_mask_suspend));
if (exynos4_soc == EXYNOS4210)
samsung_clk_extended_sleep_init(reg_base,
exynos4210_clk_save, ARRAY_SIZE(exynos4210_clk_save),
src_mask_suspend_e4210, ARRAY_SIZE(src_mask_suspend_e4210));
else
samsung_clk_sleep_init(reg_base, exynos4x12_clk_save,
ARRAY_SIZE(exynos4x12_clk_save));
clk: samsung: exynos4: Move suspend/resume handling to SoC driver Since there are multiple differences in how suspend/resume of particular Exynos SoCs must be handled, SoC driver is better place for suspend/resume handlers and so this patch moves them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.ab@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-02-14 07:16:00 +08:00
clk: samsung: Register clk provider only after registering its all clocks Ensure the clock provider is not registered until after all its related clocks were created and are ready to use. Currently there are races possible and any (of_)clk_get() call right after a clock provider's clk_init_cb callback call may fail. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-06-18 23:46:52 +08:00
samsung_clk_of_add_provider(np, ctx);
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
pr_info("%s clocks: sclk_apll = %ld, sclk_mpll = %ld\n"
"\tsclk_epll = %ld, sclk_vpll = %ld, arm_clk = %ld\n",
exynos4_soc == EXYNOS4210 ? "Exynos4210" : "Exynos4x12",
clk: samsung: remove __clk_lookup() usage __clk_lookup() interface is obsolete, so remove it from the Samsung clock drivers. This has been achieved by getting rid of custom _get_rate() helper and replacing it with clk_hw_get_rate(). Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Link: https://lore.kernel.org/r/20211018125456.8292-2-m.szyprowski@samsung.com Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2021-10-18 20:54:56 +08:00
clk_hw_get_rate(hws[CLK_SCLK_APLL]),
clk_hw_get_rate(hws[CLK_SCLK_MPLL]),
clk_hw_get_rate(hws[CLK_SCLK_EPLL]),
clk_hw_get_rate(hws[CLK_SCLK_VPLL]),
clk_hw_get_rate(hws[CLK_DIV_CORE2]));
clk: exynos4: register clocks using common clock framework The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-03-09 16:02:52 +08:00
}
clk: exynos: prepare for multiplatform The new common clock drivers for exynos are using compile time constants and soc_is_exynos* macros to provide backwards compatibility for pre-DT systems, which is not possible with multiplatform kernels. This moves all the necessary information back into platform code and removes the mach/* header inclusions. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Cc: Mike Turquette <mturquette@linaro.org>
2013-04-10 17:31:44 +08:00
static void __init exynos4210_clk_init(struct device_node *np)
{
clk: exynos4: Remove remnants of non-DT support This patch simplifies a bit clock initialization code by removing remnants of non-DT clock initialization, such as reg_base and xom values passed in function parameters. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.ab@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-02-14 07:16:00 +08:00
exynos4_clk_init(np, EXYNOS4210);
clk: exynos: prepare for multiplatform The new common clock drivers for exynos are using compile time constants and soc_is_exynos* macros to provide backwards compatibility for pre-DT systems, which is not possible with multiplatform kernels. This moves all the necessary information back into platform code and removes the mach/* header inclusions. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Cc: Mike Turquette <mturquette@linaro.org>
2013-04-10 17:31:44 +08:00
}
CLK_OF_DECLARE(exynos4210_clk, "samsung,exynos4210-clock", exynos4210_clk_init);
clk: samsung: Re-add support for Exynos4212 CPU clock Support for the Exynos4212 SoC was originally dropped as there were no boards using it. We will be adding a device that uses it, so add it back. This reverts commit c9194fb623b0158029a268376df09fe28a2a2b05. Signed-off-by: Artur Weber <aweber.kernel@gmail.com> Link: https://lore.kernel.org/r/20230501195525.6268-7-aweber.kernel@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2023-05-02 03:55:18 +08:00
static void __init exynos4212_clk_init(struct device_node *np)
{
exynos4_clk_init(np, EXYNOS4212);
}
CLK_OF_DECLARE(exynos4212_clk, "samsung,exynos4212-clock", exynos4212_clk_init);
clk: exynos: prepare for multiplatform The new common clock drivers for exynos are using compile time constants and soc_is_exynos* macros to provide backwards compatibility for pre-DT systems, which is not possible with multiplatform kernels. This moves all the necessary information back into platform code and removes the mach/* header inclusions. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Cc: Mike Turquette <mturquette@linaro.org>
2013-04-10 17:31:44 +08:00
static void __init exynos4412_clk_init(struct device_node *np)
{
clk: samsung: Re-add support for Exynos4212 CPU clock Support for the Exynos4212 SoC was originally dropped as there were no boards using it. We will be adding a device that uses it, so add it back. This reverts commit c9194fb623b0158029a268376df09fe28a2a2b05. Signed-off-by: Artur Weber <aweber.kernel@gmail.com> Link: https://lore.kernel.org/r/20230501195525.6268-7-aweber.kernel@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2023-05-02 03:55:18 +08:00
exynos4_clk_init(np, EXYNOS4412);
clk: exynos: prepare for multiplatform The new common clock drivers for exynos are using compile time constants and soc_is_exynos* macros to provide backwards compatibility for pre-DT systems, which is not possible with multiplatform kernels. This moves all the necessary information back into platform code and removes the mach/* header inclusions. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Cc: Mike Turquette <mturquette@linaro.org>
2013-04-10 17:31:44 +08:00
}
CLK_OF_DECLARE(exynos4412_clk, "samsung,exynos4412-clock", exynos4412_clk_init);
Reference in New Issue Copy Permalink