2019-05-29 22:17:59 +08:00
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// SPDX-License-Identifier: GPL-2.0-only
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2017-03-24 23:33:21 +08:00
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/*
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* Copyright (c) 2017, National Instruments Corp.
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2021-02-11 13:11:48 +08:00
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* Copyright (c) 2017, Xilinx Inc
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2017-03-24 23:33:21 +08:00
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*
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* FPGA Bridge Driver for the Xilinx LogiCORE Partial Reconfiguration
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* Decoupler IP Core.
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*/
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/of_device.h>
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#include <linux/module.h>
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#include <linux/fpga/fpga-bridge.h>
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#define CTRL_CMD_DECOUPLE BIT(0)
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#define CTRL_CMD_COUPLE 0
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#define CTRL_OFFSET 0
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2021-02-11 13:11:48 +08:00
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struct xlnx_config_data {
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const char *name;
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};
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2017-03-24 23:33:21 +08:00
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struct xlnx_pr_decoupler_data {
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2021-02-11 13:11:48 +08:00
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const struct xlnx_config_data *ipconfig;
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2017-03-24 23:33:21 +08:00
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void __iomem *io_base;
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struct clk *clk;
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};
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static inline void xlnx_pr_decoupler_write(struct xlnx_pr_decoupler_data *d,
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u32 offset, u32 val)
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{
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writel(val, d->io_base + offset);
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}
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static inline u32 xlnx_pr_decouple_read(const struct xlnx_pr_decoupler_data *d,
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u32 offset)
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{
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return readl(d->io_base + offset);
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}
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static int xlnx_pr_decoupler_enable_set(struct fpga_bridge *bridge, bool enable)
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{
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int err;
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struct xlnx_pr_decoupler_data *priv = bridge->priv;
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err = clk_enable(priv->clk);
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if (err)
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return err;
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if (enable)
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xlnx_pr_decoupler_write(priv, CTRL_OFFSET, CTRL_CMD_COUPLE);
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else
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xlnx_pr_decoupler_write(priv, CTRL_OFFSET, CTRL_CMD_DECOUPLE);
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clk_disable(priv->clk);
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return 0;
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}
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static int xlnx_pr_decoupler_enable_show(struct fpga_bridge *bridge)
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{
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const struct xlnx_pr_decoupler_data *priv = bridge->priv;
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u32 status;
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int err;
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err = clk_enable(priv->clk);
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if (err)
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return err;
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status = readl(priv->io_base);
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clk_disable(priv->clk);
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return !status;
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}
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2017-09-21 22:52:41 +08:00
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static const struct fpga_bridge_ops xlnx_pr_decoupler_br_ops = {
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2017-03-24 23:33:21 +08:00
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.enable_set = xlnx_pr_decoupler_enable_set,
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.enable_show = xlnx_pr_decoupler_enable_show,
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};
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2021-07-02 11:54:03 +08:00
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#ifdef CONFIG_OF
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2021-02-11 13:11:48 +08:00
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static const struct xlnx_config_data decoupler_config = {
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.name = "Xilinx PR Decoupler",
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};
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static const struct xlnx_config_data shutdown_config = {
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.name = "Xilinx DFX AXI Shutdown Manager",
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};
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2017-03-24 23:33:21 +08:00
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static const struct of_device_id xlnx_pr_decoupler_of_match[] = {
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2021-02-11 13:11:48 +08:00
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{ .compatible = "xlnx,pr-decoupler-1.00", .data = &decoupler_config },
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{ .compatible = "xlnx,pr-decoupler", .data = &decoupler_config },
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{ .compatible = "xlnx,dfx-axi-shutdown-manager-1.00",
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.data = &shutdown_config },
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{ .compatible = "xlnx,dfx-axi-shutdown-manager",
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.data = &shutdown_config },
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2017-03-24 23:33:21 +08:00
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{},
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};
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MODULE_DEVICE_TABLE(of, xlnx_pr_decoupler_of_match);
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2021-07-02 11:54:03 +08:00
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#endif
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2017-03-24 23:33:21 +08:00
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static int xlnx_pr_decoupler_probe(struct platform_device *pdev)
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{
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2021-02-11 13:11:48 +08:00
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struct device_node *np = pdev->dev.of_node;
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2017-03-24 23:33:21 +08:00
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struct xlnx_pr_decoupler_data *priv;
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2018-05-17 07:49:56 +08:00
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struct fpga_bridge *br;
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2017-03-24 23:33:21 +08:00
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int err;
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struct resource *res;
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priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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2021-02-11 13:11:48 +08:00
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if (np) {
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const struct of_device_id *match;
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match = of_match_node(xlnx_pr_decoupler_of_match, np);
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if (match && match->data)
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priv->ipconfig = match->data;
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}
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2017-03-24 23:33:21 +08:00
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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priv->io_base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(priv->io_base))
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return PTR_ERR(priv->io_base);
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priv->clk = devm_clk_get(&pdev->dev, "aclk");
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2021-02-04 21:36:11 +08:00
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if (IS_ERR(priv->clk))
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return dev_err_probe(&pdev->dev, PTR_ERR(priv->clk),
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"input clock not found\n");
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2017-03-24 23:33:21 +08:00
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err = clk_prepare_enable(priv->clk);
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if (err) {
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dev_err(&pdev->dev, "unable to enable clock\n");
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return err;
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}
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clk_disable(priv->clk);
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2021-02-11 13:11:48 +08:00
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br = devm_fpga_bridge_create(&pdev->dev, priv->ipconfig->name,
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2018-10-16 06:20:02 +08:00
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&xlnx_pr_decoupler_br_ops, priv);
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2018-05-17 07:49:56 +08:00
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if (!br) {
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err = -ENOMEM;
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goto err_clk;
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}
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platform_set_drvdata(pdev, br);
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2017-03-24 23:33:21 +08:00
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2018-05-17 07:49:56 +08:00
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err = fpga_bridge_register(br);
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2017-03-24 23:33:21 +08:00
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if (err) {
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2021-02-11 13:11:48 +08:00
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dev_err(&pdev->dev, "unable to register %s",
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priv->ipconfig->name);
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2018-05-17 07:49:56 +08:00
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goto err_clk;
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2017-03-24 23:33:21 +08:00
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}
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return 0;
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2018-05-17 07:49:56 +08:00
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err_clk:
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clk_unprepare(priv->clk);
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return err;
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2017-03-24 23:33:21 +08:00
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}
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static int xlnx_pr_decoupler_remove(struct platform_device *pdev)
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{
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struct fpga_bridge *bridge = platform_get_drvdata(pdev);
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struct xlnx_pr_decoupler_data *p = bridge->priv;
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2018-05-17 07:49:56 +08:00
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fpga_bridge_unregister(bridge);
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2017-03-24 23:33:21 +08:00
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clk_unprepare(p->clk);
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return 0;
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}
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static struct platform_driver xlnx_pr_decoupler_driver = {
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.probe = xlnx_pr_decoupler_probe,
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.remove = xlnx_pr_decoupler_remove,
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.driver = {
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.name = "xlnx_pr_decoupler",
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.of_match_table = of_match_ptr(xlnx_pr_decoupler_of_match),
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},
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};
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module_platform_driver(xlnx_pr_decoupler_driver);
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MODULE_DESCRIPTION("Xilinx Partial Reconfiguration Decoupler");
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MODULE_AUTHOR("Moritz Fischer <mdf@kernel.org>");
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MODULE_AUTHOR("Michal Simek <michal.simek@xilinx.com>");
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MODULE_LICENSE("GPL v2");
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