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572 lines
14 KiB
C
572 lines
14 KiB
C
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/*
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* Performance counter x86 architecture code
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*
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* Copyright(C) 2008 Thomas Gleixner <tglx@linutronix.de>
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* Copyright(C) 2008 Red Hat, Inc., Ingo Molnar
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*
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* For licencing details see kernel-base/COPYING
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*/
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#include <linux/perf_counter.h>
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#include <linux/capability.h>
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#include <linux/notifier.h>
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#include <linux/hardirq.h>
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#include <linux/kprobes.h>
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#include <linux/kdebug.h>
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#include <linux/sched.h>
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#include <asm/intel_arch_perfmon.h>
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#include <asm/apic.h>
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static bool perf_counters_initialized __read_mostly;
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/*
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* Number of (generic) HW counters:
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*/
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static int nr_hw_counters __read_mostly;
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static u32 perf_counter_mask __read_mostly;
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/* No support for fixed function counters yet */
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#define MAX_HW_COUNTERS 8
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struct cpu_hw_counters {
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struct perf_counter *counters[MAX_HW_COUNTERS];
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unsigned long used[BITS_TO_LONGS(MAX_HW_COUNTERS)];
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int enable_all;
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};
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/*
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* Intel PerfMon v3. Used on Core2 and later.
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*/
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static DEFINE_PER_CPU(struct cpu_hw_counters, cpu_hw_counters);
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const int intel_perfmon_event_map[] =
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{
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[PERF_COUNT_CYCLES] = 0x003c,
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[PERF_COUNT_INSTRUCTIONS] = 0x00c0,
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[PERF_COUNT_CACHE_REFERENCES] = 0x4f2e,
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[PERF_COUNT_CACHE_MISSES] = 0x412e,
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[PERF_COUNT_BRANCH_INSTRUCTIONS] = 0x00c4,
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[PERF_COUNT_BRANCH_MISSES] = 0x00c5,
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};
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const int max_intel_perfmon_events = ARRAY_SIZE(intel_perfmon_event_map);
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/*
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* Setup the hardware configuration for a given hw_event_type
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*/
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int hw_perf_counter_init(struct perf_counter *counter, s32 hw_event_type)
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{
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struct hw_perf_counter *hwc = &counter->hw;
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if (unlikely(!perf_counters_initialized))
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return -EINVAL;
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/*
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* Count user events, and generate PMC IRQs:
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* (keep 'enabled' bit clear for now)
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*/
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hwc->config = ARCH_PERFMON_EVENTSEL_USR | ARCH_PERFMON_EVENTSEL_INT;
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/*
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* If privileged enough, count OS events too, and allow
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* NMI events as well:
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*/
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hwc->nmi = 0;
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if (capable(CAP_SYS_ADMIN)) {
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hwc->config |= ARCH_PERFMON_EVENTSEL_OS;
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if (hw_event_type & PERF_COUNT_NMI)
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hwc->nmi = 1;
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}
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hwc->config_base = MSR_ARCH_PERFMON_EVENTSEL0;
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hwc->counter_base = MSR_ARCH_PERFMON_PERFCTR0;
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hwc->irq_period = counter->__irq_period;
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/*
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* Intel PMCs cannot be accessed sanely above 32 bit width,
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* so we install an artificial 1<<31 period regardless of
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* the generic counter period:
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*/
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if (!hwc->irq_period)
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hwc->irq_period = 0x7FFFFFFF;
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hwc->next_count = -((s32) hwc->irq_period);
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/*
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* Negative event types mean raw encoded event+umask values:
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*/
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if (hw_event_type < 0) {
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counter->hw_event_type = -hw_event_type;
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counter->hw_event_type &= ~PERF_COUNT_NMI;
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} else {
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hw_event_type &= ~PERF_COUNT_NMI;
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if (hw_event_type >= max_intel_perfmon_events)
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return -EINVAL;
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/*
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* The generic map:
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*/
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counter->hw_event_type = intel_perfmon_event_map[hw_event_type];
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}
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hwc->config |= counter->hw_event_type;
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counter->wakeup_pending = 0;
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return 0;
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}
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static void __hw_perf_enable_all(void)
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{
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wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, perf_counter_mask, 0);
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}
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void hw_perf_enable_all(void)
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{
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struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
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cpuc->enable_all = 1;
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__hw_perf_enable_all();
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}
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void hw_perf_disable_all(void)
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{
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struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
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cpuc->enable_all = 0;
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wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, 0, 0);
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}
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static DEFINE_PER_CPU(u64, prev_next_count[MAX_HW_COUNTERS]);
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static void __hw_perf_counter_enable(struct hw_perf_counter *hwc, int idx)
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{
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per_cpu(prev_next_count[idx], smp_processor_id()) = hwc->next_count;
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wrmsr(hwc->counter_base + idx, hwc->next_count, 0);
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wrmsr(hwc->config_base + idx, hwc->config, 0);
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}
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void hw_perf_counter_enable(struct perf_counter *counter)
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{
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struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
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struct hw_perf_counter *hwc = &counter->hw;
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int idx = hwc->idx;
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/* Try to get the previous counter again */
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if (test_and_set_bit(idx, cpuc->used)) {
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idx = find_first_zero_bit(cpuc->used, nr_hw_counters);
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set_bit(idx, cpuc->used);
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hwc->idx = idx;
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}
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perf_counters_lapic_init(hwc->nmi);
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wrmsr(hwc->config_base + idx,
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hwc->config & ~ARCH_PERFMON_EVENTSEL0_ENABLE, 0);
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cpuc->counters[idx] = counter;
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counter->hw.config |= ARCH_PERFMON_EVENTSEL0_ENABLE;
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__hw_perf_counter_enable(hwc, idx);
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}
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#ifdef CONFIG_X86_64
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static inline void atomic64_counter_set(struct perf_counter *counter, u64 val)
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{
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atomic64_set(&counter->count, val);
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}
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static inline u64 atomic64_counter_read(struct perf_counter *counter)
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{
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return atomic64_read(&counter->count);
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}
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#else
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/*
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* Todo: add proper atomic64_t support to 32-bit x86:
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*/
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static inline void atomic64_counter_set(struct perf_counter *counter, u64 val64)
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{
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u32 *val32 = (void *)&val64;
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atomic_set(counter->count32 + 0, *(val32 + 0));
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atomic_set(counter->count32 + 1, *(val32 + 1));
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}
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static inline u64 atomic64_counter_read(struct perf_counter *counter)
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{
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return atomic_read(counter->count32 + 0) |
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(u64) atomic_read(counter->count32 + 1) << 32;
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}
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#endif
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static void __hw_perf_save_counter(struct perf_counter *counter,
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struct hw_perf_counter *hwc, int idx)
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{
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s64 raw = -1;
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s64 delta;
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int err;
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/*
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* Get the raw hw counter value:
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*/
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err = rdmsrl_safe(hwc->counter_base + idx, &raw);
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WARN_ON_ONCE(err);
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/*
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* Rebase it to zero (it started counting at -irq_period),
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* to see the delta since ->prev_count:
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*/
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delta = (s64)hwc->irq_period + (s64)(s32)raw;
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atomic64_counter_set(counter, hwc->prev_count + delta);
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/*
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* Adjust the ->prev_count offset - if we went beyond
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* irq_period of units, then we got an IRQ and the counter
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* was set back to -irq_period:
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*/
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while (delta >= (s64)hwc->irq_period) {
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hwc->prev_count += hwc->irq_period;
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delta -= (s64)hwc->irq_period;
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}
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/*
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* Calculate the next raw counter value we'll write into
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* the counter at the next sched-in time:
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*/
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delta -= (s64)hwc->irq_period;
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hwc->next_count = (s32)delta;
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}
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void perf_counter_print_debug(void)
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{
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u64 ctrl, status, overflow, pmc_ctrl, pmc_count, next_count;
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int cpu, err, idx;
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local_irq_disable();
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cpu = smp_processor_id();
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err = rdmsrl_safe(MSR_CORE_PERF_GLOBAL_CTRL, &ctrl);
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WARN_ON_ONCE(err);
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err = rdmsrl_safe(MSR_CORE_PERF_GLOBAL_STATUS, &status);
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WARN_ON_ONCE(err);
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err = rdmsrl_safe(MSR_CORE_PERF_GLOBAL_OVF_CTRL, &overflow);
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WARN_ON_ONCE(err);
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printk(KERN_INFO "\n");
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printk(KERN_INFO "CPU#%d: ctrl: %016llx\n", cpu, ctrl);
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printk(KERN_INFO "CPU#%d: status: %016llx\n", cpu, status);
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printk(KERN_INFO "CPU#%d: overflow: %016llx\n", cpu, overflow);
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for (idx = 0; idx < nr_hw_counters; idx++) {
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err = rdmsrl_safe(MSR_ARCH_PERFMON_EVENTSEL0 + idx, &pmc_ctrl);
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WARN_ON_ONCE(err);
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err = rdmsrl_safe(MSR_ARCH_PERFMON_PERFCTR0 + idx, &pmc_count);
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WARN_ON_ONCE(err);
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next_count = per_cpu(prev_next_count[idx], cpu);
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printk(KERN_INFO "CPU#%d: PMC%d ctrl: %016llx\n",
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cpu, idx, pmc_ctrl);
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printk(KERN_INFO "CPU#%d: PMC%d count: %016llx\n",
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cpu, idx, pmc_count);
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printk(KERN_INFO "CPU#%d: PMC%d next: %016llx\n",
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cpu, idx, next_count);
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}
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local_irq_enable();
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}
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void hw_perf_counter_disable(struct perf_counter *counter)
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{
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struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
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struct hw_perf_counter *hwc = &counter->hw;
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unsigned int idx = hwc->idx;
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counter->hw.config &= ~ARCH_PERFMON_EVENTSEL0_ENABLE;
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wrmsr(hwc->config_base + idx, hwc->config, 0);
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clear_bit(idx, cpuc->used);
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cpuc->counters[idx] = NULL;
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__hw_perf_save_counter(counter, hwc, idx);
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}
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void hw_perf_counter_read(struct perf_counter *counter)
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{
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struct hw_perf_counter *hwc = &counter->hw;
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unsigned long addr = hwc->counter_base + hwc->idx;
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s64 offs, val = -1LL;
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s32 val32;
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int err;
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/* Careful: NMI might modify the counter offset */
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do {
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offs = hwc->prev_count;
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err = rdmsrl_safe(addr, &val);
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WARN_ON_ONCE(err);
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} while (offs != hwc->prev_count);
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val32 = (s32) val;
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val = (s64)hwc->irq_period + (s64)val32;
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atomic64_counter_set(counter, hwc->prev_count + val);
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}
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static void perf_store_irq_data(struct perf_counter *counter, u64 data)
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{
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struct perf_data *irqdata = counter->irqdata;
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if (irqdata->len > PERF_DATA_BUFLEN - sizeof(u64)) {
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irqdata->overrun++;
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} else {
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u64 *p = (u64 *) &irqdata->data[irqdata->len];
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*p = data;
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irqdata->len += sizeof(u64);
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}
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}
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static void perf_save_and_restart(struct perf_counter *counter)
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{
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struct hw_perf_counter *hwc = &counter->hw;
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int idx = hwc->idx;
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wrmsr(hwc->config_base + idx,
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hwc->config & ~ARCH_PERFMON_EVENTSEL0_ENABLE, 0);
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if (hwc->config & ARCH_PERFMON_EVENTSEL0_ENABLE) {
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__hw_perf_save_counter(counter, hwc, idx);
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__hw_perf_counter_enable(hwc, idx);
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}
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}
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static void
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perf_handle_group(struct perf_counter *leader, u64 *status, u64 *overflown)
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{
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struct perf_counter_context *ctx = leader->ctx;
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struct perf_counter *counter;
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int bit;
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list_for_each_entry(counter, &ctx->counters, list) {
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if (counter->record_type != PERF_RECORD_SIMPLE ||
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counter == leader)
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continue;
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if (counter->active) {
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/*
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* When counter was not in the overflow mask, we have to
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* read it from hardware. We read it as well, when it
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* has not been read yet and clear the bit in the
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* status mask.
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*/
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bit = counter->hw.idx;
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if (!test_bit(bit, (unsigned long *) overflown) ||
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test_bit(bit, (unsigned long *) status)) {
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clear_bit(bit, (unsigned long *) status);
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perf_save_and_restart(counter);
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}
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}
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perf_store_irq_data(leader, counter->hw_event_type);
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perf_store_irq_data(leader, atomic64_counter_read(counter));
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}
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}
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/*
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* This handler is triggered by the local APIC, so the APIC IRQ handling
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* rules apply:
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*/
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static void __smp_perf_counter_interrupt(struct pt_regs *regs, int nmi)
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{
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int bit, cpu = smp_processor_id();
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struct cpu_hw_counters *cpuc;
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u64 ack, status;
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rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
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if (!status) {
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ack_APIC_irq();
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return;
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}
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/* Disable counters globally */
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wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, 0, 0);
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ack_APIC_irq();
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cpuc = &per_cpu(cpu_hw_counters, cpu);
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again:
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ack = status;
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for_each_bit(bit, (unsigned long *) &status, nr_hw_counters) {
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struct perf_counter *counter = cpuc->counters[bit];
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clear_bit(bit, (unsigned long *) &status);
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if (!counter)
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continue;
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perf_save_and_restart(counter);
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switch (counter->record_type) {
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case PERF_RECORD_SIMPLE:
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continue;
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case PERF_RECORD_IRQ:
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perf_store_irq_data(counter, instruction_pointer(regs));
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break;
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case PERF_RECORD_GROUP:
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perf_store_irq_data(counter, counter->hw_event_type);
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perf_store_irq_data(counter,
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atomic64_counter_read(counter));
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perf_handle_group(counter, &status, &ack);
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break;
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}
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/*
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* From NMI context we cannot call into the scheduler to
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* do a task wakeup - but we mark these counters as
|
||
|
* wakeup_pending and initate a wakeup callback:
|
||
|
*/
|
||
|
if (nmi) {
|
||
|
counter->wakeup_pending = 1;
|
||
|
set_tsk_thread_flag(current, TIF_PERF_COUNTERS);
|
||
|
} else {
|
||
|
wake_up(&counter->waitq);
|
||
|
}
|
||
|
}
|
||
|
|
||
|
wrmsr(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack, 0);
|
||
|
|
||
|
/*
|
||
|
* Repeat if there is more work to be done:
|
||
|
*/
|
||
|
rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
|
||
|
if (status)
|
||
|
goto again;
|
||
|
|
||
|
/*
|
||
|
* Do not reenable when global enable is off:
|
||
|
*/
|
||
|
if (cpuc->enable_all)
|
||
|
__hw_perf_enable_all();
|
||
|
}
|
||
|
|
||
|
void smp_perf_counter_interrupt(struct pt_regs *regs)
|
||
|
{
|
||
|
irq_enter();
|
||
|
#ifdef CONFIG_X86_64
|
||
|
add_pda(apic_perf_irqs, 1);
|
||
|
#else
|
||
|
per_cpu(irq_stat, smp_processor_id()).apic_perf_irqs++;
|
||
|
#endif
|
||
|
apic_write(APIC_LVTPC, LOCAL_PERF_VECTOR);
|
||
|
__smp_perf_counter_interrupt(regs, 0);
|
||
|
|
||
|
irq_exit();
|
||
|
}
|
||
|
|
||
|
/*
|
||
|
* This handler is triggered by NMI contexts:
|
||
|
*/
|
||
|
void perf_counter_notify(struct pt_regs *regs)
|
||
|
{
|
||
|
struct cpu_hw_counters *cpuc;
|
||
|
unsigned long flags;
|
||
|
int bit, cpu;
|
||
|
|
||
|
local_irq_save(flags);
|
||
|
cpu = smp_processor_id();
|
||
|
cpuc = &per_cpu(cpu_hw_counters, cpu);
|
||
|
|
||
|
for_each_bit(bit, cpuc->used, nr_hw_counters) {
|
||
|
struct perf_counter *counter = cpuc->counters[bit];
|
||
|
|
||
|
if (!counter)
|
||
|
continue;
|
||
|
|
||
|
if (counter->wakeup_pending) {
|
||
|
counter->wakeup_pending = 0;
|
||
|
wake_up(&counter->waitq);
|
||
|
}
|
||
|
}
|
||
|
|
||
|
local_irq_restore(flags);
|
||
|
}
|
||
|
|
||
|
void __cpuinit perf_counters_lapic_init(int nmi)
|
||
|
{
|
||
|
u32 apic_val;
|
||
|
|
||
|
if (!perf_counters_initialized)
|
||
|
return;
|
||
|
/*
|
||
|
* Enable the performance counter vector in the APIC LVT:
|
||
|
*/
|
||
|
apic_val = apic_read(APIC_LVTERR);
|
||
|
|
||
|
apic_write(APIC_LVTERR, apic_val | APIC_LVT_MASKED);
|
||
|
if (nmi)
|
||
|
apic_write(APIC_LVTPC, APIC_DM_NMI);
|
||
|
else
|
||
|
apic_write(APIC_LVTPC, LOCAL_PERF_VECTOR);
|
||
|
apic_write(APIC_LVTERR, apic_val);
|
||
|
}
|
||
|
|
||
|
static int __kprobes
|
||
|
perf_counter_nmi_handler(struct notifier_block *self,
|
||
|
unsigned long cmd, void *__args)
|
||
|
{
|
||
|
struct die_args *args = __args;
|
||
|
struct pt_regs *regs;
|
||
|
|
||
|
if (likely(cmd != DIE_NMI_IPI))
|
||
|
return NOTIFY_DONE;
|
||
|
|
||
|
regs = args->regs;
|
||
|
|
||
|
apic_write(APIC_LVTPC, APIC_DM_NMI);
|
||
|
__smp_perf_counter_interrupt(regs, 1);
|
||
|
|
||
|
return NOTIFY_STOP;
|
||
|
}
|
||
|
|
||
|
static __read_mostly struct notifier_block perf_counter_nmi_notifier = {
|
||
|
.notifier_call = perf_counter_nmi_handler
|
||
|
};
|
||
|
|
||
|
void __init init_hw_perf_counters(void)
|
||
|
{
|
||
|
union cpuid10_eax eax;
|
||
|
unsigned int unused;
|
||
|
unsigned int ebx;
|
||
|
|
||
|
if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
|
||
|
return;
|
||
|
|
||
|
/*
|
||
|
* Check whether the Architectural PerfMon supports
|
||
|
* Branch Misses Retired Event or not.
|
||
|
*/
|
||
|
cpuid(10, &(eax.full), &ebx, &unused, &unused);
|
||
|
if (eax.split.mask_length <= ARCH_PERFMON_BRANCH_MISSES_RETIRED)
|
||
|
return;
|
||
|
|
||
|
printk(KERN_INFO "Intel Performance Monitoring support detected.\n");
|
||
|
|
||
|
printk(KERN_INFO "... version: %d\n", eax.split.version_id);
|
||
|
printk(KERN_INFO "... num_counters: %d\n", eax.split.num_counters);
|
||
|
nr_hw_counters = eax.split.num_counters;
|
||
|
if (nr_hw_counters > MAX_HW_COUNTERS) {
|
||
|
nr_hw_counters = MAX_HW_COUNTERS;
|
||
|
WARN(1, KERN_ERR "hw perf counters %d > max(%d), clipping!",
|
||
|
nr_hw_counters, MAX_HW_COUNTERS);
|
||
|
}
|
||
|
perf_counter_mask = (1 << nr_hw_counters) - 1;
|
||
|
perf_max_counters = nr_hw_counters;
|
||
|
|
||
|
printk(KERN_INFO "... bit_width: %d\n", eax.split.bit_width);
|
||
|
printk(KERN_INFO "... mask_length: %d\n", eax.split.mask_length);
|
||
|
|
||
|
perf_counters_lapic_init(0);
|
||
|
register_die_notifier(&perf_counter_nmi_notifier);
|
||
|
|
||
|
perf_counters_initialized = true;
|
||
|
}
|