2019-05-19 21:51:43 +08:00
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// SPDX-License-Identifier: GPL-2.0-or-later
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2018-03-09 22:47:01 +08:00
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/*
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* HiSilicon INNO USB2 PHY Driver.
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*
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* Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/phy/phy.h>
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#include <linux/reset.h>
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#define INNO_PHY_PORT_NUM 2
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#define REF_CLK_STABLE_TIME 100 /* unit:us */
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#define UTMI_CLK_STABLE_TIME 200 /* unit:us */
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#define TEST_CLK_STABLE_TIME 2 /* unit:ms */
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#define PHY_CLK_STABLE_TIME 2 /* unit:ms */
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#define UTMI_RST_COMPLETE_TIME 2 /* unit:ms */
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#define POR_RST_COMPLETE_TIME 300 /* unit:us */
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#define PHY_TEST_DATA GENMASK(7, 0)
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#define PHY_TEST_ADDR GENMASK(15, 8)
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#define PHY_TEST_PORT GENMASK(18, 16)
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#define PHY_TEST_WREN BIT(21)
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#define PHY_TEST_CLK BIT(22) /* rising edge active */
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#define PHY_TEST_RST BIT(23) /* low active */
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#define PHY_CLK_ENABLE BIT(2)
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struct hisi_inno_phy_port {
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struct reset_control *utmi_rst;
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struct hisi_inno_phy_priv *priv;
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};
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struct hisi_inno_phy_priv {
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void __iomem *mmio;
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struct clk *ref_clk;
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struct reset_control *por_rst;
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struct hisi_inno_phy_port ports[INNO_PHY_PORT_NUM];
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};
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static void hisi_inno_phy_write_reg(struct hisi_inno_phy_priv *priv,
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u8 port, u32 addr, u32 data)
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{
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void __iomem *reg = priv->mmio;
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u32 val;
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val = (data & PHY_TEST_DATA) |
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((addr << 8) & PHY_TEST_ADDR) |
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((port << 16) & PHY_TEST_PORT) |
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PHY_TEST_WREN | PHY_TEST_RST;
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writel(val, reg);
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val |= PHY_TEST_CLK;
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writel(val, reg);
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val &= ~PHY_TEST_CLK;
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writel(val, reg);
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}
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static void hisi_inno_phy_setup(struct hisi_inno_phy_priv *priv)
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{
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/* The phy clk is controlled by the port0 register 0x06. */
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hisi_inno_phy_write_reg(priv, 0, 0x06, PHY_CLK_ENABLE);
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msleep(PHY_CLK_STABLE_TIME);
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}
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static int hisi_inno_phy_init(struct phy *phy)
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{
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struct hisi_inno_phy_port *port = phy_get_drvdata(phy);
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struct hisi_inno_phy_priv *priv = port->priv;
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int ret;
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ret = clk_prepare_enable(priv->ref_clk);
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if (ret)
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return ret;
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udelay(REF_CLK_STABLE_TIME);
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reset_control_deassert(priv->por_rst);
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udelay(POR_RST_COMPLETE_TIME);
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/* Set up phy registers */
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hisi_inno_phy_setup(priv);
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reset_control_deassert(port->utmi_rst);
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udelay(UTMI_RST_COMPLETE_TIME);
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return 0;
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}
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static int hisi_inno_phy_exit(struct phy *phy)
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{
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struct hisi_inno_phy_port *port = phy_get_drvdata(phy);
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struct hisi_inno_phy_priv *priv = port->priv;
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reset_control_assert(port->utmi_rst);
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reset_control_assert(priv->por_rst);
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clk_disable_unprepare(priv->ref_clk);
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return 0;
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}
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static const struct phy_ops hisi_inno_phy_ops = {
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.init = hisi_inno_phy_init,
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.exit = hisi_inno_phy_exit,
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.owner = THIS_MODULE,
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};
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static int hisi_inno_phy_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct device_node *np = dev->of_node;
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struct hisi_inno_phy_priv *priv;
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struct phy_provider *provider;
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struct device_node *child;
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int i = 0;
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int ret;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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2019-10-16 21:57:35 +08:00
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priv->mmio = devm_platform_ioremap_resource(pdev, 0);
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2018-03-09 22:47:01 +08:00
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if (IS_ERR(priv->mmio)) {
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ret = PTR_ERR(priv->mmio);
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return ret;
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}
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priv->ref_clk = devm_clk_get(dev, NULL);
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if (IS_ERR(priv->ref_clk))
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return PTR_ERR(priv->ref_clk);
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priv->por_rst = devm_reset_control_get_exclusive(dev, NULL);
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if (IS_ERR(priv->por_rst))
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return PTR_ERR(priv->por_rst);
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for_each_child_of_node(np, child) {
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struct reset_control *rst;
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struct phy *phy;
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rst = of_reset_control_get_exclusive(child, NULL);
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2021-10-15 16:01:51 +08:00
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if (IS_ERR(rst)) {
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of_node_put(child);
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2018-03-09 22:47:01 +08:00
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return PTR_ERR(rst);
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2021-10-15 16:01:51 +08:00
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}
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2018-03-09 22:47:01 +08:00
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priv->ports[i].utmi_rst = rst;
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priv->ports[i].priv = priv;
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phy = devm_phy_create(dev, child, &hisi_inno_phy_ops);
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2021-10-15 16:01:51 +08:00
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if (IS_ERR(phy)) {
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of_node_put(child);
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2018-03-09 22:47:01 +08:00
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return PTR_ERR(phy);
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2021-10-15 16:01:51 +08:00
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}
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2018-03-09 22:47:01 +08:00
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phy_set_bus_width(phy, 8);
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phy_set_drvdata(phy, &priv->ports[i]);
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i++;
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if (i > INNO_PHY_PORT_NUM) {
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dev_warn(dev, "Support %d ports in maximum\n", i);
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2021-10-15 16:01:51 +08:00
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of_node_put(child);
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2018-03-09 22:47:01 +08:00
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break;
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}
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}
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provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
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return PTR_ERR_OR_ZERO(provider);
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}
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static const struct of_device_id hisi_inno_phy_of_match[] = {
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{ .compatible = "hisilicon,inno-usb2-phy", },
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{ .compatible = "hisilicon,hi3798cv200-usb2-phy", },
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{ },
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};
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MODULE_DEVICE_TABLE(of, hisi_inno_phy_of_match);
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static struct platform_driver hisi_inno_phy_driver = {
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.probe = hisi_inno_phy_probe,
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.driver = {
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.name = "hisi-inno-phy",
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.of_match_table = hisi_inno_phy_of_match,
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}
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};
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module_platform_driver(hisi_inno_phy_driver);
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MODULE_DESCRIPTION("HiSilicon INNO USB2 PHY Driver");
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MODULE_LICENSE("GPL v2");
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