2005-06-28 20:48:56 +08:00
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/* via_dma.c -- DMA support for the VIA Unichrome/Pro
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2005-09-25 12:28:13 +08:00
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*
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2005-06-28 20:48:56 +08:00
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* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
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* All Rights Reserved.
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*
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* Copyright 2004 Digeo, Inc., Palo Alto, CA, U.S.A.
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* All Rights Reserved.
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2005-09-25 12:28:13 +08:00
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*
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2005-06-28 20:48:56 +08:00
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* Copyright 2004 The Unichrome project.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sub license,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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2005-09-25 12:28:13 +08:00
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* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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2005-06-28 20:48:56 +08:00
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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2005-09-25 12:28:13 +08:00
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* Authors:
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* Tungsten Graphics,
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* Erdi Chen,
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2005-06-28 20:48:56 +08:00
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* Thomas Hellstrom.
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*/
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#include "drmP.h"
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#include "drm.h"
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#include "via_drm.h"
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#include "via_drv.h"
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#include "via_3d_reg.h"
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#define CMDBUF_ALIGNMENT_SIZE (0x100)
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#define CMDBUF_ALIGNMENT_MASK (0x0ff)
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/* defines for VIA 3D registers */
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#define VIA_REG_STATUS 0x400
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#define VIA_REG_TRANSET 0x43C
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#define VIA_REG_TRANSPACE 0x440
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/* VIA_REG_STATUS(0x400): Engine Status */
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#define VIA_CMD_RGTR_BUSY 0x00000080 /* Command Regulator is busy */
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#define VIA_2D_ENG_BUSY 0x00000001 /* 2D Engine is busy */
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#define VIA_3D_ENG_BUSY 0x00000002 /* 3D Engine is busy */
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#define VIA_VR_QUEUE_BUSY 0x00020000 /* Virtual Queue is busy */
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#define SetReg2DAGP(nReg, nData) { \
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*((uint32_t *)(vb)) = ((nReg) >> 2) | HALCYON_HEADER1; \
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*((uint32_t *)(vb) + 1) = (nData); \
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vb = ((uint32_t *)vb) + 2; \
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dev_priv->dma_low +=8; \
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}
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2005-09-25 12:28:13 +08:00
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#define via_flush_write_combine() DRM_MEMORYBARRIER()
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2005-06-28 20:48:56 +08:00
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#define VIA_OUT_RING_QW(w1,w2) \
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*vb++ = (w1); \
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*vb++ = (w2); \
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2005-09-25 12:28:13 +08:00
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dev_priv->dma_low += 8;
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2005-06-28 20:48:56 +08:00
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static void via_cmdbuf_start(drm_via_private_t * dev_priv);
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static void via_cmdbuf_pause(drm_via_private_t * dev_priv);
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static void via_cmdbuf_reset(drm_via_private_t * dev_priv);
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static void via_cmdbuf_rewind(drm_via_private_t * dev_priv);
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static int via_wait_idle(drm_via_private_t * dev_priv);
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2005-09-25 12:28:13 +08:00
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static void via_pad_cache(drm_via_private_t * dev_priv, int qwords);
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2005-06-28 20:48:56 +08:00
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/*
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* Free space in command buffer.
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*/
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2005-09-25 12:28:13 +08:00
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static uint32_t via_cmdbuf_space(drm_via_private_t * dev_priv)
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2005-06-28 20:48:56 +08:00
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{
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2005-09-25 12:28:13 +08:00
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uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
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2005-06-28 20:48:56 +08:00
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uint32_t hw_addr = *(dev_priv->hw_addr_ptr) - agp_base;
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2005-09-25 12:28:13 +08:00
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return ((hw_addr <= dev_priv->dma_low) ?
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(dev_priv->dma_high + hw_addr - dev_priv->dma_low) :
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2005-06-28 20:48:56 +08:00
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(hw_addr - dev_priv->dma_low));
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}
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/*
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* How much does the command regulator lag behind?
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*/
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2005-09-25 12:28:13 +08:00
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static uint32_t via_cmdbuf_lag(drm_via_private_t * dev_priv)
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2005-06-28 20:48:56 +08:00
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{
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2005-09-25 12:28:13 +08:00
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uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
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2005-06-28 20:48:56 +08:00
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uint32_t hw_addr = *(dev_priv->hw_addr_ptr) - agp_base;
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2005-09-25 12:28:13 +08:00
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return ((hw_addr <= dev_priv->dma_low) ?
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(dev_priv->dma_low - hw_addr) :
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2005-06-28 20:48:56 +08:00
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(dev_priv->dma_wrap + dev_priv->dma_low - hw_addr));
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}
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/*
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* Check that the given size fits in the buffer, otherwise wait.
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*/
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static inline int
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via_cmdbuf_wait(drm_via_private_t * dev_priv, unsigned int size)
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{
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uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
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uint32_t cur_addr, hw_addr, next_addr;
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volatile uint32_t *hw_addr_ptr;
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uint32_t count;
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hw_addr_ptr = dev_priv->hw_addr_ptr;
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cur_addr = dev_priv->dma_low;
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2005-09-25 12:28:13 +08:00
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next_addr = cur_addr + size + 512 * 1024;
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2005-06-28 20:48:56 +08:00
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count = 1000000;
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do {
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2005-09-25 12:28:13 +08:00
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hw_addr = *hw_addr_ptr - agp_base;
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2005-06-28 20:48:56 +08:00
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if (count-- == 0) {
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2005-09-25 12:28:13 +08:00
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DRM_ERROR
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("via_cmdbuf_wait timed out hw %x cur_addr %x next_addr %x\n",
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hw_addr, cur_addr, next_addr);
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2005-06-28 20:48:56 +08:00
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return -1;
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}
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} while ((cur_addr < hw_addr) && (next_addr >= hw_addr));
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return 0;
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}
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/*
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* Checks whether buffer head has reach the end. Rewind the ring buffer
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* when necessary.
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*
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* Returns virtual pointer to ring buffer.
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*/
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static inline uint32_t *via_check_dma(drm_via_private_t * dev_priv,
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unsigned int size)
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{
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2005-09-25 12:28:13 +08:00
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if ((dev_priv->dma_low + size + 4 * CMDBUF_ALIGNMENT_SIZE) >
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dev_priv->dma_high) {
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2005-06-28 20:48:56 +08:00
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via_cmdbuf_rewind(dev_priv);
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}
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if (via_cmdbuf_wait(dev_priv, size) != 0) {
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return NULL;
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}
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return (uint32_t *) (dev_priv->dma_ptr + dev_priv->dma_low);
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}
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2007-07-11 13:53:27 +08:00
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int via_dma_cleanup(struct drm_device * dev)
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2005-06-28 20:48:56 +08:00
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{
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if (dev->dev_private) {
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drm_via_private_t *dev_priv =
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2005-09-25 12:28:13 +08:00
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(drm_via_private_t *) dev->dev_private;
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2005-06-28 20:48:56 +08:00
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if (dev_priv->ring.virtual_start) {
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via_cmdbuf_reset(dev_priv);
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drm_core_ioremapfree(&dev_priv->ring.map, dev);
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dev_priv->ring.virtual_start = NULL;
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}
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}
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return 0;
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}
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2007-07-11 13:53:27 +08:00
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static int via_initialize(struct drm_device * dev,
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2005-06-28 20:48:56 +08:00
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drm_via_private_t * dev_priv,
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drm_via_dma_init_t * init)
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{
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if (!dev_priv || !dev_priv->mmio) {
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DRM_ERROR("via_dma_init called before via_map_init\n");
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2007-08-25 17:22:43 +08:00
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return -EFAULT;
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2005-06-28 20:48:56 +08:00
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}
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if (dev_priv->ring.virtual_start != NULL) {
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DRM_ERROR("%s called again without calling cleanup\n",
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__FUNCTION__);
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2007-08-25 17:22:43 +08:00
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return -EFAULT;
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2005-06-28 20:48:56 +08:00
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}
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if (!dev->agp || !dev->agp->base) {
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2005-09-25 12:28:13 +08:00
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DRM_ERROR("%s called with no agp memory available\n",
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2005-06-28 20:48:56 +08:00
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__FUNCTION__);
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2007-08-25 17:22:43 +08:00
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return -EFAULT;
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2005-06-28 20:48:56 +08:00
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}
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2007-02-08 09:57:40 +08:00
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if (dev_priv->chipset == VIA_DX9_0) {
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DRM_ERROR("AGP DMA is not supported on this chip\n");
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2007-08-25 17:22:43 +08:00
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return -EINVAL;
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2007-02-08 09:57:40 +08:00
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}
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2005-06-28 20:48:56 +08:00
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dev_priv->ring.map.offset = dev->agp->base + init->offset;
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dev_priv->ring.map.size = init->size;
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dev_priv->ring.map.type = 0;
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dev_priv->ring.map.flags = 0;
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dev_priv->ring.map.mtrr = 0;
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drm_core_ioremap(&dev_priv->ring.map, dev);
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if (dev_priv->ring.map.handle == NULL) {
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via_dma_cleanup(dev);
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DRM_ERROR("can not ioremap virtual address for"
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" ring buffer\n");
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2007-08-25 17:22:43 +08:00
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return -ENOMEM;
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2005-06-28 20:48:56 +08:00
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}
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dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
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dev_priv->dma_ptr = dev_priv->ring.virtual_start;
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dev_priv->dma_low = 0;
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dev_priv->dma_high = init->size;
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dev_priv->dma_wrap = init->size;
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dev_priv->dma_offset = init->offset;
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dev_priv->last_pause_ptr = NULL;
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2005-11-12 18:52:46 +08:00
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dev_priv->hw_addr_ptr =
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(volatile uint32_t *)((char *)dev_priv->mmio->handle +
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init->reg_pause_addr);
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2005-06-28 20:48:56 +08:00
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via_cmdbuf_start(dev_priv);
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return 0;
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}
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2006-02-02 16:21:38 +08:00
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static int via_dma_init(DRM_IOCTL_ARGS)
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2005-06-28 20:48:56 +08:00
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{
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DRM_DEVICE;
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drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
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drm_via_dma_init_t init;
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int retcode = 0;
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2005-07-28 02:43:56 +08:00
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DRM_COPY_FROM_USER_IOCTL(init, (drm_via_dma_init_t __user *) data,
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2005-06-28 20:48:56 +08:00
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sizeof(init));
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switch (init.func) {
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case VIA_INIT_DMA:
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2005-11-12 18:52:46 +08:00
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if (!DRM_SUSER(DRM_CURPROC))
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2007-08-25 17:22:43 +08:00
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retcode = -EPERM;
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2005-06-28 20:48:56 +08:00
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else
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retcode = via_initialize(dev, dev_priv, &init);
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break;
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case VIA_CLEANUP_DMA:
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2005-11-12 18:52:46 +08:00
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if (!DRM_SUSER(DRM_CURPROC))
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2007-08-25 17:22:43 +08:00
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retcode = -EPERM;
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2005-06-28 20:48:56 +08:00
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else
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retcode = via_dma_cleanup(dev);
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break;
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2005-09-25 12:28:13 +08:00
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case VIA_DMA_INITIALIZED:
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retcode = (dev_priv->ring.virtual_start != NULL) ?
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2007-08-25 17:22:43 +08:00
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0 : -EFAULT;
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2005-09-25 12:28:13 +08:00
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break;
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2005-06-28 20:48:56 +08:00
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default:
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2007-08-25 17:22:43 +08:00
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retcode = -EINVAL;
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2005-06-28 20:48:56 +08:00
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break;
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}
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return retcode;
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}
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2007-07-11 13:53:27 +08:00
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static int via_dispatch_cmdbuffer(struct drm_device * dev, drm_via_cmdbuffer_t * cmd)
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2005-06-28 20:48:56 +08:00
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{
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drm_via_private_t *dev_priv;
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uint32_t *vb;
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int ret;
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dev_priv = (drm_via_private_t *) dev->dev_private;
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if (dev_priv->ring.virtual_start == NULL) {
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DRM_ERROR("%s called without initializing AGP ring buffer.\n",
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__FUNCTION__);
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2007-08-25 17:22:43 +08:00
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return -EFAULT;
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2005-06-28 20:48:56 +08:00
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}
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if (cmd->size > VIA_PCI_BUF_SIZE) {
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2007-08-25 17:22:43 +08:00
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return -ENOMEM;
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2005-09-25 12:28:13 +08:00
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}
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2005-06-28 20:48:56 +08:00
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if (DRM_COPY_FROM_USER(dev_priv->pci_buf, cmd->buf, cmd->size))
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2007-08-25 17:22:43 +08:00
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return -EFAULT;
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2005-06-28 20:48:56 +08:00
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/*
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* Running this function on AGP memory is dead slow. Therefore
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* we run it on a temporary cacheable system memory buffer and
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* copy it to AGP memory when ready.
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*/
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2005-09-25 12:28:13 +08:00
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if ((ret =
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via_verify_command_stream((uint32_t *) dev_priv->pci_buf,
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cmd->size, dev, 1))) {
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2005-06-28 20:48:56 +08:00
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return ret;
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}
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2005-09-25 12:28:13 +08:00
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2005-06-28 20:48:56 +08:00
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vb = via_check_dma(dev_priv, (cmd->size < 0x100) ? 0x102 : cmd->size);
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if (vb == NULL) {
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2007-08-25 17:22:43 +08:00
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|
return -EAGAIN;
|
2005-06-28 20:48:56 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
memcpy(vb, dev_priv->pci_buf, cmd->size);
|
2005-09-25 12:28:13 +08:00
|
|
|
|
2005-06-28 20:48:56 +08:00
|
|
|
dev_priv->dma_low += cmd->size;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Small submissions somehow stalls the CPU. (AGP cache effects?)
|
|
|
|
* pad to greater size.
|
|
|
|
*/
|
|
|
|
|
|
|
|
if (cmd->size < 0x100)
|
2005-09-25 12:28:13 +08:00
|
|
|
via_pad_cache(dev_priv, (0x100 - cmd->size) >> 3);
|
2005-06-28 20:48:56 +08:00
|
|
|
via_cmdbuf_pause(dev_priv);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2007-07-11 13:53:27 +08:00
|
|
|
int via_driver_dma_quiescent(struct drm_device * dev)
|
2005-06-28 20:48:56 +08:00
|
|
|
{
|
|
|
|
drm_via_private_t *dev_priv = dev->dev_private;
|
|
|
|
|
|
|
|
if (!via_wait_idle(dev_priv)) {
|
2007-08-25 17:22:43 +08:00
|
|
|
return -EBUSY;
|
2005-06-28 20:48:56 +08:00
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2006-02-02 16:21:38 +08:00
|
|
|
static int via_flush_ioctl(DRM_IOCTL_ARGS)
|
2005-06-28 20:48:56 +08:00
|
|
|
{
|
|
|
|
DRM_DEVICE;
|
|
|
|
|
2005-09-25 12:28:13 +08:00
|
|
|
LOCK_TEST_WITH_RETURN(dev, filp);
|
2005-06-28 20:48:56 +08:00
|
|
|
|
|
|
|
return via_driver_dma_quiescent(dev);
|
|
|
|
}
|
|
|
|
|
2006-02-02 16:21:38 +08:00
|
|
|
static int via_cmdbuffer(DRM_IOCTL_ARGS)
|
2005-06-28 20:48:56 +08:00
|
|
|
{
|
|
|
|
DRM_DEVICE;
|
|
|
|
drm_via_cmdbuffer_t cmdbuf;
|
|
|
|
int ret;
|
|
|
|
|
2005-09-25 12:28:13 +08:00
|
|
|
LOCK_TEST_WITH_RETURN(dev, filp);
|
2005-06-28 20:48:56 +08:00
|
|
|
|
2005-07-28 02:43:56 +08:00
|
|
|
DRM_COPY_FROM_USER_IOCTL(cmdbuf, (drm_via_cmdbuffer_t __user *) data,
|
2005-06-28 20:48:56 +08:00
|
|
|
sizeof(cmdbuf));
|
|
|
|
|
|
|
|
DRM_DEBUG("via cmdbuffer, buf %p size %lu\n", cmdbuf.buf, cmdbuf.size);
|
|
|
|
|
|
|
|
ret = via_dispatch_cmdbuffer(dev, &cmdbuf);
|
|
|
|
if (ret) {
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2007-07-11 13:53:27 +08:00
|
|
|
static int via_dispatch_pci_cmdbuffer(struct drm_device * dev,
|
2005-06-28 20:48:56 +08:00
|
|
|
drm_via_cmdbuffer_t * cmd)
|
|
|
|
{
|
|
|
|
drm_via_private_t *dev_priv = dev->dev_private;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (cmd->size > VIA_PCI_BUF_SIZE) {
|
2007-08-25 17:22:43 +08:00
|
|
|
return -ENOMEM;
|
2005-09-25 12:28:13 +08:00
|
|
|
}
|
2005-06-28 20:48:56 +08:00
|
|
|
if (DRM_COPY_FROM_USER(dev_priv->pci_buf, cmd->buf, cmd->size))
|
2007-08-25 17:22:43 +08:00
|
|
|
return -EFAULT;
|
2005-09-25 12:28:13 +08:00
|
|
|
|
|
|
|
if ((ret =
|
|
|
|
via_verify_command_stream((uint32_t *) dev_priv->pci_buf,
|
|
|
|
cmd->size, dev, 0))) {
|
2005-06-28 20:48:56 +08:00
|
|
|
return ret;
|
|
|
|
}
|
2005-09-25 12:28:13 +08:00
|
|
|
|
|
|
|
ret =
|
|
|
|
via_parse_command_stream(dev, (const uint32_t *)dev_priv->pci_buf,
|
|
|
|
cmd->size);
|
2005-06-28 20:48:56 +08:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2006-02-02 16:21:38 +08:00
|
|
|
static int via_pci_cmdbuffer(DRM_IOCTL_ARGS)
|
2005-06-28 20:48:56 +08:00
|
|
|
{
|
|
|
|
DRM_DEVICE;
|
|
|
|
drm_via_cmdbuffer_t cmdbuf;
|
|
|
|
int ret;
|
|
|
|
|
2005-09-25 12:28:13 +08:00
|
|
|
LOCK_TEST_WITH_RETURN(dev, filp);
|
2005-06-28 20:48:56 +08:00
|
|
|
|
2005-07-28 02:43:56 +08:00
|
|
|
DRM_COPY_FROM_USER_IOCTL(cmdbuf, (drm_via_cmdbuffer_t __user *) data,
|
2005-06-28 20:48:56 +08:00
|
|
|
sizeof(cmdbuf));
|
|
|
|
|
|
|
|
DRM_DEBUG("via_pci_cmdbuffer, buf %p size %lu\n", cmdbuf.buf,
|
|
|
|
cmdbuf.size);
|
|
|
|
|
|
|
|
ret = via_dispatch_pci_cmdbuffer(dev, &cmdbuf);
|
|
|
|
if (ret) {
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline uint32_t *via_align_buffer(drm_via_private_t * dev_priv,
|
|
|
|
uint32_t * vb, int qw_count)
|
|
|
|
{
|
2005-09-25 12:28:13 +08:00
|
|
|
for (; qw_count > 0; --qw_count) {
|
2005-06-28 20:48:56 +08:00
|
|
|
VIA_OUT_RING_QW(HC_DUMMY, HC_DUMMY);
|
|
|
|
}
|
|
|
|
return vb;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* This function is used internally by ring buffer mangement code.
|
|
|
|
*
|
|
|
|
* Returns virtual pointer to ring buffer.
|
|
|
|
*/
|
|
|
|
static inline uint32_t *via_get_dma(drm_via_private_t * dev_priv)
|
|
|
|
{
|
|
|
|
return (uint32_t *) (dev_priv->dma_ptr + dev_priv->dma_low);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Hooks a segment of data into the tail of the ring-buffer by
|
|
|
|
* modifying the pause address stored in the buffer itself. If
|
|
|
|
* the regulator has already paused, restart it.
|
|
|
|
*/
|
2005-09-25 12:28:13 +08:00
|
|
|
static int via_hook_segment(drm_via_private_t * dev_priv,
|
2005-06-28 20:48:56 +08:00
|
|
|
uint32_t pause_addr_hi, uint32_t pause_addr_lo,
|
|
|
|
int no_pci_fire)
|
|
|
|
{
|
|
|
|
int paused, count;
|
|
|
|
volatile uint32_t *paused_at = dev_priv->last_pause_ptr;
|
2007-05-08 13:47:41 +08:00
|
|
|
uint32_t reader,ptr;
|
2005-06-28 20:48:56 +08:00
|
|
|
|
2007-05-08 13:47:41 +08:00
|
|
|
paused = 0;
|
2005-06-28 20:48:56 +08:00
|
|
|
via_flush_write_combine();
|
2007-05-08 13:48:39 +08:00
|
|
|
(void) *(volatile uint32_t *)(via_get_dma(dev_priv) -1);
|
|
|
|
*paused_at = pause_addr_lo;
|
2005-06-28 20:48:56 +08:00
|
|
|
via_flush_write_combine();
|
2007-05-08 13:48:39 +08:00
|
|
|
(void) *paused_at;
|
2007-05-08 13:47:41 +08:00
|
|
|
reader = *(dev_priv->hw_addr_ptr);
|
|
|
|
ptr = ((volatile char *)paused_at - dev_priv->dma_ptr) +
|
|
|
|
dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr + 4;
|
2005-06-28 20:48:56 +08:00
|
|
|
dev_priv->last_pause_ptr = via_get_dma(dev_priv) - 1;
|
|
|
|
|
2007-05-08 13:47:41 +08:00
|
|
|
if ((ptr - reader) <= dev_priv->dma_diff ) {
|
|
|
|
count = 10000000;
|
|
|
|
while (!(paused = (VIA_READ(0x41c) & 0x80000000)) && count--);
|
2005-06-28 20:48:56 +08:00
|
|
|
}
|
2005-09-25 12:28:13 +08:00
|
|
|
|
2005-06-28 20:48:56 +08:00
|
|
|
if (paused && !no_pci_fire) {
|
2007-05-08 13:47:41 +08:00
|
|
|
reader = *(dev_priv->hw_addr_ptr);
|
|
|
|
if ((ptr - reader) == dev_priv->dma_diff) {
|
2005-06-28 20:48:56 +08:00
|
|
|
|
2007-05-08 13:47:41 +08:00
|
|
|
/*
|
|
|
|
* There is a concern that these writes may stall the PCI bus
|
|
|
|
* if the GPU is not idle. However, idling the GPU first
|
|
|
|
* doesn't make a difference.
|
|
|
|
*/
|
2005-09-25 12:28:13 +08:00
|
|
|
|
2005-06-28 20:48:56 +08:00
|
|
|
VIA_WRITE(VIA_REG_TRANSET, (HC_ParaType_PreCR << 16));
|
|
|
|
VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_hi);
|
|
|
|
VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_lo);
|
2007-01-08 18:03:23 +08:00
|
|
|
VIA_READ(VIA_REG_TRANSPACE);
|
2005-09-25 12:28:13 +08:00
|
|
|
}
|
2005-06-28 20:48:56 +08:00
|
|
|
}
|
|
|
|
return paused;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int via_wait_idle(drm_via_private_t * dev_priv)
|
|
|
|
{
|
|
|
|
int count = 10000000;
|
2007-05-08 13:47:41 +08:00
|
|
|
|
|
|
|
while (!(VIA_READ(VIA_REG_STATUS) & VIA_VR_QUEUE_BUSY) && count--);
|
|
|
|
|
2005-06-28 20:48:56 +08:00
|
|
|
while (count-- && (VIA_READ(VIA_REG_STATUS) &
|
|
|
|
(VIA_CMD_RGTR_BUSY | VIA_2D_ENG_BUSY |
|
|
|
|
VIA_3D_ENG_BUSY))) ;
|
|
|
|
return count;
|
|
|
|
}
|
|
|
|
|
|
|
|
static uint32_t *via_align_cmd(drm_via_private_t * dev_priv, uint32_t cmd_type,
|
2005-09-25 12:28:13 +08:00
|
|
|
uint32_t addr, uint32_t * cmd_addr_hi,
|
|
|
|
uint32_t * cmd_addr_lo, int skip_wait)
|
2005-06-28 20:48:56 +08:00
|
|
|
{
|
|
|
|
uint32_t agp_base;
|
|
|
|
uint32_t cmd_addr, addr_lo, addr_hi;
|
|
|
|
uint32_t *vb;
|
|
|
|
uint32_t qw_pad_count;
|
|
|
|
|
|
|
|
if (!skip_wait)
|
2005-09-25 12:28:13 +08:00
|
|
|
via_cmdbuf_wait(dev_priv, 2 * CMDBUF_ALIGNMENT_SIZE);
|
2005-06-28 20:48:56 +08:00
|
|
|
|
|
|
|
vb = via_get_dma(dev_priv);
|
2005-09-25 12:28:13 +08:00
|
|
|
VIA_OUT_RING_QW(HC_HEADER2 | ((VIA_REG_TRANSET >> 2) << 12) |
|
|
|
|
(VIA_REG_TRANSPACE >> 2), HC_ParaType_PreCR << 16);
|
2005-06-28 20:48:56 +08:00
|
|
|
agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
|
|
|
|
qw_pad_count = (CMDBUF_ALIGNMENT_SIZE >> 3) -
|
2005-09-25 12:28:13 +08:00
|
|
|
((dev_priv->dma_low & CMDBUF_ALIGNMENT_MASK) >> 3);
|
2005-06-28 20:48:56 +08:00
|
|
|
|
2005-09-25 12:28:13 +08:00
|
|
|
cmd_addr = (addr) ? addr :
|
|
|
|
agp_base + dev_priv->dma_low - 8 + (qw_pad_count << 3);
|
2005-06-28 20:48:56 +08:00
|
|
|
addr_lo = ((HC_SubA_HAGPBpL << 24) | (cmd_type & HC_HAGPBpID_MASK) |
|
|
|
|
(cmd_addr & HC_HAGPBpL_MASK));
|
|
|
|
addr_hi = ((HC_SubA_HAGPBpH << 24) | (cmd_addr >> 24));
|
|
|
|
|
|
|
|
vb = via_align_buffer(dev_priv, vb, qw_pad_count - 1);
|
2005-09-25 12:28:13 +08:00
|
|
|
VIA_OUT_RING_QW(*cmd_addr_hi = addr_hi, *cmd_addr_lo = addr_lo);
|
2005-06-28 20:48:56 +08:00
|
|
|
return vb;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void via_cmdbuf_start(drm_via_private_t * dev_priv)
|
|
|
|
{
|
|
|
|
uint32_t pause_addr_lo, pause_addr_hi;
|
|
|
|
uint32_t start_addr, start_addr_lo;
|
|
|
|
uint32_t end_addr, end_addr_lo;
|
|
|
|
uint32_t command;
|
|
|
|
uint32_t agp_base;
|
2007-05-08 13:47:41 +08:00
|
|
|
uint32_t ptr;
|
|
|
|
uint32_t reader;
|
|
|
|
int count;
|
2005-06-28 20:48:56 +08:00
|
|
|
|
|
|
|
dev_priv->dma_low = 0;
|
|
|
|
|
|
|
|
agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
|
|
|
|
start_addr = agp_base;
|
|
|
|
end_addr = agp_base + dev_priv->dma_high;
|
|
|
|
|
|
|
|
start_addr_lo = ((HC_SubA_HAGPBstL << 24) | (start_addr & 0xFFFFFF));
|
|
|
|
end_addr_lo = ((HC_SubA_HAGPBendL << 24) | (end_addr & 0xFFFFFF));
|
|
|
|
command = ((HC_SubA_HAGPCMNT << 24) | (start_addr >> 24) |
|
|
|
|
((end_addr & 0xff000000) >> 16));
|
|
|
|
|
2005-09-25 12:28:13 +08:00
|
|
|
dev_priv->last_pause_ptr =
|
|
|
|
via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0,
|
|
|
|
&pause_addr_hi, &pause_addr_lo, 1) - 1;
|
2005-06-28 20:48:56 +08:00
|
|
|
|
|
|
|
via_flush_write_combine();
|
2007-05-08 13:48:39 +08:00
|
|
|
(void) *(volatile uint32_t *)dev_priv->last_pause_ptr;
|
2005-06-28 20:48:56 +08:00
|
|
|
|
|
|
|
VIA_WRITE(VIA_REG_TRANSET, (HC_ParaType_PreCR << 16));
|
|
|
|
VIA_WRITE(VIA_REG_TRANSPACE, command);
|
|
|
|
VIA_WRITE(VIA_REG_TRANSPACE, start_addr_lo);
|
|
|
|
VIA_WRITE(VIA_REG_TRANSPACE, end_addr_lo);
|
|
|
|
|
|
|
|
VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_hi);
|
|
|
|
VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_lo);
|
2007-01-08 18:03:23 +08:00
|
|
|
DRM_WRITEMEMORYBARRIER();
|
2005-06-28 20:48:56 +08:00
|
|
|
VIA_WRITE(VIA_REG_TRANSPACE, command | HC_HAGPCMNT_MASK);
|
2007-01-08 18:03:23 +08:00
|
|
|
VIA_READ(VIA_REG_TRANSPACE);
|
2007-05-08 13:47:41 +08:00
|
|
|
|
|
|
|
dev_priv->dma_diff = 0;
|
|
|
|
|
|
|
|
count = 10000000;
|
|
|
|
while (!(VIA_READ(0x41c) & 0x80000000) && count--);
|
|
|
|
|
|
|
|
reader = *(dev_priv->hw_addr_ptr);
|
|
|
|
ptr = ((volatile char *)dev_priv->last_pause_ptr - dev_priv->dma_ptr) +
|
|
|
|
dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr + 4;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* This is the difference between where we tell the
|
|
|
|
* command reader to pause and where it actually pauses.
|
|
|
|
* This differs between hw implementation so we need to
|
|
|
|
* detect it.
|
|
|
|
*/
|
|
|
|
|
|
|
|
dev_priv->dma_diff = ptr - reader;
|
2005-06-28 20:48:56 +08:00
|
|
|
}
|
|
|
|
|
2005-09-25 12:28:13 +08:00
|
|
|
static void via_pad_cache(drm_via_private_t * dev_priv, int qwords)
|
2005-06-28 20:48:56 +08:00
|
|
|
{
|
|
|
|
uint32_t *vb;
|
|
|
|
|
|
|
|
via_cmdbuf_wait(dev_priv, qwords + 2);
|
|
|
|
vb = via_get_dma(dev_priv);
|
2005-09-25 12:28:13 +08:00
|
|
|
VIA_OUT_RING_QW(HC_HEADER2, HC_ParaType_NotTex << 16);
|
|
|
|
via_align_buffer(dev_priv, vb, qwords);
|
2005-06-28 20:48:56 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline void via_dummy_bitblt(drm_via_private_t * dev_priv)
|
|
|
|
{
|
|
|
|
uint32_t *vb = via_get_dma(dev_priv);
|
|
|
|
SetReg2DAGP(0x0C, (0 | (0 << 16)));
|
|
|
|
SetReg2DAGP(0x10, 0 | (0 << 16));
|
2005-09-25 12:28:13 +08:00
|
|
|
SetReg2DAGP(0x0, 0x1 | 0x2000 | 0xAA000000);
|
2005-06-28 20:48:56 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static void via_cmdbuf_jump(drm_via_private_t * dev_priv)
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{
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uint32_t agp_base;
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uint32_t pause_addr_lo, pause_addr_hi;
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uint32_t jump_addr_lo, jump_addr_hi;
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volatile uint32_t *last_pause_ptr;
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agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
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2005-09-25 12:28:13 +08:00
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via_align_cmd(dev_priv, HC_HAGPBpID_JUMP, 0, &jump_addr_hi,
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2005-06-28 20:48:56 +08:00
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&jump_addr_lo, 0);
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2005-09-25 12:28:13 +08:00
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dev_priv->dma_wrap = dev_priv->dma_low;
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2005-06-28 20:48:56 +08:00
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/*
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* Wrap command buffer to the beginning.
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*/
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dev_priv->dma_low = 0;
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if (via_cmdbuf_wait(dev_priv, CMDBUF_ALIGNMENT_SIZE) != 0) {
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DRM_ERROR("via_cmdbuf_jump failed\n");
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}
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via_dummy_bitblt(dev_priv);
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2005-09-25 12:28:13 +08:00
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via_dummy_bitblt(dev_priv);
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2005-06-28 20:48:56 +08:00
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2005-09-25 12:28:13 +08:00
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last_pause_ptr =
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via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi,
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&pause_addr_lo, 0) - 1;
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via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi,
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2005-06-28 20:48:56 +08:00
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&pause_addr_lo, 0);
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*last_pause_ptr = pause_addr_lo;
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2007-05-08 13:47:41 +08:00
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via_hook_segment( dev_priv, jump_addr_hi, jump_addr_lo, 0);
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2005-06-28 20:48:56 +08:00
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}
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2007-05-08 13:47:41 +08:00
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2005-06-28 20:48:56 +08:00
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static void via_cmdbuf_rewind(drm_via_private_t * dev_priv)
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{
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2005-09-25 12:28:13 +08:00
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via_cmdbuf_jump(dev_priv);
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2005-06-28 20:48:56 +08:00
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}
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static void via_cmdbuf_flush(drm_via_private_t * dev_priv, uint32_t cmd_type)
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{
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uint32_t pause_addr_lo, pause_addr_hi;
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via_align_cmd(dev_priv, cmd_type, 0, &pause_addr_hi, &pause_addr_lo, 0);
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2005-09-25 12:28:13 +08:00
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via_hook_segment(dev_priv, pause_addr_hi, pause_addr_lo, 0);
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2005-06-28 20:48:56 +08:00
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}
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static void via_cmdbuf_pause(drm_via_private_t * dev_priv)
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{
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via_cmdbuf_flush(dev_priv, HC_HAGPBpID_PAUSE);
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}
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static void via_cmdbuf_reset(drm_via_private_t * dev_priv)
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{
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via_cmdbuf_flush(dev_priv, HC_HAGPBpID_STOP);
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via_wait_idle(dev_priv);
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}
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/*
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* User interface to the space and lag functions.
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*/
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2006-02-02 16:21:38 +08:00
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static int via_cmdbuf_size(DRM_IOCTL_ARGS)
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2005-06-28 20:48:56 +08:00
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{
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DRM_DEVICE;
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drm_via_cmdbuf_size_t d_siz;
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int ret = 0;
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uint32_t tmp_size, count;
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drm_via_private_t *dev_priv;
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DRM_DEBUG("via cmdbuf_size\n");
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2005-09-25 12:28:13 +08:00
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LOCK_TEST_WITH_RETURN(dev, filp);
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2005-06-28 20:48:56 +08:00
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dev_priv = (drm_via_private_t *) dev->dev_private;
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if (dev_priv->ring.virtual_start == NULL) {
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DRM_ERROR("%s called without initializing AGP ring buffer.\n",
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__FUNCTION__);
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2007-08-25 17:22:43 +08:00
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return -EFAULT;
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2005-06-28 20:48:56 +08:00
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}
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2005-07-28 02:43:56 +08:00
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DRM_COPY_FROM_USER_IOCTL(d_siz, (drm_via_cmdbuf_size_t __user *) data,
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2005-06-28 20:48:56 +08:00
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sizeof(d_siz));
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count = 1000000;
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tmp_size = d_siz.size;
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2005-09-25 12:28:13 +08:00
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switch (d_siz.func) {
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2005-06-28 20:48:56 +08:00
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case VIA_CMDBUF_SPACE:
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2005-09-25 12:28:13 +08:00
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while (((tmp_size = via_cmdbuf_space(dev_priv)) < d_siz.size)
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&& count--) {
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2005-06-28 20:48:56 +08:00
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if (!d_siz.wait) {
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break;
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}
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}
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if (!count) {
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DRM_ERROR("VIA_CMDBUF_SPACE timed out.\n");
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2007-08-25 17:22:43 +08:00
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ret = -EAGAIN;
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2005-06-28 20:48:56 +08:00
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}
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break;
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case VIA_CMDBUF_LAG:
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2005-09-25 12:28:13 +08:00
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while (((tmp_size = via_cmdbuf_lag(dev_priv)) > d_siz.size)
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&& count--) {
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2005-06-28 20:48:56 +08:00
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if (!d_siz.wait) {
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break;
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}
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}
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if (!count) {
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DRM_ERROR("VIA_CMDBUF_LAG timed out.\n");
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2007-08-25 17:22:43 +08:00
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ret = -EAGAIN;
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2005-06-28 20:48:56 +08:00
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}
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break;
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default:
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2007-08-25 17:22:43 +08:00
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ret = -EFAULT;
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2005-06-28 20:48:56 +08:00
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}
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d_siz.size = tmp_size;
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2005-07-28 02:43:56 +08:00
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DRM_COPY_TO_USER_IOCTL((drm_via_cmdbuf_size_t __user *) data, d_siz,
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2005-06-28 20:48:56 +08:00
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sizeof(d_siz));
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return ret;
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}
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2005-11-12 18:52:46 +08:00
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drm_ioctl_desc_t via_ioctls[] = {
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2006-01-02 10:54:04 +08:00
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[DRM_IOCTL_NR(DRM_VIA_ALLOCMEM)] = {via_mem_alloc, DRM_AUTH},
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[DRM_IOCTL_NR(DRM_VIA_FREEMEM)] = {via_mem_free, DRM_AUTH},
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[DRM_IOCTL_NR(DRM_VIA_AGP_INIT)] = {via_agp_init, DRM_AUTH|DRM_MASTER},
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[DRM_IOCTL_NR(DRM_VIA_FB_INIT)] = {via_fb_init, DRM_AUTH|DRM_MASTER},
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[DRM_IOCTL_NR(DRM_VIA_MAP_INIT)] = {via_map_init, DRM_AUTH|DRM_MASTER},
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[DRM_IOCTL_NR(DRM_VIA_DEC_FUTEX)] = {via_decoder_futex, DRM_AUTH},
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[DRM_IOCTL_NR(DRM_VIA_DMA_INIT)] = {via_dma_init, DRM_AUTH},
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[DRM_IOCTL_NR(DRM_VIA_CMDBUFFER)] = {via_cmdbuffer, DRM_AUTH},
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[DRM_IOCTL_NR(DRM_VIA_FLUSH)] = {via_flush_ioctl, DRM_AUTH},
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[DRM_IOCTL_NR(DRM_VIA_PCICMD)] = {via_pci_cmdbuffer, DRM_AUTH},
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[DRM_IOCTL_NR(DRM_VIA_CMDBUF_SIZE)] = {via_cmdbuf_size, DRM_AUTH},
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2006-01-02 11:26:20 +08:00
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[DRM_IOCTL_NR(DRM_VIA_WAIT_IRQ)] = {via_wait_irq, DRM_AUTH},
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[DRM_IOCTL_NR(DRM_VIA_DMA_BLIT)] = {via_dma_blit, DRM_AUTH},
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[DRM_IOCTL_NR(DRM_VIA_BLIT_SYNC)] = {via_dma_blit_sync, DRM_AUTH}
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2005-11-12 18:52:46 +08:00
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};
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int via_max_ioctl = DRM_ARRAY_SIZE(via_ioctls);
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