linux/arch/blackfin/lib/smulsi3_highpart.S

.align 2
.global ___smulsi3_highpart;
.type ___smulsi3_highpart, STT_FUNC;

#ifdef CONFIG_ARITHMETIC_OPS_L1
.section .l1.text
#else
.text
#endif

___smulsi3_highpart:
	R2 = R1.L * R0.L (FU);
	R3 = R1.H * R0.L (IS,M);
	R0 = R0.H * R1.H, R1 = R0.H * R1.L (IS,M);

	R1.L = R2.H + R1.L;
	cc = ac0;
	R2 = cc;

	R1.L = R1.L + R3.L;
	cc = ac0;
	R1 >>>= 16;
	R3 >>>= 16;
	R1 = R1 + R3;
	R1 = R1 + R2;
	R2 = cc;
	R1 = R1 + R2;

	R0 = R0 + R1;
	RTS;

.size ___smulsi3_highpart, .-___smulsi3_highpart
blackfin architecture This adds support for the Analog Devices Blackfin processor architecture, and currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561 (Dual Core) devices, with a variety of development platforms including those avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP, BF561-EZKIT), and Bluetechnix! Tinyboards. The Blackfin architecture was jointly developed by Intel and Analog Devices Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in December of 2000. Since then ADI has put this core into its Blackfin processor family of devices. The Blackfin core has the advantages of a clean, orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC (Multiply/Accumulate), state-of-the-art signal processing engine and single-instruction, multiple-data (SIMD) multimedia capabilities into a single instruction-set architecture. The Blackfin architecture, including the instruction set, is described by the ADSP-BF53x/BF56x Blackfin Processor Programming Reference http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf The Blackfin processor is already supported by major releases of gcc, and there are binary and source rpms/tarballs for many architectures at: http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete documentation, including "getting started" guides available at: http://docs.blackfin.uclinux.org/ which provides links to the sources and patches you will need in order to set up a cross-compiling environment for bfin-linux-uclibc This patch, as well as the other patches (toolchain, distribution, uClibc) are actively supported by Analog Devices Inc, at: http://blackfin.uclinux.org/ We have tested this on LTP, and our test plan (including pass/fails) can be found at: http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel [m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files] Signed-off-by: Bryan Wu <bryan.wu@analog.com> Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl> Signed-off-by: Aubrey Li <aubrey.li@analog.com> Signed-off-by: Jie Zhang <jie.zhang@analog.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org> 2007-05-07 05:50:22 +08:00			`.align 2`
			`.global ___smulsi3_highpart;`
			`.type ___smulsi3_highpart, STT_FUNC;`

			`#ifdef CONFIG_ARITHMETIC_OPS_L1`
			`.section .l1.text`
			`#else`
			`.text`
			`#endif`

			`___smulsi3_highpart:`
			`R2 = R1.L * R0.L (FU);`
			`R3 = R1.H * R0.L (IS,M);`
			`R0 = R0.H * R1.H, R1 = R0.H * R1.L (IS,M);`

			`R1.L = R2.H + R1.L;`
			`cc = ac0;`
			`R2 = cc;`

			`R1.L = R1.L + R3.L;`
			`cc = ac0;`
			`R1 >>>= 16;`
			`R3 >>>= 16;`
			`R1 = R1 + R3;`
			`R1 = R1 + R2;`
			`R2 = cc;`
			`R1 = R1 + R2;`

			`R0 = R0 + R1;`
			`RTS;`
Blackfin arch: add proper ENDPROC() add proper ENDPROC() to close out assembly functions so size/type is set properly in the final ELF image Signed-off-by: Mike Frysinger <michael.frysinger@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com> 2007-06-11 15:31:30 +08:00
			`.size ___smulsi3_highpart, .-___smulsi3_highpart`