2018-01-10 02:29:54 +08:00
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/* SPDX-License-Identifier: GPL-2.0 */
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2013-03-05 01:03:10 +08:00
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/*
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2011-02-14 15:33:10 +08:00
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* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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2018-01-10 02:29:54 +08:00
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*/
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2010-07-26 20:08:52 +08:00
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/* pull in the relevant register and map files. */
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2013-03-05 01:03:10 +08:00
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#define S3C_ADDR_BASE 0xF6000000
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#define S3C_VA_UART S3C_ADDR_BASE + 0x01000000
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#define EXYNOS4_PA_UART 0x13800000
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#define EXYNOS5_PA_UART 0x12C00000
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2010-07-26 20:08:52 +08:00
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/* note, for the boot process to work we have to keep the UART
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* virtual address aligned to an 1MiB boundary for the L1
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* mapping the head code makes. We keep the UART virtual address
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* aligned and add in the offset when we load the value here.
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*/
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2011-09-01 10:55:46 +08:00
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.macro addruart, rp, rv, tmp
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2012-04-05 00:27:19 +08:00
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mrc p15, 0, \tmp, c0, c0, 0
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and \tmp, \tmp, #0xf0
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teq \tmp, #0xf0 @@ A15
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2014-09-26 18:43:54 +08:00
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beq 100f
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mrc p15, 0, \tmp, c0, c0, 5
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and \tmp, \tmp, #0xf00
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teq \tmp, #0x100 @@ A15 + A7 but boot to A7
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100: ldreq \rp, =EXYNOS5_PA_UART
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2012-02-10 10:57:53 +08:00
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movne \rp, #EXYNOS4_PA_UART @@ EXYNOS4
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ldr \rv, =S3C_VA_UART
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2010-07-26 20:08:52 +08:00
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#if CONFIG_DEBUG_S3C_UART != 0
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2010-07-06 18:30:06 +08:00
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add \rp, \rp, #(0x10000 * CONFIG_DEBUG_S3C_UART)
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add \rv, \rv, #(0x10000 * CONFIG_DEBUG_S3C_UART)
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2010-07-26 20:08:52 +08:00
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#endif
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.endm
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#define fifo_full fifo_full_s5pv210
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#define fifo_level fifo_level_s5pv210
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2013-03-05 01:03:10 +08:00
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#include <debug/samsung.S>
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