2006-01-02 17:14:23 +08:00
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/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
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2005-04-17 06:20:36 +08:00
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*/
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2006-01-02 17:14:23 +08:00
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/*
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2005-04-17 06:20:36 +08:00
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* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
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* All Rights Reserved.
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2005-06-23 20:46:46 +08:00
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
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* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
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* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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2006-01-02 17:14:23 +08:00
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*/
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2005-04-17 06:20:36 +08:00
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2012-03-19 04:00:11 +08:00
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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2009-06-19 07:56:52 +08:00
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#include <linux/sysrq.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 16:04:11 +08:00
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#include <linux/slab.h>
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2013-10-16 01:55:29 +08:00
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#include <linux/circ_buf.h>
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2012-10-03 01:01:07 +08:00
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#include <drm/drmP.h>
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#include <drm/i915_drm.h>
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2005-04-17 06:20:36 +08:00
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#include "i915_drv.h"
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2009-08-25 18:15:50 +08:00
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#include "i915_trace.h"
|
DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-08 06:24:08 +08:00
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#include "intel_drv.h"
|
2005-04-17 06:20:36 +08:00
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2014-09-30 16:56:45 +08:00
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/**
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* DOC: interrupt handling
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*
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* These functions provide the basic support for enabling and disabling the
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* interrupt handling support. There's a lot more functionality in i915_irq.c
|
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* and related files, but that will be described in separate chapters.
|
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*/
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|
2015-01-09 20:21:12 +08:00
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static const u32 hpd_ibx[HPD_NUM_PINS] = {
|
2013-02-28 17:17:12 +08:00
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[HPD_CRT] = SDE_CRT_HOTPLUG,
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[HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
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[HPD_PORT_B] = SDE_PORTB_HOTPLUG,
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[HPD_PORT_C] = SDE_PORTC_HOTPLUG,
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[HPD_PORT_D] = SDE_PORTD_HOTPLUG
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};
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2015-01-09 20:21:12 +08:00
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static const u32 hpd_cpt[HPD_NUM_PINS] = {
|
2013-02-28 17:17:12 +08:00
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[HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
|
2013-03-27 05:38:43 +08:00
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[HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
|
2013-02-28 17:17:12 +08:00
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[HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
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[HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
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[HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
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};
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|
2015-01-09 20:21:12 +08:00
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static const u32 hpd_mask_i915[HPD_NUM_PINS] = {
|
2013-02-28 17:17:12 +08:00
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[HPD_CRT] = CRT_HOTPLUG_INT_EN,
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[HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
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[HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
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[HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
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[HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
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[HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
|
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};
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|
2015-01-09 20:21:12 +08:00
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static const u32 hpd_status_g4x[HPD_NUM_PINS] = {
|
2013-02-28 17:17:12 +08:00
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[HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
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[HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
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[HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
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[HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
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[HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
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[HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
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};
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|
drm/i915: Use HOTPLUG_INT_STATUS_G4X on VLV/CHV
Use HOTPLUG_INT_STATUS_G4X instead of HOTPLUG_INT_STATUS_I915 on VLV/CHV
so that we don't confuse the AUX status bits with SDVO status bits.
Avoid pointless log spam as below while handling AUX interrupts:
[drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
[drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
[drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
[drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
[drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
[drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
Note that there's no functional issue, it's just that the sdvo bits
overlap with the dp aux bits. Hence every time we receive an aux
interrupt we also think there's an sdvo hpd interrupt, but due to lack
of any sdvo encoders nothing ever happens because of that.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
[danvet: Add Ville's explanation why nothing functional really
changes.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-05-12 01:49:10 +08:00
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static const u32 hpd_status_i915[HPD_NUM_PINS] = {
|
2013-02-28 17:17:12 +08:00
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[HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
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[HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
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[HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
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[HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
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[HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
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[HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
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};
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2015-03-27 20:54:14 +08:00
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/* BXT hpd list */
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static const u32 hpd_bxt[HPD_NUM_PINS] = {
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[HPD_PORT_B] = BXT_DE_PORT_HP_DDIB,
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[HPD_PORT_C] = BXT_DE_PORT_HP_DDIC
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};
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|
2014-04-02 02:37:11 +08:00
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/* IIR can theoretically queue up two events. Be paranoid. */
|
2014-04-02 02:37:14 +08:00
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#define GEN8_IRQ_RESET_NDX(type, which) do { \
|
2014-04-02 02:37:11 +08:00
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I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
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POSTING_READ(GEN8_##type##_IMR(which)); \
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I915_WRITE(GEN8_##type##_IER(which), 0); \
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I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
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POSTING_READ(GEN8_##type##_IIR(which)); \
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I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
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POSTING_READ(GEN8_##type##_IIR(which)); \
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} while (0)
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|
2014-04-02 02:37:14 +08:00
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#define GEN5_IRQ_RESET(type) do { \
|
2014-04-02 02:37:09 +08:00
|
|
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I915_WRITE(type##IMR, 0xffffffff); \
|
2014-04-02 02:37:11 +08:00
|
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POSTING_READ(type##IMR); \
|
2014-04-02 02:37:09 +08:00
|
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I915_WRITE(type##IER, 0); \
|
2014-04-02 02:37:11 +08:00
|
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I915_WRITE(type##IIR, 0xffffffff); \
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POSTING_READ(type##IIR); \
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I915_WRITE(type##IIR, 0xffffffff); \
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POSTING_READ(type##IIR); \
|
2014-04-02 02:37:09 +08:00
|
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} while (0)
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|
2014-04-02 02:37:16 +08:00
|
|
|
/*
|
|
|
|
* We should clear IMR at preinstall/uninstall, and just check at postinstall.
|
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*/
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#define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \
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u32 val = I915_READ(reg); \
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if (val) { \
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WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", \
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(reg), val); \
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I915_WRITE((reg), 0xffffffff); \
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POSTING_READ(reg); \
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I915_WRITE((reg), 0xffffffff); \
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POSTING_READ(reg); \
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} \
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} while (0)
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|
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|
|
2014-04-02 02:37:15 +08:00
|
|
|
#define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
|
2014-04-02 02:37:16 +08:00
|
|
|
GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \
|
2014-04-02 02:37:15 +08:00
|
|
|
I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
|
drm/i915: Apply some ocd for IMR vs. IER order during irq enable
When disabling interrupts we do the writes in this order:
IMR,IER,IIR,IIR. But when enabling interrupts we don't do use the
mirrored order, and instead do IIR,IIR,IMR,IER.
I like consistency unless there's a good reason against it, which I
can't think of here, so change the enable order to IIR,IIR,IER,IMR.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-10-31 01:42:50 +08:00
|
|
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I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
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POSTING_READ(GEN8_##type##_IMR(which)); \
|
2014-04-02 02:37:15 +08:00
|
|
|
} while (0)
|
|
|
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|
|
#define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
|
2014-04-02 02:37:16 +08:00
|
|
|
GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \
|
2014-04-02 02:37:15 +08:00
|
|
|
I915_WRITE(type##IER, (ier_val)); \
|
drm/i915: Apply some ocd for IMR vs. IER order during irq enable
When disabling interrupts we do the writes in this order:
IMR,IER,IIR,IIR. But when enabling interrupts we don't do use the
mirrored order, and instead do IIR,IIR,IMR,IER.
I like consistency unless there's a good reason against it, which I
can't think of here, so change the enable order to IIR,IIR,IER,IMR.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-10-31 01:42:50 +08:00
|
|
|
I915_WRITE(type##IMR, (imr_val)); \
|
|
|
|
POSTING_READ(type##IMR); \
|
2014-04-02 02:37:15 +08:00
|
|
|
} while (0)
|
|
|
|
|
2014-11-06 02:48:37 +08:00
|
|
|
static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
|
|
|
|
|
2009-06-08 14:40:19 +08:00
|
|
|
/* For display hotplug interrupt */
|
2014-09-30 16:56:46 +08:00
|
|
|
void
|
2014-03-31 19:27:17 +08:00
|
|
|
ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
|
2009-06-08 14:40:19 +08:00
|
|
|
{
|
2013-06-27 19:44:58 +08:00
|
|
|
assert_spin_locked(&dev_priv->irq_lock);
|
|
|
|
|
2014-06-21 00:29:20 +08:00
|
|
|
if (WARN_ON(!intel_irqs_enabled(dev_priv)))
|
2013-08-20 00:18:09 +08:00
|
|
|
return;
|
|
|
|
|
2010-12-04 19:30:53 +08:00
|
|
|
if ((dev_priv->irq_mask & mask) != 0) {
|
|
|
|
dev_priv->irq_mask &= ~mask;
|
|
|
|
I915_WRITE(DEIMR, dev_priv->irq_mask);
|
2010-11-16 23:55:10 +08:00
|
|
|
POSTING_READ(DEIMR);
|
2009-06-08 14:40:19 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-09-30 16:56:46 +08:00
|
|
|
void
|
2014-03-31 19:27:17 +08:00
|
|
|
ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
|
2009-06-08 14:40:19 +08:00
|
|
|
{
|
2013-06-27 19:44:58 +08:00
|
|
|
assert_spin_locked(&dev_priv->irq_lock);
|
|
|
|
|
2014-07-18 04:43:46 +08:00
|
|
|
if (WARN_ON(!intel_irqs_enabled(dev_priv)))
|
2013-08-20 00:18:09 +08:00
|
|
|
return;
|
|
|
|
|
2010-12-04 19:30:53 +08:00
|
|
|
if ((dev_priv->irq_mask & mask) != mask) {
|
|
|
|
dev_priv->irq_mask |= mask;
|
|
|
|
I915_WRITE(DEIMR, dev_priv->irq_mask);
|
2010-11-16 23:55:10 +08:00
|
|
|
POSTING_READ(DEIMR);
|
2009-06-08 14:40:19 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-08-07 05:57:12 +08:00
|
|
|
/**
|
|
|
|
* ilk_update_gt_irq - update GTIMR
|
|
|
|
* @dev_priv: driver private
|
|
|
|
* @interrupt_mask: mask of interrupt bits to update
|
|
|
|
* @enabled_irq_mask: mask of interrupt bits to enable
|
|
|
|
*/
|
|
|
|
static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
|
|
|
|
uint32_t interrupt_mask,
|
|
|
|
uint32_t enabled_irq_mask)
|
|
|
|
{
|
|
|
|
assert_spin_locked(&dev_priv->irq_lock);
|
|
|
|
|
2014-12-08 23:30:00 +08:00
|
|
|
WARN_ON(enabled_irq_mask & ~interrupt_mask);
|
|
|
|
|
2014-06-21 00:29:20 +08:00
|
|
|
if (WARN_ON(!intel_irqs_enabled(dev_priv)))
|
2013-08-20 00:18:09 +08:00
|
|
|
return;
|
|
|
|
|
2013-08-07 05:57:12 +08:00
|
|
|
dev_priv->gt_irq_mask &= ~interrupt_mask;
|
|
|
|
dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
|
|
|
|
I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
|
|
|
|
POSTING_READ(GTIMR);
|
|
|
|
}
|
|
|
|
|
2014-07-16 15:49:40 +08:00
|
|
|
void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
|
2013-08-07 05:57:12 +08:00
|
|
|
{
|
|
|
|
ilk_update_gt_irq(dev_priv, mask, mask);
|
|
|
|
}
|
|
|
|
|
2014-07-16 15:49:40 +08:00
|
|
|
void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
|
2013-08-07 05:57:12 +08:00
|
|
|
{
|
|
|
|
ilk_update_gt_irq(dev_priv, mask, 0);
|
|
|
|
}
|
|
|
|
|
2014-11-06 02:48:48 +08:00
|
|
|
static u32 gen6_pm_iir(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
|
|
|
|
}
|
|
|
|
|
2014-11-06 02:48:31 +08:00
|
|
|
static u32 gen6_pm_imr(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR;
|
|
|
|
}
|
|
|
|
|
2014-11-06 02:48:48 +08:00
|
|
|
static u32 gen6_pm_ier(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER;
|
|
|
|
}
|
|
|
|
|
2013-08-07 05:57:13 +08:00
|
|
|
/**
|
|
|
|
* snb_update_pm_irq - update GEN6_PMIMR
|
|
|
|
* @dev_priv: driver private
|
|
|
|
* @interrupt_mask: mask of interrupt bits to update
|
|
|
|
* @enabled_irq_mask: mask of interrupt bits to enable
|
|
|
|
*/
|
|
|
|
static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
|
|
|
|
uint32_t interrupt_mask,
|
|
|
|
uint32_t enabled_irq_mask)
|
|
|
|
{
|
2013-08-07 05:57:15 +08:00
|
|
|
uint32_t new_val;
|
2013-08-07 05:57:13 +08:00
|
|
|
|
2014-12-08 23:30:00 +08:00
|
|
|
WARN_ON(enabled_irq_mask & ~interrupt_mask);
|
|
|
|
|
2013-08-07 05:57:13 +08:00
|
|
|
assert_spin_locked(&dev_priv->irq_lock);
|
|
|
|
|
2013-08-07 05:57:15 +08:00
|
|
|
new_val = dev_priv->pm_irq_mask;
|
2013-08-07 05:57:14 +08:00
|
|
|
new_val &= ~interrupt_mask;
|
|
|
|
new_val |= (~enabled_irq_mask & interrupt_mask);
|
|
|
|
|
2013-08-07 05:57:15 +08:00
|
|
|
if (new_val != dev_priv->pm_irq_mask) {
|
|
|
|
dev_priv->pm_irq_mask = new_val;
|
2014-11-06 02:48:31 +08:00
|
|
|
I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_irq_mask);
|
|
|
|
POSTING_READ(gen6_pm_imr(dev_priv));
|
2013-08-07 05:57:14 +08:00
|
|
|
}
|
2013-08-07 05:57:13 +08:00
|
|
|
}
|
|
|
|
|
2014-07-16 15:49:40 +08:00
|
|
|
void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
|
2013-08-07 05:57:13 +08:00
|
|
|
{
|
2014-11-21 05:01:47 +08:00
|
|
|
if (WARN_ON(!intel_irqs_enabled(dev_priv)))
|
|
|
|
return;
|
|
|
|
|
2013-08-07 05:57:13 +08:00
|
|
|
snb_update_pm_irq(dev_priv, mask, mask);
|
|
|
|
}
|
|
|
|
|
2014-11-21 05:01:47 +08:00
|
|
|
static void __gen6_disable_pm_irq(struct drm_i915_private *dev_priv,
|
|
|
|
uint32_t mask)
|
2013-08-07 05:57:13 +08:00
|
|
|
{
|
|
|
|
snb_update_pm_irq(dev_priv, mask, 0);
|
|
|
|
}
|
|
|
|
|
2014-11-21 05:01:47 +08:00
|
|
|
void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
|
|
|
|
{
|
|
|
|
if (WARN_ON(!intel_irqs_enabled(dev_priv)))
|
|
|
|
return;
|
|
|
|
|
|
|
|
__gen6_disable_pm_irq(dev_priv, mask);
|
|
|
|
}
|
|
|
|
|
2014-11-19 21:30:03 +08:00
|
|
|
void gen6_reset_rps_interrupts(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
uint32_t reg = gen6_pm_iir(dev_priv);
|
|
|
|
|
|
|
|
spin_lock_irq(&dev_priv->irq_lock);
|
|
|
|
I915_WRITE(reg, dev_priv->pm_rps_events);
|
|
|
|
I915_WRITE(reg, dev_priv->pm_rps_events);
|
|
|
|
POSTING_READ(reg);
|
2015-03-24 01:11:35 +08:00
|
|
|
dev_priv->rps.pm_iir = 0;
|
2014-11-19 21:30:03 +08:00
|
|
|
spin_unlock_irq(&dev_priv->irq_lock);
|
|
|
|
}
|
|
|
|
|
2014-11-06 02:48:48 +08:00
|
|
|
void gen6_enable_rps_interrupts(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
|
|
|
|
spin_lock_irq(&dev_priv->irq_lock);
|
2014-12-16 00:59:27 +08:00
|
|
|
|
2014-11-06 02:48:48 +08:00
|
|
|
WARN_ON(dev_priv->rps.pm_iir);
|
2014-11-19 21:30:03 +08:00
|
|
|
WARN_ON(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
|
drm/i915: sanitize rps irq disabling
When disabling the RPS interrupts there is a tricky dependency between
the thread disabling the interrupts, the RPS interrupt handler and the
corresponding RPS work. The RPS work can reenable the interrupts, so
there is no straightforward order in the disabling thread to (1) make
sure that any RPS work is flushed and to (2) disable all RPS
interrupts. Currently this is solved by masking the interrupts using two
separate mask registers (first level display IMR and PM IMR) and doing
the disabling when all first level interrupts are disabled.
This works, but the requirement to run with all first level interrupts
disabled is unnecessary making the suspend / unload time ordering of RPS
disabling wrt. other unitialization steps difficult and error prone.
Removing this restriction allows us to disable RPS early during suspend
/ unload and forget about it for the rest of the sequence. By adding a
more explicit method for avoiding the above race, it also becomes easier
to prove its correctness. Finally currently we can hit the WARN in
snb_update_pm_irq(), when a final RPS work runs with the first level
interrupts already disabled. This won't lead to any problem (due to the
separate interrupt masks), but with the change in this and the next
patch we can get rid of the WARN, while leaving it in place for other
scenarios.
To address the above points, add a new RPS interrupts_enabled flag and
use this during RPS disabling to avoid requeuing the RPS work and
reenabling of the RPS interrupts. Since the interrupt disabling happens
now in intel_suspend_gt_powersave(), we will disable RPS interrupts
explicitly during suspend (and not just through the first level mask),
but there is no problem doing so, it's also more consistent and allows
us to unify more of the RPS disabling during suspend and unload time in
the next patch.
v2/v3:
- rebase on patch "drm/i915: move rps irq disable one level up" in the
patchset
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-19 21:30:04 +08:00
|
|
|
dev_priv->rps.interrupts_enabled = true;
|
2014-12-16 00:59:27 +08:00
|
|
|
I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) |
|
|
|
|
dev_priv->pm_rps_events);
|
2014-11-06 02:48:48 +08:00
|
|
|
gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
|
2014-12-16 00:59:27 +08:00
|
|
|
|
2014-11-06 02:48:48 +08:00
|
|
|
spin_unlock_irq(&dev_priv->irq_lock);
|
|
|
|
}
|
|
|
|
|
2014-12-20 01:33:26 +08:00
|
|
|
u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask)
|
|
|
|
{
|
|
|
|
/*
|
2014-12-20 01:33:27 +08:00
|
|
|
* SNB,IVB can while VLV,CHV may hard hang on looping batchbuffer
|
2014-12-20 01:33:26 +08:00
|
|
|
* if GEN6_PM_UP_EI_EXPIRED is masked.
|
2014-12-20 01:33:27 +08:00
|
|
|
*
|
|
|
|
* TODO: verify if this can be reproduced on VLV,CHV.
|
2014-12-20 01:33:26 +08:00
|
|
|
*/
|
|
|
|
if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv))
|
|
|
|
mask &= ~GEN6_PM_RP_UP_EI_EXPIRED;
|
|
|
|
|
|
|
|
if (INTEL_INFO(dev_priv)->gen >= 8)
|
|
|
|
mask &= ~GEN8_PMINTR_REDIRECT_TO_NON_DISP;
|
|
|
|
|
|
|
|
return mask;
|
|
|
|
}
|
|
|
|
|
2014-11-06 02:48:48 +08:00
|
|
|
void gen6_disable_rps_interrupts(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
|
drm/i915: sanitize rps irq disabling
When disabling the RPS interrupts there is a tricky dependency between
the thread disabling the interrupts, the RPS interrupt handler and the
corresponding RPS work. The RPS work can reenable the interrupts, so
there is no straightforward order in the disabling thread to (1) make
sure that any RPS work is flushed and to (2) disable all RPS
interrupts. Currently this is solved by masking the interrupts using two
separate mask registers (first level display IMR and PM IMR) and doing
the disabling when all first level interrupts are disabled.
This works, but the requirement to run with all first level interrupts
disabled is unnecessary making the suspend / unload time ordering of RPS
disabling wrt. other unitialization steps difficult and error prone.
Removing this restriction allows us to disable RPS early during suspend
/ unload and forget about it for the rest of the sequence. By adding a
more explicit method for avoiding the above race, it also becomes easier
to prove its correctness. Finally currently we can hit the WARN in
snb_update_pm_irq(), when a final RPS work runs with the first level
interrupts already disabled. This won't lead to any problem (due to the
separate interrupt masks), but with the change in this and the next
patch we can get rid of the WARN, while leaving it in place for other
scenarios.
To address the above points, add a new RPS interrupts_enabled flag and
use this during RPS disabling to avoid requeuing the RPS work and
reenabling of the RPS interrupts. Since the interrupt disabling happens
now in intel_suspend_gt_powersave(), we will disable RPS interrupts
explicitly during suspend (and not just through the first level mask),
but there is no problem doing so, it's also more consistent and allows
us to unify more of the RPS disabling during suspend and unload time in
the next patch.
v2/v3:
- rebase on patch "drm/i915: move rps irq disable one level up" in the
patchset
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-19 21:30:04 +08:00
|
|
|
spin_lock_irq(&dev_priv->irq_lock);
|
|
|
|
dev_priv->rps.interrupts_enabled = false;
|
|
|
|
spin_unlock_irq(&dev_priv->irq_lock);
|
|
|
|
|
|
|
|
cancel_work_sync(&dev_priv->rps.work);
|
|
|
|
|
2014-11-21 05:01:47 +08:00
|
|
|
spin_lock_irq(&dev_priv->irq_lock);
|
|
|
|
|
2014-12-20 01:33:26 +08:00
|
|
|
I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0));
|
2014-11-21 05:01:47 +08:00
|
|
|
|
|
|
|
__gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events);
|
2014-11-06 02:48:48 +08:00
|
|
|
I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) &
|
|
|
|
~dev_priv->pm_rps_events);
|
2015-03-24 01:11:34 +08:00
|
|
|
|
|
|
|
spin_unlock_irq(&dev_priv->irq_lock);
|
|
|
|
|
|
|
|
synchronize_irq(dev->irq);
|
2014-11-06 02:48:48 +08:00
|
|
|
}
|
|
|
|
|
2013-07-05 05:35:21 +08:00
|
|
|
/**
|
|
|
|
* ibx_display_interrupt_update - update SDEIMR
|
|
|
|
* @dev_priv: driver private
|
|
|
|
* @interrupt_mask: mask of interrupt bits to update
|
|
|
|
* @enabled_irq_mask: mask of interrupt bits to enable
|
|
|
|
*/
|
2014-09-30 16:56:46 +08:00
|
|
|
void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
|
|
|
|
uint32_t interrupt_mask,
|
|
|
|
uint32_t enabled_irq_mask)
|
2013-07-05 05:35:21 +08:00
|
|
|
{
|
|
|
|
uint32_t sdeimr = I915_READ(SDEIMR);
|
|
|
|
sdeimr &= ~interrupt_mask;
|
|
|
|
sdeimr |= (~enabled_irq_mask & interrupt_mask);
|
|
|
|
|
2014-12-08 23:30:00 +08:00
|
|
|
WARN_ON(enabled_irq_mask & ~interrupt_mask);
|
|
|
|
|
2013-07-05 05:35:21 +08:00
|
|
|
assert_spin_locked(&dev_priv->irq_lock);
|
|
|
|
|
2014-06-21 00:29:20 +08:00
|
|
|
if (WARN_ON(!intel_irqs_enabled(dev_priv)))
|
2013-08-20 00:18:09 +08:00
|
|
|
return;
|
|
|
|
|
2013-07-05 05:35:21 +08:00
|
|
|
I915_WRITE(SDEIMR, sdeimr);
|
|
|
|
POSTING_READ(SDEIMR);
|
|
|
|
}
|
drm/i915: report Gen5+ CPU and PCH FIFO underruns
In this commit we enable both CPU and PCH FIFO underrun reporting and
start reporting them. We follow a few rules:
- after we receive one of these errors, we mask the interrupt, so
we won't get an "interrupt storm" and we also won't flood dmesg;
- at each mode set we enable the interrupts again, so we'll see each
message at most once per mode set;
- in the specific places where we need to ignore the errors, we
completely mask the interrupts.
The downside of this patch is that since we're completely disabling
(masking) the interrupts instead of just not printing error messages,
we will mask more than just what we want on IVB/HSW CPU interrupts
(due to GEN7_ERR_INT) and on CPT/PPT/LPT PCHs (due to SERR_INT). So
when we decide to mask PCH FIFO underruns for pipe A on CPT, we'll
also be masking PCH FIFO underruns for pipe B, because both are
reported by SERR_INT, which has to be either completely enabled or
completely disabled (in othe words, there's no way to disable/enable
specific bits of GEN7_ERR_INT and SERR_INT).
V2: Rename some functions and variables, downgrade messages to
DRM_DEBUG_DRIVER and rebase.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-13 04:57:57 +08:00
|
|
|
|
2014-03-03 04:18:00 +08:00
|
|
|
static void
|
2014-02-11 00:42:47 +08:00
|
|
|
__i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
|
|
|
|
u32 enable_mask, u32 status_mask)
|
2008-11-04 18:03:27 +08:00
|
|
|
{
|
2013-02-21 03:16:18 +08:00
|
|
|
u32 reg = PIPESTAT(pipe);
|
2014-02-11 00:42:47 +08:00
|
|
|
u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
|
2008-11-04 18:03:27 +08:00
|
|
|
|
2013-06-27 23:52:10 +08:00
|
|
|
assert_spin_locked(&dev_priv->irq_lock);
|
2014-08-27 16:43:37 +08:00
|
|
|
WARN_ON(!intel_irqs_enabled(dev_priv));
|
2013-06-27 23:52:10 +08:00
|
|
|
|
2014-04-03 18:28:33 +08:00
|
|
|
if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
|
|
|
|
status_mask & ~PIPESTAT_INT_STATUS_MASK,
|
|
|
|
"pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
|
|
|
|
pipe_name(pipe), enable_mask, status_mask))
|
2014-02-11 00:42:47 +08:00
|
|
|
return;
|
|
|
|
|
|
|
|
if ((pipestat & enable_mask) == enable_mask)
|
2013-02-21 03:16:18 +08:00
|
|
|
return;
|
|
|
|
|
2014-02-11 00:42:49 +08:00
|
|
|
dev_priv->pipestat_irq_mask[pipe] |= status_mask;
|
|
|
|
|
2013-02-21 03:16:18 +08:00
|
|
|
/* Enable the interrupt, clear any pending status */
|
2014-02-11 00:42:47 +08:00
|
|
|
pipestat |= enable_mask | status_mask;
|
2013-02-21 03:16:18 +08:00
|
|
|
I915_WRITE(reg, pipestat);
|
|
|
|
POSTING_READ(reg);
|
2008-11-04 18:03:27 +08:00
|
|
|
}
|
|
|
|
|
2014-03-03 04:18:00 +08:00
|
|
|
static void
|
2014-02-11 00:42:47 +08:00
|
|
|
__i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
|
|
|
|
u32 enable_mask, u32 status_mask)
|
2008-11-04 18:03:27 +08:00
|
|
|
{
|
2013-02-21 03:16:18 +08:00
|
|
|
u32 reg = PIPESTAT(pipe);
|
2014-02-11 00:42:47 +08:00
|
|
|
u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
|
2008-11-04 18:03:27 +08:00
|
|
|
|
2013-06-27 23:52:10 +08:00
|
|
|
assert_spin_locked(&dev_priv->irq_lock);
|
2014-08-27 16:43:37 +08:00
|
|
|
WARN_ON(!intel_irqs_enabled(dev_priv));
|
2013-06-27 23:52:10 +08:00
|
|
|
|
2014-04-03 18:28:33 +08:00
|
|
|
if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
|
|
|
|
status_mask & ~PIPESTAT_INT_STATUS_MASK,
|
|
|
|
"pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
|
|
|
|
pipe_name(pipe), enable_mask, status_mask))
|
2013-02-21 03:16:18 +08:00
|
|
|
return;
|
|
|
|
|
2014-02-11 00:42:47 +08:00
|
|
|
if ((pipestat & enable_mask) == 0)
|
|
|
|
return;
|
|
|
|
|
2014-02-11 00:42:49 +08:00
|
|
|
dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
|
|
|
|
|
2014-02-11 00:42:47 +08:00
|
|
|
pipestat &= ~enable_mask;
|
2013-02-21 03:16:18 +08:00
|
|
|
I915_WRITE(reg, pipestat);
|
|
|
|
POSTING_READ(reg);
|
2008-11-04 18:03:27 +08:00
|
|
|
}
|
|
|
|
|
2014-02-11 00:42:48 +08:00
|
|
|
static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
|
|
|
|
{
|
|
|
|
u32 enable_mask = status_mask << 16;
|
|
|
|
|
|
|
|
/*
|
2014-04-09 18:28:48 +08:00
|
|
|
* On pipe A we don't support the PSR interrupt yet,
|
|
|
|
* on pipe B and C the same bit MBZ.
|
2014-02-11 00:42:48 +08:00
|
|
|
*/
|
|
|
|
if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
|
|
|
|
return 0;
|
2014-04-09 18:28:48 +08:00
|
|
|
/*
|
|
|
|
* On pipe B and C we don't support the PSR interrupt yet, on pipe
|
|
|
|
* A the same bit is for perf counters which we don't use either.
|
|
|
|
*/
|
|
|
|
if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))
|
|
|
|
return 0;
|
2014-02-11 00:42:48 +08:00
|
|
|
|
|
|
|
enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
|
|
|
|
SPRITE0_FLIP_DONE_INT_EN_VLV |
|
|
|
|
SPRITE1_FLIP_DONE_INT_EN_VLV);
|
|
|
|
if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
|
|
|
|
enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
|
|
|
|
if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
|
|
|
|
enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
|
|
|
|
|
|
|
|
return enable_mask;
|
|
|
|
}
|
|
|
|
|
2014-02-11 00:42:47 +08:00
|
|
|
void
|
|
|
|
i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
|
|
|
|
u32 status_mask)
|
|
|
|
{
|
|
|
|
u32 enable_mask;
|
|
|
|
|
2014-02-11 00:42:48 +08:00
|
|
|
if (IS_VALLEYVIEW(dev_priv->dev))
|
|
|
|
enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
|
|
|
|
status_mask);
|
|
|
|
else
|
|
|
|
enable_mask = status_mask << 16;
|
2014-02-11 00:42:47 +08:00
|
|
|
__i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
|
|
|
|
u32 status_mask)
|
|
|
|
{
|
|
|
|
u32 enable_mask;
|
|
|
|
|
2014-02-11 00:42:48 +08:00
|
|
|
if (IS_VALLEYVIEW(dev_priv->dev))
|
|
|
|
enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
|
|
|
|
status_mask);
|
|
|
|
else
|
|
|
|
enable_mask = status_mask << 16;
|
2014-02-11 00:42:47 +08:00
|
|
|
__i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
|
|
|
|
}
|
|
|
|
|
2009-10-28 13:10:00 +08:00
|
|
|
/**
|
2013-04-29 18:02:54 +08:00
|
|
|
* i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
|
2009-10-28 13:10:00 +08:00
|
|
|
*/
|
2013-04-29 18:02:54 +08:00
|
|
|
static void i915_enable_asle_pipestat(struct drm_device *dev)
|
2009-10-28 13:10:00 +08:00
|
|
|
{
|
2014-03-31 19:27:17 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2010-12-04 19:30:53 +08:00
|
|
|
|
2013-04-29 18:02:54 +08:00
|
|
|
if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
|
|
|
|
return;
|
|
|
|
|
2014-09-15 20:55:29 +08:00
|
|
|
spin_lock_irq(&dev_priv->irq_lock);
|
2009-10-28 13:10:00 +08:00
|
|
|
|
2014-02-11 00:42:47 +08:00
|
|
|
i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
|
2013-04-29 18:02:53 +08:00
|
|
|
if (INTEL_INFO(dev)->gen >= 4)
|
2013-10-22 00:04:35 +08:00
|
|
|
i915_enable_pipestat(dev_priv, PIPE_A,
|
2014-02-11 00:42:47 +08:00
|
|
|
PIPE_LEGACY_BLC_EVENT_STATUS);
|
2010-12-04 19:30:53 +08:00
|
|
|
|
2014-09-15 20:55:29 +08:00
|
|
|
spin_unlock_irq(&dev_priv->irq_lock);
|
2009-10-28 13:10:00 +08:00
|
|
|
}
|
|
|
|
|
2014-05-16 01:20:36 +08:00
|
|
|
/*
|
|
|
|
* This timing diagram depicts the video signal in and
|
|
|
|
* around the vertical blanking period.
|
|
|
|
*
|
|
|
|
* Assumptions about the fictitious mode used in this example:
|
|
|
|
* vblank_start >= 3
|
|
|
|
* vsync_start = vblank_start + 1
|
|
|
|
* vsync_end = vblank_start + 2
|
|
|
|
* vtotal = vblank_start + 3
|
|
|
|
*
|
|
|
|
* start of vblank:
|
|
|
|
* latch double buffered registers
|
|
|
|
* increment frame counter (ctg+)
|
|
|
|
* generate start of vblank interrupt (gen4+)
|
|
|
|
* |
|
|
|
|
* | frame start:
|
|
|
|
* | generate frame start interrupt (aka. vblank interrupt) (gmch)
|
|
|
|
* | may be shifted forward 1-3 extra lines via PIPECONF
|
|
|
|
* | |
|
|
|
|
* | | start of vsync:
|
|
|
|
* | | generate vsync interrupt
|
|
|
|
* | | |
|
|
|
|
* ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx
|
|
|
|
* . \hs/ . \hs/ \hs/ \hs/ . \hs/
|
|
|
|
* ----va---> <-----------------vb--------------------> <--------va-------------
|
|
|
|
* | | <----vs-----> |
|
|
|
|
* -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
|
|
|
|
* -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
|
|
|
|
* -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
|
|
|
|
* | | |
|
|
|
|
* last visible pixel first visible pixel
|
|
|
|
* | increment frame counter (gen3/4)
|
|
|
|
* pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4)
|
|
|
|
*
|
|
|
|
* x = horizontal active
|
|
|
|
* _ = horizontal blanking
|
|
|
|
* hs = horizontal sync
|
|
|
|
* va = vertical active
|
|
|
|
* vb = vertical blanking
|
|
|
|
* vs = vertical sync
|
|
|
|
* vbs = vblank_start (number)
|
|
|
|
*
|
|
|
|
* Summary:
|
|
|
|
* - most events happen at the start of horizontal sync
|
|
|
|
* - frame start happens at the start of horizontal blank, 1-4 lines
|
|
|
|
* (depending on PIPECONF settings) after the start of vblank
|
|
|
|
* - gen3/4 pixel and frame counter are synchronized with the start
|
|
|
|
* of horizontal active on the first line of vertical active
|
|
|
|
*/
|
|
|
|
|
2013-10-12 02:52:44 +08:00
|
|
|
static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe)
|
|
|
|
{
|
|
|
|
/* Gen2 doesn't have a hardware frame counter */
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2008-10-19 10:39:29 +08:00
|
|
|
/* Called from drm generic code, passed a 'crtc', which
|
|
|
|
* we use as a pipe index
|
|
|
|
*/
|
2011-06-29 04:00:41 +08:00
|
|
|
static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
|
2008-10-01 03:14:26 +08:00
|
|
|
{
|
2014-03-31 19:27:17 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2008-10-01 03:14:26 +08:00
|
|
|
unsigned long high_frame;
|
|
|
|
unsigned long low_frame;
|
2014-04-29 18:35:50 +08:00
|
|
|
u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
|
2015-02-14 04:03:44 +08:00
|
|
|
struct intel_crtc *intel_crtc =
|
|
|
|
to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
|
|
|
|
const struct drm_display_mode *mode =
|
|
|
|
&intel_crtc->config->base.adjusted_mode;
|
2008-10-01 03:14:26 +08:00
|
|
|
|
2015-02-14 04:03:44 +08:00
|
|
|
htotal = mode->crtc_htotal;
|
|
|
|
hsync_start = mode->crtc_hsync_start;
|
|
|
|
vbl_start = mode->crtc_vblank_start;
|
|
|
|
if (mode->flags & DRM_MODE_FLAG_INTERLACE)
|
|
|
|
vbl_start = DIV_ROUND_UP(vbl_start, 2);
|
2013-09-26 00:55:26 +08:00
|
|
|
|
2014-04-29 18:35:50 +08:00
|
|
|
/* Convert to pixel count */
|
|
|
|
vbl_start *= htotal;
|
|
|
|
|
|
|
|
/* Start of vblank event occurs at start of hsync */
|
|
|
|
vbl_start -= htotal - hsync_start;
|
|
|
|
|
2011-02-08 04:26:52 +08:00
|
|
|
high_frame = PIPEFRAME(pipe);
|
|
|
|
low_frame = PIPEFRAMEPIXEL(pipe);
|
2010-09-11 20:48:45 +08:00
|
|
|
|
2008-10-01 03:14:26 +08:00
|
|
|
/*
|
|
|
|
* High & low register fields aren't synchronized, so make sure
|
|
|
|
* we get a low value that's stable across two reads of the high
|
|
|
|
* register.
|
|
|
|
*/
|
|
|
|
do {
|
2010-09-11 20:48:45 +08:00
|
|
|
high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
|
2013-09-26 00:55:26 +08:00
|
|
|
low = I915_READ(low_frame);
|
2010-09-11 20:48:45 +08:00
|
|
|
high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
|
2008-10-01 03:14:26 +08:00
|
|
|
} while (high1 != high2);
|
|
|
|
|
2010-09-11 20:48:45 +08:00
|
|
|
high1 >>= PIPE_FRAME_HIGH_SHIFT;
|
2013-09-26 00:55:26 +08:00
|
|
|
pixel = low & PIPE_PIXEL_MASK;
|
2010-09-11 20:48:45 +08:00
|
|
|
low >>= PIPE_FRAME_LOW_SHIFT;
|
2013-09-26 00:55:26 +08:00
|
|
|
|
|
|
|
/*
|
|
|
|
* The frame counter increments at beginning of active.
|
|
|
|
* Cook up a vblank counter by also checking the pixel
|
|
|
|
* counter against vblank start.
|
|
|
|
*/
|
2013-11-06 23:56:27 +08:00
|
|
|
return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
|
2008-10-01 03:14:26 +08:00
|
|
|
}
|
|
|
|
|
2011-06-29 04:00:41 +08:00
|
|
|
static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
|
2009-02-07 02:22:41 +08:00
|
|
|
{
|
2014-03-31 19:27:17 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2011-02-08 04:26:52 +08:00
|
|
|
int reg = PIPE_FRMCOUNT_GM45(pipe);
|
2009-02-07 02:22:41 +08:00
|
|
|
|
|
|
|
return I915_READ(reg);
|
|
|
|
}
|
|
|
|
|
2013-10-30 12:13:08 +08:00
|
|
|
/* raw reads, only for fast reads of display block, no need for forcewake etc. */
|
|
|
|
#define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
|
|
|
|
|
2014-04-29 18:35:45 +08:00
|
|
|
static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = crtc->base.dev;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2015-01-15 20:55:25 +08:00
|
|
|
const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
|
2014-04-29 18:35:45 +08:00
|
|
|
enum pipe pipe = crtc->pipe;
|
2014-05-16 01:23:23 +08:00
|
|
|
int position, vtotal;
|
2014-04-29 18:35:45 +08:00
|
|
|
|
2014-05-16 01:23:23 +08:00
|
|
|
vtotal = mode->crtc_vtotal;
|
2014-04-29 18:35:45 +08:00
|
|
|
if (mode->flags & DRM_MODE_FLAG_INTERLACE)
|
|
|
|
vtotal /= 2;
|
|
|
|
|
|
|
|
if (IS_GEN2(dev))
|
|
|
|
position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
|
|
|
|
else
|
|
|
|
position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
|
|
|
|
|
|
|
|
/*
|
2014-05-16 01:23:23 +08:00
|
|
|
* See update_scanline_offset() for the details on the
|
|
|
|
* scanline_offset adjustment.
|
2014-04-29 18:35:45 +08:00
|
|
|
*/
|
2014-05-16 01:23:23 +08:00
|
|
|
return (position + crtc->scanline_offset) % vtotal;
|
2014-04-29 18:35:45 +08:00
|
|
|
}
|
|
|
|
|
2011-06-29 04:00:41 +08:00
|
|
|
static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
|
2013-10-29 02:50:48 +08:00
|
|
|
unsigned int flags, int *vpos, int *hpos,
|
|
|
|
ktime_t *stime, ktime_t *etime)
|
2010-12-08 11:07:19 +08:00
|
|
|
{
|
2013-09-23 19:48:50 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
|
|
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
2015-01-15 20:55:25 +08:00
|
|
|
const struct drm_display_mode *mode = &intel_crtc->config->base.adjusted_mode;
|
2013-10-12 00:10:32 +08:00
|
|
|
int position;
|
2014-04-29 18:35:44 +08:00
|
|
|
int vbl_start, vbl_end, hsync_start, htotal, vtotal;
|
2010-12-08 11:07:19 +08:00
|
|
|
bool in_vbl = true;
|
|
|
|
int ret = 0;
|
2013-10-30 12:13:08 +08:00
|
|
|
unsigned long irqflags;
|
2010-12-08 11:07:19 +08:00
|
|
|
|
2013-09-23 19:48:50 +08:00
|
|
|
if (!intel_crtc->active) {
|
2010-12-08 11:07:19 +08:00
|
|
|
DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
|
2011-02-08 04:26:52 +08:00
|
|
|
"pipe %c\n", pipe_name(pipe));
|
2010-12-08 11:07:19 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2013-09-23 19:48:50 +08:00
|
|
|
htotal = mode->crtc_htotal;
|
2014-04-29 18:35:44 +08:00
|
|
|
hsync_start = mode->crtc_hsync_start;
|
2013-09-23 19:48:50 +08:00
|
|
|
vtotal = mode->crtc_vtotal;
|
|
|
|
vbl_start = mode->crtc_vblank_start;
|
|
|
|
vbl_end = mode->crtc_vblank_end;
|
2010-12-08 11:07:19 +08:00
|
|
|
|
2013-10-28 22:31:41 +08:00
|
|
|
if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
|
|
|
|
vbl_start = DIV_ROUND_UP(vbl_start, 2);
|
|
|
|
vbl_end /= 2;
|
|
|
|
vtotal /= 2;
|
|
|
|
}
|
|
|
|
|
2013-09-23 19:48:50 +08:00
|
|
|
ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
|
|
|
|
|
2013-10-30 12:13:08 +08:00
|
|
|
/*
|
|
|
|
* Lock uncore.lock, as we will do multiple timing critical raw
|
|
|
|
* register reads, potentially with preemption disabled, so the
|
|
|
|
* following code must not block on uncore.lock.
|
|
|
|
*/
|
|
|
|
spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
|
2014-04-29 18:35:44 +08:00
|
|
|
|
2013-10-30 12:13:08 +08:00
|
|
|
/* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
|
|
|
|
|
|
|
|
/* Get optional system timestamp before query. */
|
|
|
|
if (stime)
|
|
|
|
*stime = ktime_get();
|
|
|
|
|
2013-10-12 02:52:43 +08:00
|
|
|
if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
|
2010-12-08 11:07:19 +08:00
|
|
|
/* No obvious pixelcount register. Only query vertical
|
|
|
|
* scanout position from Display scan line register.
|
|
|
|
*/
|
2014-04-29 18:35:45 +08:00
|
|
|
position = __intel_get_crtc_scanline(intel_crtc);
|
2010-12-08 11:07:19 +08:00
|
|
|
} else {
|
|
|
|
/* Have access to pixelcount since start of frame.
|
|
|
|
* We can split this into vertical and horizontal
|
|
|
|
* scanout position.
|
|
|
|
*/
|
2013-10-30 12:13:08 +08:00
|
|
|
position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
|
2010-12-08 11:07:19 +08:00
|
|
|
|
2013-10-12 00:10:32 +08:00
|
|
|
/* convert to pixel counts */
|
|
|
|
vbl_start *= htotal;
|
|
|
|
vbl_end *= htotal;
|
|
|
|
vtotal *= htotal;
|
2014-04-29 18:35:44 +08:00
|
|
|
|
2014-04-29 18:35:49 +08:00
|
|
|
/*
|
|
|
|
* In interlaced modes, the pixel counter counts all pixels,
|
|
|
|
* so one field will have htotal more pixels. In order to avoid
|
|
|
|
* the reported position from jumping backwards when the pixel
|
|
|
|
* counter is beyond the length of the shorter field, just
|
|
|
|
* clamp the position the length of the shorter field. This
|
|
|
|
* matches how the scanline counter based position works since
|
|
|
|
* the scanline counter doesn't count the two half lines.
|
|
|
|
*/
|
|
|
|
if (position >= vtotal)
|
|
|
|
position = vtotal - 1;
|
|
|
|
|
2014-04-29 18:35:44 +08:00
|
|
|
/*
|
|
|
|
* Start of vblank interrupt is triggered at start of hsync,
|
|
|
|
* just prior to the first active line of vblank. However we
|
|
|
|
* consider lines to start at the leading edge of horizontal
|
|
|
|
* active. So, should we get here before we've crossed into
|
|
|
|
* the horizontal active of the first line in vblank, we would
|
|
|
|
* not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
|
|
|
|
* always add htotal-hsync_start to the current pixel position.
|
|
|
|
*/
|
|
|
|
position = (position + htotal - hsync_start) % vtotal;
|
2010-12-08 11:07:19 +08:00
|
|
|
}
|
|
|
|
|
2013-10-30 12:13:08 +08:00
|
|
|
/* Get optional system timestamp after query. */
|
|
|
|
if (etime)
|
|
|
|
*etime = ktime_get();
|
|
|
|
|
|
|
|
/* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
|
|
|
|
|
2013-10-12 00:10:32 +08:00
|
|
|
in_vbl = position >= vbl_start && position < vbl_end;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* While in vblank, position will be negative
|
|
|
|
* counting up towards 0 at vbl_end. And outside
|
|
|
|
* vblank, position will be positive counting
|
|
|
|
* up since vbl_end.
|
|
|
|
*/
|
|
|
|
if (position >= vbl_start)
|
|
|
|
position -= vbl_end;
|
|
|
|
else
|
|
|
|
position += vtotal - vbl_end;
|
2010-12-08 11:07:19 +08:00
|
|
|
|
2013-10-12 02:52:43 +08:00
|
|
|
if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
|
2013-10-12 00:10:32 +08:00
|
|
|
*vpos = position;
|
|
|
|
*hpos = 0;
|
|
|
|
} else {
|
|
|
|
*vpos = position / htotal;
|
|
|
|
*hpos = position - (*vpos * htotal);
|
|
|
|
}
|
2010-12-08 11:07:19 +08:00
|
|
|
|
|
|
|
/* In vblank? */
|
|
|
|
if (in_vbl)
|
2014-09-10 23:36:11 +08:00
|
|
|
ret |= DRM_SCANOUTPOS_IN_VBLANK;
|
2010-12-08 11:07:19 +08:00
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2014-04-29 18:35:45 +08:00
|
|
|
int intel_get_crtc_scanline(struct intel_crtc *crtc)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
|
|
|
|
unsigned long irqflags;
|
|
|
|
int position;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
|
|
|
|
position = __intel_get_crtc_scanline(crtc);
|
|
|
|
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
|
|
|
|
|
|
|
|
return position;
|
|
|
|
}
|
|
|
|
|
2011-06-29 04:00:41 +08:00
|
|
|
static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
|
2010-12-08 11:07:19 +08:00
|
|
|
int *max_error,
|
|
|
|
struct timeval *vblank_time,
|
|
|
|
unsigned flags)
|
|
|
|
{
|
2011-01-22 18:07:56 +08:00
|
|
|
struct drm_crtc *crtc;
|
2010-12-08 11:07:19 +08:00
|
|
|
|
2013-03-14 05:05:41 +08:00
|
|
|
if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
|
2011-01-22 18:07:56 +08:00
|
|
|
DRM_ERROR("Invalid crtc %d\n", pipe);
|
2010-12-08 11:07:19 +08:00
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Get drm_crtc to timestamp: */
|
2011-01-22 18:07:56 +08:00
|
|
|
crtc = intel_get_crtc_for_pipe(dev, pipe);
|
|
|
|
if (crtc == NULL) {
|
|
|
|
DRM_ERROR("Invalid crtc %d\n", pipe);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2015-06-01 18:49:52 +08:00
|
|
|
if (!crtc->state->active) {
|
2011-01-22 18:07:56 +08:00
|
|
|
DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
|
|
|
|
return -EBUSY;
|
|
|
|
}
|
2010-12-08 11:07:19 +08:00
|
|
|
|
|
|
|
/* Helper routine in DRM core does all the work: */
|
2011-01-22 18:07:56 +08:00
|
|
|
return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
|
|
|
|
vblank_time, flags,
|
2013-10-26 22:57:31 +08:00
|
|
|
crtc,
|
2015-01-15 20:55:25 +08:00
|
|
|
&to_intel_crtc(crtc)->config->base.adjusted_mode);
|
2010-12-08 11:07:19 +08:00
|
|
|
}
|
|
|
|
|
2013-09-17 19:26:34 +08:00
|
|
|
static bool intel_hpd_irq_event(struct drm_device *dev,
|
|
|
|
struct drm_connector *connector)
|
2013-04-11 22:00:26 +08:00
|
|
|
{
|
|
|
|
enum drm_connector_status old_status;
|
|
|
|
|
|
|
|
WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
|
|
|
|
old_status = connector->status;
|
|
|
|
|
|
|
|
connector->status = connector->funcs->detect(connector, false);
|
2013-09-17 19:26:34 +08:00
|
|
|
if (old_status == connector->status)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
|
2013-04-11 22:00:26 +08:00
|
|
|
connector->base.id,
|
2014-06-03 19:56:17 +08:00
|
|
|
connector->name,
|
2013-09-17 19:26:34 +08:00
|
|
|
drm_get_connector_status_name(old_status),
|
|
|
|
drm_get_connector_status_name(connector->status));
|
|
|
|
|
|
|
|
return true;
|
2013-04-11 22:00:26 +08:00
|
|
|
}
|
|
|
|
|
2014-06-18 09:29:35 +08:00
|
|
|
static void i915_digport_work_func(struct work_struct *work)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv =
|
2015-05-27 20:03:42 +08:00
|
|
|
container_of(work, struct drm_i915_private, hotplug.dig_port_work);
|
2014-06-18 09:29:35 +08:00
|
|
|
u32 long_port_mask, short_port_mask;
|
|
|
|
struct intel_digital_port *intel_dig_port;
|
2015-01-23 13:00:31 +08:00
|
|
|
int i;
|
2014-06-18 09:29:35 +08:00
|
|
|
u32 old_bits = 0;
|
|
|
|
|
2014-09-15 20:55:26 +08:00
|
|
|
spin_lock_irq(&dev_priv->irq_lock);
|
2015-05-27 20:03:42 +08:00
|
|
|
long_port_mask = dev_priv->hotplug.long_port_mask;
|
|
|
|
dev_priv->hotplug.long_port_mask = 0;
|
|
|
|
short_port_mask = dev_priv->hotplug.short_port_mask;
|
|
|
|
dev_priv->hotplug.short_port_mask = 0;
|
2014-09-15 20:55:26 +08:00
|
|
|
spin_unlock_irq(&dev_priv->irq_lock);
|
2014-06-18 09:29:35 +08:00
|
|
|
|
|
|
|
for (i = 0; i < I915_MAX_PORTS; i++) {
|
|
|
|
bool valid = false;
|
|
|
|
bool long_hpd = false;
|
2015-05-27 20:03:42 +08:00
|
|
|
intel_dig_port = dev_priv->hotplug.irq_port[i];
|
2014-06-18 09:29:35 +08:00
|
|
|
if (!intel_dig_port || !intel_dig_port->hpd_pulse)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (long_port_mask & (1 << i)) {
|
|
|
|
valid = true;
|
|
|
|
long_hpd = true;
|
|
|
|
} else if (short_port_mask & (1 << i))
|
|
|
|
valid = true;
|
|
|
|
|
|
|
|
if (valid) {
|
2015-01-23 13:00:31 +08:00
|
|
|
enum irqreturn ret;
|
|
|
|
|
2014-06-18 09:29:35 +08:00
|
|
|
ret = intel_dig_port->hpd_pulse(intel_dig_port, long_hpd);
|
2015-01-23 13:00:31 +08:00
|
|
|
if (ret == IRQ_NONE) {
|
|
|
|
/* fall back to old school hpd */
|
2014-06-18 09:29:35 +08:00
|
|
|
old_bits |= (1 << intel_dig_port->base.hpd_pin);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (old_bits) {
|
2014-09-15 20:55:26 +08:00
|
|
|
spin_lock_irq(&dev_priv->irq_lock);
|
2015-05-27 20:03:42 +08:00
|
|
|
dev_priv->hotplug.event_bits |= old_bits;
|
2014-09-15 20:55:26 +08:00
|
|
|
spin_unlock_irq(&dev_priv->irq_lock);
|
2015-05-27 20:03:42 +08:00
|
|
|
schedule_work(&dev_priv->hotplug.hotplug_work);
|
2014-06-18 09:29:35 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-04-01 05:11:15 +08:00
|
|
|
/*
|
|
|
|
* Handle hotplug events outside the interrupt handler proper.
|
|
|
|
*/
|
2013-04-16 19:36:58 +08:00
|
|
|
#define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
|
|
|
|
|
2009-04-01 05:11:15 +08:00
|
|
|
static void i915_hotplug_work_func(struct work_struct *work)
|
|
|
|
{
|
2014-03-31 19:27:17 +08:00
|
|
|
struct drm_i915_private *dev_priv =
|
2015-05-27 20:03:42 +08:00
|
|
|
container_of(work, struct drm_i915_private, hotplug.hotplug_work);
|
2009-04-01 05:11:15 +08:00
|
|
|
struct drm_device *dev = dev_priv->dev;
|
2009-05-07 02:48:58 +08:00
|
|
|
struct drm_mode_config *mode_config = &dev->mode_config;
|
2013-04-16 19:36:57 +08:00
|
|
|
struct intel_connector *intel_connector;
|
|
|
|
struct intel_encoder *intel_encoder;
|
|
|
|
struct drm_connector *connector;
|
|
|
|
bool hpd_disabled = false;
|
2013-04-11 22:00:26 +08:00
|
|
|
bool changed = false;
|
2013-04-11 21:57:57 +08:00
|
|
|
u32 hpd_event_bits;
|
2010-09-09 22:14:28 +08:00
|
|
|
|
2011-07-26 01:04:56 +08:00
|
|
|
mutex_lock(&mode_config->mutex);
|
2011-02-12 06:44:51 +08:00
|
|
|
DRM_DEBUG_KMS("running encoder hotplug functions\n");
|
|
|
|
|
2014-09-15 20:55:26 +08:00
|
|
|
spin_lock_irq(&dev_priv->irq_lock);
|
2013-04-11 21:57:57 +08:00
|
|
|
|
2015-05-27 20:03:42 +08:00
|
|
|
hpd_event_bits = dev_priv->hotplug.event_bits;
|
|
|
|
dev_priv->hotplug.event_bits = 0;
|
2013-04-16 19:36:57 +08:00
|
|
|
list_for_each_entry(connector, &mode_config->connector_list, head) {
|
|
|
|
intel_connector = to_intel_connector(connector);
|
2014-05-02 11:44:18 +08:00
|
|
|
if (!intel_connector->encoder)
|
|
|
|
continue;
|
2013-04-16 19:36:57 +08:00
|
|
|
intel_encoder = intel_connector->encoder;
|
|
|
|
if (intel_encoder->hpd_pin > HPD_NONE &&
|
2015-05-27 20:03:42 +08:00
|
|
|
dev_priv->hotplug.stats[intel_encoder->hpd_pin].state == HPD_MARK_DISABLED &&
|
2013-04-16 19:36:57 +08:00
|
|
|
connector->polled == DRM_CONNECTOR_POLL_HPD) {
|
|
|
|
DRM_INFO("HPD interrupt storm detected on connector %s: "
|
|
|
|
"switching from hotplug detection to polling\n",
|
2014-06-03 19:56:17 +08:00
|
|
|
connector->name);
|
2015-05-27 20:03:42 +08:00
|
|
|
dev_priv->hotplug.stats[intel_encoder->hpd_pin].state = HPD_DISABLED;
|
2013-04-16 19:36:57 +08:00
|
|
|
connector->polled = DRM_CONNECTOR_POLL_CONNECT
|
|
|
|
| DRM_CONNECTOR_POLL_DISCONNECT;
|
|
|
|
hpd_disabled = true;
|
|
|
|
}
|
2013-04-11 21:57:57 +08:00
|
|
|
if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
|
|
|
|
DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
|
2014-06-03 19:56:17 +08:00
|
|
|
connector->name, intel_encoder->hpd_pin);
|
2013-04-11 21:57:57 +08:00
|
|
|
}
|
2013-04-16 19:36:57 +08:00
|
|
|
}
|
|
|
|
/* if there were no outputs to poll, poll was disabled,
|
|
|
|
* therefore make sure it's enabled when disabling HPD on
|
|
|
|
* some connectors */
|
2013-04-16 19:36:58 +08:00
|
|
|
if (hpd_disabled) {
|
2013-04-16 19:36:57 +08:00
|
|
|
drm_kms_helper_poll_enable(dev);
|
2015-05-27 20:03:42 +08:00
|
|
|
mod_delayed_work(system_wq, &dev_priv->hotplug.reenable_work,
|
2014-08-18 20:37:02 +08:00
|
|
|
msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
|
2013-04-16 19:36:58 +08:00
|
|
|
}
|
2013-04-16 19:36:57 +08:00
|
|
|
|
2014-09-15 20:55:26 +08:00
|
|
|
spin_unlock_irq(&dev_priv->irq_lock);
|
2013-04-16 19:36:57 +08:00
|
|
|
|
2013-04-11 22:00:26 +08:00
|
|
|
list_for_each_entry(connector, &mode_config->connector_list, head) {
|
|
|
|
intel_connector = to_intel_connector(connector);
|
2014-05-02 11:44:18 +08:00
|
|
|
if (!intel_connector->encoder)
|
|
|
|
continue;
|
2013-04-11 22:00:26 +08:00
|
|
|
intel_encoder = intel_connector->encoder;
|
|
|
|
if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
|
|
|
|
if (intel_encoder->hot_plug)
|
|
|
|
intel_encoder->hot_plug(intel_encoder);
|
|
|
|
if (intel_hpd_irq_event(dev, connector))
|
|
|
|
changed = true;
|
|
|
|
}
|
|
|
|
}
|
2011-07-29 06:31:19 +08:00
|
|
|
mutex_unlock(&mode_config->mutex);
|
|
|
|
|
2013-04-11 22:00:26 +08:00
|
|
|
if (changed)
|
|
|
|
drm_kms_helper_hotplug_event(dev);
|
2009-04-01 05:11:15 +08:00
|
|
|
}
|
|
|
|
|
2013-07-05 05:35:25 +08:00
|
|
|
static void ironlake_rps_change_irq_handler(struct drm_device *dev)
|
2010-01-30 03:27:07 +08:00
|
|
|
{
|
2014-03-31 19:27:17 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2010-02-03 02:30:47 +08:00
|
|
|
u32 busy_up, busy_down, max_avg, min_avg;
|
2012-08-09 22:46:01 +08:00
|
|
|
u8 new_delay;
|
|
|
|
|
2013-07-05 05:35:25 +08:00
|
|
|
spin_lock(&mchdev_lock);
|
2010-01-30 03:27:07 +08:00
|
|
|
|
2012-08-09 05:35:37 +08:00
|
|
|
I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
|
|
|
|
|
2012-08-09 05:35:39 +08:00
|
|
|
new_delay = dev_priv->ips.cur_delay;
|
2012-08-09 22:46:01 +08:00
|
|
|
|
2010-05-21 05:28:11 +08:00
|
|
|
I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
|
2010-02-03 02:30:47 +08:00
|
|
|
busy_up = I915_READ(RCPREVBSYTUPAVG);
|
|
|
|
busy_down = I915_READ(RCPREVBSYTDNAVG);
|
2010-01-30 03:27:07 +08:00
|
|
|
max_avg = I915_READ(RCBMAXAVG);
|
|
|
|
min_avg = I915_READ(RCBMINAVG);
|
|
|
|
|
|
|
|
/* Handle RCS change request from hw */
|
2010-02-03 02:30:47 +08:00
|
|
|
if (busy_up > max_avg) {
|
2012-08-09 05:35:39 +08:00
|
|
|
if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
|
|
|
|
new_delay = dev_priv->ips.cur_delay - 1;
|
|
|
|
if (new_delay < dev_priv->ips.max_delay)
|
|
|
|
new_delay = dev_priv->ips.max_delay;
|
2010-02-03 02:30:47 +08:00
|
|
|
} else if (busy_down < min_avg) {
|
2012-08-09 05:35:39 +08:00
|
|
|
if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
|
|
|
|
new_delay = dev_priv->ips.cur_delay + 1;
|
|
|
|
if (new_delay > dev_priv->ips.min_delay)
|
|
|
|
new_delay = dev_priv->ips.min_delay;
|
2010-01-30 03:27:07 +08:00
|
|
|
}
|
|
|
|
|
2010-05-21 05:28:11 +08:00
|
|
|
if (ironlake_set_drps(dev, new_delay))
|
2012-08-09 05:35:39 +08:00
|
|
|
dev_priv->ips.cur_delay = new_delay;
|
2010-01-30 03:27:07 +08:00
|
|
|
|
2013-07-05 05:35:25 +08:00
|
|
|
spin_unlock(&mchdev_lock);
|
2012-08-09 22:46:01 +08:00
|
|
|
|
2010-01-30 03:27:07 +08:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2015-04-07 23:21:05 +08:00
|
|
|
static void notify_ring(struct intel_engine_cs *ring)
|
2010-10-19 18:19:32 +08:00
|
|
|
{
|
2014-05-22 21:13:36 +08:00
|
|
|
if (!intel_ring_initialized(ring))
|
2011-01-20 17:52:56 +08:00
|
|
|
return;
|
|
|
|
|
2014-12-05 21:49:36 +08:00
|
|
|
trace_i915_gem_request_notify(ring);
|
2011-01-05 06:22:17 +08:00
|
|
|
|
2010-10-19 18:19:32 +08:00
|
|
|
wake_up_all(&ring->irq_queue);
|
|
|
|
}
|
|
|
|
|
2015-03-18 17:48:22 +08:00
|
|
|
static void vlv_c0_read(struct drm_i915_private *dev_priv,
|
|
|
|
struct intel_rps_ei *ei)
|
2014-07-04 05:33:01 +08:00
|
|
|
{
|
2015-03-18 17:48:22 +08:00
|
|
|
ei->cz_clock = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP);
|
|
|
|
ei->render_c0 = I915_READ(VLV_RENDER_C0_COUNT);
|
|
|
|
ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT);
|
|
|
|
}
|
2014-07-04 05:33:01 +08:00
|
|
|
|
2015-03-18 17:48:22 +08:00
|
|
|
static bool vlv_c0_above(struct drm_i915_private *dev_priv,
|
|
|
|
const struct intel_rps_ei *old,
|
|
|
|
const struct intel_rps_ei *now,
|
|
|
|
int threshold)
|
|
|
|
{
|
|
|
|
u64 time, c0;
|
2014-07-04 05:33:01 +08:00
|
|
|
|
2015-03-18 17:48:22 +08:00
|
|
|
if (old->cz_clock == 0)
|
|
|
|
return false;
|
2014-07-04 05:33:01 +08:00
|
|
|
|
2015-03-18 17:48:22 +08:00
|
|
|
time = now->cz_clock - old->cz_clock;
|
|
|
|
time *= threshold * dev_priv->mem_freq;
|
2014-07-04 05:33:01 +08:00
|
|
|
|
2015-03-18 17:48:22 +08:00
|
|
|
/* Workload can be split between render + media, e.g. SwapBuffers
|
|
|
|
* being blitted in X after being rendered in mesa. To account for
|
|
|
|
* this we need to combine both engines into our activity counter.
|
2014-07-04 05:33:01 +08:00
|
|
|
*/
|
2015-03-18 17:48:22 +08:00
|
|
|
c0 = now->render_c0 - old->render_c0;
|
|
|
|
c0 += now->media_c0 - old->media_c0;
|
|
|
|
c0 *= 100 * VLV_CZ_CLOCK_TO_MILLI_SEC * 4 / 1000;
|
2014-07-04 05:33:01 +08:00
|
|
|
|
2015-03-18 17:48:22 +08:00
|
|
|
return c0 >= time;
|
2014-07-04 05:33:01 +08:00
|
|
|
}
|
|
|
|
|
2015-03-18 17:48:22 +08:00
|
|
|
void gen6_rps_reset_ei(struct drm_i915_private *dev_priv)
|
2014-07-04 05:33:01 +08:00
|
|
|
{
|
2015-03-18 17:48:22 +08:00
|
|
|
vlv_c0_read(dev_priv, &dev_priv->rps.down_ei);
|
|
|
|
dev_priv->rps.up_ei = dev_priv->rps.down_ei;
|
|
|
|
}
|
2014-07-04 05:33:01 +08:00
|
|
|
|
2015-03-18 17:48:22 +08:00
|
|
|
static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
|
|
|
|
{
|
|
|
|
struct intel_rps_ei now;
|
|
|
|
u32 events = 0;
|
2014-07-04 05:33:01 +08:00
|
|
|
|
2015-03-18 17:48:23 +08:00
|
|
|
if ((pm_iir & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED)) == 0)
|
2015-03-18 17:48:22 +08:00
|
|
|
return 0;
|
2014-07-04 05:33:01 +08:00
|
|
|
|
2015-03-18 17:48:22 +08:00
|
|
|
vlv_c0_read(dev_priv, &now);
|
|
|
|
if (now.cz_clock == 0)
|
|
|
|
return 0;
|
2014-07-04 05:33:01 +08:00
|
|
|
|
2015-03-18 17:48:22 +08:00
|
|
|
if (pm_iir & GEN6_PM_RP_DOWN_EI_EXPIRED) {
|
|
|
|
if (!vlv_c0_above(dev_priv,
|
|
|
|
&dev_priv->rps.down_ei, &now,
|
2015-04-07 23:20:28 +08:00
|
|
|
dev_priv->rps.down_threshold))
|
2015-03-18 17:48:22 +08:00
|
|
|
events |= GEN6_PM_RP_DOWN_THRESHOLD;
|
|
|
|
dev_priv->rps.down_ei = now;
|
|
|
|
}
|
2014-07-04 05:33:01 +08:00
|
|
|
|
2015-03-18 17:48:22 +08:00
|
|
|
if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) {
|
|
|
|
if (vlv_c0_above(dev_priv,
|
|
|
|
&dev_priv->rps.up_ei, &now,
|
2015-04-07 23:20:28 +08:00
|
|
|
dev_priv->rps.up_threshold))
|
2015-03-18 17:48:22 +08:00
|
|
|
events |= GEN6_PM_RP_UP_THRESHOLD;
|
|
|
|
dev_priv->rps.up_ei = now;
|
2014-07-04 05:33:01 +08:00
|
|
|
}
|
|
|
|
|
2015-03-18 17:48:22 +08:00
|
|
|
return events;
|
2014-07-04 05:33:01 +08:00
|
|
|
}
|
|
|
|
|
2015-04-27 20:41:23 +08:00
|
|
|
static bool any_waiters(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
struct intel_engine_cs *ring;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for_each_ring(ring, dev_priv, i)
|
|
|
|
if (ring->irq_refcount)
|
|
|
|
return true;
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2011-04-26 02:25:20 +08:00
|
|
|
static void gen6_pm_rps_work(struct work_struct *work)
|
2010-12-18 06:19:02 +08:00
|
|
|
{
|
2014-03-31 19:27:17 +08:00
|
|
|
struct drm_i915_private *dev_priv =
|
|
|
|
container_of(work, struct drm_i915_private, rps.work);
|
2015-05-22 04:01:47 +08:00
|
|
|
bool client_boost;
|
|
|
|
int new_delay, adj, min, max;
|
2013-08-07 05:57:13 +08:00
|
|
|
u32 pm_iir;
|
2011-04-26 02:25:20 +08:00
|
|
|
|
2013-07-05 05:35:28 +08:00
|
|
|
spin_lock_irq(&dev_priv->irq_lock);
|
drm/i915: sanitize rps irq disabling
When disabling the RPS interrupts there is a tricky dependency between
the thread disabling the interrupts, the RPS interrupt handler and the
corresponding RPS work. The RPS work can reenable the interrupts, so
there is no straightforward order in the disabling thread to (1) make
sure that any RPS work is flushed and to (2) disable all RPS
interrupts. Currently this is solved by masking the interrupts using two
separate mask registers (first level display IMR and PM IMR) and doing
the disabling when all first level interrupts are disabled.
This works, but the requirement to run with all first level interrupts
disabled is unnecessary making the suspend / unload time ordering of RPS
disabling wrt. other unitialization steps difficult and error prone.
Removing this restriction allows us to disable RPS early during suspend
/ unload and forget about it for the rest of the sequence. By adding a
more explicit method for avoiding the above race, it also becomes easier
to prove its correctness. Finally currently we can hit the WARN in
snb_update_pm_irq(), when a final RPS work runs with the first level
interrupts already disabled. This won't lead to any problem (due to the
separate interrupt masks), but with the change in this and the next
patch we can get rid of the WARN, while leaving it in place for other
scenarios.
To address the above points, add a new RPS interrupts_enabled flag and
use this during RPS disabling to avoid requeuing the RPS work and
reenabling of the RPS interrupts. Since the interrupt disabling happens
now in intel_suspend_gt_powersave(), we will disable RPS interrupts
explicitly during suspend (and not just through the first level mask),
but there is no problem doing so, it's also more consistent and allows
us to unify more of the RPS disabling during suspend and unload time in
the next patch.
v2/v3:
- rebase on patch "drm/i915: move rps irq disable one level up" in the
patchset
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-19 21:30:04 +08:00
|
|
|
/* Speed up work cancelation during disabling rps interrupts. */
|
|
|
|
if (!dev_priv->rps.interrupts_enabled) {
|
|
|
|
spin_unlock_irq(&dev_priv->irq_lock);
|
|
|
|
return;
|
|
|
|
}
|
2012-08-09 05:35:35 +08:00
|
|
|
pm_iir = dev_priv->rps.pm_iir;
|
|
|
|
dev_priv->rps.pm_iir = 0;
|
2014-11-06 02:48:31 +08:00
|
|
|
/* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
|
|
|
|
gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
|
2015-05-22 04:01:47 +08:00
|
|
|
client_boost = dev_priv->rps.client_boost;
|
|
|
|
dev_priv->rps.client_boost = false;
|
2013-07-05 05:35:28 +08:00
|
|
|
spin_unlock_irq(&dev_priv->irq_lock);
|
2010-12-18 06:19:02 +08:00
|
|
|
|
2013-08-15 22:50:01 +08:00
|
|
|
/* Make sure we didn't queue anything we're not going to process. */
|
2014-03-15 22:53:22 +08:00
|
|
|
WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
|
2013-08-15 22:50:01 +08:00
|
|
|
|
2015-05-22 04:01:47 +08:00
|
|
|
if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost)
|
2010-12-18 06:19:02 +08:00
|
|
|
return;
|
|
|
|
|
2012-11-03 02:14:01 +08:00
|
|
|
mutex_lock(&dev_priv->rps.hw_lock);
|
2012-04-28 15:56:39 +08:00
|
|
|
|
2015-03-18 17:48:22 +08:00
|
|
|
pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir);
|
|
|
|
|
drm/i915: Tweak RPS thresholds to more aggressively downclock
After applying wait-boost we often find ourselves stuck at higher clocks
than required. The current threshold value requires the GPU to be
continuously and completely idle for 313ms before it is dropped by one
bin. Conversely, we require the GPU to be busy for an average of 90% over
a 84ms period before we upclock. So the current thresholds almost never
downclock the GPU, and respond very slowly to sudden demands for more
power. It is easy to observe that we currently lock into the wrong bin
and both underperform in benchmarks and consume more power than optimal
(just by repeating the task and measuring the different results).
An alternative approach, as discussed in the bspec, is to use a
continuous threshold for upclocking, and an average value for downclocking.
This is good for quickly detecting and reacting to state changes within a
frame, however it fails with the common throttling method of waiting
upon the outstanding frame - at least it is difficult to choose a
threshold that works well at 15,000fps and at 60fps. So continue to use
average busy/idle loads to determine frequency change.
v2: Use 3 power zones to keep frequencies low in steady-state mostly
idle (e.g. scrolling, interactive 2D drawing), and frequencies high
for demanding games. In between those end-states, we use a
fast-reclocking algorithm to converge more quickly on the desired bin.
v3: Bug fixes - make sure we reset adj after switching power zones.
v4: Tune - drop the continuous busy thresholds as it prevents us from
choosing the right frequency for glxgears style swap benchmarks. Instead
the goal is to be able to find the right clocks irrespective of the
wait-boost.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Cc: Stéphane Marchesin <stephane.marchesin@gmail.com>
Cc: Owen Taylor <otaylor@redhat.com>
Cc: "Meng, Mengmeng" <mengmeng.meng@intel.com>
Cc: "Zhuang, Lena" <lena.zhuang@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-09-26 00:34:57 +08:00
|
|
|
adj = dev_priv->rps.last_adj;
|
2015-04-07 23:20:29 +08:00
|
|
|
new_delay = dev_priv->rps.cur_freq;
|
2015-05-22 04:01:47 +08:00
|
|
|
min = dev_priv->rps.min_freq_softlimit;
|
|
|
|
max = dev_priv->rps.max_freq_softlimit;
|
|
|
|
|
|
|
|
if (client_boost) {
|
|
|
|
new_delay = dev_priv->rps.max_freq_softlimit;
|
|
|
|
adj = 0;
|
|
|
|
} else if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
|
drm/i915: Tweak RPS thresholds to more aggressively downclock
After applying wait-boost we often find ourselves stuck at higher clocks
than required. The current threshold value requires the GPU to be
continuously and completely idle for 313ms before it is dropped by one
bin. Conversely, we require the GPU to be busy for an average of 90% over
a 84ms period before we upclock. So the current thresholds almost never
downclock the GPU, and respond very slowly to sudden demands for more
power. It is easy to observe that we currently lock into the wrong bin
and both underperform in benchmarks and consume more power than optimal
(just by repeating the task and measuring the different results).
An alternative approach, as discussed in the bspec, is to use a
continuous threshold for upclocking, and an average value for downclocking.
This is good for quickly detecting and reacting to state changes within a
frame, however it fails with the common throttling method of waiting
upon the outstanding frame - at least it is difficult to choose a
threshold that works well at 15,000fps and at 60fps. So continue to use
average busy/idle loads to determine frequency change.
v2: Use 3 power zones to keep frequencies low in steady-state mostly
idle (e.g. scrolling, interactive 2D drawing), and frequencies high
for demanding games. In between those end-states, we use a
fast-reclocking algorithm to converge more quickly on the desired bin.
v3: Bug fixes - make sure we reset adj after switching power zones.
v4: Tune - drop the continuous busy thresholds as it prevents us from
choosing the right frequency for glxgears style swap benchmarks. Instead
the goal is to be able to find the right clocks irrespective of the
wait-boost.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Cc: Stéphane Marchesin <stephane.marchesin@gmail.com>
Cc: Owen Taylor <otaylor@redhat.com>
Cc: "Meng, Mengmeng" <mengmeng.meng@intel.com>
Cc: "Zhuang, Lena" <lena.zhuang@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-09-26 00:34:57 +08:00
|
|
|
if (adj > 0)
|
|
|
|
adj *= 2;
|
2015-04-07 23:20:29 +08:00
|
|
|
else /* CHV needs even encode values */
|
|
|
|
adj = IS_CHERRYVIEW(dev_priv) ? 2 : 1;
|
2013-06-26 02:38:11 +08:00
|
|
|
/*
|
|
|
|
* For better performance, jump directly
|
|
|
|
* to RPe if we're below it.
|
|
|
|
*/
|
2015-04-07 23:20:29 +08:00
|
|
|
if (new_delay < dev_priv->rps.efficient_freq - adj) {
|
2014-03-20 09:31:11 +08:00
|
|
|
new_delay = dev_priv->rps.efficient_freq;
|
2015-04-07 23:20:29 +08:00
|
|
|
adj = 0;
|
|
|
|
}
|
2015-04-27 20:41:23 +08:00
|
|
|
} else if (any_waiters(dev_priv)) {
|
|
|
|
adj = 0;
|
drm/i915: Tweak RPS thresholds to more aggressively downclock
After applying wait-boost we often find ourselves stuck at higher clocks
than required. The current threshold value requires the GPU to be
continuously and completely idle for 313ms before it is dropped by one
bin. Conversely, we require the GPU to be busy for an average of 90% over
a 84ms period before we upclock. So the current thresholds almost never
downclock the GPU, and respond very slowly to sudden demands for more
power. It is easy to observe that we currently lock into the wrong bin
and both underperform in benchmarks and consume more power than optimal
(just by repeating the task and measuring the different results).
An alternative approach, as discussed in the bspec, is to use a
continuous threshold for upclocking, and an average value for downclocking.
This is good for quickly detecting and reacting to state changes within a
frame, however it fails with the common throttling method of waiting
upon the outstanding frame - at least it is difficult to choose a
threshold that works well at 15,000fps and at 60fps. So continue to use
average busy/idle loads to determine frequency change.
v2: Use 3 power zones to keep frequencies low in steady-state mostly
idle (e.g. scrolling, interactive 2D drawing), and frequencies high
for demanding games. In between those end-states, we use a
fast-reclocking algorithm to converge more quickly on the desired bin.
v3: Bug fixes - make sure we reset adj after switching power zones.
v4: Tune - drop the continuous busy thresholds as it prevents us from
choosing the right frequency for glxgears style swap benchmarks. Instead
the goal is to be able to find the right clocks irrespective of the
wait-boost.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Cc: Stéphane Marchesin <stephane.marchesin@gmail.com>
Cc: Owen Taylor <otaylor@redhat.com>
Cc: "Meng, Mengmeng" <mengmeng.meng@intel.com>
Cc: "Zhuang, Lena" <lena.zhuang@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-09-26 00:34:57 +08:00
|
|
|
} else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
|
2014-03-20 09:31:11 +08:00
|
|
|
if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
|
|
|
|
new_delay = dev_priv->rps.efficient_freq;
|
drm/i915: Tweak RPS thresholds to more aggressively downclock
After applying wait-boost we often find ourselves stuck at higher clocks
than required. The current threshold value requires the GPU to be
continuously and completely idle for 313ms before it is dropped by one
bin. Conversely, we require the GPU to be busy for an average of 90% over
a 84ms period before we upclock. So the current thresholds almost never
downclock the GPU, and respond very slowly to sudden demands for more
power. It is easy to observe that we currently lock into the wrong bin
and both underperform in benchmarks and consume more power than optimal
(just by repeating the task and measuring the different results).
An alternative approach, as discussed in the bspec, is to use a
continuous threshold for upclocking, and an average value for downclocking.
This is good for quickly detecting and reacting to state changes within a
frame, however it fails with the common throttling method of waiting
upon the outstanding frame - at least it is difficult to choose a
threshold that works well at 15,000fps and at 60fps. So continue to use
average busy/idle loads to determine frequency change.
v2: Use 3 power zones to keep frequencies low in steady-state mostly
idle (e.g. scrolling, interactive 2D drawing), and frequencies high
for demanding games. In between those end-states, we use a
fast-reclocking algorithm to converge more quickly on the desired bin.
v3: Bug fixes - make sure we reset adj after switching power zones.
v4: Tune - drop the continuous busy thresholds as it prevents us from
choosing the right frequency for glxgears style swap benchmarks. Instead
the goal is to be able to find the right clocks irrespective of the
wait-boost.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Cc: Stéphane Marchesin <stephane.marchesin@gmail.com>
Cc: Owen Taylor <otaylor@redhat.com>
Cc: "Meng, Mengmeng" <mengmeng.meng@intel.com>
Cc: "Zhuang, Lena" <lena.zhuang@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-09-26 00:34:57 +08:00
|
|
|
else
|
2014-03-20 09:31:11 +08:00
|
|
|
new_delay = dev_priv->rps.min_freq_softlimit;
|
drm/i915: Tweak RPS thresholds to more aggressively downclock
After applying wait-boost we often find ourselves stuck at higher clocks
than required. The current threshold value requires the GPU to be
continuously and completely idle for 313ms before it is dropped by one
bin. Conversely, we require the GPU to be busy for an average of 90% over
a 84ms period before we upclock. So the current thresholds almost never
downclock the GPU, and respond very slowly to sudden demands for more
power. It is easy to observe that we currently lock into the wrong bin
and both underperform in benchmarks and consume more power than optimal
(just by repeating the task and measuring the different results).
An alternative approach, as discussed in the bspec, is to use a
continuous threshold for upclocking, and an average value for downclocking.
This is good for quickly detecting and reacting to state changes within a
frame, however it fails with the common throttling method of waiting
upon the outstanding frame - at least it is difficult to choose a
threshold that works well at 15,000fps and at 60fps. So continue to use
average busy/idle loads to determine frequency change.
v2: Use 3 power zones to keep frequencies low in steady-state mostly
idle (e.g. scrolling, interactive 2D drawing), and frequencies high
for demanding games. In between those end-states, we use a
fast-reclocking algorithm to converge more quickly on the desired bin.
v3: Bug fixes - make sure we reset adj after switching power zones.
v4: Tune - drop the continuous busy thresholds as it prevents us from
choosing the right frequency for glxgears style swap benchmarks. Instead
the goal is to be able to find the right clocks irrespective of the
wait-boost.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Cc: Stéphane Marchesin <stephane.marchesin@gmail.com>
Cc: Owen Taylor <otaylor@redhat.com>
Cc: "Meng, Mengmeng" <mengmeng.meng@intel.com>
Cc: "Zhuang, Lena" <lena.zhuang@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-09-26 00:34:57 +08:00
|
|
|
adj = 0;
|
|
|
|
} else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
|
|
|
|
if (adj < 0)
|
|
|
|
adj *= 2;
|
2015-04-07 23:20:29 +08:00
|
|
|
else /* CHV needs even encode values */
|
|
|
|
adj = IS_CHERRYVIEW(dev_priv) ? -2 : -1;
|
drm/i915: Tweak RPS thresholds to more aggressively downclock
After applying wait-boost we often find ourselves stuck at higher clocks
than required. The current threshold value requires the GPU to be
continuously and completely idle for 313ms before it is dropped by one
bin. Conversely, we require the GPU to be busy for an average of 90% over
a 84ms period before we upclock. So the current thresholds almost never
downclock the GPU, and respond very slowly to sudden demands for more
power. It is easy to observe that we currently lock into the wrong bin
and both underperform in benchmarks and consume more power than optimal
(just by repeating the task and measuring the different results).
An alternative approach, as discussed in the bspec, is to use a
continuous threshold for upclocking, and an average value for downclocking.
This is good for quickly detecting and reacting to state changes within a
frame, however it fails with the common throttling method of waiting
upon the outstanding frame - at least it is difficult to choose a
threshold that works well at 15,000fps and at 60fps. So continue to use
average busy/idle loads to determine frequency change.
v2: Use 3 power zones to keep frequencies low in steady-state mostly
idle (e.g. scrolling, interactive 2D drawing), and frequencies high
for demanding games. In between those end-states, we use a
fast-reclocking algorithm to converge more quickly on the desired bin.
v3: Bug fixes - make sure we reset adj after switching power zones.
v4: Tune - drop the continuous busy thresholds as it prevents us from
choosing the right frequency for glxgears style swap benchmarks. Instead
the goal is to be able to find the right clocks irrespective of the
wait-boost.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Cc: Stéphane Marchesin <stephane.marchesin@gmail.com>
Cc: Owen Taylor <otaylor@redhat.com>
Cc: "Meng, Mengmeng" <mengmeng.meng@intel.com>
Cc: "Zhuang, Lena" <lena.zhuang@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-09-26 00:34:57 +08:00
|
|
|
} else { /* unknown event */
|
2015-04-07 23:20:29 +08:00
|
|
|
adj = 0;
|
drm/i915: Tweak RPS thresholds to more aggressively downclock
After applying wait-boost we often find ourselves stuck at higher clocks
than required. The current threshold value requires the GPU to be
continuously and completely idle for 313ms before it is dropped by one
bin. Conversely, we require the GPU to be busy for an average of 90% over
a 84ms period before we upclock. So the current thresholds almost never
downclock the GPU, and respond very slowly to sudden demands for more
power. It is easy to observe that we currently lock into the wrong bin
and both underperform in benchmarks and consume more power than optimal
(just by repeating the task and measuring the different results).
An alternative approach, as discussed in the bspec, is to use a
continuous threshold for upclocking, and an average value for downclocking.
This is good for quickly detecting and reacting to state changes within a
frame, however it fails with the common throttling method of waiting
upon the outstanding frame - at least it is difficult to choose a
threshold that works well at 15,000fps and at 60fps. So continue to use
average busy/idle loads to determine frequency change.
v2: Use 3 power zones to keep frequencies low in steady-state mostly
idle (e.g. scrolling, interactive 2D drawing), and frequencies high
for demanding games. In between those end-states, we use a
fast-reclocking algorithm to converge more quickly on the desired bin.
v3: Bug fixes - make sure we reset adj after switching power zones.
v4: Tune - drop the continuous busy thresholds as it prevents us from
choosing the right frequency for glxgears style swap benchmarks. Instead
the goal is to be able to find the right clocks irrespective of the
wait-boost.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Cc: Stéphane Marchesin <stephane.marchesin@gmail.com>
Cc: Owen Taylor <otaylor@redhat.com>
Cc: "Meng, Mengmeng" <mengmeng.meng@intel.com>
Cc: "Zhuang, Lena" <lena.zhuang@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-09-26 00:34:57 +08:00
|
|
|
}
|
2010-12-18 06:19:02 +08:00
|
|
|
|
2015-04-07 23:20:29 +08:00
|
|
|
dev_priv->rps.last_adj = adj;
|
|
|
|
|
2012-09-08 10:43:42 +08:00
|
|
|
/* sysfs frequency interfaces may have snuck in while servicing the
|
|
|
|
* interrupt
|
|
|
|
*/
|
2015-04-07 23:20:29 +08:00
|
|
|
new_delay += adj;
|
2015-05-22 04:01:47 +08:00
|
|
|
new_delay = clamp_t(int, new_delay, min, max);
|
2014-01-28 00:05:05 +08:00
|
|
|
|
2015-02-03 01:09:50 +08:00
|
|
|
intel_set_rps(dev_priv->dev, new_delay);
|
2010-12-18 06:19:02 +08:00
|
|
|
|
2012-11-03 02:14:01 +08:00
|
|
|
mutex_unlock(&dev_priv->rps.hw_lock);
|
2010-12-18 06:19:02 +08:00
|
|
|
}
|
|
|
|
|
2012-05-26 07:56:22 +08:00
|
|
|
|
|
|
|
/**
|
|
|
|
* ivybridge_parity_work - Workqueue called when a parity error interrupt
|
|
|
|
* occurred.
|
|
|
|
* @work: workqueue struct
|
|
|
|
*
|
|
|
|
* Doesn't actually do anything except notify userspace. As a consequence of
|
|
|
|
* this event, userspace should try to remap the bad rows since statistically
|
|
|
|
* it is likely the same row is more likely to go bad again.
|
|
|
|
*/
|
|
|
|
static void ivybridge_parity_work(struct work_struct *work)
|
|
|
|
{
|
2014-03-31 19:27:17 +08:00
|
|
|
struct drm_i915_private *dev_priv =
|
|
|
|
container_of(work, struct drm_i915_private, l3_parity.error_work);
|
2012-05-26 07:56:22 +08:00
|
|
|
u32 error_status, row, bank, subbank;
|
2013-09-20 02:13:41 +08:00
|
|
|
char *parity_event[6];
|
2012-05-26 07:56:22 +08:00
|
|
|
uint32_t misccpctl;
|
2013-09-20 02:13:41 +08:00
|
|
|
uint8_t slice = 0;
|
2012-05-26 07:56:22 +08:00
|
|
|
|
|
|
|
/* We must turn off DOP level clock gating to access the L3 registers.
|
|
|
|
* In order to prevent a get/put style interface, acquire struct mutex
|
|
|
|
* any time we access those registers.
|
|
|
|
*/
|
|
|
|
mutex_lock(&dev_priv->dev->struct_mutex);
|
|
|
|
|
2013-09-20 02:13:41 +08:00
|
|
|
/* If we've screwed up tracking, just let the interrupt fire again */
|
|
|
|
if (WARN_ON(!dev_priv->l3_parity.which_slice))
|
|
|
|
goto out;
|
|
|
|
|
2012-05-26 07:56:22 +08:00
|
|
|
misccpctl = I915_READ(GEN7_MISCCPCTL);
|
|
|
|
I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
|
|
|
|
POSTING_READ(GEN7_MISCCPCTL);
|
|
|
|
|
2013-09-20 02:13:41 +08:00
|
|
|
while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
|
|
|
|
u32 reg;
|
2012-05-26 07:56:22 +08:00
|
|
|
|
2013-09-20 02:13:41 +08:00
|
|
|
slice--;
|
|
|
|
if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
|
|
|
|
break;
|
2012-05-26 07:56:22 +08:00
|
|
|
|
2013-09-20 02:13:41 +08:00
|
|
|
dev_priv->l3_parity.which_slice &= ~(1<<slice);
|
2012-05-26 07:56:22 +08:00
|
|
|
|
2013-09-20 02:13:41 +08:00
|
|
|
reg = GEN7_L3CDERRST1 + (slice * 0x200);
|
2012-05-26 07:56:22 +08:00
|
|
|
|
2013-09-20 02:13:41 +08:00
|
|
|
error_status = I915_READ(reg);
|
|
|
|
row = GEN7_PARITY_ERROR_ROW(error_status);
|
|
|
|
bank = GEN7_PARITY_ERROR_BANK(error_status);
|
|
|
|
subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
|
|
|
|
|
|
|
|
I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
|
|
|
|
POSTING_READ(reg);
|
|
|
|
|
|
|
|
parity_event[0] = I915_L3_PARITY_UEVENT "=1";
|
|
|
|
parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
|
|
|
|
parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
|
|
|
|
parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
|
|
|
|
parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
|
|
|
|
parity_event[5] = NULL;
|
|
|
|
|
2013-10-11 12:07:25 +08:00
|
|
|
kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj,
|
2013-09-20 02:13:41 +08:00
|
|
|
KOBJ_CHANGE, parity_event);
|
2012-05-26 07:56:22 +08:00
|
|
|
|
2013-09-20 02:13:41 +08:00
|
|
|
DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
|
|
|
|
slice, row, bank, subbank);
|
2012-05-26 07:56:22 +08:00
|
|
|
|
2013-09-20 02:13:41 +08:00
|
|
|
kfree(parity_event[4]);
|
|
|
|
kfree(parity_event[3]);
|
|
|
|
kfree(parity_event[2]);
|
|
|
|
kfree(parity_event[1]);
|
|
|
|
}
|
2012-05-26 07:56:22 +08:00
|
|
|
|
2013-09-20 02:13:41 +08:00
|
|
|
I915_WRITE(GEN7_MISCCPCTL, misccpctl);
|
2012-05-26 07:56:22 +08:00
|
|
|
|
2013-09-20 02:13:41 +08:00
|
|
|
out:
|
|
|
|
WARN_ON(dev_priv->l3_parity.which_slice);
|
2014-09-15 20:55:26 +08:00
|
|
|
spin_lock_irq(&dev_priv->irq_lock);
|
2014-07-16 15:49:40 +08:00
|
|
|
gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
|
2014-09-15 20:55:26 +08:00
|
|
|
spin_unlock_irq(&dev_priv->irq_lock);
|
2013-09-20 02:13:41 +08:00
|
|
|
|
|
|
|
mutex_unlock(&dev_priv->dev->struct_mutex);
|
2012-05-26 07:56:22 +08:00
|
|
|
}
|
|
|
|
|
2013-09-20 02:13:41 +08:00
|
|
|
static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
|
2012-05-26 07:56:22 +08:00
|
|
|
{
|
2014-03-31 19:27:17 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2012-05-26 07:56:22 +08:00
|
|
|
|
2013-09-20 02:01:40 +08:00
|
|
|
if (!HAS_L3_DPF(dev))
|
2012-05-26 07:56:22 +08:00
|
|
|
return;
|
|
|
|
|
2013-07-05 05:35:25 +08:00
|
|
|
spin_lock(&dev_priv->irq_lock);
|
2014-07-16 15:49:40 +08:00
|
|
|
gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
|
2013-07-05 05:35:25 +08:00
|
|
|
spin_unlock(&dev_priv->irq_lock);
|
2012-05-26 07:56:22 +08:00
|
|
|
|
2013-09-20 02:13:41 +08:00
|
|
|
iir &= GT_PARITY_ERROR(dev);
|
|
|
|
if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
|
|
|
|
dev_priv->l3_parity.which_slice |= 1 << 1;
|
|
|
|
|
|
|
|
if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
|
|
|
|
dev_priv->l3_parity.which_slice |= 1 << 0;
|
|
|
|
|
2012-11-03 02:55:07 +08:00
|
|
|
queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
|
2012-05-26 07:56:22 +08:00
|
|
|
}
|
|
|
|
|
2013-07-13 06:56:30 +08:00
|
|
|
static void ilk_gt_irq_handler(struct drm_device *dev,
|
|
|
|
struct drm_i915_private *dev_priv,
|
|
|
|
u32 gt_iir)
|
|
|
|
{
|
|
|
|
if (gt_iir &
|
|
|
|
(GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
|
2015-04-07 23:21:05 +08:00
|
|
|
notify_ring(&dev_priv->ring[RCS]);
|
2013-07-13 06:56:30 +08:00
|
|
|
if (gt_iir & ILK_BSD_USER_INTERRUPT)
|
2015-04-07 23:21:05 +08:00
|
|
|
notify_ring(&dev_priv->ring[VCS]);
|
2013-07-13 06:56:30 +08:00
|
|
|
}
|
|
|
|
|
2012-03-31 02:24:35 +08:00
|
|
|
static void snb_gt_irq_handler(struct drm_device *dev,
|
|
|
|
struct drm_i915_private *dev_priv,
|
|
|
|
u32 gt_iir)
|
|
|
|
{
|
|
|
|
|
2013-05-29 10:22:29 +08:00
|
|
|
if (gt_iir &
|
|
|
|
(GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
|
2015-04-07 23:21:05 +08:00
|
|
|
notify_ring(&dev_priv->ring[RCS]);
|
2013-05-29 10:22:29 +08:00
|
|
|
if (gt_iir & GT_BSD_USER_INTERRUPT)
|
2015-04-07 23:21:05 +08:00
|
|
|
notify_ring(&dev_priv->ring[VCS]);
|
2013-05-29 10:22:29 +08:00
|
|
|
if (gt_iir & GT_BLT_USER_INTERRUPT)
|
2015-04-07 23:21:05 +08:00
|
|
|
notify_ring(&dev_priv->ring[BCS]);
|
2012-03-31 02:24:35 +08:00
|
|
|
|
2013-05-29 10:22:29 +08:00
|
|
|
if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
|
|
|
|
GT_BSD_CS_ERROR_INTERRUPT |
|
2014-11-04 22:52:22 +08:00
|
|
|
GT_RENDER_CS_MASTER_ERROR_INTERRUPT))
|
|
|
|
DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir);
|
2012-05-26 07:56:22 +08:00
|
|
|
|
2013-09-20 02:13:41 +08:00
|
|
|
if (gt_iir & GT_PARITY_ERROR(dev))
|
|
|
|
ivybridge_parity_error_irq_handler(dev, gt_iir);
|
2012-03-31 02:24:35 +08:00
|
|
|
}
|
|
|
|
|
2015-04-07 23:21:05 +08:00
|
|
|
static irqreturn_t gen8_gt_irq_handler(struct drm_i915_private *dev_priv,
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 12:07:09 +08:00
|
|
|
u32 master_ctl)
|
|
|
|
{
|
|
|
|
irqreturn_t ret = IRQ_NONE;
|
|
|
|
|
|
|
|
if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
|
2015-04-07 23:21:05 +08:00
|
|
|
u32 tmp = I915_READ_FW(GEN8_GT_IIR(0));
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 12:07:09 +08:00
|
|
|
if (tmp) {
|
2015-04-07 23:21:04 +08:00
|
|
|
I915_WRITE_FW(GEN8_GT_IIR(0), tmp);
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 12:07:09 +08:00
|
|
|
ret = IRQ_HANDLED;
|
drm/i915/bdw: Handle context switch events
Handle all context status events in the context status buffer on every
context switch interrupt. We only remove work from the execlist queue
after a context status buffer reports that it has completed and we only
attempt to schedule new contexts on interrupt when a previously submitted
context completes (unless no contexts are queued, which means the GPU is
free).
We canot call intel_runtime_pm_get() in an interrupt (or with a spinlock
grabbed, FWIW), because it might sleep, which is not a nice thing to do.
Instead, do the runtime_pm get/put together with the create/destroy request,
and handle the forcewake get/put directly.
Signed-off-by: Thomas Daniel <thomas.daniel@intel.com>
v2: Unreferencing the context when we are freeing the request might free
the backing bo, which requires the struct_mutex to be grabbed, so defer
unreferencing and freeing to a bottom half.
v3:
- Ack the interrupt inmediately, before trying to handle it (fix for
missing interrupts by Bob Beckett <robert.beckett@intel.com>).
- Update the Context Status Buffer Read Pointer, just in case (spotted
by Damien Lespiau).
v4: New namespace and multiple rebase changes.
v5: Squash with "drm/i915/bdw: Do not call intel_runtime_pm_get() in an
interrupt", as suggested by Daniel.
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
[danvet: Checkpatch ...]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-07-25 00:04:39 +08:00
|
|
|
|
2015-04-07 23:21:05 +08:00
|
|
|
if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT))
|
|
|
|
intel_lrc_irq_handler(&dev_priv->ring[RCS]);
|
|
|
|
if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT))
|
|
|
|
notify_ring(&dev_priv->ring[RCS]);
|
|
|
|
|
|
|
|
if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT))
|
|
|
|
intel_lrc_irq_handler(&dev_priv->ring[BCS]);
|
|
|
|
if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT))
|
|
|
|
notify_ring(&dev_priv->ring[BCS]);
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 12:07:09 +08:00
|
|
|
} else
|
|
|
|
DRM_ERROR("The master control interrupt lied (GT0)!\n");
|
|
|
|
}
|
|
|
|
|
2014-04-17 10:37:38 +08:00
|
|
|
if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
|
2015-04-07 23:21:05 +08:00
|
|
|
u32 tmp = I915_READ_FW(GEN8_GT_IIR(1));
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 12:07:09 +08:00
|
|
|
if (tmp) {
|
2015-04-07 23:21:04 +08:00
|
|
|
I915_WRITE_FW(GEN8_GT_IIR(1), tmp);
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 12:07:09 +08:00
|
|
|
ret = IRQ_HANDLED;
|
drm/i915/bdw: Handle context switch events
Handle all context status events in the context status buffer on every
context switch interrupt. We only remove work from the execlist queue
after a context status buffer reports that it has completed and we only
attempt to schedule new contexts on interrupt when a previously submitted
context completes (unless no contexts are queued, which means the GPU is
free).
We canot call intel_runtime_pm_get() in an interrupt (or with a spinlock
grabbed, FWIW), because it might sleep, which is not a nice thing to do.
Instead, do the runtime_pm get/put together with the create/destroy request,
and handle the forcewake get/put directly.
Signed-off-by: Thomas Daniel <thomas.daniel@intel.com>
v2: Unreferencing the context when we are freeing the request might free
the backing bo, which requires the struct_mutex to be grabbed, so defer
unreferencing and freeing to a bottom half.
v3:
- Ack the interrupt inmediately, before trying to handle it (fix for
missing interrupts by Bob Beckett <robert.beckett@intel.com>).
- Update the Context Status Buffer Read Pointer, just in case (spotted
by Damien Lespiau).
v4: New namespace and multiple rebase changes.
v5: Squash with "drm/i915/bdw: Do not call intel_runtime_pm_get() in an
interrupt", as suggested by Daniel.
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
[danvet: Checkpatch ...]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-07-25 00:04:39 +08:00
|
|
|
|
2015-04-07 23:21:05 +08:00
|
|
|
if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT))
|
|
|
|
intel_lrc_irq_handler(&dev_priv->ring[VCS]);
|
|
|
|
if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT))
|
|
|
|
notify_ring(&dev_priv->ring[VCS]);
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 12:07:09 +08:00
|
|
|
|
2015-04-07 23:21:05 +08:00
|
|
|
if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT))
|
|
|
|
intel_lrc_irq_handler(&dev_priv->ring[VCS2]);
|
|
|
|
if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT))
|
|
|
|
notify_ring(&dev_priv->ring[VCS2]);
|
2014-05-16 01:58:08 +08:00
|
|
|
} else
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 12:07:09 +08:00
|
|
|
DRM_ERROR("The master control interrupt lied (GT1)!\n");
|
2014-05-16 01:58:08 +08:00
|
|
|
}
|
|
|
|
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 12:07:09 +08:00
|
|
|
if (master_ctl & GEN8_GT_VECS_IRQ) {
|
2015-04-07 23:21:05 +08:00
|
|
|
u32 tmp = I915_READ_FW(GEN8_GT_IIR(3));
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 12:07:09 +08:00
|
|
|
if (tmp) {
|
2015-04-07 23:21:05 +08:00
|
|
|
I915_WRITE_FW(GEN8_GT_IIR(3), tmp);
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 12:07:09 +08:00
|
|
|
ret = IRQ_HANDLED;
|
drm/i915/bdw: Handle context switch events
Handle all context status events in the context status buffer on every
context switch interrupt. We only remove work from the execlist queue
after a context status buffer reports that it has completed and we only
attempt to schedule new contexts on interrupt when a previously submitted
context completes (unless no contexts are queued, which means the GPU is
free).
We canot call intel_runtime_pm_get() in an interrupt (or with a spinlock
grabbed, FWIW), because it might sleep, which is not a nice thing to do.
Instead, do the runtime_pm get/put together with the create/destroy request,
and handle the forcewake get/put directly.
Signed-off-by: Thomas Daniel <thomas.daniel@intel.com>
v2: Unreferencing the context when we are freeing the request might free
the backing bo, which requires the struct_mutex to be grabbed, so defer
unreferencing and freeing to a bottom half.
v3:
- Ack the interrupt inmediately, before trying to handle it (fix for
missing interrupts by Bob Beckett <robert.beckett@intel.com>).
- Update the Context Status Buffer Read Pointer, just in case (spotted
by Damien Lespiau).
v4: New namespace and multiple rebase changes.
v5: Squash with "drm/i915/bdw: Do not call intel_runtime_pm_get() in an
interrupt", as suggested by Daniel.
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
[danvet: Checkpatch ...]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-07-25 00:04:39 +08:00
|
|
|
|
2015-04-07 23:21:05 +08:00
|
|
|
if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT))
|
|
|
|
intel_lrc_irq_handler(&dev_priv->ring[VECS]);
|
|
|
|
if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT))
|
|
|
|
notify_ring(&dev_priv->ring[VECS]);
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 12:07:09 +08:00
|
|
|
} else
|
|
|
|
DRM_ERROR("The master control interrupt lied (GT3)!\n");
|
|
|
|
}
|
|
|
|
|
2014-05-16 01:58:08 +08:00
|
|
|
if (master_ctl & GEN8_GT_PM_IRQ) {
|
2015-04-07 23:21:05 +08:00
|
|
|
u32 tmp = I915_READ_FW(GEN8_GT_IIR(2));
|
2014-05-16 01:58:08 +08:00
|
|
|
if (tmp & dev_priv->pm_rps_events) {
|
2015-04-07 23:21:04 +08:00
|
|
|
I915_WRITE_FW(GEN8_GT_IIR(2),
|
|
|
|
tmp & dev_priv->pm_rps_events);
|
2014-06-16 23:10:59 +08:00
|
|
|
ret = IRQ_HANDLED;
|
2014-11-06 02:48:37 +08:00
|
|
|
gen6_rps_irq_handler(dev_priv, tmp);
|
2014-05-16 01:58:08 +08:00
|
|
|
} else
|
|
|
|
DRM_ERROR("The master control interrupt lied (PM)!\n");
|
|
|
|
}
|
|
|
|
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 12:07:09 +08:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2013-04-16 19:36:54 +08:00
|
|
|
#define HPD_STORM_DETECT_PERIOD 1000
|
|
|
|
#define HPD_STORM_THRESHOLD 5
|
|
|
|
|
2015-05-29 21:14:37 +08:00
|
|
|
/**
|
|
|
|
* intel_hpd_irq_storm - gather stats and detect HPD irq storm on a pin
|
|
|
|
* @dev_priv: private driver data pointer
|
|
|
|
* @pin: the pin to gather stats on
|
|
|
|
*
|
|
|
|
* Gather stats about HPD irqs from the specified @pin, and detect irq
|
|
|
|
* storms. Only the pin specific stats and state are changed, the caller is
|
|
|
|
* responsible for further action.
|
|
|
|
*
|
|
|
|
* @HPD_STORM_THRESHOLD irqs are allowed within @HPD_STORM_DETECT_PERIOD ms,
|
|
|
|
* otherwise it's considered an irq storm, and the irq state is set to
|
|
|
|
* @HPD_MARK_DISABLED.
|
|
|
|
*
|
|
|
|
* Return true if an irq storm was detected on @pin.
|
|
|
|
*/
|
|
|
|
static bool intel_hpd_irq_storm(struct drm_i915_private *dev_priv,
|
|
|
|
enum hpd_pin pin)
|
|
|
|
{
|
|
|
|
unsigned long start = dev_priv->hotplug.stats[pin].last_jiffies;
|
|
|
|
unsigned long end = start + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD);
|
|
|
|
bool storm = false;
|
|
|
|
|
|
|
|
if (!time_in_range(jiffies, start, end)) {
|
|
|
|
dev_priv->hotplug.stats[pin].last_jiffies = jiffies;
|
|
|
|
dev_priv->hotplug.stats[pin].count = 0;
|
|
|
|
DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", pin);
|
|
|
|
} else if (dev_priv->hotplug.stats[pin].count > HPD_STORM_THRESHOLD) {
|
|
|
|
dev_priv->hotplug.stats[pin].state = HPD_MARK_DISABLED;
|
|
|
|
DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", pin);
|
|
|
|
storm = true;
|
|
|
|
} else {
|
|
|
|
dev_priv->hotplug.stats[pin].count++;
|
|
|
|
DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", pin,
|
|
|
|
dev_priv->hotplug.stats[pin].count);
|
|
|
|
}
|
|
|
|
|
|
|
|
return storm;
|
|
|
|
}
|
|
|
|
|
2015-05-28 20:43:53 +08:00
|
|
|
static bool pch_port_hotplug_long_detect(enum port port, u32 val)
|
2014-06-18 09:29:35 +08:00
|
|
|
{
|
|
|
|
switch (port) {
|
|
|
|
case PORT_B:
|
2015-05-28 20:43:53 +08:00
|
|
|
return val & PORTB_HOTPLUG_LONG_DETECT;
|
2014-06-18 09:29:35 +08:00
|
|
|
case PORT_C:
|
2015-05-28 20:43:53 +08:00
|
|
|
return val & PORTC_HOTPLUG_LONG_DETECT;
|
2014-06-18 09:29:35 +08:00
|
|
|
case PORT_D:
|
2015-05-28 20:43:53 +08:00
|
|
|
return val & PORTD_HOTPLUG_LONG_DETECT;
|
|
|
|
default:
|
|
|
|
return false;
|
2014-06-18 09:29:35 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-05-28 20:43:53 +08:00
|
|
|
static bool i9xx_port_hotplug_long_detect(enum port port, u32 val)
|
2014-06-18 09:29:35 +08:00
|
|
|
{
|
|
|
|
switch (port) {
|
|
|
|
case PORT_B:
|
2015-05-28 20:43:53 +08:00
|
|
|
return val & PORTB_HOTPLUG_INT_LONG_PULSE;
|
2014-06-18 09:29:35 +08:00
|
|
|
case PORT_C:
|
2015-05-28 20:43:53 +08:00
|
|
|
return val & PORTC_HOTPLUG_INT_LONG_PULSE;
|
2014-06-18 09:29:35 +08:00
|
|
|
case PORT_D:
|
2015-05-28 20:43:53 +08:00
|
|
|
return val & PORTD_HOTPLUG_INT_LONG_PULSE;
|
|
|
|
default:
|
|
|
|
return false;
|
2014-06-18 09:29:35 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-05-12 01:49:09 +08:00
|
|
|
static enum port get_port_from_pin(enum hpd_pin pin)
|
2014-06-18 09:29:35 +08:00
|
|
|
{
|
|
|
|
switch (pin) {
|
|
|
|
case HPD_PORT_B:
|
|
|
|
return PORT_B;
|
|
|
|
case HPD_PORT_C:
|
|
|
|
return PORT_C;
|
|
|
|
case HPD_PORT_D:
|
|
|
|
return PORT_D;
|
|
|
|
default:
|
|
|
|
return PORT_A; /* no hpd */
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-05-28 20:43:53 +08:00
|
|
|
/* Get a bit mask of pins that have triggered, and which ones may be long. */
|
|
|
|
static void pch_get_hpd_pins(u32 *pin_mask, u32 *long_mask,
|
|
|
|
u32 hotplug_trigger, u32 dig_hotplug_reg, const u32 hpd[HPD_NUM_PINS])
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
*pin_mask = 0;
|
|
|
|
*long_mask = 0;
|
|
|
|
|
|
|
|
if (!hotplug_trigger)
|
|
|
|
return;
|
|
|
|
|
|
|
|
for_each_hpd_pin(i) {
|
|
|
|
if (hpd[i] & hotplug_trigger) {
|
|
|
|
*pin_mask |= BIT(i);
|
|
|
|
|
|
|
|
if (pch_port_hotplug_long_detect(get_port_from_pin(i), dig_hotplug_reg))
|
|
|
|
*long_mask |= BIT(i);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x\n",
|
|
|
|
hotplug_trigger, dig_hotplug_reg, *pin_mask);
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Get a bit mask of pins that have triggered, and which ones may be long. */
|
|
|
|
static void i9xx_get_hpd_pins(u32 *pin_mask, u32 *long_mask,
|
|
|
|
u32 hotplug_trigger, const u32 hpd[HPD_NUM_PINS])
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
*pin_mask = 0;
|
|
|
|
*long_mask = 0;
|
|
|
|
|
|
|
|
if (!hotplug_trigger)
|
|
|
|
return;
|
|
|
|
|
|
|
|
for_each_hpd_pin(i) {
|
|
|
|
if (hpd[i] & hotplug_trigger) {
|
|
|
|
*pin_mask |= BIT(i);
|
|
|
|
|
|
|
|
if (i9xx_port_hotplug_long_detect(get_port_from_pin(i), hotplug_trigger))
|
|
|
|
*long_mask |= BIT(i);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, pins 0x%08x\n",
|
|
|
|
hotplug_trigger, *pin_mask);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* intel_hpd_irq_handler - main hotplug irq handler
|
|
|
|
* @dev: drm device
|
|
|
|
* @pin_mask: a mask of hpd pins that have triggered the irq
|
|
|
|
* @long_mask: a mask of hpd pins that may be long hpd pulses
|
|
|
|
*
|
|
|
|
* This is the main hotplug irq handler for all platforms. The platform specific
|
|
|
|
* irq handlers call the platform specific hotplug irq handlers, which read and
|
|
|
|
* decode the appropriate registers into bitmasks about hpd pins that have
|
|
|
|
* triggered (@pin_mask), and which of those pins may be long pulses
|
|
|
|
* (@long_mask). The @long_mask is ignored if the port corresponding to the pin
|
|
|
|
* is not a digital port.
|
|
|
|
*
|
|
|
|
* Here, we do hotplug irq storm detection and mitigation, and pass further
|
|
|
|
* processing to appropriate bottom halves.
|
|
|
|
*/
|
2015-05-12 01:49:09 +08:00
|
|
|
static void intel_hpd_irq_handler(struct drm_device *dev,
|
2015-05-28 20:43:53 +08:00
|
|
|
u32 pin_mask, u32 long_mask)
|
2013-04-16 19:36:54 +08:00
|
|
|
{
|
2014-03-31 19:27:17 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2013-04-16 19:36:54 +08:00
|
|
|
int i;
|
2014-06-18 09:29:35 +08:00
|
|
|
enum port port;
|
2013-06-27 23:52:12 +08:00
|
|
|
bool storm_detected = false;
|
2014-06-18 09:29:35 +08:00
|
|
|
bool queue_dig = false, queue_hp = false;
|
2015-05-28 20:43:52 +08:00
|
|
|
bool is_dig_port;
|
2013-04-16 19:36:54 +08:00
|
|
|
|
2015-05-28 20:43:53 +08:00
|
|
|
if (!pin_mask)
|
2013-06-27 23:52:14 +08:00
|
|
|
return;
|
|
|
|
|
2013-06-27 23:52:15 +08:00
|
|
|
spin_lock(&dev_priv->irq_lock);
|
2015-05-28 20:43:48 +08:00
|
|
|
for_each_hpd_pin(i) {
|
2015-05-28 20:43:53 +08:00
|
|
|
if (!(BIT(i) & pin_mask))
|
2014-06-18 09:29:35 +08:00
|
|
|
continue;
|
|
|
|
|
|
|
|
port = get_port_from_pin(i);
|
2015-05-28 20:43:52 +08:00
|
|
|
is_dig_port = port && dev_priv->hotplug.irq_port[port];
|
|
|
|
|
|
|
|
if (is_dig_port) {
|
2015-05-28 20:43:53 +08:00
|
|
|
bool long_hpd = long_mask & BIT(i);
|
2014-06-18 09:29:35 +08:00
|
|
|
|
2015-05-28 20:43:50 +08:00
|
|
|
DRM_DEBUG_DRIVER("digital hpd port %c - %s\n", port_name(port),
|
|
|
|
long_hpd ? "long" : "short");
|
|
|
|
/*
|
|
|
|
* For long HPD pulses we want to have the digital queue happen,
|
|
|
|
* but we still want HPD storm detection to function.
|
|
|
|
*/
|
2015-05-28 20:43:51 +08:00
|
|
|
queue_dig = true;
|
2015-05-28 20:43:50 +08:00
|
|
|
if (long_hpd) {
|
|
|
|
dev_priv->hotplug.long_port_mask |= (1 << port);
|
|
|
|
} else {
|
|
|
|
/* for short HPD just trigger the digital queue */
|
|
|
|
dev_priv->hotplug.short_port_mask |= (1 << port);
|
2015-05-28 20:43:51 +08:00
|
|
|
continue;
|
2015-05-28 20:43:50 +08:00
|
|
|
}
|
2015-05-27 20:03:41 +08:00
|
|
|
}
|
2015-05-28 20:43:49 +08:00
|
|
|
|
|
|
|
if (dev_priv->hotplug.stats[i].state == HPD_DISABLED) {
|
2014-04-24 18:03:17 +08:00
|
|
|
/*
|
|
|
|
* On GMCH platforms the interrupt mask bits only
|
|
|
|
* prevent irq generation, not the setting of the
|
|
|
|
* hotplug bits itself. So only WARN about unexpected
|
|
|
|
* interrupts on saner platforms.
|
|
|
|
*/
|
|
|
|
WARN_ONCE(INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev),
|
2015-05-28 20:43:53 +08:00
|
|
|
"Received HPD interrupt on pin %d although disabled\n", i);
|
2014-04-24 18:03:17 +08:00
|
|
|
continue;
|
|
|
|
}
|
2013-07-26 20:14:24 +08:00
|
|
|
|
2015-05-28 20:43:49 +08:00
|
|
|
if (dev_priv->hotplug.stats[i].state != HPD_ENABLED)
|
2013-04-16 19:36:54 +08:00
|
|
|
continue;
|
|
|
|
|
2015-05-28 20:43:52 +08:00
|
|
|
if (!is_dig_port) {
|
2015-05-28 20:43:53 +08:00
|
|
|
dev_priv->hotplug.event_bits |= BIT(i);
|
2014-06-18 09:29:35 +08:00
|
|
|
queue_hp = true;
|
|
|
|
}
|
|
|
|
|
2015-05-29 21:14:37 +08:00
|
|
|
if (intel_hpd_irq_storm(dev_priv, i)) {
|
2015-05-28 20:43:53 +08:00
|
|
|
dev_priv->hotplug.event_bits &= ~BIT(i);
|
2013-06-27 23:52:12 +08:00
|
|
|
storm_detected = true;
|
2013-04-16 19:36:54 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-06-27 23:52:12 +08:00
|
|
|
if (storm_detected)
|
|
|
|
dev_priv->display.hpd_irq_setup(dev);
|
2013-06-27 23:52:15 +08:00
|
|
|
spin_unlock(&dev_priv->irq_lock);
|
2013-06-27 23:52:13 +08:00
|
|
|
|
2013-09-02 22:22:25 +08:00
|
|
|
/*
|
|
|
|
* Our hotplug handler can grab modeset locks (by calling down into the
|
|
|
|
* fb helpers). Hence it must not be run on our own dev-priv->wq work
|
|
|
|
* queue for otherwise the flush_work in the pageflip code will
|
|
|
|
* deadlock.
|
|
|
|
*/
|
2014-06-18 09:29:35 +08:00
|
|
|
if (queue_dig)
|
2015-05-27 20:03:42 +08:00
|
|
|
queue_work(dev_priv->hotplug.dp_wq, &dev_priv->hotplug.dig_port_work);
|
2014-06-18 09:29:35 +08:00
|
|
|
if (queue_hp)
|
2015-05-27 20:03:42 +08:00
|
|
|
schedule_work(&dev_priv->hotplug.hotplug_work);
|
2013-04-16 19:36:54 +08:00
|
|
|
}
|
|
|
|
|
2012-12-01 20:53:44 +08:00
|
|
|
static void gmbus_irq_handler(struct drm_device *dev)
|
|
|
|
{
|
2014-03-31 19:27:17 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2012-12-01 20:53:45 +08:00
|
|
|
|
|
|
|
wake_up_all(&dev_priv->gmbus_wait_queue);
|
2012-12-01 20:53:44 +08:00
|
|
|
}
|
|
|
|
|
2012-12-01 20:53:47 +08:00
|
|
|
static void dp_aux_irq_handler(struct drm_device *dev)
|
|
|
|
{
|
2014-03-31 19:27:17 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
drm/i915: irq-drive the dp aux communication
At least on the platforms that have a dp aux irq and also have it
enabled - vlvhsw should have one, too. But I don't have a machine to
test this on. Judging from docs there's no dp aux interrupt for gm45.
Also, I only have an ivb cpu edp machine, so the dp aux A code for
snb/ilk is untested.
For dpcd probing when nothing is connected it slashes about 5ms of cpu
time (cpu time is now negligible), which agrees with 3 * 5 400 usec
timeouts.
A previous version of this patch increases the time required to go
through the dp_detect cycle (which includes reading the edid) from
around 33 ms to around 40 ms. Experiments indicated that this is
purely due to the irq latency - the hw doesn't allow us to queue up
dp aux transactions and hence irq latency directly affects throughput.
gmbus is much better, there we have a 8 byte buffer, and we get the
irq once another 4 bytes can be queued up.
But by using the pm_qos interface to request the lowest possible cpu
wake-up latency this slowdown completely disappeared.
Since all our output detection logic is single-threaded with the
mode_config mutex right now anyway, I've decide not ot play fancy and
to just reuse the gmbus wait queue. But this would definitely prep the
way to run dp detection on different ports in parallel
v2: Add a timeout for dp aux transfers when using interrupts - the hw
_does_ prevent this with the hw-based 400 usec timeout, but if the
irq somehow doesn't arrive we're screwed. Lesson learned while
developing this ;-)
v3: While at it also convert the busy-loop to wait_for_atomic, so that
we don't run the risk of an infinite loop any more.
v4: Ensure we have the smallest possible irq latency by using the
pm_qos interface.
v5: Add a comment to the code to explain why we frob pm_qos. Suggested
by Chris Wilson.
v6: Disable dp irq for vlv, that's easier than trying to get at docs
and hw.
v7: Squash in a fix for Haswell that Paulo Zanoni tracked down - the
dp aux registers aren't at a fixed offset any more, but can be on the
PCH while the DP port is on the cpu die.
Reviewed-by: Imre Deak <imre.deak@intel.com> (v6)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-12-01 20:53:48 +08:00
|
|
|
|
|
|
|
wake_up_all(&dev_priv->gmbus_wait_queue);
|
2012-12-01 20:53:47 +08:00
|
|
|
}
|
|
|
|
|
2013-10-16 01:55:27 +08:00
|
|
|
#if defined(CONFIG_DEBUG_FS)
|
2013-10-18 22:37:07 +08:00
|
|
|
static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
|
|
|
|
uint32_t crc0, uint32_t crc1,
|
|
|
|
uint32_t crc2, uint32_t crc3,
|
|
|
|
uint32_t crc4)
|
2013-10-16 01:55:27 +08:00
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
|
|
|
|
struct intel_pipe_crc_entry *entry;
|
2013-10-16 01:55:30 +08:00
|
|
|
int head, tail;
|
2013-10-16 01:55:29 +08:00
|
|
|
|
2013-10-21 21:29:30 +08:00
|
|
|
spin_lock(&pipe_crc->lock);
|
|
|
|
|
2013-10-16 01:55:37 +08:00
|
|
|
if (!pipe_crc->entries) {
|
2013-10-21 21:29:30 +08:00
|
|
|
spin_unlock(&pipe_crc->lock);
|
2014-11-26 23:29:04 +08:00
|
|
|
DRM_DEBUG_KMS("spurious interrupt\n");
|
2013-10-16 01:55:37 +08:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2013-10-21 21:29:30 +08:00
|
|
|
head = pipe_crc->head;
|
|
|
|
tail = pipe_crc->tail;
|
2013-10-16 01:55:29 +08:00
|
|
|
|
|
|
|
if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
|
2013-10-21 21:29:30 +08:00
|
|
|
spin_unlock(&pipe_crc->lock);
|
2013-10-16 01:55:29 +08:00
|
|
|
DRM_ERROR("CRC buffer overflowing\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
entry = &pipe_crc->entries[head];
|
2013-10-16 01:55:27 +08:00
|
|
|
|
2013-10-17 04:55:49 +08:00
|
|
|
entry->frame = dev->driver->get_vblank_counter(dev, pipe);
|
2013-10-17 04:55:46 +08:00
|
|
|
entry->crc[0] = crc0;
|
|
|
|
entry->crc[1] = crc1;
|
|
|
|
entry->crc[2] = crc2;
|
|
|
|
entry->crc[3] = crc3;
|
|
|
|
entry->crc[4] = crc4;
|
2013-10-16 01:55:29 +08:00
|
|
|
|
|
|
|
head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
|
2013-10-21 21:29:30 +08:00
|
|
|
pipe_crc->head = head;
|
|
|
|
|
|
|
|
spin_unlock(&pipe_crc->lock);
|
2013-10-16 01:55:40 +08:00
|
|
|
|
|
|
|
wake_up_interruptible(&pipe_crc->wq);
|
2013-10-16 01:55:27 +08:00
|
|
|
}
|
2013-10-18 22:37:07 +08:00
|
|
|
#else
|
|
|
|
static inline void
|
|
|
|
display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
|
|
|
|
uint32_t crc0, uint32_t crc1,
|
|
|
|
uint32_t crc2, uint32_t crc3,
|
|
|
|
uint32_t crc4) {}
|
|
|
|
#endif
|
|
|
|
|
2013-10-17 04:55:46 +08:00
|
|
|
|
2013-10-18 22:37:07 +08:00
|
|
|
static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
|
2013-10-17 04:55:52 +08:00
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
|
2013-10-18 22:37:07 +08:00
|
|
|
display_pipe_crc_irq_handler(dev, pipe,
|
|
|
|
I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
|
|
|
|
0, 0, 0, 0);
|
2013-10-17 04:55:52 +08:00
|
|
|
}
|
|
|
|
|
2013-10-18 22:37:07 +08:00
|
|
|
static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
|
2013-10-17 04:55:46 +08:00
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
|
2013-10-18 22:37:07 +08:00
|
|
|
display_pipe_crc_irq_handler(dev, pipe,
|
|
|
|
I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
|
|
|
|
I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
|
|
|
|
I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
|
|
|
|
I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
|
|
|
|
I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
|
2013-10-17 04:55:46 +08:00
|
|
|
}
|
2013-10-17 04:55:48 +08:00
|
|
|
|
2013-10-18 22:37:07 +08:00
|
|
|
static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
|
2013-10-17 04:55:48 +08:00
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2013-10-17 04:55:53 +08:00
|
|
|
uint32_t res1, res2;
|
|
|
|
|
|
|
|
if (INTEL_INFO(dev)->gen >= 3)
|
|
|
|
res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
|
|
|
|
else
|
|
|
|
res1 = 0;
|
|
|
|
|
|
|
|
if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
|
|
|
|
res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
|
|
|
|
else
|
|
|
|
res2 = 0;
|
2013-10-17 04:55:48 +08:00
|
|
|
|
2013-10-18 22:37:07 +08:00
|
|
|
display_pipe_crc_irq_handler(dev, pipe,
|
|
|
|
I915_READ(PIPE_CRC_RES_RED(pipe)),
|
|
|
|
I915_READ(PIPE_CRC_RES_GREEN(pipe)),
|
|
|
|
I915_READ(PIPE_CRC_RES_BLUE(pipe)),
|
|
|
|
res1, res2);
|
2013-10-17 04:55:48 +08:00
|
|
|
}
|
2013-10-16 01:55:27 +08:00
|
|
|
|
2013-08-15 22:51:32 +08:00
|
|
|
/* The RPS events need forcewake, so we add them to a work queue and mask their
|
|
|
|
* IMR bits until the work is done. Other interrupts can be processed without
|
|
|
|
* the work queue. */
|
|
|
|
static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
|
2013-05-29 10:22:24 +08:00
|
|
|
{
|
2014-03-15 22:53:22 +08:00
|
|
|
if (pm_iir & dev_priv->pm_rps_events) {
|
2013-07-05 05:35:28 +08:00
|
|
|
spin_lock(&dev_priv->irq_lock);
|
2014-07-16 15:49:40 +08:00
|
|
|
gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
|
drm/i915: sanitize rps irq disabling
When disabling the RPS interrupts there is a tricky dependency between
the thread disabling the interrupts, the RPS interrupt handler and the
corresponding RPS work. The RPS work can reenable the interrupts, so
there is no straightforward order in the disabling thread to (1) make
sure that any RPS work is flushed and to (2) disable all RPS
interrupts. Currently this is solved by masking the interrupts using two
separate mask registers (first level display IMR and PM IMR) and doing
the disabling when all first level interrupts are disabled.
This works, but the requirement to run with all first level interrupts
disabled is unnecessary making the suspend / unload time ordering of RPS
disabling wrt. other unitialization steps difficult and error prone.
Removing this restriction allows us to disable RPS early during suspend
/ unload and forget about it for the rest of the sequence. By adding a
more explicit method for avoiding the above race, it also becomes easier
to prove its correctness. Finally currently we can hit the WARN in
snb_update_pm_irq(), when a final RPS work runs with the first level
interrupts already disabled. This won't lead to any problem (due to the
separate interrupt masks), but with the change in this and the next
patch we can get rid of the WARN, while leaving it in place for other
scenarios.
To address the above points, add a new RPS interrupts_enabled flag and
use this during RPS disabling to avoid requeuing the RPS work and
reenabling of the RPS interrupts. Since the interrupt disabling happens
now in intel_suspend_gt_powersave(), we will disable RPS interrupts
explicitly during suspend (and not just through the first level mask),
but there is no problem doing so, it's also more consistent and allows
us to unify more of the RPS disabling during suspend and unload time in
the next patch.
v2/v3:
- rebase on patch "drm/i915: move rps irq disable one level up" in the
patchset
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-19 21:30:04 +08:00
|
|
|
if (dev_priv->rps.interrupts_enabled) {
|
|
|
|
dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
|
|
|
|
queue_work(dev_priv->wq, &dev_priv->rps.work);
|
|
|
|
}
|
2013-07-05 05:35:28 +08:00
|
|
|
spin_unlock(&dev_priv->irq_lock);
|
2013-05-29 10:22:24 +08:00
|
|
|
}
|
|
|
|
|
2014-11-06 02:48:37 +08:00
|
|
|
if (INTEL_INFO(dev_priv)->gen >= 8)
|
|
|
|
return;
|
|
|
|
|
2013-08-15 22:51:32 +08:00
|
|
|
if (HAS_VEBOX(dev_priv->dev)) {
|
|
|
|
if (pm_iir & PM_VEBOX_USER_INTERRUPT)
|
2015-04-07 23:21:05 +08:00
|
|
|
notify_ring(&dev_priv->ring[VECS]);
|
2013-05-29 10:22:31 +08:00
|
|
|
|
2014-11-04 22:52:22 +08:00
|
|
|
if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT)
|
|
|
|
DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir);
|
2013-05-29 10:22:31 +08:00
|
|
|
}
|
2013-05-29 10:22:24 +08:00
|
|
|
}
|
|
|
|
|
2014-04-29 18:35:46 +08:00
|
|
|
static bool intel_pipe_handle_vblank(struct drm_device *dev, enum pipe pipe)
|
|
|
|
{
|
|
|
|
if (!drm_handle_vblank(dev, pipe))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2014-02-05 03:35:46 +08:00
|
|
|
static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2014-02-11 00:42:49 +08:00
|
|
|
u32 pipe_stats[I915_MAX_PIPES] = { };
|
2014-02-05 03:35:46 +08:00
|
|
|
int pipe;
|
|
|
|
|
2014-02-05 03:35:47 +08:00
|
|
|
spin_lock(&dev_priv->irq_lock);
|
2014-08-18 20:49:10 +08:00
|
|
|
for_each_pipe(dev_priv, pipe) {
|
2014-02-11 00:42:49 +08:00
|
|
|
int reg;
|
2014-02-13 00:55:36 +08:00
|
|
|
u32 mask, iir_bit = 0;
|
2014-02-11 00:42:49 +08:00
|
|
|
|
2014-02-13 00:55:36 +08:00
|
|
|
/*
|
|
|
|
* PIPESTAT bits get signalled even when the interrupt is
|
|
|
|
* disabled with the mask bits, and some of the status bits do
|
|
|
|
* not generate interrupts at all (like the underrun bit). Hence
|
|
|
|
* we need to be careful that we only handle what we want to
|
|
|
|
* handle.
|
|
|
|
*/
|
2014-09-30 16:56:49 +08:00
|
|
|
|
|
|
|
/* fifo underruns are filterered in the underrun handler. */
|
|
|
|
mask = PIPE_FIFO_UNDERRUN_STATUS;
|
2014-02-13 00:55:36 +08:00
|
|
|
|
|
|
|
switch (pipe) {
|
|
|
|
case PIPE_A:
|
|
|
|
iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
|
|
|
|
break;
|
|
|
|
case PIPE_B:
|
|
|
|
iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
|
|
|
|
break;
|
2014-04-09 18:28:49 +08:00
|
|
|
case PIPE_C:
|
|
|
|
iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
|
|
|
|
break;
|
2014-02-13 00:55:36 +08:00
|
|
|
}
|
|
|
|
if (iir & iir_bit)
|
|
|
|
mask |= dev_priv->pipestat_irq_mask[pipe];
|
|
|
|
|
|
|
|
if (!mask)
|
2014-02-11 00:42:49 +08:00
|
|
|
continue;
|
|
|
|
|
|
|
|
reg = PIPESTAT(pipe);
|
2014-02-13 00:55:36 +08:00
|
|
|
mask |= PIPESTAT_INT_ENABLE_MASK;
|
|
|
|
pipe_stats[pipe] = I915_READ(reg) & mask;
|
2014-02-05 03:35:46 +08:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Clear the PIPE*STAT regs before the IIR
|
|
|
|
*/
|
2014-02-11 00:42:49 +08:00
|
|
|
if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
|
|
|
|
PIPESTAT_INT_STATUS_MASK))
|
2014-02-05 03:35:46 +08:00
|
|
|
I915_WRITE(reg, pipe_stats[pipe]);
|
|
|
|
}
|
2014-02-05 03:35:47 +08:00
|
|
|
spin_unlock(&dev_priv->irq_lock);
|
2014-02-05 03:35:46 +08:00
|
|
|
|
2014-08-18 20:49:10 +08:00
|
|
|
for_each_pipe(dev_priv, pipe) {
|
drm/i915: Check for a stalled page flip after each vblank
Long ago, back in the racy haydays of 915gm interrupt handling, page
flips would occasionally go astray and leave the hardware stuck, and the
display not updating. This annoyed people who relied on their systems
being able to display continuously updating information 24/7, and so
some code to detect when the driver missed the page flip completion
signal was added. Until recently, it was presumed that the interrupt
handling was now flawless, but once again Simon Farnsworth has found a
system whose display will stall. Reinstate the pageflip stall detection,
which works by checking to see if the hardware has been updated to the
new framebuffer address following each vblank. If the hardware is
scanning out from the new framebuffer, but we still think the flip is
pending, then we kick our driver into submision.
This is a continuation of the effort started with
commit 4e5359cd053bfb7d8dabe4a63624a5726848ffbc
Author: Simon Farnsworth <simon.farnsworth@onelan.co.uk>
Date: Wed Sep 1 17:47:52 2010 +0100
drm/i915: Avoid pageflipping freeze when we miss the flip prepare interrupt
This now includes a belt-and-braces approach to make sure the driver
(or the hardware) doesn't miss an interrupt and cause us to stop
updating the display should the unthinkable happen and the pageflip fail - i.e.
that the user is able to continue submitting flips.
v2: Cleanup, refactor, and rename
v3: Only start counting vblanks after the flip command has been seen by
the hardware.
v4: Record the seqno after we touch the ring, or else there may be no
seqno allocated yet.
v5: Rebase on mmio-flip.
v6: Rebase, rebase.
Reported-by: Simon Farnsworth <simon@farnz.org.uk>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75502
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> [v4]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-05 14:13:24 +08:00
|
|
|
if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
|
|
|
|
intel_pipe_handle_vblank(dev, pipe))
|
|
|
|
intel_check_page_flip(dev, pipe);
|
2014-02-05 03:35:46 +08:00
|
|
|
|
2014-02-05 03:35:48 +08:00
|
|
|
if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) {
|
2014-02-05 03:35:46 +08:00
|
|
|
intel_prepare_page_flip(dev, pipe);
|
|
|
|
intel_finish_page_flip(dev, pipe);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
|
|
|
|
i9xx_pipe_crc_irq_handler(dev, pipe);
|
|
|
|
|
2014-09-30 16:56:48 +08:00
|
|
|
if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
|
|
|
|
intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
|
2014-02-05 03:35:46 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
|
|
|
|
gmbus_irq_handler(dev);
|
|
|
|
}
|
|
|
|
|
2014-04-01 15:54:36 +08:00
|
|
|
static void i9xx_hpd_irq_handler(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
|
2015-05-28 20:43:53 +08:00
|
|
|
u32 pin_mask, long_mask;
|
2014-04-01 15:54:36 +08:00
|
|
|
|
2015-05-27 20:03:39 +08:00
|
|
|
if (!hotplug_status)
|
|
|
|
return;
|
2014-04-01 15:54:36 +08:00
|
|
|
|
2015-05-27 20:03:39 +08:00
|
|
|
I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
|
|
|
|
/*
|
|
|
|
* Make sure hotplug status is cleared before we clear IIR, or else we
|
|
|
|
* may miss hotplug events.
|
|
|
|
*/
|
|
|
|
POSTING_READ(PORT_HOTPLUG_STAT);
|
2014-04-01 15:54:36 +08:00
|
|
|
|
2015-05-27 20:03:39 +08:00
|
|
|
if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
|
|
|
|
u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
|
2014-04-01 15:54:36 +08:00
|
|
|
|
2015-05-28 20:43:53 +08:00
|
|
|
i9xx_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger, hpd_status_g4x);
|
|
|
|
intel_hpd_irq_handler(dev, pin_mask, long_mask);
|
2015-05-27 20:03:40 +08:00
|
|
|
|
|
|
|
if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
|
|
|
|
dp_aux_irq_handler(dev);
|
2015-05-27 20:03:39 +08:00
|
|
|
} else {
|
|
|
|
u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
|
2014-04-01 15:54:36 +08:00
|
|
|
|
2015-05-28 20:43:53 +08:00
|
|
|
i9xx_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger, hpd_status_i915);
|
|
|
|
intel_hpd_irq_handler(dev, pin_mask, long_mask);
|
2014-06-16 23:10:58 +08:00
|
|
|
}
|
2014-04-01 15:54:36 +08:00
|
|
|
}
|
|
|
|
|
2012-10-02 21:10:55 +08:00
|
|
|
static irqreturn_t valleyview_irq_handler(int irq, void *arg)
|
2012-03-29 04:39:38 +08:00
|
|
|
{
|
2014-05-13 01:17:55 +08:00
|
|
|
struct drm_device *dev = arg;
|
2014-03-31 19:27:17 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2012-03-29 04:39:38 +08:00
|
|
|
u32 iir, gt_iir, pm_iir;
|
|
|
|
irqreturn_t ret = IRQ_NONE;
|
|
|
|
|
2015-02-24 17:14:30 +08:00
|
|
|
if (!intel_irqs_enabled(dev_priv))
|
|
|
|
return IRQ_NONE;
|
|
|
|
|
2012-03-29 04:39:38 +08:00
|
|
|
while (true) {
|
2014-06-16 23:10:58 +08:00
|
|
|
/* Find, clear, then process each source of interrupt */
|
|
|
|
|
2012-03-29 04:39:38 +08:00
|
|
|
gt_iir = I915_READ(GTIIR);
|
2014-06-16 23:10:58 +08:00
|
|
|
if (gt_iir)
|
|
|
|
I915_WRITE(GTIIR, gt_iir);
|
|
|
|
|
2012-03-29 04:39:38 +08:00
|
|
|
pm_iir = I915_READ(GEN6_PMIIR);
|
2014-06-16 23:10:58 +08:00
|
|
|
if (pm_iir)
|
|
|
|
I915_WRITE(GEN6_PMIIR, pm_iir);
|
|
|
|
|
|
|
|
iir = I915_READ(VLV_IIR);
|
|
|
|
if (iir) {
|
|
|
|
/* Consume port before clearing IIR or we'll miss events */
|
|
|
|
if (iir & I915_DISPLAY_PORT_INTERRUPT)
|
|
|
|
i9xx_hpd_irq_handler(dev);
|
|
|
|
I915_WRITE(VLV_IIR, iir);
|
|
|
|
}
|
2012-03-29 04:39:38 +08:00
|
|
|
|
|
|
|
if (gt_iir == 0 && pm_iir == 0 && iir == 0)
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
ret = IRQ_HANDLED;
|
|
|
|
|
2014-06-16 23:10:58 +08:00
|
|
|
if (gt_iir)
|
|
|
|
snb_gt_irq_handler(dev, dev_priv, gt_iir);
|
2013-08-15 22:50:01 +08:00
|
|
|
if (pm_iir)
|
2013-07-05 05:35:25 +08:00
|
|
|
gen6_rps_irq_handler(dev_priv, pm_iir);
|
2014-06-16 23:10:58 +08:00
|
|
|
/* Call regardless, as some status bits might not be
|
|
|
|
* signalled in iir */
|
|
|
|
valleyview_pipestat_irq_handler(dev, iir);
|
2012-03-29 04:39:38 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
out:
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2014-04-10 01:40:52 +08:00
|
|
|
static irqreturn_t cherryview_irq_handler(int irq, void *arg)
|
|
|
|
{
|
2014-05-13 01:17:55 +08:00
|
|
|
struct drm_device *dev = arg;
|
2014-04-10 01:40:52 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
u32 master_ctl, iir;
|
|
|
|
irqreturn_t ret = IRQ_NONE;
|
|
|
|
|
2015-02-24 17:14:30 +08:00
|
|
|
if (!intel_irqs_enabled(dev_priv))
|
|
|
|
return IRQ_NONE;
|
|
|
|
|
2014-04-09 18:28:50 +08:00
|
|
|
for (;;) {
|
|
|
|
master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
|
|
|
|
iir = I915_READ(VLV_IIR);
|
2014-04-10 01:40:52 +08:00
|
|
|
|
2014-04-09 18:28:50 +08:00
|
|
|
if (master_ctl == 0 && iir == 0)
|
|
|
|
break;
|
2014-04-10 01:40:52 +08:00
|
|
|
|
2014-06-16 23:11:00 +08:00
|
|
|
ret = IRQ_HANDLED;
|
|
|
|
|
2014-04-09 18:28:50 +08:00
|
|
|
I915_WRITE(GEN8_MASTER_IRQ, 0);
|
2014-04-10 01:40:52 +08:00
|
|
|
|
2014-06-16 23:11:00 +08:00
|
|
|
/* Find, clear, then process each source of interrupt */
|
2014-04-10 01:40:52 +08:00
|
|
|
|
2014-06-16 23:11:00 +08:00
|
|
|
if (iir) {
|
|
|
|
/* Consume port before clearing IIR or we'll miss events */
|
|
|
|
if (iir & I915_DISPLAY_PORT_INTERRUPT)
|
|
|
|
i9xx_hpd_irq_handler(dev);
|
|
|
|
I915_WRITE(VLV_IIR, iir);
|
|
|
|
}
|
2014-04-10 01:40:52 +08:00
|
|
|
|
2015-04-07 23:21:05 +08:00
|
|
|
gen8_gt_irq_handler(dev_priv, master_ctl);
|
2014-04-10 01:40:52 +08:00
|
|
|
|
2014-06-16 23:11:00 +08:00
|
|
|
/* Call regardless, as some status bits might not be
|
|
|
|
* signalled in iir */
|
|
|
|
valleyview_pipestat_irq_handler(dev, iir);
|
2014-04-10 01:40:52 +08:00
|
|
|
|
2014-04-09 18:28:50 +08:00
|
|
|
I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
|
|
|
|
POSTING_READ(GEN8_MASTER_IRQ);
|
|
|
|
}
|
2014-04-09 18:28:49 +08:00
|
|
|
|
2014-04-10 01:40:52 +08:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2012-06-07 03:45:44 +08:00
|
|
|
static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
|
2011-01-05 07:09:39 +08:00
|
|
|
{
|
2014-03-31 19:27:17 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2011-02-08 04:26:52 +08:00
|
|
|
int pipe;
|
2013-04-16 19:36:54 +08:00
|
|
|
u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
|
2014-06-18 09:29:35 +08:00
|
|
|
u32 dig_hotplug_reg;
|
2015-05-28 20:43:53 +08:00
|
|
|
u32 pin_mask, long_mask;
|
2014-06-18 09:29:35 +08:00
|
|
|
|
|
|
|
dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
|
|
|
|
I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
|
2011-01-05 07:09:39 +08:00
|
|
|
|
2015-05-28 20:43:53 +08:00
|
|
|
pch_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger, dig_hotplug_reg, hpd_ibx);
|
|
|
|
intel_hpd_irq_handler(dev, pin_mask, long_mask);
|
2013-06-27 23:52:14 +08:00
|
|
|
|
2013-04-17 22:48:48 +08:00
|
|
|
if (pch_iir & SDE_AUDIO_POWER_MASK) {
|
|
|
|
int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
|
|
|
|
SDE_AUDIO_POWER_SHIFT);
|
2011-01-05 07:09:39 +08:00
|
|
|
DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
|
2013-04-17 22:48:48 +08:00
|
|
|
port_name(port));
|
|
|
|
}
|
2011-01-05 07:09:39 +08:00
|
|
|
|
2012-12-01 20:53:47 +08:00
|
|
|
if (pch_iir & SDE_AUX_MASK)
|
|
|
|
dp_aux_irq_handler(dev);
|
|
|
|
|
2011-01-05 07:09:39 +08:00
|
|
|
if (pch_iir & SDE_GMBUS)
|
2012-12-01 20:53:44 +08:00
|
|
|
gmbus_irq_handler(dev);
|
2011-01-05 07:09:39 +08:00
|
|
|
|
|
|
|
if (pch_iir & SDE_AUDIO_HDCP_MASK)
|
|
|
|
DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
|
|
|
|
|
|
|
|
if (pch_iir & SDE_AUDIO_TRANS_MASK)
|
|
|
|
DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
|
|
|
|
|
|
|
|
if (pch_iir & SDE_POISON)
|
|
|
|
DRM_ERROR("PCH poison interrupt\n");
|
|
|
|
|
2011-02-08 04:26:52 +08:00
|
|
|
if (pch_iir & SDE_FDI_MASK)
|
2014-08-18 20:49:10 +08:00
|
|
|
for_each_pipe(dev_priv, pipe)
|
2011-02-08 04:26:52 +08:00
|
|
|
DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
|
|
|
|
pipe_name(pipe),
|
|
|
|
I915_READ(FDI_RX_IIR(pipe)));
|
2011-01-05 07:09:39 +08:00
|
|
|
|
|
|
|
if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
|
|
|
|
DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
|
|
|
|
|
|
|
|
if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
|
|
|
|
DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
|
|
|
|
|
|
|
|
if (pch_iir & SDE_TRANSA_FIFO_UNDER)
|
2014-09-30 16:56:48 +08:00
|
|
|
intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
|
drm/i915: report Gen5+ CPU and PCH FIFO underruns
In this commit we enable both CPU and PCH FIFO underrun reporting and
start reporting them. We follow a few rules:
- after we receive one of these errors, we mask the interrupt, so
we won't get an "interrupt storm" and we also won't flood dmesg;
- at each mode set we enable the interrupts again, so we'll see each
message at most once per mode set;
- in the specific places where we need to ignore the errors, we
completely mask the interrupts.
The downside of this patch is that since we're completely disabling
(masking) the interrupts instead of just not printing error messages,
we will mask more than just what we want on IVB/HSW CPU interrupts
(due to GEN7_ERR_INT) and on CPT/PPT/LPT PCHs (due to SERR_INT). So
when we decide to mask PCH FIFO underruns for pipe A on CPT, we'll
also be masking PCH FIFO underruns for pipe B, because both are
reported by SERR_INT, which has to be either completely enabled or
completely disabled (in othe words, there's no way to disable/enable
specific bits of GEN7_ERR_INT and SERR_INT).
V2: Rename some functions and variables, downgrade messages to
DRM_DEBUG_DRIVER and rebase.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-13 04:57:57 +08:00
|
|
|
|
|
|
|
if (pch_iir & SDE_TRANSB_FIFO_UNDER)
|
2014-09-30 16:56:48 +08:00
|
|
|
intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
|
drm/i915: report Gen5+ CPU and PCH FIFO underruns
In this commit we enable both CPU and PCH FIFO underrun reporting and
start reporting them. We follow a few rules:
- after we receive one of these errors, we mask the interrupt, so
we won't get an "interrupt storm" and we also won't flood dmesg;
- at each mode set we enable the interrupts again, so we'll see each
message at most once per mode set;
- in the specific places where we need to ignore the errors, we
completely mask the interrupts.
The downside of this patch is that since we're completely disabling
(masking) the interrupts instead of just not printing error messages,
we will mask more than just what we want on IVB/HSW CPU interrupts
(due to GEN7_ERR_INT) and on CPT/PPT/LPT PCHs (due to SERR_INT). So
when we decide to mask PCH FIFO underruns for pipe A on CPT, we'll
also be masking PCH FIFO underruns for pipe B, because both are
reported by SERR_INT, which has to be either completely enabled or
completely disabled (in othe words, there's no way to disable/enable
specific bits of GEN7_ERR_INT and SERR_INT).
V2: Rename some functions and variables, downgrade messages to
DRM_DEBUG_DRIVER and rebase.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-13 04:57:57 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static void ivb_err_int_handler(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
u32 err_int = I915_READ(GEN7_ERR_INT);
|
2013-10-17 04:55:52 +08:00
|
|
|
enum pipe pipe;
|
drm/i915: report Gen5+ CPU and PCH FIFO underruns
In this commit we enable both CPU and PCH FIFO underrun reporting and
start reporting them. We follow a few rules:
- after we receive one of these errors, we mask the interrupt, so
we won't get an "interrupt storm" and we also won't flood dmesg;
- at each mode set we enable the interrupts again, so we'll see each
message at most once per mode set;
- in the specific places where we need to ignore the errors, we
completely mask the interrupts.
The downside of this patch is that since we're completely disabling
(masking) the interrupts instead of just not printing error messages,
we will mask more than just what we want on IVB/HSW CPU interrupts
(due to GEN7_ERR_INT) and on CPT/PPT/LPT PCHs (due to SERR_INT). So
when we decide to mask PCH FIFO underruns for pipe A on CPT, we'll
also be masking PCH FIFO underruns for pipe B, because both are
reported by SERR_INT, which has to be either completely enabled or
completely disabled (in othe words, there's no way to disable/enable
specific bits of GEN7_ERR_INT and SERR_INT).
V2: Rename some functions and variables, downgrade messages to
DRM_DEBUG_DRIVER and rebase.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-13 04:57:57 +08:00
|
|
|
|
2013-04-13 04:57:58 +08:00
|
|
|
if (err_int & ERR_INT_POISON)
|
|
|
|
DRM_ERROR("Poison interrupt\n");
|
|
|
|
|
2014-08-18 20:49:10 +08:00
|
|
|
for_each_pipe(dev_priv, pipe) {
|
2014-09-30 16:56:48 +08:00
|
|
|
if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
|
|
|
|
intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
|
2013-10-16 01:55:27 +08:00
|
|
|
|
2013-10-17 04:55:52 +08:00
|
|
|
if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
|
|
|
|
if (IS_IVYBRIDGE(dev))
|
2013-10-18 22:37:07 +08:00
|
|
|
ivb_pipe_crc_irq_handler(dev, pipe);
|
2013-10-17 04:55:52 +08:00
|
|
|
else
|
2013-10-18 22:37:07 +08:00
|
|
|
hsw_pipe_crc_irq_handler(dev, pipe);
|
2013-10-17 04:55:52 +08:00
|
|
|
}
|
|
|
|
}
|
2013-10-16 01:55:27 +08:00
|
|
|
|
drm/i915: report Gen5+ CPU and PCH FIFO underruns
In this commit we enable both CPU and PCH FIFO underrun reporting and
start reporting them. We follow a few rules:
- after we receive one of these errors, we mask the interrupt, so
we won't get an "interrupt storm" and we also won't flood dmesg;
- at each mode set we enable the interrupts again, so we'll see each
message at most once per mode set;
- in the specific places where we need to ignore the errors, we
completely mask the interrupts.
The downside of this patch is that since we're completely disabling
(masking) the interrupts instead of just not printing error messages,
we will mask more than just what we want on IVB/HSW CPU interrupts
(due to GEN7_ERR_INT) and on CPT/PPT/LPT PCHs (due to SERR_INT). So
when we decide to mask PCH FIFO underruns for pipe A on CPT, we'll
also be masking PCH FIFO underruns for pipe B, because both are
reported by SERR_INT, which has to be either completely enabled or
completely disabled (in othe words, there's no way to disable/enable
specific bits of GEN7_ERR_INT and SERR_INT).
V2: Rename some functions and variables, downgrade messages to
DRM_DEBUG_DRIVER and rebase.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-13 04:57:57 +08:00
|
|
|
I915_WRITE(GEN7_ERR_INT, err_int);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void cpt_serr_int_handler(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
u32 serr_int = I915_READ(SERR_INT);
|
|
|
|
|
2013-04-13 04:57:58 +08:00
|
|
|
if (serr_int & SERR_INT_POISON)
|
|
|
|
DRM_ERROR("PCH poison interrupt\n");
|
|
|
|
|
drm/i915: report Gen5+ CPU and PCH FIFO underruns
In this commit we enable both CPU and PCH FIFO underrun reporting and
start reporting them. We follow a few rules:
- after we receive one of these errors, we mask the interrupt, so
we won't get an "interrupt storm" and we also won't flood dmesg;
- at each mode set we enable the interrupts again, so we'll see each
message at most once per mode set;
- in the specific places where we need to ignore the errors, we
completely mask the interrupts.
The downside of this patch is that since we're completely disabling
(masking) the interrupts instead of just not printing error messages,
we will mask more than just what we want on IVB/HSW CPU interrupts
(due to GEN7_ERR_INT) and on CPT/PPT/LPT PCHs (due to SERR_INT). So
when we decide to mask PCH FIFO underruns for pipe A on CPT, we'll
also be masking PCH FIFO underruns for pipe B, because both are
reported by SERR_INT, which has to be either completely enabled or
completely disabled (in othe words, there's no way to disable/enable
specific bits of GEN7_ERR_INT and SERR_INT).
V2: Rename some functions and variables, downgrade messages to
DRM_DEBUG_DRIVER and rebase.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-13 04:57:57 +08:00
|
|
|
if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
|
2014-09-30 16:56:48 +08:00
|
|
|
intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
|
drm/i915: report Gen5+ CPU and PCH FIFO underruns
In this commit we enable both CPU and PCH FIFO underrun reporting and
start reporting them. We follow a few rules:
- after we receive one of these errors, we mask the interrupt, so
we won't get an "interrupt storm" and we also won't flood dmesg;
- at each mode set we enable the interrupts again, so we'll see each
message at most once per mode set;
- in the specific places where we need to ignore the errors, we
completely mask the interrupts.
The downside of this patch is that since we're completely disabling
(masking) the interrupts instead of just not printing error messages,
we will mask more than just what we want on IVB/HSW CPU interrupts
(due to GEN7_ERR_INT) and on CPT/PPT/LPT PCHs (due to SERR_INT). So
when we decide to mask PCH FIFO underruns for pipe A on CPT, we'll
also be masking PCH FIFO underruns for pipe B, because both are
reported by SERR_INT, which has to be either completely enabled or
completely disabled (in othe words, there's no way to disable/enable
specific bits of GEN7_ERR_INT and SERR_INT).
V2: Rename some functions and variables, downgrade messages to
DRM_DEBUG_DRIVER and rebase.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-13 04:57:57 +08:00
|
|
|
|
|
|
|
if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
|
2014-09-30 16:56:48 +08:00
|
|
|
intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
|
drm/i915: report Gen5+ CPU and PCH FIFO underruns
In this commit we enable both CPU and PCH FIFO underrun reporting and
start reporting them. We follow a few rules:
- after we receive one of these errors, we mask the interrupt, so
we won't get an "interrupt storm" and we also won't flood dmesg;
- at each mode set we enable the interrupts again, so we'll see each
message at most once per mode set;
- in the specific places where we need to ignore the errors, we
completely mask the interrupts.
The downside of this patch is that since we're completely disabling
(masking) the interrupts instead of just not printing error messages,
we will mask more than just what we want on IVB/HSW CPU interrupts
(due to GEN7_ERR_INT) and on CPT/PPT/LPT PCHs (due to SERR_INT). So
when we decide to mask PCH FIFO underruns for pipe A on CPT, we'll
also be masking PCH FIFO underruns for pipe B, because both are
reported by SERR_INT, which has to be either completely enabled or
completely disabled (in othe words, there's no way to disable/enable
specific bits of GEN7_ERR_INT and SERR_INT).
V2: Rename some functions and variables, downgrade messages to
DRM_DEBUG_DRIVER and rebase.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-13 04:57:57 +08:00
|
|
|
|
|
|
|
if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
|
2014-09-30 16:56:48 +08:00
|
|
|
intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C);
|
drm/i915: report Gen5+ CPU and PCH FIFO underruns
In this commit we enable both CPU and PCH FIFO underrun reporting and
start reporting them. We follow a few rules:
- after we receive one of these errors, we mask the interrupt, so
we won't get an "interrupt storm" and we also won't flood dmesg;
- at each mode set we enable the interrupts again, so we'll see each
message at most once per mode set;
- in the specific places where we need to ignore the errors, we
completely mask the interrupts.
The downside of this patch is that since we're completely disabling
(masking) the interrupts instead of just not printing error messages,
we will mask more than just what we want on IVB/HSW CPU interrupts
(due to GEN7_ERR_INT) and on CPT/PPT/LPT PCHs (due to SERR_INT). So
when we decide to mask PCH FIFO underruns for pipe A on CPT, we'll
also be masking PCH FIFO underruns for pipe B, because both are
reported by SERR_INT, which has to be either completely enabled or
completely disabled (in othe words, there's no way to disable/enable
specific bits of GEN7_ERR_INT and SERR_INT).
V2: Rename some functions and variables, downgrade messages to
DRM_DEBUG_DRIVER and rebase.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-13 04:57:57 +08:00
|
|
|
|
|
|
|
I915_WRITE(SERR_INT, serr_int);
|
2011-01-05 07:09:39 +08:00
|
|
|
}
|
|
|
|
|
2012-06-07 03:45:44 +08:00
|
|
|
static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
|
|
|
|
{
|
2014-03-31 19:27:17 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2012-06-07 03:45:44 +08:00
|
|
|
int pipe;
|
2013-04-16 19:36:54 +08:00
|
|
|
u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
|
2014-06-18 09:29:35 +08:00
|
|
|
u32 dig_hotplug_reg;
|
2015-05-28 20:43:53 +08:00
|
|
|
u32 pin_mask, long_mask;
|
2014-06-18 09:29:35 +08:00
|
|
|
|
|
|
|
dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
|
|
|
|
I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
|
2012-06-07 03:45:44 +08:00
|
|
|
|
2015-05-28 20:43:53 +08:00
|
|
|
pch_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger, dig_hotplug_reg, hpd_cpt);
|
|
|
|
intel_hpd_irq_handler(dev, pin_mask, long_mask);
|
2013-06-27 23:52:14 +08:00
|
|
|
|
2013-04-17 22:48:48 +08:00
|
|
|
if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
|
|
|
|
int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
|
|
|
|
SDE_AUDIO_POWER_SHIFT_CPT);
|
|
|
|
DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
|
|
|
|
port_name(port));
|
|
|
|
}
|
2012-06-07 03:45:44 +08:00
|
|
|
|
|
|
|
if (pch_iir & SDE_AUX_MASK_CPT)
|
2012-12-01 20:53:47 +08:00
|
|
|
dp_aux_irq_handler(dev);
|
2012-06-07 03:45:44 +08:00
|
|
|
|
|
|
|
if (pch_iir & SDE_GMBUS_CPT)
|
2012-12-01 20:53:44 +08:00
|
|
|
gmbus_irq_handler(dev);
|
2012-06-07 03:45:44 +08:00
|
|
|
|
|
|
|
if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
|
|
|
|
DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
|
|
|
|
|
|
|
|
if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
|
|
|
|
DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
|
|
|
|
|
|
|
|
if (pch_iir & SDE_FDI_MASK_CPT)
|
2014-08-18 20:49:10 +08:00
|
|
|
for_each_pipe(dev_priv, pipe)
|
2012-06-07 03:45:44 +08:00
|
|
|
DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
|
|
|
|
pipe_name(pipe),
|
|
|
|
I915_READ(FDI_RX_IIR(pipe)));
|
drm/i915: report Gen5+ CPU and PCH FIFO underruns
In this commit we enable both CPU and PCH FIFO underrun reporting and
start reporting them. We follow a few rules:
- after we receive one of these errors, we mask the interrupt, so
we won't get an "interrupt storm" and we also won't flood dmesg;
- at each mode set we enable the interrupts again, so we'll see each
message at most once per mode set;
- in the specific places where we need to ignore the errors, we
completely mask the interrupts.
The downside of this patch is that since we're completely disabling
(masking) the interrupts instead of just not printing error messages,
we will mask more than just what we want on IVB/HSW CPU interrupts
(due to GEN7_ERR_INT) and on CPT/PPT/LPT PCHs (due to SERR_INT). So
when we decide to mask PCH FIFO underruns for pipe A on CPT, we'll
also be masking PCH FIFO underruns for pipe B, because both are
reported by SERR_INT, which has to be either completely enabled or
completely disabled (in othe words, there's no way to disable/enable
specific bits of GEN7_ERR_INT and SERR_INT).
V2: Rename some functions and variables, downgrade messages to
DRM_DEBUG_DRIVER and rebase.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-13 04:57:57 +08:00
|
|
|
|
|
|
|
if (pch_iir & SDE_ERROR_CPT)
|
|
|
|
cpt_serr_int_handler(dev);
|
2012-06-07 03:45:44 +08:00
|
|
|
}
|
|
|
|
|
2013-07-13 03:35:10 +08:00
|
|
|
static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2013-10-22 00:04:36 +08:00
|
|
|
enum pipe pipe;
|
2013-07-13 03:35:10 +08:00
|
|
|
|
|
|
|
if (de_iir & DE_AUX_CHANNEL_A)
|
|
|
|
dp_aux_irq_handler(dev);
|
|
|
|
|
|
|
|
if (de_iir & DE_GSE)
|
|
|
|
intel_opregion_asle_intr(dev);
|
|
|
|
|
|
|
|
if (de_iir & DE_POISON)
|
|
|
|
DRM_ERROR("Poison interrupt\n");
|
|
|
|
|
2014-08-18 20:49:10 +08:00
|
|
|
for_each_pipe(dev_priv, pipe) {
|
drm/i915: Check for a stalled page flip after each vblank
Long ago, back in the racy haydays of 915gm interrupt handling, page
flips would occasionally go astray and leave the hardware stuck, and the
display not updating. This annoyed people who relied on their systems
being able to display continuously updating information 24/7, and so
some code to detect when the driver missed the page flip completion
signal was added. Until recently, it was presumed that the interrupt
handling was now flawless, but once again Simon Farnsworth has found a
system whose display will stall. Reinstate the pageflip stall detection,
which works by checking to see if the hardware has been updated to the
new framebuffer address following each vblank. If the hardware is
scanning out from the new framebuffer, but we still think the flip is
pending, then we kick our driver into submision.
This is a continuation of the effort started with
commit 4e5359cd053bfb7d8dabe4a63624a5726848ffbc
Author: Simon Farnsworth <simon.farnsworth@onelan.co.uk>
Date: Wed Sep 1 17:47:52 2010 +0100
drm/i915: Avoid pageflipping freeze when we miss the flip prepare interrupt
This now includes a belt-and-braces approach to make sure the driver
(or the hardware) doesn't miss an interrupt and cause us to stop
updating the display should the unthinkable happen and the pageflip fail - i.e.
that the user is able to continue submitting flips.
v2: Cleanup, refactor, and rename
v3: Only start counting vblanks after the flip command has been seen by
the hardware.
v4: Record the seqno after we touch the ring, or else there may be no
seqno allocated yet.
v5: Rebase on mmio-flip.
v6: Rebase, rebase.
Reported-by: Simon Farnsworth <simon@farnz.org.uk>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75502
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> [v4]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-05 14:13:24 +08:00
|
|
|
if (de_iir & DE_PIPE_VBLANK(pipe) &&
|
|
|
|
intel_pipe_handle_vblank(dev, pipe))
|
|
|
|
intel_check_page_flip(dev, pipe);
|
2013-10-17 04:55:48 +08:00
|
|
|
|
2013-10-22 00:04:36 +08:00
|
|
|
if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
|
2014-09-30 16:56:48 +08:00
|
|
|
intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
|
2013-10-17 04:55:48 +08:00
|
|
|
|
2013-10-22 00:04:36 +08:00
|
|
|
if (de_iir & DE_PIPE_CRC_DONE(pipe))
|
|
|
|
i9xx_pipe_crc_irq_handler(dev, pipe);
|
2013-07-13 03:35:10 +08:00
|
|
|
|
2013-10-22 00:04:36 +08:00
|
|
|
/* plane/pipes map 1:1 on ilk+ */
|
|
|
|
if (de_iir & DE_PLANE_FLIP_DONE(pipe)) {
|
|
|
|
intel_prepare_page_flip(dev, pipe);
|
|
|
|
intel_finish_page_flip_plane(dev, pipe);
|
|
|
|
}
|
2013-07-13 03:35:10 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/* check event from PCH */
|
|
|
|
if (de_iir & DE_PCH_EVENT) {
|
|
|
|
u32 pch_iir = I915_READ(SDEIIR);
|
|
|
|
|
|
|
|
if (HAS_PCH_CPT(dev))
|
|
|
|
cpt_irq_handler(dev, pch_iir);
|
|
|
|
else
|
|
|
|
ibx_irq_handler(dev, pch_iir);
|
|
|
|
|
|
|
|
/* should clear PCH hotplug event before clear CPU irq */
|
|
|
|
I915_WRITE(SDEIIR, pch_iir);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
|
|
|
|
ironlake_rps_change_irq_handler(dev);
|
|
|
|
}
|
|
|
|
|
2013-07-13 03:35:11 +08:00
|
|
|
static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2014-03-04 01:31:46 +08:00
|
|
|
enum pipe pipe;
|
2013-07-13 03:35:11 +08:00
|
|
|
|
|
|
|
if (de_iir & DE_ERR_INT_IVB)
|
|
|
|
ivb_err_int_handler(dev);
|
|
|
|
|
|
|
|
if (de_iir & DE_AUX_CHANNEL_A_IVB)
|
|
|
|
dp_aux_irq_handler(dev);
|
|
|
|
|
|
|
|
if (de_iir & DE_GSE_IVB)
|
|
|
|
intel_opregion_asle_intr(dev);
|
|
|
|
|
2014-08-18 20:49:10 +08:00
|
|
|
for_each_pipe(dev_priv, pipe) {
|
drm/i915: Check for a stalled page flip after each vblank
Long ago, back in the racy haydays of 915gm interrupt handling, page
flips would occasionally go astray and leave the hardware stuck, and the
display not updating. This annoyed people who relied on their systems
being able to display continuously updating information 24/7, and so
some code to detect when the driver missed the page flip completion
signal was added. Until recently, it was presumed that the interrupt
handling was now flawless, but once again Simon Farnsworth has found a
system whose display will stall. Reinstate the pageflip stall detection,
which works by checking to see if the hardware has been updated to the
new framebuffer address following each vblank. If the hardware is
scanning out from the new framebuffer, but we still think the flip is
pending, then we kick our driver into submision.
This is a continuation of the effort started with
commit 4e5359cd053bfb7d8dabe4a63624a5726848ffbc
Author: Simon Farnsworth <simon.farnsworth@onelan.co.uk>
Date: Wed Sep 1 17:47:52 2010 +0100
drm/i915: Avoid pageflipping freeze when we miss the flip prepare interrupt
This now includes a belt-and-braces approach to make sure the driver
(or the hardware) doesn't miss an interrupt and cause us to stop
updating the display should the unthinkable happen and the pageflip fail - i.e.
that the user is able to continue submitting flips.
v2: Cleanup, refactor, and rename
v3: Only start counting vblanks after the flip command has been seen by
the hardware.
v4: Record the seqno after we touch the ring, or else there may be no
seqno allocated yet.
v5: Rebase on mmio-flip.
v6: Rebase, rebase.
Reported-by: Simon Farnsworth <simon@farnz.org.uk>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75502
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> [v4]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-05 14:13:24 +08:00
|
|
|
if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) &&
|
|
|
|
intel_pipe_handle_vblank(dev, pipe))
|
|
|
|
intel_check_page_flip(dev, pipe);
|
2013-10-22 00:04:36 +08:00
|
|
|
|
|
|
|
/* plane/pipes map 1:1 on ilk+ */
|
2014-03-04 01:31:46 +08:00
|
|
|
if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) {
|
|
|
|
intel_prepare_page_flip(dev, pipe);
|
|
|
|
intel_finish_page_flip_plane(dev, pipe);
|
2013-07-13 03:35:11 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* check event from PCH */
|
|
|
|
if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
|
|
|
|
u32 pch_iir = I915_READ(SDEIIR);
|
|
|
|
|
|
|
|
cpt_irq_handler(dev, pch_iir);
|
|
|
|
|
|
|
|
/* clear PCH hotplug event before clear CPU irq */
|
|
|
|
I915_WRITE(SDEIIR, pch_iir);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-06-16 23:10:57 +08:00
|
|
|
/*
|
|
|
|
* To handle irqs with the minimum potential races with fresh interrupts, we:
|
|
|
|
* 1 - Disable Master Interrupt Control.
|
|
|
|
* 2 - Find the source(s) of the interrupt.
|
|
|
|
* 3 - Clear the Interrupt Identity bits (IIR).
|
|
|
|
* 4 - Process the interrupt(s) that had bits set in the IIRs.
|
|
|
|
* 5 - Re-enable Master Interrupt Control.
|
|
|
|
*/
|
2013-07-13 06:56:30 +08:00
|
|
|
static irqreturn_t ironlake_irq_handler(int irq, void *arg)
|
2011-04-07 03:13:38 +08:00
|
|
|
{
|
2014-05-13 01:17:55 +08:00
|
|
|
struct drm_device *dev = arg;
|
2014-03-31 19:27:17 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2013-07-13 06:56:30 +08:00
|
|
|
u32 de_iir, gt_iir, de_ier, sde_ier = 0;
|
2012-05-10 04:45:44 +08:00
|
|
|
irqreturn_t ret = IRQ_NONE;
|
2011-04-07 03:13:38 +08:00
|
|
|
|
2015-02-24 17:14:30 +08:00
|
|
|
if (!intel_irqs_enabled(dev_priv))
|
|
|
|
return IRQ_NONE;
|
|
|
|
|
drm/i915: report Gen5+ CPU and PCH FIFO underruns
In this commit we enable both CPU and PCH FIFO underrun reporting and
start reporting them. We follow a few rules:
- after we receive one of these errors, we mask the interrupt, so
we won't get an "interrupt storm" and we also won't flood dmesg;
- at each mode set we enable the interrupts again, so we'll see each
message at most once per mode set;
- in the specific places where we need to ignore the errors, we
completely mask the interrupts.
The downside of this patch is that since we're completely disabling
(masking) the interrupts instead of just not printing error messages,
we will mask more than just what we want on IVB/HSW CPU interrupts
(due to GEN7_ERR_INT) and on CPT/PPT/LPT PCHs (due to SERR_INT). So
when we decide to mask PCH FIFO underruns for pipe A on CPT, we'll
also be masking PCH FIFO underruns for pipe B, because both are
reported by SERR_INT, which has to be either completely enabled or
completely disabled (in othe words, there's no way to disable/enable
specific bits of GEN7_ERR_INT and SERR_INT).
V2: Rename some functions and variables, downgrade messages to
DRM_DEBUG_DRIVER and rebase.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-13 04:57:57 +08:00
|
|
|
/* We get interrupts on unclaimed registers, so check for this before we
|
|
|
|
* do any I915_{READ,WRITE}. */
|
2013-07-20 03:36:52 +08:00
|
|
|
intel_uncore_check_errors(dev);
|
drm/i915: report Gen5+ CPU and PCH FIFO underruns
In this commit we enable both CPU and PCH FIFO underrun reporting and
start reporting them. We follow a few rules:
- after we receive one of these errors, we mask the interrupt, so
we won't get an "interrupt storm" and we also won't flood dmesg;
- at each mode set we enable the interrupts again, so we'll see each
message at most once per mode set;
- in the specific places where we need to ignore the errors, we
completely mask the interrupts.
The downside of this patch is that since we're completely disabling
(masking) the interrupts instead of just not printing error messages,
we will mask more than just what we want on IVB/HSW CPU interrupts
(due to GEN7_ERR_INT) and on CPT/PPT/LPT PCHs (due to SERR_INT). So
when we decide to mask PCH FIFO underruns for pipe A on CPT, we'll
also be masking PCH FIFO underruns for pipe B, because both are
reported by SERR_INT, which has to be either completely enabled or
completely disabled (in othe words, there's no way to disable/enable
specific bits of GEN7_ERR_INT and SERR_INT).
V2: Rename some functions and variables, downgrade messages to
DRM_DEBUG_DRIVER and rebase.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-13 04:57:57 +08:00
|
|
|
|
2011-04-07 03:13:38 +08:00
|
|
|
/* disable master interrupt before clearing iir */
|
|
|
|
de_ier = I915_READ(DEIER);
|
|
|
|
I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
|
2013-07-13 03:35:14 +08:00
|
|
|
POSTING_READ(DEIER);
|
2011-04-07 03:13:38 +08:00
|
|
|
|
drm/i915: also disable south interrupts when handling them
From the docs:
"IIR can queue up to two interrupt events. When the IIR is cleared,
it will set itself again after one clock if a second event was
stored."
"Only the rising edge of the PCH Display interrupt will cause the
North Display IIR (DEIIR) PCH Display Interrupt even bit to be set,
so all PCH Display Interrupts, including back to back interrupts,
must be cleared before a new PCH Display interrupt can cause DEIIR
to be set".
The current code works fine because we don't get many interrupts, but
if we enable the PCH FIFO underrun interrupts we'll start getting so
many interrupts that at some point new PCH interrupts won't cause
DEIIR to be set.
The initial implementation I tried was to turn the code that checks
SDEIIR into a loop, but we can still get interrupts even after the
loop is done (and before the irq handler finishes), so we have to
either disable the interrupts or mask them. In the end I concluded
that just disabling the PCH interrupts is enough, you don't even need
the loop, so this is what this patch implements. I've tested it and it
passes the 2 "PCH FIFO underrun interrupt storms" I can reproduce:
the "ironlake_crtc_disable" case and the "wrong watermarks" case.
In other words, here's how to reproduce the problem fixed by this
patch:
1 - Enable PCH FIFO underrun interrupts (SERR_INT on SNB+)
2 - Boot the machine
3 - While booting we'll get tons of PCH FIFO underrun interrupts
4 - Plug a new monitor
5 - Run xrandr, notice it won't detect the new monitor
6 - Read SDEIIR and notice it's not 0 while DEIIR is 0
Q: Can't we just clear DEIIR before SDEIIR?
A: It doesn't work. SDEIIR has to be completely cleared (including the
interrupts stored on its back queue) before it can flip DEIIR's bit to
1 again, and even while you're clearing it you'll be getting more and
more interrupts.
Q: Why does it work by just disabling+enabling the south interrupts?
A: Because when we re-enable them, if there's something on the SDEIIR
register (maybe an interrupt stored on the queue), the re-enabling
will make DEIIR's bit flip to 1, and since we'll already have
interrupts enabled we'll get another interrupt, then run our irq
handler again to process the "back" interrupts.
v2: Even bigger commit message, added code comments.
Note that this fixes missed dp aux irqs which have been reported for
3.9-rc1. This regression has been introduced by switching to
irq-driven dp aux transactions with
commit 9ee32fea5fe810ec06af3a15e4c65478de56d4f5
Author: Daniel Vetter <daniel.vetter@ffwll.ch>
Date: Sat Dec 1 13:53:48 2012 +0100
drm/i915: irq-drive the dp aux communication
References: http://www.mail-archive.com/intel-gfx@lists.freedesktop.org/msg18588.html
References: https://lkml.org/lkml/2013/2/26/769
Tested-by: Imre Deak <imre.deak@intel.com>
Reported-by: Sedat Dilek <sedat.dilek@gmail.com>
Reported-by: Linus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: Pimp commit message with references for the dp aux irq
timeout regression this fixes.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-02-23 04:05:28 +08:00
|
|
|
/* Disable south interrupts. We'll only write to SDEIIR once, so further
|
|
|
|
* interrupts will will be stored on its back queue, and then we'll be
|
|
|
|
* able to process them after we restore SDEIER (as soon as we restore
|
|
|
|
* it, we'll get an interrupt if SDEIIR still has something to process
|
|
|
|
* due to its back queue). */
|
2013-04-06 04:12:41 +08:00
|
|
|
if (!HAS_PCH_NOP(dev)) {
|
|
|
|
sde_ier = I915_READ(SDEIER);
|
|
|
|
I915_WRITE(SDEIER, 0);
|
|
|
|
POSTING_READ(SDEIER);
|
|
|
|
}
|
drm/i915: also disable south interrupts when handling them
From the docs:
"IIR can queue up to two interrupt events. When the IIR is cleared,
it will set itself again after one clock if a second event was
stored."
"Only the rising edge of the PCH Display interrupt will cause the
North Display IIR (DEIIR) PCH Display Interrupt even bit to be set,
so all PCH Display Interrupts, including back to back interrupts,
must be cleared before a new PCH Display interrupt can cause DEIIR
to be set".
The current code works fine because we don't get many interrupts, but
if we enable the PCH FIFO underrun interrupts we'll start getting so
many interrupts that at some point new PCH interrupts won't cause
DEIIR to be set.
The initial implementation I tried was to turn the code that checks
SDEIIR into a loop, but we can still get interrupts even after the
loop is done (and before the irq handler finishes), so we have to
either disable the interrupts or mask them. In the end I concluded
that just disabling the PCH interrupts is enough, you don't even need
the loop, so this is what this patch implements. I've tested it and it
passes the 2 "PCH FIFO underrun interrupt storms" I can reproduce:
the "ironlake_crtc_disable" case and the "wrong watermarks" case.
In other words, here's how to reproduce the problem fixed by this
patch:
1 - Enable PCH FIFO underrun interrupts (SERR_INT on SNB+)
2 - Boot the machine
3 - While booting we'll get tons of PCH FIFO underrun interrupts
4 - Plug a new monitor
5 - Run xrandr, notice it won't detect the new monitor
6 - Read SDEIIR and notice it's not 0 while DEIIR is 0
Q: Can't we just clear DEIIR before SDEIIR?
A: It doesn't work. SDEIIR has to be completely cleared (including the
interrupts stored on its back queue) before it can flip DEIIR's bit to
1 again, and even while you're clearing it you'll be getting more and
more interrupts.
Q: Why does it work by just disabling+enabling the south interrupts?
A: Because when we re-enable them, if there's something on the SDEIIR
register (maybe an interrupt stored on the queue), the re-enabling
will make DEIIR's bit flip to 1, and since we'll already have
interrupts enabled we'll get another interrupt, then run our irq
handler again to process the "back" interrupts.
v2: Even bigger commit message, added code comments.
Note that this fixes missed dp aux irqs which have been reported for
3.9-rc1. This regression has been introduced by switching to
irq-driven dp aux transactions with
commit 9ee32fea5fe810ec06af3a15e4c65478de56d4f5
Author: Daniel Vetter <daniel.vetter@ffwll.ch>
Date: Sat Dec 1 13:53:48 2012 +0100
drm/i915: irq-drive the dp aux communication
References: http://www.mail-archive.com/intel-gfx@lists.freedesktop.org/msg18588.html
References: https://lkml.org/lkml/2013/2/26/769
Tested-by: Imre Deak <imre.deak@intel.com>
Reported-by: Sedat Dilek <sedat.dilek@gmail.com>
Reported-by: Linus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: Pimp commit message with references for the dp aux irq
timeout regression this fixes.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-02-23 04:05:28 +08:00
|
|
|
|
2014-06-16 23:10:57 +08:00
|
|
|
/* Find, clear, then process each source of interrupt */
|
|
|
|
|
2011-04-07 03:13:38 +08:00
|
|
|
gt_iir = I915_READ(GTIIR);
|
2012-05-10 04:45:44 +08:00
|
|
|
if (gt_iir) {
|
2014-06-16 23:10:57 +08:00
|
|
|
I915_WRITE(GTIIR, gt_iir);
|
|
|
|
ret = IRQ_HANDLED;
|
2013-07-20 05:57:55 +08:00
|
|
|
if (INTEL_INFO(dev)->gen >= 6)
|
2013-07-13 06:56:30 +08:00
|
|
|
snb_gt_irq_handler(dev, dev_priv, gt_iir);
|
2013-07-20 05:57:55 +08:00
|
|
|
else
|
|
|
|
ilk_gt_irq_handler(dev, dev_priv, gt_iir);
|
2011-04-07 03:13:38 +08:00
|
|
|
}
|
|
|
|
|
2012-05-10 04:45:44 +08:00
|
|
|
de_iir = I915_READ(DEIIR);
|
|
|
|
if (de_iir) {
|
2014-06-16 23:10:57 +08:00
|
|
|
I915_WRITE(DEIIR, de_iir);
|
|
|
|
ret = IRQ_HANDLED;
|
2013-07-13 06:56:30 +08:00
|
|
|
if (INTEL_INFO(dev)->gen >= 7)
|
|
|
|
ivb_display_irq_handler(dev, de_iir);
|
|
|
|
else
|
|
|
|
ilk_display_irq_handler(dev, de_iir);
|
2011-04-07 03:13:38 +08:00
|
|
|
}
|
|
|
|
|
2013-07-13 06:56:30 +08:00
|
|
|
if (INTEL_INFO(dev)->gen >= 6) {
|
|
|
|
u32 pm_iir = I915_READ(GEN6_PMIIR);
|
|
|
|
if (pm_iir) {
|
|
|
|
I915_WRITE(GEN6_PMIIR, pm_iir);
|
|
|
|
ret = IRQ_HANDLED;
|
2014-06-16 23:10:57 +08:00
|
|
|
gen6_rps_irq_handler(dev_priv, pm_iir);
|
2013-07-13 06:56:30 +08:00
|
|
|
}
|
2012-05-10 04:45:44 +08:00
|
|
|
}
|
2011-04-07 03:13:38 +08:00
|
|
|
|
|
|
|
I915_WRITE(DEIER, de_ier);
|
|
|
|
POSTING_READ(DEIER);
|
2013-04-06 04:12:41 +08:00
|
|
|
if (!HAS_PCH_NOP(dev)) {
|
|
|
|
I915_WRITE(SDEIER, sde_ier);
|
|
|
|
POSTING_READ(SDEIER);
|
|
|
|
}
|
2011-04-07 03:13:38 +08:00
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2014-08-22 20:10:41 +08:00
|
|
|
static void bxt_hpd_handler(struct drm_device *dev, uint32_t iir_status)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2015-05-28 20:43:53 +08:00
|
|
|
u32 hp_control, hp_trigger;
|
|
|
|
u32 pin_mask, long_mask;
|
2014-08-22 20:10:41 +08:00
|
|
|
|
|
|
|
/* Get the status */
|
|
|
|
hp_trigger = iir_status & BXT_DE_PORT_HOTPLUG_MASK;
|
|
|
|
hp_control = I915_READ(BXT_HOTPLUG_CTL);
|
|
|
|
|
|
|
|
/* Hotplug not enabled ? */
|
|
|
|
if (!(hp_control & BXT_HOTPLUG_CTL_MASK)) {
|
|
|
|
DRM_ERROR("Interrupt when HPD disabled\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2015-05-28 20:43:54 +08:00
|
|
|
/* Clear sticky bits in hpd status */
|
|
|
|
I915_WRITE(BXT_HOTPLUG_CTL, hp_control);
|
2014-08-22 20:10:41 +08:00
|
|
|
|
2015-05-28 20:43:53 +08:00
|
|
|
pch_get_hpd_pins(&pin_mask, &long_mask, hp_trigger, hp_control, hpd_bxt);
|
|
|
|
intel_hpd_irq_handler(dev, pin_mask, long_mask);
|
2014-08-22 20:10:41 +08:00
|
|
|
}
|
|
|
|
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 12:07:09 +08:00
|
|
|
static irqreturn_t gen8_irq_handler(int irq, void *arg)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = arg;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
u32 master_ctl;
|
|
|
|
irqreturn_t ret = IRQ_NONE;
|
|
|
|
uint32_t tmp = 0;
|
2013-11-07 18:05:40 +08:00
|
|
|
enum pipe pipe;
|
2014-11-14 01:51:48 +08:00
|
|
|
u32 aux_mask = GEN8_AUX_CHANNEL_A;
|
|
|
|
|
2015-02-24 17:14:30 +08:00
|
|
|
if (!intel_irqs_enabled(dev_priv))
|
|
|
|
return IRQ_NONE;
|
|
|
|
|
2014-11-14 01:51:48 +08:00
|
|
|
if (IS_GEN9(dev))
|
|
|
|
aux_mask |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
|
|
|
|
GEN9_AUX_CHANNEL_D;
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 12:07:09 +08:00
|
|
|
|
2015-04-07 23:21:04 +08:00
|
|
|
master_ctl = I915_READ_FW(GEN8_MASTER_IRQ);
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 12:07:09 +08:00
|
|
|
master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
|
|
|
|
if (!master_ctl)
|
|
|
|
return IRQ_NONE;
|
|
|
|
|
2015-04-07 23:21:04 +08:00
|
|
|
I915_WRITE_FW(GEN8_MASTER_IRQ, 0);
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 12:07:09 +08:00
|
|
|
|
2014-06-16 23:10:59 +08:00
|
|
|
/* Find, clear, then process each source of interrupt */
|
|
|
|
|
2015-04-07 23:21:05 +08:00
|
|
|
ret = gen8_gt_irq_handler(dev_priv, master_ctl);
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 12:07:09 +08:00
|
|
|
|
|
|
|
if (master_ctl & GEN8_DE_MISC_IRQ) {
|
|
|
|
tmp = I915_READ(GEN8_DE_MISC_IIR);
|
|
|
|
if (tmp) {
|
|
|
|
I915_WRITE(GEN8_DE_MISC_IIR, tmp);
|
|
|
|
ret = IRQ_HANDLED;
|
2014-06-16 23:10:59 +08:00
|
|
|
if (tmp & GEN8_DE_MISC_GSE)
|
|
|
|
intel_opregion_asle_intr(dev);
|
|
|
|
else
|
|
|
|
DRM_ERROR("Unexpected DE Misc interrupt\n");
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 12:07:09 +08:00
|
|
|
}
|
2014-06-16 23:10:59 +08:00
|
|
|
else
|
|
|
|
DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 12:07:09 +08:00
|
|
|
}
|
|
|
|
|
2013-11-07 21:49:55 +08:00
|
|
|
if (master_ctl & GEN8_DE_PORT_IRQ) {
|
|
|
|
tmp = I915_READ(GEN8_DE_PORT_IIR);
|
|
|
|
if (tmp) {
|
2014-08-22 20:10:41 +08:00
|
|
|
bool found = false;
|
|
|
|
|
2013-11-07 21:49:55 +08:00
|
|
|
I915_WRITE(GEN8_DE_PORT_IIR, tmp);
|
|
|
|
ret = IRQ_HANDLED;
|
2014-11-14 01:51:48 +08:00
|
|
|
|
2014-08-22 20:10:41 +08:00
|
|
|
if (tmp & aux_mask) {
|
2014-06-16 23:10:59 +08:00
|
|
|
dp_aux_irq_handler(dev);
|
2014-08-22 20:10:41 +08:00
|
|
|
found = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (IS_BROXTON(dev) && tmp & BXT_DE_PORT_HOTPLUG_MASK) {
|
|
|
|
bxt_hpd_handler(dev, tmp);
|
|
|
|
found = true;
|
|
|
|
}
|
|
|
|
|
2014-08-22 20:10:43 +08:00
|
|
|
if (IS_BROXTON(dev) && (tmp & BXT_DE_PORT_GMBUS)) {
|
|
|
|
gmbus_irq_handler(dev);
|
|
|
|
found = true;
|
|
|
|
}
|
|
|
|
|
2014-08-22 20:10:41 +08:00
|
|
|
if (!found)
|
2014-06-16 23:10:59 +08:00
|
|
|
DRM_ERROR("Unexpected DE Port interrupt\n");
|
2013-11-07 21:49:55 +08:00
|
|
|
}
|
2014-06-16 23:10:59 +08:00
|
|
|
else
|
|
|
|
DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
|
2013-11-07 21:49:55 +08:00
|
|
|
}
|
|
|
|
|
2014-08-18 20:49:10 +08:00
|
|
|
for_each_pipe(dev_priv, pipe) {
|
2014-03-21 04:45:01 +08:00
|
|
|
uint32_t pipe_iir, flip_done = 0, fault_errors = 0;
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 12:07:09 +08:00
|
|
|
|
2013-11-07 18:05:40 +08:00
|
|
|
if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
|
|
|
|
continue;
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 12:07:09 +08:00
|
|
|
|
2013-11-07 18:05:40 +08:00
|
|
|
pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
|
|
|
|
if (pipe_iir) {
|
|
|
|
ret = IRQ_HANDLED;
|
|
|
|
I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
|
2014-03-21 04:45:01 +08:00
|
|
|
|
drm/i915: Check for a stalled page flip after each vblank
Long ago, back in the racy haydays of 915gm interrupt handling, page
flips would occasionally go astray and leave the hardware stuck, and the
display not updating. This annoyed people who relied on their systems
being able to display continuously updating information 24/7, and so
some code to detect when the driver missed the page flip completion
signal was added. Until recently, it was presumed that the interrupt
handling was now flawless, but once again Simon Farnsworth has found a
system whose display will stall. Reinstate the pageflip stall detection,
which works by checking to see if the hardware has been updated to the
new framebuffer address following each vblank. If the hardware is
scanning out from the new framebuffer, but we still think the flip is
pending, then we kick our driver into submision.
This is a continuation of the effort started with
commit 4e5359cd053bfb7d8dabe4a63624a5726848ffbc
Author: Simon Farnsworth <simon.farnsworth@onelan.co.uk>
Date: Wed Sep 1 17:47:52 2010 +0100
drm/i915: Avoid pageflipping freeze when we miss the flip prepare interrupt
This now includes a belt-and-braces approach to make sure the driver
(or the hardware) doesn't miss an interrupt and cause us to stop
updating the display should the unthinkable happen and the pageflip fail - i.e.
that the user is able to continue submitting flips.
v2: Cleanup, refactor, and rename
v3: Only start counting vblanks after the flip command has been seen by
the hardware.
v4: Record the seqno after we touch the ring, or else there may be no
seqno allocated yet.
v5: Rebase on mmio-flip.
v6: Rebase, rebase.
Reported-by: Simon Farnsworth <simon@farnz.org.uk>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75502
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> [v4]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-05 14:13:24 +08:00
|
|
|
if (pipe_iir & GEN8_PIPE_VBLANK &&
|
|
|
|
intel_pipe_handle_vblank(dev, pipe))
|
|
|
|
intel_check_page_flip(dev, pipe);
|
2014-06-16 23:10:59 +08:00
|
|
|
|
2014-03-21 04:45:01 +08:00
|
|
|
if (IS_GEN9(dev))
|
|
|
|
flip_done = pipe_iir & GEN9_PIPE_PLANE1_FLIP_DONE;
|
|
|
|
else
|
|
|
|
flip_done = pipe_iir & GEN8_PIPE_PRIMARY_FLIP_DONE;
|
|
|
|
|
|
|
|
if (flip_done) {
|
2014-06-16 23:10:59 +08:00
|
|
|
intel_prepare_page_flip(dev, pipe);
|
|
|
|
intel_finish_page_flip_plane(dev, pipe);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE)
|
|
|
|
hsw_pipe_crc_irq_handler(dev, pipe);
|
|
|
|
|
2014-09-30 16:56:48 +08:00
|
|
|
if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN)
|
|
|
|
intel_cpu_fifo_underrun_irq_handler(dev_priv,
|
|
|
|
pipe);
|
2014-06-16 23:10:59 +08:00
|
|
|
|
2014-03-21 04:45:01 +08:00
|
|
|
|
|
|
|
if (IS_GEN9(dev))
|
|
|
|
fault_errors = pipe_iir & GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
|
|
|
|
else
|
|
|
|
fault_errors = pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
|
|
|
|
|
|
|
|
if (fault_errors)
|
2014-06-16 23:10:59 +08:00
|
|
|
DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
|
|
|
|
pipe_name(pipe),
|
|
|
|
pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS);
|
2013-11-07 18:05:40 +08:00
|
|
|
} else
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 12:07:09 +08:00
|
|
|
DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
|
|
|
|
}
|
|
|
|
|
2014-08-22 20:10:42 +08:00
|
|
|
if (HAS_PCH_SPLIT(dev) && !HAS_PCH_NOP(dev) &&
|
|
|
|
master_ctl & GEN8_DE_PCH_IRQ) {
|
2013-11-07 18:05:43 +08:00
|
|
|
/*
|
|
|
|
* FIXME(BDW): Assume for now that the new interrupt handling
|
|
|
|
* scheme also closed the SDE interrupt handling race we've seen
|
|
|
|
* on older pch-split platforms. But this needs testing.
|
|
|
|
*/
|
|
|
|
u32 pch_iir = I915_READ(SDEIIR);
|
|
|
|
if (pch_iir) {
|
|
|
|
I915_WRITE(SDEIIR, pch_iir);
|
|
|
|
ret = IRQ_HANDLED;
|
2014-06-16 23:10:59 +08:00
|
|
|
cpt_irq_handler(dev, pch_iir);
|
|
|
|
} else
|
|
|
|
DRM_ERROR("The master control interrupt lied (SDE)!\n");
|
|
|
|
|
2013-11-07 18:05:43 +08:00
|
|
|
}
|
|
|
|
|
2015-04-07 23:21:04 +08:00
|
|
|
I915_WRITE_FW(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
|
|
|
|
POSTING_READ_FW(GEN8_MASTER_IRQ);
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 12:07:09 +08:00
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2013-09-09 03:57:13 +08:00
|
|
|
static void i915_error_wake_up(struct drm_i915_private *dev_priv,
|
|
|
|
bool reset_completed)
|
|
|
|
{
|
2014-05-22 21:13:33 +08:00
|
|
|
struct intel_engine_cs *ring;
|
2013-09-09 03:57:13 +08:00
|
|
|
int i;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Notify all waiters for GPU completion events that reset state has
|
|
|
|
* been changed, and that they need to restart their wait after
|
|
|
|
* checking for potential errors (and bail out to drop locks if there is
|
|
|
|
* a gpu reset pending so that i915_error_work_func can acquire them).
|
|
|
|
*/
|
|
|
|
|
|
|
|
/* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
|
|
|
|
for_each_ring(ring, dev_priv, i)
|
|
|
|
wake_up_all(&ring->irq_queue);
|
|
|
|
|
|
|
|
/* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
|
|
|
|
wake_up_all(&dev_priv->pending_flip_queue);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Signal tasks blocked in i915_gem_wait_for_error that the pending
|
|
|
|
* reset state is cleared.
|
|
|
|
*/
|
|
|
|
if (reset_completed)
|
|
|
|
wake_up_all(&dev_priv->gpu_error.reset_queue);
|
|
|
|
}
|
|
|
|
|
2009-07-12 04:48:03 +08:00
|
|
|
/**
|
2015-01-28 23:03:14 +08:00
|
|
|
* i915_reset_and_wakeup - do process context error handling work
|
2009-07-12 04:48:03 +08:00
|
|
|
*
|
|
|
|
* Fire an error uevent so userspace can see that a hang or error
|
|
|
|
* was detected.
|
|
|
|
*/
|
2015-01-28 23:03:14 +08:00
|
|
|
static void i915_reset_and_wakeup(struct drm_device *dev)
|
2009-07-12 04:48:03 +08:00
|
|
|
{
|
2015-01-28 23:03:14 +08:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
|
struct i915_gpu_error *error = &dev_priv->gpu_error;
|
2013-07-20 00:16:42 +08:00
|
|
|
char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
|
|
|
|
char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
|
|
|
|
char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
|
2013-09-09 03:57:13 +08:00
|
|
|
int ret;
|
2009-07-12 04:48:03 +08:00
|
|
|
|
2013-10-11 12:07:25 +08:00
|
|
|
kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event);
|
2009-09-15 05:48:46 +08:00
|
|
|
|
2012-12-06 23:23:37 +08:00
|
|
|
/*
|
|
|
|
* Note that there's only one work item which does gpu resets, so we
|
|
|
|
* need not worry about concurrent gpu resets potentially incrementing
|
|
|
|
* error->reset_counter twice. We only need to take care of another
|
|
|
|
* racing irq/hangcheck declaring the gpu dead for a second time. A
|
|
|
|
* quick check for that is good enough: schedule_work ensures the
|
|
|
|
* correct ordering between hang detection and this work item, and since
|
|
|
|
* the reset in-progress bit is only ever set by code outside of this
|
|
|
|
* work we don't need to worry about any other races.
|
|
|
|
*/
|
|
|
|
if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
|
2010-09-19 19:38:26 +08:00
|
|
|
DRM_DEBUG_DRIVER("resetting chip\n");
|
2013-10-11 12:07:25 +08:00
|
|
|
kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE,
|
2012-12-06 23:23:37 +08:00
|
|
|
reset_event);
|
2012-11-16 00:17:22 +08:00
|
|
|
|
2014-04-23 06:09:04 +08:00
|
|
|
/*
|
|
|
|
* In most cases it's guaranteed that we get here with an RPM
|
|
|
|
* reference held, for example because there is a pending GPU
|
|
|
|
* request that won't finish until the reset is done. This
|
|
|
|
* isn't the case at least when we get here by doing a
|
|
|
|
* simulated reset via debugs, so get an RPM reference.
|
|
|
|
*/
|
|
|
|
intel_runtime_pm_get(dev_priv);
|
2014-11-25 00:28:11 +08:00
|
|
|
|
|
|
|
intel_prepare_reset(dev);
|
|
|
|
|
2013-09-09 03:57:13 +08:00
|
|
|
/*
|
|
|
|
* All state reset _must_ be completed before we update the
|
|
|
|
* reset counter, for otherwise waiters might miss the reset
|
|
|
|
* pending state and not properly drop locks, resulting in
|
|
|
|
* deadlocks with the reset work.
|
|
|
|
*/
|
drm/i915: create a race-free reset detection
With the previous patch the state transition handling of the reset
code itself is now (hopefully) race free and solid. But that still
leaves out everyone else - with the various lock-free wait paths
we have there's the possibility that the reset happens between the
point where we read the seqno we should wait on and the actual wait.
And if __wait_seqno then never sees the RESET_IN_PROGRESS state, we'll
happily wait for a seqno which will in all likelyhood never signal.
In practice this is not a big problem since the X server gets
constantly interrupted, and can then submit more work (hopefully) to
unblock everyone else: As soon as a new seqno write lands, all waiters
will unblock. But running the i-g-t reset testcase ZZ_hangman can
expose this race, especially on slower hw with fewer cpu cores.
Now looking forward to ARB_robustness and friends that's not the best
possible behaviour, hence this patch adds a reset_counter to be able
to detect any reset, even if a given thread never observed the
in-progress state.
The important part is to correctly order things:
- The write side needs to increment the counter after any seqno gets
reset. Hence we need to do that at the end of the reset work, and
again wake everyone up. We also need to place a barrier in between
any possible seqno changes and the counter increment, since any
unlock operations only guarantee that nothing leaks out, but not
that at later load operation gets moved ahead.
- On the read side we need to ensure that no reset can sneak in and
invalidate the seqno. In all cases we can use the one-sided barrier
that unlock operations guarantee (of the lock protecting the
respective seqno/ring pair) to ensure correct ordering. Hence it is
sufficient to place the atomic read before the mutex/spin_unlock and
no additional barriers are required.
The end-result of all this is that we need to wake up everyone twice
in a reset operation:
- First, before the reset starts, to get any lockholders of the locks,
so that the reset can proceed.
- Second, after the reset is completed, to allow waiters to properly
and reliably detect the reset condition and bail out.
I admit that this entire reset_counter thing smells a bit like
overkill, but I think it's justified since it makes it really explicit
what the bail-out condition is. And we need a reset counter anyway to
implement ARB_robustness, and imo with finer-grained locking on the
horizont this is the most resilient scheme I could think of.
v2: Drop spurious change in the wait_for_error EXIT_COND - we only
need to wait until we leave the reset-in-progress wedged state.
v3: Don't play tricks with barriers in the throttle ioctl, the
spin_unlock is barrier enough.
I've also considered using a little helper to grab the current
reset_counter, but then decided that hiding the atomic_read isn't a
great idea, since having it explicitly show up in the code is a nice
remainder to reviews to check the memory barriers.
v4: Add a comment to explain why we need to fall through in
__wait_seqno in the end variable assignments.
v5: Review from Damien:
- s/smb/smp/ in a comment
- don't increment the reset counter after we've set it to WEDGED. Now
we (again) properly wedge the gpu when the reset fails.
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-12-06 16:01:42 +08:00
|
|
|
ret = i915_reset(dev);
|
|
|
|
|
2014-11-25 00:28:11 +08:00
|
|
|
intel_finish_reset(dev);
|
2013-09-09 03:57:13 +08:00
|
|
|
|
2014-04-23 06:09:04 +08:00
|
|
|
intel_runtime_pm_put(dev_priv);
|
|
|
|
|
drm/i915: create a race-free reset detection
With the previous patch the state transition handling of the reset
code itself is now (hopefully) race free and solid. But that still
leaves out everyone else - with the various lock-free wait paths
we have there's the possibility that the reset happens between the
point where we read the seqno we should wait on and the actual wait.
And if __wait_seqno then never sees the RESET_IN_PROGRESS state, we'll
happily wait for a seqno which will in all likelyhood never signal.
In practice this is not a big problem since the X server gets
constantly interrupted, and can then submit more work (hopefully) to
unblock everyone else: As soon as a new seqno write lands, all waiters
will unblock. But running the i-g-t reset testcase ZZ_hangman can
expose this race, especially on slower hw with fewer cpu cores.
Now looking forward to ARB_robustness and friends that's not the best
possible behaviour, hence this patch adds a reset_counter to be able
to detect any reset, even if a given thread never observed the
in-progress state.
The important part is to correctly order things:
- The write side needs to increment the counter after any seqno gets
reset. Hence we need to do that at the end of the reset work, and
again wake everyone up. We also need to place a barrier in between
any possible seqno changes and the counter increment, since any
unlock operations only guarantee that nothing leaks out, but not
that at later load operation gets moved ahead.
- On the read side we need to ensure that no reset can sneak in and
invalidate the seqno. In all cases we can use the one-sided barrier
that unlock operations guarantee (of the lock protecting the
respective seqno/ring pair) to ensure correct ordering. Hence it is
sufficient to place the atomic read before the mutex/spin_unlock and
no additional barriers are required.
The end-result of all this is that we need to wake up everyone twice
in a reset operation:
- First, before the reset starts, to get any lockholders of the locks,
so that the reset can proceed.
- Second, after the reset is completed, to allow waiters to properly
and reliably detect the reset condition and bail out.
I admit that this entire reset_counter thing smells a bit like
overkill, but I think it's justified since it makes it really explicit
what the bail-out condition is. And we need a reset counter anyway to
implement ARB_robustness, and imo with finer-grained locking on the
horizont this is the most resilient scheme I could think of.
v2: Drop spurious change in the wait_for_error EXIT_COND - we only
need to wait until we leave the reset-in-progress wedged state.
v3: Don't play tricks with barriers in the throttle ioctl, the
spin_unlock is barrier enough.
I've also considered using a little helper to grab the current
reset_counter, but then decided that hiding the atomic_read isn't a
great idea, since having it explicitly show up in the code is a nice
remainder to reviews to check the memory barriers.
v4: Add a comment to explain why we need to fall through in
__wait_seqno in the end variable assignments.
v5: Review from Damien:
- s/smb/smp/ in a comment
- don't increment the reset counter after we've set it to WEDGED. Now
we (again) properly wedge the gpu when the reset fails.
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-12-06 16:01:42 +08:00
|
|
|
if (ret == 0) {
|
|
|
|
/*
|
|
|
|
* After all the gem state is reset, increment the reset
|
|
|
|
* counter and wake up everyone waiting for the reset to
|
|
|
|
* complete.
|
|
|
|
*
|
|
|
|
* Since unlock operations are a one-sided barrier only,
|
|
|
|
* we need to insert a barrier here to order any seqno
|
|
|
|
* updates before
|
|
|
|
* the counter increment.
|
|
|
|
*/
|
2014-03-18 01:06:10 +08:00
|
|
|
smp_mb__before_atomic();
|
drm/i915: create a race-free reset detection
With the previous patch the state transition handling of the reset
code itself is now (hopefully) race free and solid. But that still
leaves out everyone else - with the various lock-free wait paths
we have there's the possibility that the reset happens between the
point where we read the seqno we should wait on and the actual wait.
And if __wait_seqno then never sees the RESET_IN_PROGRESS state, we'll
happily wait for a seqno which will in all likelyhood never signal.
In practice this is not a big problem since the X server gets
constantly interrupted, and can then submit more work (hopefully) to
unblock everyone else: As soon as a new seqno write lands, all waiters
will unblock. But running the i-g-t reset testcase ZZ_hangman can
expose this race, especially on slower hw with fewer cpu cores.
Now looking forward to ARB_robustness and friends that's not the best
possible behaviour, hence this patch adds a reset_counter to be able
to detect any reset, even if a given thread never observed the
in-progress state.
The important part is to correctly order things:
- The write side needs to increment the counter after any seqno gets
reset. Hence we need to do that at the end of the reset work, and
again wake everyone up. We also need to place a barrier in between
any possible seqno changes and the counter increment, since any
unlock operations only guarantee that nothing leaks out, but not
that at later load operation gets moved ahead.
- On the read side we need to ensure that no reset can sneak in and
invalidate the seqno. In all cases we can use the one-sided barrier
that unlock operations guarantee (of the lock protecting the
respective seqno/ring pair) to ensure correct ordering. Hence it is
sufficient to place the atomic read before the mutex/spin_unlock and
no additional barriers are required.
The end-result of all this is that we need to wake up everyone twice
in a reset operation:
- First, before the reset starts, to get any lockholders of the locks,
so that the reset can proceed.
- Second, after the reset is completed, to allow waiters to properly
and reliably detect the reset condition and bail out.
I admit that this entire reset_counter thing smells a bit like
overkill, but I think it's justified since it makes it really explicit
what the bail-out condition is. And we need a reset counter anyway to
implement ARB_robustness, and imo with finer-grained locking on the
horizont this is the most resilient scheme I could think of.
v2: Drop spurious change in the wait_for_error EXIT_COND - we only
need to wait until we leave the reset-in-progress wedged state.
v3: Don't play tricks with barriers in the throttle ioctl, the
spin_unlock is barrier enough.
I've also considered using a little helper to grab the current
reset_counter, but then decided that hiding the atomic_read isn't a
great idea, since having it explicitly show up in the code is a nice
remainder to reviews to check the memory barriers.
v4: Add a comment to explain why we need to fall through in
__wait_seqno in the end variable assignments.
v5: Review from Damien:
- s/smb/smp/ in a comment
- don't increment the reset counter after we've set it to WEDGED. Now
we (again) properly wedge the gpu when the reset fails.
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-12-06 16:01:42 +08:00
|
|
|
atomic_inc(&dev_priv->gpu_error.reset_counter);
|
|
|
|
|
2013-10-11 12:07:25 +08:00
|
|
|
kobject_uevent_env(&dev->primary->kdev->kobj,
|
drm/i915: create a race-free reset detection
With the previous patch the state transition handling of the reset
code itself is now (hopefully) race free and solid. But that still
leaves out everyone else - with the various lock-free wait paths
we have there's the possibility that the reset happens between the
point where we read the seqno we should wait on and the actual wait.
And if __wait_seqno then never sees the RESET_IN_PROGRESS state, we'll
happily wait for a seqno which will in all likelyhood never signal.
In practice this is not a big problem since the X server gets
constantly interrupted, and can then submit more work (hopefully) to
unblock everyone else: As soon as a new seqno write lands, all waiters
will unblock. But running the i-g-t reset testcase ZZ_hangman can
expose this race, especially on slower hw with fewer cpu cores.
Now looking forward to ARB_robustness and friends that's not the best
possible behaviour, hence this patch adds a reset_counter to be able
to detect any reset, even if a given thread never observed the
in-progress state.
The important part is to correctly order things:
- The write side needs to increment the counter after any seqno gets
reset. Hence we need to do that at the end of the reset work, and
again wake everyone up. We also need to place a barrier in between
any possible seqno changes and the counter increment, since any
unlock operations only guarantee that nothing leaks out, but not
that at later load operation gets moved ahead.
- On the read side we need to ensure that no reset can sneak in and
invalidate the seqno. In all cases we can use the one-sided barrier
that unlock operations guarantee (of the lock protecting the
respective seqno/ring pair) to ensure correct ordering. Hence it is
sufficient to place the atomic read before the mutex/spin_unlock and
no additional barriers are required.
The end-result of all this is that we need to wake up everyone twice
in a reset operation:
- First, before the reset starts, to get any lockholders of the locks,
so that the reset can proceed.
- Second, after the reset is completed, to allow waiters to properly
and reliably detect the reset condition and bail out.
I admit that this entire reset_counter thing smells a bit like
overkill, but I think it's justified since it makes it really explicit
what the bail-out condition is. And we need a reset counter anyway to
implement ARB_robustness, and imo with finer-grained locking on the
horizont this is the most resilient scheme I could think of.
v2: Drop spurious change in the wait_for_error EXIT_COND - we only
need to wait until we leave the reset-in-progress wedged state.
v3: Don't play tricks with barriers in the throttle ioctl, the
spin_unlock is barrier enough.
I've also considered using a little helper to grab the current
reset_counter, but then decided that hiding the atomic_read isn't a
great idea, since having it explicitly show up in the code is a nice
remainder to reviews to check the memory barriers.
v4: Add a comment to explain why we need to fall through in
__wait_seqno in the end variable assignments.
v5: Review from Damien:
- s/smb/smp/ in a comment
- don't increment the reset counter after we've set it to WEDGED. Now
we (again) properly wedge the gpu when the reset fails.
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-12-06 16:01:42 +08:00
|
|
|
KOBJ_CHANGE, reset_done_event);
|
2012-11-16 00:17:22 +08:00
|
|
|
} else {
|
2013-11-12 20:44:19 +08:00
|
|
|
atomic_set_mask(I915_WEDGED, &error->reset_counter);
|
2009-09-15 05:48:46 +08:00
|
|
|
}
|
2012-11-16 00:17:22 +08:00
|
|
|
|
2013-09-09 03:57:13 +08:00
|
|
|
/*
|
|
|
|
* Note: The wake_up also serves as a memory barrier so that
|
|
|
|
* waiters see the update value of the reset counter atomic_t.
|
|
|
|
*/
|
|
|
|
i915_error_wake_up(dev_priv, true);
|
2009-09-15 05:48:46 +08:00
|
|
|
}
|
2009-07-12 04:48:03 +08:00
|
|
|
}
|
|
|
|
|
2010-05-27 20:18:12 +08:00
|
|
|
static void i915_report_and_clear_eir(struct drm_device *dev)
|
2009-07-12 04:48:03 +08:00
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2012-08-24 06:18:09 +08:00
|
|
|
uint32_t instdone[I915_NUM_INSTDONE_REG];
|
2009-07-12 04:48:03 +08:00
|
|
|
u32 eir = I915_READ(EIR);
|
2012-08-23 02:32:15 +08:00
|
|
|
int pipe, i;
|
2009-07-12 04:48:03 +08:00
|
|
|
|
2010-05-27 20:18:12 +08:00
|
|
|
if (!eir)
|
|
|
|
return;
|
2009-07-12 04:48:03 +08:00
|
|
|
|
2012-03-19 04:00:11 +08:00
|
|
|
pr_err("render error detected, EIR: 0x%08x\n", eir);
|
2009-07-12 04:48:03 +08:00
|
|
|
|
2012-08-24 06:18:09 +08:00
|
|
|
i915_get_extra_instdone(dev, instdone);
|
|
|
|
|
2009-07-12 04:48:03 +08:00
|
|
|
if (IS_G4X(dev)) {
|
|
|
|
if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
|
|
|
|
u32 ipeir = I915_READ(IPEIR_I965);
|
|
|
|
|
2012-03-19 04:00:11 +08:00
|
|
|
pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
|
|
|
|
pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
|
2012-08-23 02:32:15 +08:00
|
|
|
for (i = 0; i < ARRAY_SIZE(instdone); i++)
|
|
|
|
pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
|
2012-03-19 04:00:11 +08:00
|
|
|
pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
|
|
|
|
pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
|
2009-07-12 04:48:03 +08:00
|
|
|
I915_WRITE(IPEIR_I965, ipeir);
|
2010-11-16 23:55:10 +08:00
|
|
|
POSTING_READ(IPEIR_I965);
|
2009-07-12 04:48:03 +08:00
|
|
|
}
|
|
|
|
if (eir & GM45_ERROR_PAGE_TABLE) {
|
|
|
|
u32 pgtbl_err = I915_READ(PGTBL_ER);
|
2012-03-19 04:00:11 +08:00
|
|
|
pr_err("page table error\n");
|
|
|
|
pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
|
2009-07-12 04:48:03 +08:00
|
|
|
I915_WRITE(PGTBL_ER, pgtbl_err);
|
2010-11-16 23:55:10 +08:00
|
|
|
POSTING_READ(PGTBL_ER);
|
2009-07-12 04:48:03 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2010-09-17 07:32:17 +08:00
|
|
|
if (!IS_GEN2(dev)) {
|
2009-07-12 04:48:03 +08:00
|
|
|
if (eir & I915_ERROR_PAGE_TABLE) {
|
|
|
|
u32 pgtbl_err = I915_READ(PGTBL_ER);
|
2012-03-19 04:00:11 +08:00
|
|
|
pr_err("page table error\n");
|
|
|
|
pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
|
2009-07-12 04:48:03 +08:00
|
|
|
I915_WRITE(PGTBL_ER, pgtbl_err);
|
2010-11-16 23:55:10 +08:00
|
|
|
POSTING_READ(PGTBL_ER);
|
2009-07-12 04:48:03 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (eir & I915_ERROR_MEMORY_REFRESH) {
|
2012-03-19 04:00:11 +08:00
|
|
|
pr_err("memory refresh error:\n");
|
2014-08-18 20:49:10 +08:00
|
|
|
for_each_pipe(dev_priv, pipe)
|
2012-03-19 04:00:11 +08:00
|
|
|
pr_err("pipe %c stat: 0x%08x\n",
|
2011-02-08 04:26:52 +08:00
|
|
|
pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
|
2009-07-12 04:48:03 +08:00
|
|
|
/* pipestat has already been acked */
|
|
|
|
}
|
|
|
|
if (eir & I915_ERROR_INSTRUCTION) {
|
2012-03-19 04:00:11 +08:00
|
|
|
pr_err("instruction error\n");
|
|
|
|
pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
|
2012-08-23 02:32:15 +08:00
|
|
|
for (i = 0; i < ARRAY_SIZE(instdone); i++)
|
|
|
|
pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
|
2010-09-17 07:32:17 +08:00
|
|
|
if (INTEL_INFO(dev)->gen < 4) {
|
2009-07-12 04:48:03 +08:00
|
|
|
u32 ipeir = I915_READ(IPEIR);
|
|
|
|
|
2012-03-19 04:00:11 +08:00
|
|
|
pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
|
|
|
|
pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
|
|
|
|
pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
|
2009-07-12 04:48:03 +08:00
|
|
|
I915_WRITE(IPEIR, ipeir);
|
2010-11-16 23:55:10 +08:00
|
|
|
POSTING_READ(IPEIR);
|
2009-07-12 04:48:03 +08:00
|
|
|
} else {
|
|
|
|
u32 ipeir = I915_READ(IPEIR_I965);
|
|
|
|
|
2012-03-19 04:00:11 +08:00
|
|
|
pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
|
|
|
|
pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
|
|
|
|
pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
|
|
|
|
pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
|
2009-07-12 04:48:03 +08:00
|
|
|
I915_WRITE(IPEIR_I965, ipeir);
|
2010-11-16 23:55:10 +08:00
|
|
|
POSTING_READ(IPEIR_I965);
|
2009-07-12 04:48:03 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
I915_WRITE(EIR, eir);
|
2010-11-16 23:55:10 +08:00
|
|
|
POSTING_READ(EIR);
|
2009-07-12 04:48:03 +08:00
|
|
|
eir = I915_READ(EIR);
|
|
|
|
if (eir) {
|
|
|
|
/*
|
|
|
|
* some errors might have become stuck,
|
|
|
|
* mask them.
|
|
|
|
*/
|
|
|
|
DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
|
|
|
|
I915_WRITE(EMR, I915_READ(EMR) | eir);
|
|
|
|
I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
|
|
|
|
}
|
2010-05-27 20:18:12 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
2015-01-28 23:03:14 +08:00
|
|
|
* i915_handle_error - handle a gpu error
|
2010-05-27 20:18:12 +08:00
|
|
|
* @dev: drm device
|
|
|
|
*
|
2015-01-28 23:03:14 +08:00
|
|
|
* Do some basic checking of regsiter state at error time and
|
2010-05-27 20:18:12 +08:00
|
|
|
* dump it to the syslog. Also call i915_capture_error_state() to make
|
|
|
|
* sure we get a record and make it available in debugfs. Fire a uevent
|
|
|
|
* so userspace knows something bad happened (should trigger collection
|
|
|
|
* of a ring dump etc.).
|
|
|
|
*/
|
2014-02-25 23:11:26 +08:00
|
|
|
void i915_handle_error(struct drm_device *dev, bool wedged,
|
|
|
|
const char *fmt, ...)
|
2010-05-27 20:18:12 +08:00
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2014-02-25 23:11:26 +08:00
|
|
|
va_list args;
|
|
|
|
char error_msg[80];
|
2010-05-27 20:18:12 +08:00
|
|
|
|
2014-02-25 23:11:26 +08:00
|
|
|
va_start(args, fmt);
|
|
|
|
vscnprintf(error_msg, sizeof(error_msg), fmt, args);
|
|
|
|
va_end(args);
|
|
|
|
|
|
|
|
i915_capture_error_state(dev, wedged, error_msg);
|
2010-05-27 20:18:12 +08:00
|
|
|
i915_report_and_clear_eir(dev);
|
2009-07-12 04:48:03 +08:00
|
|
|
|
2009-09-15 05:48:47 +08:00
|
|
|
if (wedged) {
|
drm/i915: create a race-free reset detection
With the previous patch the state transition handling of the reset
code itself is now (hopefully) race free and solid. But that still
leaves out everyone else - with the various lock-free wait paths
we have there's the possibility that the reset happens between the
point where we read the seqno we should wait on and the actual wait.
And if __wait_seqno then never sees the RESET_IN_PROGRESS state, we'll
happily wait for a seqno which will in all likelyhood never signal.
In practice this is not a big problem since the X server gets
constantly interrupted, and can then submit more work (hopefully) to
unblock everyone else: As soon as a new seqno write lands, all waiters
will unblock. But running the i-g-t reset testcase ZZ_hangman can
expose this race, especially on slower hw with fewer cpu cores.
Now looking forward to ARB_robustness and friends that's not the best
possible behaviour, hence this patch adds a reset_counter to be able
to detect any reset, even if a given thread never observed the
in-progress state.
The important part is to correctly order things:
- The write side needs to increment the counter after any seqno gets
reset. Hence we need to do that at the end of the reset work, and
again wake everyone up. We also need to place a barrier in between
any possible seqno changes and the counter increment, since any
unlock operations only guarantee that nothing leaks out, but not
that at later load operation gets moved ahead.
- On the read side we need to ensure that no reset can sneak in and
invalidate the seqno. In all cases we can use the one-sided barrier
that unlock operations guarantee (of the lock protecting the
respective seqno/ring pair) to ensure correct ordering. Hence it is
sufficient to place the atomic read before the mutex/spin_unlock and
no additional barriers are required.
The end-result of all this is that we need to wake up everyone twice
in a reset operation:
- First, before the reset starts, to get any lockholders of the locks,
so that the reset can proceed.
- Second, after the reset is completed, to allow waiters to properly
and reliably detect the reset condition and bail out.
I admit that this entire reset_counter thing smells a bit like
overkill, but I think it's justified since it makes it really explicit
what the bail-out condition is. And we need a reset counter anyway to
implement ARB_robustness, and imo with finer-grained locking on the
horizont this is the most resilient scheme I could think of.
v2: Drop spurious change in the wait_for_error EXIT_COND - we only
need to wait until we leave the reset-in-progress wedged state.
v3: Don't play tricks with barriers in the throttle ioctl, the
spin_unlock is barrier enough.
I've also considered using a little helper to grab the current
reset_counter, but then decided that hiding the atomic_read isn't a
great idea, since having it explicitly show up in the code is a nice
remainder to reviews to check the memory barriers.
v4: Add a comment to explain why we need to fall through in
__wait_seqno in the end variable assignments.
v5: Review from Damien:
- s/smb/smp/ in a comment
- don't increment the reset counter after we've set it to WEDGED. Now
we (again) properly wedge the gpu when the reset fails.
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-12-06 16:01:42 +08:00
|
|
|
atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
|
|
|
|
&dev_priv->gpu_error.reset_counter);
|
2009-09-15 05:48:47 +08:00
|
|
|
|
2009-09-15 05:48:45 +08:00
|
|
|
/*
|
2015-01-28 23:03:14 +08:00
|
|
|
* Wakeup waiting processes so that the reset function
|
|
|
|
* i915_reset_and_wakeup doesn't deadlock trying to grab
|
|
|
|
* various locks. By bumping the reset counter first, the woken
|
2013-09-09 03:57:13 +08:00
|
|
|
* processes will see a reset in progress and back off,
|
|
|
|
* releasing their locks and then wait for the reset completion.
|
|
|
|
* We must do this for _all_ gpu waiters that might hold locks
|
|
|
|
* that the reset work needs to acquire.
|
|
|
|
*
|
|
|
|
* Note: The wake_up serves as the required memory barrier to
|
|
|
|
* ensure that the waiters see the updated value of the reset
|
|
|
|
* counter atomic_t.
|
2009-09-15 05:48:45 +08:00
|
|
|
*/
|
2013-09-09 03:57:13 +08:00
|
|
|
i915_error_wake_up(dev_priv, false);
|
2009-09-15 05:48:45 +08:00
|
|
|
}
|
|
|
|
|
2015-01-28 23:03:14 +08:00
|
|
|
i915_reset_and_wakeup(dev);
|
2009-07-12 04:48:03 +08:00
|
|
|
}
|
|
|
|
|
2008-10-19 10:39:29 +08:00
|
|
|
/* Called from drm generic code, passed 'crtc' which
|
|
|
|
* we use as a pipe index
|
|
|
|
*/
|
2011-06-29 04:00:41 +08:00
|
|
|
static int i915_enable_vblank(struct drm_device *dev, int pipe)
|
2008-10-01 03:14:26 +08:00
|
|
|
{
|
2014-03-31 19:27:17 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2008-10-17 02:31:38 +08:00
|
|
|
unsigned long irqflags;
|
2009-01-09 02:42:15 +08:00
|
|
|
|
2010-12-04 19:30:53 +08:00
|
|
|
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
|
2011-04-08 04:58:17 +08:00
|
|
|
if (INTEL_INFO(dev)->gen >= 4)
|
2008-11-04 18:03:27 +08:00
|
|
|
i915_enable_pipestat(dev_priv, pipe,
|
2014-02-11 00:42:47 +08:00
|
|
|
PIPE_START_VBLANK_INTERRUPT_STATUS);
|
2008-10-17 02:31:38 +08:00
|
|
|
else
|
2008-11-04 18:03:27 +08:00
|
|
|
i915_enable_pipestat(dev_priv, pipe,
|
2014-02-11 00:42:47 +08:00
|
|
|
PIPE_VBLANK_INTERRUPT_STATUS);
|
2010-12-04 19:30:53 +08:00
|
|
|
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
|
2011-02-05 18:08:21 +08:00
|
|
|
|
2008-10-01 03:14:26 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-06-29 04:00:41 +08:00
|
|
|
static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
|
2011-04-08 04:58:17 +08:00
|
|
|
{
|
2014-03-31 19:27:17 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2011-04-08 04:58:17 +08:00
|
|
|
unsigned long irqflags;
|
2013-07-13 07:00:08 +08:00
|
|
|
uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
|
2013-10-22 00:04:36 +08:00
|
|
|
DE_PIPE_VBLANK(pipe);
|
2011-04-08 04:58:17 +08:00
|
|
|
|
|
|
|
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
|
2013-07-13 07:00:08 +08:00
|
|
|
ironlake_enable_display_irq(dev_priv, bit);
|
2011-04-07 03:13:38 +08:00
|
|
|
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-03-29 04:39:38 +08:00
|
|
|
static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
|
|
|
|
{
|
2014-03-31 19:27:17 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2012-03-29 04:39:38 +08:00
|
|
|
unsigned long irqflags;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
|
2012-06-21 01:53:11 +08:00
|
|
|
i915_enable_pipestat(dev_priv, pipe,
|
2014-02-11 00:42:47 +08:00
|
|
|
PIPE_START_VBLANK_INTERRUPT_STATUS);
|
2012-03-29 04:39:38 +08:00
|
|
|
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 12:07:09 +08:00
|
|
|
static int gen8_enable_vblank(struct drm_device *dev, int pipe)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
unsigned long irqflags;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
|
2013-11-07 18:05:45 +08:00
|
|
|
dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK;
|
|
|
|
I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
|
|
|
|
POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 12:07:09 +08:00
|
|
|
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2008-10-19 10:39:29 +08:00
|
|
|
/* Called from drm generic code, passed 'crtc' which
|
|
|
|
* we use as a pipe index
|
|
|
|
*/
|
2011-06-29 04:00:41 +08:00
|
|
|
static void i915_disable_vblank(struct drm_device *dev, int pipe)
|
2008-10-01 03:14:26 +08:00
|
|
|
{
|
2014-03-31 19:27:17 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2008-10-17 02:31:38 +08:00
|
|
|
unsigned long irqflags;
|
2008-10-01 03:14:26 +08:00
|
|
|
|
2010-12-04 19:30:53 +08:00
|
|
|
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
|
2011-04-08 04:58:17 +08:00
|
|
|
i915_disable_pipestat(dev_priv, pipe,
|
2014-02-11 00:42:47 +08:00
|
|
|
PIPE_VBLANK_INTERRUPT_STATUS |
|
|
|
|
PIPE_START_VBLANK_INTERRUPT_STATUS);
|
2011-04-08 04:58:17 +08:00
|
|
|
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
|
|
|
|
}
|
|
|
|
|
2011-06-29 04:00:41 +08:00
|
|
|
static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
|
2011-04-08 04:58:17 +08:00
|
|
|
{
|
2014-03-31 19:27:17 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2011-04-08 04:58:17 +08:00
|
|
|
unsigned long irqflags;
|
2013-07-13 07:00:08 +08:00
|
|
|
uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
|
2013-10-22 00:04:36 +08:00
|
|
|
DE_PIPE_VBLANK(pipe);
|
2011-04-08 04:58:17 +08:00
|
|
|
|
|
|
|
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
|
2013-07-13 07:00:08 +08:00
|
|
|
ironlake_disable_display_irq(dev_priv, bit);
|
2011-04-07 03:13:38 +08:00
|
|
|
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
|
|
|
|
}
|
|
|
|
|
2012-03-29 04:39:38 +08:00
|
|
|
static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
|
|
|
|
{
|
2014-03-31 19:27:17 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2012-03-29 04:39:38 +08:00
|
|
|
unsigned long irqflags;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
|
2012-06-21 01:53:11 +08:00
|
|
|
i915_disable_pipestat(dev_priv, pipe,
|
2014-02-11 00:42:47 +08:00
|
|
|
PIPE_START_VBLANK_INTERRUPT_STATUS);
|
2012-03-29 04:39:38 +08:00
|
|
|
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
|
|
|
|
}
|
|
|
|
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 12:07:09 +08:00
|
|
|
static void gen8_disable_vblank(struct drm_device *dev, int pipe)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
unsigned long irqflags;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
|
2013-11-07 18:05:45 +08:00
|
|
|
dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK;
|
|
|
|
I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
|
|
|
|
POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 12:07:09 +08:00
|
|
|
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
|
|
|
|
}
|
|
|
|
|
2014-11-25 02:49:40 +08:00
|
|
|
static struct drm_i915_gem_request *
|
|
|
|
ring_last_request(struct intel_engine_cs *ring)
|
2010-05-21 09:08:56 +08:00
|
|
|
{
|
2010-10-27 21:44:35 +08:00
|
|
|
return list_entry(ring->request_list.prev,
|
2014-11-25 02:49:40 +08:00
|
|
|
struct drm_i915_gem_request, list);
|
2010-10-27 21:44:35 +08:00
|
|
|
}
|
|
|
|
|
2013-06-10 18:20:20 +08:00
|
|
|
static bool
|
2014-11-25 02:49:40 +08:00
|
|
|
ring_idle(struct intel_engine_cs *ring)
|
2013-06-10 18:20:20 +08:00
|
|
|
{
|
|
|
|
return (list_empty(&ring->request_list) ||
|
2014-11-25 02:49:42 +08:00
|
|
|
i915_gem_request_completed(ring_last_request(ring), false));
|
2009-09-15 05:48:44 +08:00
|
|
|
}
|
|
|
|
|
2014-03-15 07:08:56 +08:00
|
|
|
static bool
|
|
|
|
ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr)
|
|
|
|
{
|
|
|
|
if (INTEL_INFO(dev)->gen >= 8) {
|
2014-07-01 00:53:39 +08:00
|
|
|
return (ipehr >> 23) == 0x1c;
|
2014-03-15 07:08:56 +08:00
|
|
|
} else {
|
|
|
|
ipehr &= ~MI_SEMAPHORE_SYNC_MASK;
|
|
|
|
return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE |
|
|
|
|
MI_SEMAPHORE_REGISTER);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-05-22 21:13:33 +08:00
|
|
|
static struct intel_engine_cs *
|
2014-07-01 00:53:39 +08:00
|
|
|
semaphore_wait_to_signaller_ring(struct intel_engine_cs *ring, u32 ipehr, u64 offset)
|
2014-03-18 17:26:04 +08:00
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = ring->dev->dev_private;
|
2014-05-22 21:13:33 +08:00
|
|
|
struct intel_engine_cs *signaller;
|
2014-03-18 17:26:04 +08:00
|
|
|
int i;
|
|
|
|
|
|
|
|
if (INTEL_INFO(dev_priv->dev)->gen >= 8) {
|
2014-07-01 00:53:39 +08:00
|
|
|
for_each_ring(signaller, dev_priv, i) {
|
|
|
|
if (ring == signaller)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (offset == signaller->semaphore.signal_ggtt[ring->id])
|
|
|
|
return signaller;
|
|
|
|
}
|
2014-03-18 17:26:04 +08:00
|
|
|
} else {
|
|
|
|
u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK;
|
|
|
|
|
|
|
|
for_each_ring(signaller, dev_priv, i) {
|
|
|
|
if(ring == signaller)
|
|
|
|
continue;
|
|
|
|
|
2014-04-30 05:52:28 +08:00
|
|
|
if (sync_bits == signaller->semaphore.mbox.wait[ring->id])
|
2014-03-18 17:26:04 +08:00
|
|
|
return signaller;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-07-01 00:53:39 +08:00
|
|
|
DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n",
|
|
|
|
ring->id, ipehr, offset);
|
2014-03-18 17:26:04 +08:00
|
|
|
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
2014-05-22 21:13:33 +08:00
|
|
|
static struct intel_engine_cs *
|
|
|
|
semaphore_waits_for(struct intel_engine_cs *ring, u32 *seqno)
|
2013-03-14 23:52:05 +08:00
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = ring->dev->dev_private;
|
2014-03-15 07:08:55 +08:00
|
|
|
u32 cmd, ipehr, head;
|
2014-07-01 00:53:39 +08:00
|
|
|
u64 offset = 0;
|
|
|
|
int i, backwards;
|
2013-03-14 23:52:05 +08:00
|
|
|
|
|
|
|
ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
|
2014-03-15 07:08:56 +08:00
|
|
|
if (!ipehr_is_semaphore_wait(ring->dev, ipehr))
|
2013-06-10 18:20:21 +08:00
|
|
|
return NULL;
|
2013-03-14 23:52:05 +08:00
|
|
|
|
2014-03-15 07:08:55 +08:00
|
|
|
/*
|
|
|
|
* HEAD is likely pointing to the dword after the actual command,
|
|
|
|
* so scan backwards until we find the MBOX. But limit it to just 3
|
2014-07-01 00:53:39 +08:00
|
|
|
* or 4 dwords depending on the semaphore wait command size.
|
|
|
|
* Note that we don't care about ACTHD here since that might
|
2014-03-15 07:08:55 +08:00
|
|
|
* point at at batch, and semaphores are always emitted into the
|
|
|
|
* ringbuffer itself.
|
2013-03-14 23:52:05 +08:00
|
|
|
*/
|
2014-03-15 07:08:55 +08:00
|
|
|
head = I915_READ_HEAD(ring) & HEAD_ADDR;
|
2014-07-01 00:53:39 +08:00
|
|
|
backwards = (INTEL_INFO(ring->dev)->gen >= 8) ? 5 : 4;
|
2014-03-15 07:08:55 +08:00
|
|
|
|
2014-07-01 00:53:39 +08:00
|
|
|
for (i = backwards; i; --i) {
|
2014-03-15 07:08:55 +08:00
|
|
|
/*
|
|
|
|
* Be paranoid and presume the hw has gone off into the wild -
|
|
|
|
* our ring is smaller than what the hardware (and hence
|
|
|
|
* HEAD_ADDR) allows. Also handles wrap-around.
|
|
|
|
*/
|
2014-05-22 21:13:35 +08:00
|
|
|
head &= ring->buffer->size - 1;
|
2014-03-15 07:08:55 +08:00
|
|
|
|
|
|
|
/* This here seems to blow up */
|
2014-05-22 21:13:35 +08:00
|
|
|
cmd = ioread32(ring->buffer->virtual_start + head);
|
2013-03-14 23:52:05 +08:00
|
|
|
if (cmd == ipehr)
|
|
|
|
break;
|
|
|
|
|
2014-03-15 07:08:55 +08:00
|
|
|
head -= 4;
|
|
|
|
}
|
2013-03-14 23:52:05 +08:00
|
|
|
|
2014-03-15 07:08:55 +08:00
|
|
|
if (!i)
|
|
|
|
return NULL;
|
2013-03-14 23:52:05 +08:00
|
|
|
|
2014-05-22 21:13:35 +08:00
|
|
|
*seqno = ioread32(ring->buffer->virtual_start + head + 4) + 1;
|
2014-07-01 00:53:39 +08:00
|
|
|
if (INTEL_INFO(ring->dev)->gen >= 8) {
|
|
|
|
offset = ioread32(ring->buffer->virtual_start + head + 12);
|
|
|
|
offset <<= 32;
|
|
|
|
offset = ioread32(ring->buffer->virtual_start + head + 8);
|
|
|
|
}
|
|
|
|
return semaphore_wait_to_signaller_ring(ring, ipehr, offset);
|
2013-03-14 23:52:05 +08:00
|
|
|
}
|
|
|
|
|
2014-05-22 21:13:33 +08:00
|
|
|
static int semaphore_passed(struct intel_engine_cs *ring)
|
2013-06-10 18:20:21 +08:00
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = ring->dev->dev_private;
|
2014-05-22 21:13:33 +08:00
|
|
|
struct intel_engine_cs *signaller;
|
2014-07-19 19:40:42 +08:00
|
|
|
u32 seqno;
|
2013-06-10 18:20:21 +08:00
|
|
|
|
2014-06-06 17:22:29 +08:00
|
|
|
ring->hangcheck.deadlock++;
|
2013-06-10 18:20:21 +08:00
|
|
|
|
|
|
|
signaller = semaphore_waits_for(ring, &seqno);
|
2014-06-06 17:22:29 +08:00
|
|
|
if (signaller == NULL)
|
|
|
|
return -1;
|
|
|
|
|
|
|
|
/* Prevent pathological recursion due to driver bugs */
|
|
|
|
if (signaller->hangcheck.deadlock >= I915_NUM_RINGS)
|
2013-06-10 18:20:21 +08:00
|
|
|
return -1;
|
|
|
|
|
2014-06-06 17:22:29 +08:00
|
|
|
if (i915_seqno_passed(signaller->get_seqno(signaller, false), seqno))
|
|
|
|
return 1;
|
|
|
|
|
2014-07-19 19:40:42 +08:00
|
|
|
/* cursory check for an unkickable deadlock */
|
|
|
|
if (I915_READ_CTL(signaller) & RING_WAIT_SEMAPHORE &&
|
|
|
|
semaphore_passed(signaller) < 0)
|
2014-06-06 17:22:29 +08:00
|
|
|
return -1;
|
|
|
|
|
|
|
|
return 0;
|
2013-06-10 18:20:21 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
2014-05-22 21:13:33 +08:00
|
|
|
struct intel_engine_cs *ring;
|
2013-06-10 18:20:21 +08:00
|
|
|
int i;
|
|
|
|
|
|
|
|
for_each_ring(ring, dev_priv, i)
|
2014-06-06 17:22:29 +08:00
|
|
|
ring->hangcheck.deadlock = 0;
|
2013-06-10 18:20:21 +08:00
|
|
|
}
|
|
|
|
|
2013-06-12 17:35:32 +08:00
|
|
|
static enum intel_ring_hangcheck_action
|
2014-05-22 21:13:33 +08:00
|
|
|
ring_stuck(struct intel_engine_cs *ring, u64 acthd)
|
2010-12-04 19:30:53 +08:00
|
|
|
{
|
|
|
|
struct drm_device *dev = ring->dev;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2013-06-10 18:20:20 +08:00
|
|
|
u32 tmp;
|
|
|
|
|
2014-08-05 22:16:26 +08:00
|
|
|
if (acthd != ring->hangcheck.acthd) {
|
|
|
|
if (acthd > ring->hangcheck.max_acthd) {
|
|
|
|
ring->hangcheck.max_acthd = acthd;
|
|
|
|
return HANGCHECK_ACTIVE;
|
|
|
|
}
|
|
|
|
|
|
|
|
return HANGCHECK_ACTIVE_LOOP;
|
|
|
|
}
|
2013-06-10 18:20:21 +08:00
|
|
|
|
2013-06-10 18:20:20 +08:00
|
|
|
if (IS_GEN2(dev))
|
2013-08-11 17:44:01 +08:00
|
|
|
return HANGCHECK_HUNG;
|
2013-06-10 18:20:20 +08:00
|
|
|
|
|
|
|
/* Is the chip hanging on a WAIT_FOR_EVENT?
|
|
|
|
* If so we can simply poke the RB_WAIT bit
|
|
|
|
* and break the hang. This should work on
|
|
|
|
* all but the second generation chipsets.
|
|
|
|
*/
|
|
|
|
tmp = I915_READ_CTL(ring);
|
2010-12-04 19:30:53 +08:00
|
|
|
if (tmp & RING_WAIT) {
|
2014-02-25 23:11:26 +08:00
|
|
|
i915_handle_error(dev, false,
|
|
|
|
"Kicking stuck wait on %s",
|
|
|
|
ring->name);
|
2010-12-04 19:30:53 +08:00
|
|
|
I915_WRITE_CTL(ring, tmp);
|
2013-08-11 17:44:01 +08:00
|
|
|
return HANGCHECK_KICK;
|
2013-06-10 18:20:21 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
|
|
|
|
switch (semaphore_passed(ring)) {
|
|
|
|
default:
|
2013-08-11 17:44:01 +08:00
|
|
|
return HANGCHECK_HUNG;
|
2013-06-10 18:20:21 +08:00
|
|
|
case 1:
|
2014-02-25 23:11:26 +08:00
|
|
|
i915_handle_error(dev, false,
|
|
|
|
"Kicking stuck semaphore on %s",
|
|
|
|
ring->name);
|
2013-06-10 18:20:21 +08:00
|
|
|
I915_WRITE_CTL(ring, tmp);
|
2013-08-11 17:44:01 +08:00
|
|
|
return HANGCHECK_KICK;
|
2013-06-10 18:20:21 +08:00
|
|
|
case 0:
|
2013-08-11 17:44:01 +08:00
|
|
|
return HANGCHECK_WAIT;
|
2013-06-10 18:20:21 +08:00
|
|
|
}
|
2013-06-10 18:20:20 +08:00
|
|
|
}
|
2013-05-13 21:32:11 +08:00
|
|
|
|
2013-08-11 17:44:01 +08:00
|
|
|
return HANGCHECK_HUNG;
|
2013-05-13 21:32:11 +08:00
|
|
|
}
|
|
|
|
|
2015-01-27 00:03:03 +08:00
|
|
|
/*
|
2009-09-15 05:48:44 +08:00
|
|
|
* This is called when the chip hasn't reported back with completed
|
2013-05-30 14:04:29 +08:00
|
|
|
* batchbuffers in a long time. We keep track per ring seqno progress and
|
|
|
|
* if there are no progress, hangcheck score for that ring is increased.
|
|
|
|
* Further, acthd is inspected to see if the ring is stuck. On stuck case
|
|
|
|
* we kick the ring. If we see no progress on three subsequent calls
|
|
|
|
* we assume chip is wedged and try to fix it by resetting the chip.
|
2009-09-15 05:48:44 +08:00
|
|
|
*/
|
2015-01-27 00:03:03 +08:00
|
|
|
static void i915_hangcheck_elapsed(struct work_struct *work)
|
2009-09-15 05:48:44 +08:00
|
|
|
{
|
2015-01-27 00:03:03 +08:00
|
|
|
struct drm_i915_private *dev_priv =
|
|
|
|
container_of(work, typeof(*dev_priv),
|
|
|
|
gpu_error.hangcheck_work.work);
|
|
|
|
struct drm_device *dev = dev_priv->dev;
|
2014-05-22 21:13:33 +08:00
|
|
|
struct intel_engine_cs *ring;
|
2012-05-11 21:29:30 +08:00
|
|
|
int i;
|
2013-05-30 14:04:29 +08:00
|
|
|
int busy_count = 0, rings_hung = 0;
|
2013-06-10 18:20:20 +08:00
|
|
|
bool stuck[I915_NUM_RINGS] = { 0 };
|
|
|
|
#define BUSY 1
|
|
|
|
#define KICK 5
|
|
|
|
#define HUNG 20
|
2010-10-27 21:44:35 +08:00
|
|
|
|
2014-01-21 17:24:25 +08:00
|
|
|
if (!i915.enable_hangcheck)
|
2011-06-30 01:26:42 +08:00
|
|
|
return;
|
|
|
|
|
2012-05-11 21:29:30 +08:00
|
|
|
for_each_ring(ring, dev_priv, i) {
|
2014-03-21 20:41:53 +08:00
|
|
|
u64 acthd;
|
|
|
|
u32 seqno;
|
2013-06-10 18:20:20 +08:00
|
|
|
bool busy = true;
|
2013-05-30 14:04:29 +08:00
|
|
|
|
2013-06-10 18:20:21 +08:00
|
|
|
semaphore_clear_deadlocks(dev_priv);
|
|
|
|
|
2013-05-30 14:04:29 +08:00
|
|
|
seqno = ring->get_seqno(ring, false);
|
|
|
|
acthd = intel_ring_get_active_head(ring);
|
2012-05-11 21:29:30 +08:00
|
|
|
|
2013-06-10 18:20:20 +08:00
|
|
|
if (ring->hangcheck.seqno == seqno) {
|
2014-11-25 02:49:40 +08:00
|
|
|
if (ring_idle(ring)) {
|
2013-09-06 21:03:28 +08:00
|
|
|
ring->hangcheck.action = HANGCHECK_IDLE;
|
|
|
|
|
2013-06-10 18:20:20 +08:00
|
|
|
if (waitqueue_active(&ring->irq_queue)) {
|
|
|
|
/* Issue a wake-up to catch stuck h/w. */
|
2013-09-26 00:34:55 +08:00
|
|
|
if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) {
|
2013-10-28 16:24:13 +08:00
|
|
|
if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring)))
|
|
|
|
DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
|
|
|
|
ring->name);
|
|
|
|
else
|
|
|
|
DRM_INFO("Fake missed irq on %s\n",
|
|
|
|
ring->name);
|
2013-09-26 00:34:55 +08:00
|
|
|
wake_up_all(&ring->irq_queue);
|
|
|
|
}
|
|
|
|
/* Safeguard against driver failure */
|
|
|
|
ring->hangcheck.score += BUSY;
|
2013-06-10 18:20:20 +08:00
|
|
|
} else
|
|
|
|
busy = false;
|
2013-05-30 14:04:29 +08:00
|
|
|
} else {
|
2013-06-10 18:20:21 +08:00
|
|
|
/* We always increment the hangcheck score
|
|
|
|
* if the ring is busy and still processing
|
|
|
|
* the same request, so that no single request
|
|
|
|
* can run indefinitely (such as a chain of
|
|
|
|
* batches). The only time we do not increment
|
|
|
|
* the hangcheck score on this ring, if this
|
|
|
|
* ring is in a legitimate wait for another
|
|
|
|
* ring. In that case the waiting ring is a
|
|
|
|
* victim and we want to be sure we catch the
|
|
|
|
* right culprit. Then every time we do kick
|
|
|
|
* the ring, add a small increment to the
|
|
|
|
* score so that we can catch a batch that is
|
|
|
|
* being repeatedly kicked and so responsible
|
|
|
|
* for stalling the machine.
|
|
|
|
*/
|
2013-06-12 17:35:32 +08:00
|
|
|
ring->hangcheck.action = ring_stuck(ring,
|
|
|
|
acthd);
|
|
|
|
|
|
|
|
switch (ring->hangcheck.action) {
|
2013-09-06 21:03:28 +08:00
|
|
|
case HANGCHECK_IDLE:
|
2013-08-11 17:44:01 +08:00
|
|
|
case HANGCHECK_WAIT:
|
|
|
|
case HANGCHECK_ACTIVE:
|
2014-08-05 22:16:26 +08:00
|
|
|
break;
|
|
|
|
case HANGCHECK_ACTIVE_LOOP:
|
2013-08-11 17:44:02 +08:00
|
|
|
ring->hangcheck.score += BUSY;
|
2013-06-10 18:20:21 +08:00
|
|
|
break;
|
2013-08-11 17:44:01 +08:00
|
|
|
case HANGCHECK_KICK:
|
2013-08-11 17:44:02 +08:00
|
|
|
ring->hangcheck.score += KICK;
|
2013-06-10 18:20:21 +08:00
|
|
|
break;
|
2013-08-11 17:44:01 +08:00
|
|
|
case HANGCHECK_HUNG:
|
2013-08-11 17:44:02 +08:00
|
|
|
ring->hangcheck.score += HUNG;
|
2013-06-10 18:20:21 +08:00
|
|
|
stuck[i] = true;
|
|
|
|
break;
|
|
|
|
}
|
2013-05-30 14:04:29 +08:00
|
|
|
}
|
2013-06-10 18:20:20 +08:00
|
|
|
} else {
|
2013-09-06 21:03:28 +08:00
|
|
|
ring->hangcheck.action = HANGCHECK_ACTIVE;
|
|
|
|
|
2013-06-10 18:20:20 +08:00
|
|
|
/* Gradually reduce the count so that we catch DoS
|
|
|
|
* attempts across multiple batches.
|
|
|
|
*/
|
|
|
|
if (ring->hangcheck.score > 0)
|
|
|
|
ring->hangcheck.score--;
|
2014-08-05 22:16:26 +08:00
|
|
|
|
|
|
|
ring->hangcheck.acthd = ring->hangcheck.max_acthd = 0;
|
2012-04-11 00:00:41 +08:00
|
|
|
}
|
|
|
|
|
2013-05-30 14:04:29 +08:00
|
|
|
ring->hangcheck.seqno = seqno;
|
|
|
|
ring->hangcheck.acthd = acthd;
|
2013-06-10 18:20:20 +08:00
|
|
|
busy_count += busy;
|
2010-10-27 21:44:35 +08:00
|
|
|
}
|
2010-01-09 06:25:16 +08:00
|
|
|
|
2013-05-24 22:16:07 +08:00
|
|
|
for_each_ring(ring, dev_priv, i) {
|
2014-01-31 01:04:43 +08:00
|
|
|
if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) {
|
2013-08-28 16:57:59 +08:00
|
|
|
DRM_INFO("%s on %s\n",
|
|
|
|
stuck[i] ? "stuck" : "no progress",
|
|
|
|
ring->name);
|
2013-06-10 18:20:22 +08:00
|
|
|
rings_hung++;
|
2013-05-24 22:16:07 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-05-30 14:04:29 +08:00
|
|
|
if (rings_hung)
|
2014-02-25 23:11:26 +08:00
|
|
|
return i915_handle_error(dev, true, "Ring hung");
|
2009-09-15 05:48:44 +08:00
|
|
|
|
2013-05-30 14:04:29 +08:00
|
|
|
if (busy_count)
|
|
|
|
/* Reset timer case chip hangs without another request
|
|
|
|
* being added */
|
2013-07-03 22:22:08 +08:00
|
|
|
i915_queue_hangcheck(dev);
|
|
|
|
}
|
|
|
|
|
|
|
|
void i915_queue_hangcheck(struct drm_device *dev)
|
|
|
|
{
|
2015-01-27 00:03:03 +08:00
|
|
|
struct i915_gpu_error *e = &to_i915(dev)->gpu_error;
|
2014-11-19 17:47:19 +08:00
|
|
|
|
2014-01-21 17:24:25 +08:00
|
|
|
if (!i915.enable_hangcheck)
|
2013-07-03 22:22:08 +08:00
|
|
|
return;
|
|
|
|
|
2015-01-27 00:03:03 +08:00
|
|
|
/* Don't continually defer the hangcheck so that it is always run at
|
|
|
|
* least once after work has been scheduled on any ring. Otherwise,
|
|
|
|
* we will ignore a hung ring if a second ring is kept busy.
|
|
|
|
*/
|
|
|
|
|
|
|
|
queue_delayed_work(e->hangcheck_wq, &e->hangcheck_work,
|
|
|
|
round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES));
|
2009-09-15 05:48:44 +08:00
|
|
|
}
|
|
|
|
|
2014-04-02 02:37:23 +08:00
|
|
|
static void ibx_irq_reset(struct drm_device *dev)
|
2013-06-06 01:21:51 +08:00
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
|
|
|
|
if (HAS_PCH_NOP(dev))
|
|
|
|
return;
|
|
|
|
|
2014-04-02 02:37:14 +08:00
|
|
|
GEN5_IRQ_RESET(SDE);
|
2014-04-02 02:37:17 +08:00
|
|
|
|
|
|
|
if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
|
|
|
|
I915_WRITE(SERR_INT, 0xffffffff);
|
2014-04-02 02:37:22 +08:00
|
|
|
}
|
2014-04-02 02:37:17 +08:00
|
|
|
|
2014-04-02 02:37:22 +08:00
|
|
|
/*
|
|
|
|
* SDEIER is also touched by the interrupt handler to work around missed PCH
|
|
|
|
* interrupts. Hence we can't update it after the interrupt handler is enabled -
|
|
|
|
* instead we unconditionally enable all PCH interrupt sources here, but then
|
|
|
|
* only unmask them as needed with SDEIMR.
|
|
|
|
*
|
|
|
|
* This function needs to be called before interrupts are enabled.
|
|
|
|
*/
|
|
|
|
static void ibx_irq_pre_postinstall(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
|
|
|
|
if (HAS_PCH_NOP(dev))
|
|
|
|
return;
|
|
|
|
|
|
|
|
WARN_ON(I915_READ(SDEIER) != 0);
|
2013-06-06 01:21:51 +08:00
|
|
|
I915_WRITE(SDEIER, 0xffffffff);
|
|
|
|
POSTING_READ(SDEIER);
|
|
|
|
}
|
|
|
|
|
2014-04-02 02:37:19 +08:00
|
|
|
static void gen5_gt_irq_reset(struct drm_device *dev)
|
2013-07-13 04:43:25 +08:00
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
|
2014-04-02 02:37:14 +08:00
|
|
|
GEN5_IRQ_RESET(GT);
|
2014-04-02 02:37:09 +08:00
|
|
|
if (INTEL_INFO(dev)->gen >= 6)
|
2014-04-02 02:37:14 +08:00
|
|
|
GEN5_IRQ_RESET(GEN6_PM);
|
2013-07-13 04:43:25 +08:00
|
|
|
}
|
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
/* drm_dma.h hooks
|
|
|
|
*/
|
2014-04-02 02:37:25 +08:00
|
|
|
static void ironlake_irq_reset(struct drm_device *dev)
|
2009-06-08 14:40:19 +08:00
|
|
|
{
|
2014-03-31 19:27:17 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2009-06-08 14:40:19 +08:00
|
|
|
|
2014-04-02 02:37:27 +08:00
|
|
|
I915_WRITE(HWSTAM, 0xffffffff);
|
2012-01-05 08:05:26 +08:00
|
|
|
|
2014-04-02 02:37:14 +08:00
|
|
|
GEN5_IRQ_RESET(DE);
|
2014-04-02 02:37:18 +08:00
|
|
|
if (IS_GEN7(dev))
|
|
|
|
I915_WRITE(GEN7_ERR_INT, 0xffffffff);
|
2009-06-08 14:40:19 +08:00
|
|
|
|
2014-04-02 02:37:19 +08:00
|
|
|
gen5_gt_irq_reset(dev);
|
2009-11-04 02:57:21 +08:00
|
|
|
|
2014-04-02 02:37:23 +08:00
|
|
|
ibx_irq_reset(dev);
|
2013-05-29 10:22:25 +08:00
|
|
|
}
|
2009-11-04 02:57:21 +08:00
|
|
|
|
2014-10-31 01:42:58 +08:00
|
|
|
static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
enum pipe pipe;
|
|
|
|
|
|
|
|
I915_WRITE(PORT_HOTPLUG_EN, 0);
|
|
|
|
I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
|
|
|
|
|
|
|
|
for_each_pipe(dev_priv, pipe)
|
|
|
|
I915_WRITE(PIPESTAT(pipe), 0xffff);
|
|
|
|
|
|
|
|
GEN5_IRQ_RESET(VLV_);
|
|
|
|
}
|
|
|
|
|
2012-03-29 04:39:38 +08:00
|
|
|
static void valleyview_irq_preinstall(struct drm_device *dev)
|
|
|
|
{
|
2014-03-31 19:27:17 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2012-03-29 04:39:38 +08:00
|
|
|
|
|
|
|
/* VLV magic */
|
|
|
|
I915_WRITE(VLV_IMR, 0);
|
|
|
|
I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
|
|
|
|
I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
|
|
|
|
I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
|
|
|
|
|
2014-04-02 02:37:19 +08:00
|
|
|
gen5_gt_irq_reset(dev);
|
2012-03-29 04:39:38 +08:00
|
|
|
|
2014-10-31 01:42:51 +08:00
|
|
|
I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
|
2012-03-29 04:39:38 +08:00
|
|
|
|
2014-10-31 01:42:58 +08:00
|
|
|
vlv_display_irq_reset(dev_priv);
|
2012-03-29 04:39:38 +08:00
|
|
|
}
|
|
|
|
|
2014-05-23 04:18:22 +08:00
|
|
|
static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
GEN8_IRQ_RESET_NDX(GT, 0);
|
|
|
|
GEN8_IRQ_RESET_NDX(GT, 1);
|
|
|
|
GEN8_IRQ_RESET_NDX(GT, 2);
|
|
|
|
GEN8_IRQ_RESET_NDX(GT, 3);
|
|
|
|
}
|
|
|
|
|
2014-04-02 02:37:26 +08:00
|
|
|
static void gen8_irq_reset(struct drm_device *dev)
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 12:07:09 +08:00
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
int pipe;
|
|
|
|
|
|
|
|
I915_WRITE(GEN8_MASTER_IRQ, 0);
|
|
|
|
POSTING_READ(GEN8_MASTER_IRQ);
|
|
|
|
|
2014-05-23 04:18:22 +08:00
|
|
|
gen8_gt_irq_reset(dev_priv);
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 12:07:09 +08:00
|
|
|
|
2014-08-18 20:49:10 +08:00
|
|
|
for_each_pipe(dev_priv, pipe)
|
2014-09-30 16:56:39 +08:00
|
|
|
if (intel_display_power_is_enabled(dev_priv,
|
|
|
|
POWER_DOMAIN_PIPE(pipe)))
|
2014-07-04 22:50:29 +08:00
|
|
|
GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 12:07:09 +08:00
|
|
|
|
2014-04-02 02:37:14 +08:00
|
|
|
GEN5_IRQ_RESET(GEN8_DE_PORT_);
|
|
|
|
GEN5_IRQ_RESET(GEN8_DE_MISC_);
|
|
|
|
GEN5_IRQ_RESET(GEN8_PCU_);
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 12:07:09 +08:00
|
|
|
|
2014-08-22 20:10:42 +08:00
|
|
|
if (HAS_PCH_SPLIT(dev))
|
|
|
|
ibx_irq_reset(dev);
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 12:07:09 +08:00
|
|
|
}
|
2014-01-11 05:13:09 +08:00
|
|
|
|
2015-03-07 02:50:48 +08:00
|
|
|
void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
|
|
|
|
unsigned int pipe_mask)
|
2014-07-04 22:50:31 +08:00
|
|
|
{
|
2014-10-08 05:02:52 +08:00
|
|
|
uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
|
2014-07-04 22:50:31 +08:00
|
|
|
|
2014-09-15 20:55:29 +08:00
|
|
|
spin_lock_irq(&dev_priv->irq_lock);
|
2015-03-07 02:50:51 +08:00
|
|
|
if (pipe_mask & 1 << PIPE_A)
|
|
|
|
GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_A,
|
|
|
|
dev_priv->de_irq_mask[PIPE_A],
|
|
|
|
~dev_priv->de_irq_mask[PIPE_A] | extra_ier);
|
2015-03-07 02:50:48 +08:00
|
|
|
if (pipe_mask & 1 << PIPE_B)
|
|
|
|
GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B,
|
|
|
|
dev_priv->de_irq_mask[PIPE_B],
|
|
|
|
~dev_priv->de_irq_mask[PIPE_B] | extra_ier);
|
|
|
|
if (pipe_mask & 1 << PIPE_C)
|
|
|
|
GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C,
|
|
|
|
dev_priv->de_irq_mask[PIPE_C],
|
|
|
|
~dev_priv->de_irq_mask[PIPE_C] | extra_ier);
|
2014-09-15 20:55:29 +08:00
|
|
|
spin_unlock_irq(&dev_priv->irq_lock);
|
2014-07-04 22:50:31 +08:00
|
|
|
}
|
|
|
|
|
2014-04-10 01:40:52 +08:00
|
|
|
static void cherryview_irq_preinstall(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
|
|
|
|
I915_WRITE(GEN8_MASTER_IRQ, 0);
|
|
|
|
POSTING_READ(GEN8_MASTER_IRQ);
|
|
|
|
|
2014-05-23 04:18:22 +08:00
|
|
|
gen8_gt_irq_reset(dev_priv);
|
2014-04-10 01:40:52 +08:00
|
|
|
|
|
|
|
GEN5_IRQ_RESET(GEN8_PCU_);
|
|
|
|
|
|
|
|
I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
|
|
|
|
|
2014-10-31 01:42:58 +08:00
|
|
|
vlv_display_irq_reset(dev_priv);
|
2014-04-10 01:40:52 +08:00
|
|
|
}
|
|
|
|
|
2013-03-27 22:55:01 +08:00
|
|
|
static void ibx_hpd_irq_setup(struct drm_device *dev)
|
2011-09-20 04:31:02 +08:00
|
|
|
{
|
2014-03-31 19:27:17 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2013-03-27 22:55:01 +08:00
|
|
|
struct intel_encoder *intel_encoder;
|
2013-07-05 05:35:21 +08:00
|
|
|
u32 hotplug_irqs, hotplug, enabled_irqs = 0;
|
2013-03-27 22:55:01 +08:00
|
|
|
|
|
|
|
if (HAS_PCH_IBX(dev)) {
|
2013-07-05 05:35:21 +08:00
|
|
|
hotplug_irqs = SDE_HOTPLUG_MASK;
|
2014-08-05 18:29:37 +08:00
|
|
|
for_each_intel_encoder(dev, intel_encoder)
|
2015-05-27 20:03:42 +08:00
|
|
|
if (dev_priv->hotplug.stats[intel_encoder->hpd_pin].state == HPD_ENABLED)
|
2013-07-05 05:35:21 +08:00
|
|
|
enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
|
2013-03-27 22:55:01 +08:00
|
|
|
} else {
|
2013-07-05 05:35:21 +08:00
|
|
|
hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
|
2014-08-05 18:29:37 +08:00
|
|
|
for_each_intel_encoder(dev, intel_encoder)
|
2015-05-27 20:03:42 +08:00
|
|
|
if (dev_priv->hotplug.stats[intel_encoder->hpd_pin].state == HPD_ENABLED)
|
2013-07-05 05:35:21 +08:00
|
|
|
enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin];
|
2013-03-27 22:55:01 +08:00
|
|
|
}
|
2011-09-20 04:31:02 +08:00
|
|
|
|
2013-07-05 05:35:21 +08:00
|
|
|
ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
|
2013-03-27 22:55:01 +08:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Enable digital hotplug on the PCH, and configure the DP short pulse
|
|
|
|
* duration to 2ms (which is the minimum in the Display Port spec)
|
|
|
|
*
|
|
|
|
* This register is the same on all known PCH chips.
|
|
|
|
*/
|
2011-09-20 04:31:02 +08:00
|
|
|
hotplug = I915_READ(PCH_PORT_HOTPLUG);
|
|
|
|
hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
|
|
|
|
hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
|
|
|
|
hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
|
|
|
|
hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
|
|
|
|
I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
|
|
|
|
}
|
|
|
|
|
2015-03-27 20:54:14 +08:00
|
|
|
static void bxt_hpd_irq_setup(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
struct intel_encoder *intel_encoder;
|
|
|
|
u32 hotplug_port = 0;
|
|
|
|
u32 hotplug_ctrl;
|
|
|
|
|
|
|
|
/* Now, enable HPD */
|
|
|
|
for_each_intel_encoder(dev, intel_encoder) {
|
2015-05-27 20:03:42 +08:00
|
|
|
if (dev_priv->hotplug.stats[intel_encoder->hpd_pin].state
|
2015-03-27 20:54:14 +08:00
|
|
|
== HPD_ENABLED)
|
|
|
|
hotplug_port |= hpd_bxt[intel_encoder->hpd_pin];
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Mask all HPD control bits */
|
|
|
|
hotplug_ctrl = I915_READ(BXT_HOTPLUG_CTL) & ~BXT_HOTPLUG_CTL_MASK;
|
|
|
|
|
|
|
|
/* Enable requested port in hotplug control */
|
|
|
|
/* TODO: implement (short) HPD support on port A */
|
|
|
|
WARN_ON_ONCE(hotplug_port & BXT_DE_PORT_HP_DDIA);
|
|
|
|
if (hotplug_port & BXT_DE_PORT_HP_DDIB)
|
|
|
|
hotplug_ctrl |= BXT_DDIB_HPD_ENABLE;
|
|
|
|
if (hotplug_port & BXT_DE_PORT_HP_DDIC)
|
|
|
|
hotplug_ctrl |= BXT_DDIC_HPD_ENABLE;
|
|
|
|
I915_WRITE(BXT_HOTPLUG_CTL, hotplug_ctrl);
|
|
|
|
|
|
|
|
/* Unmask DDI hotplug in IMR */
|
|
|
|
hotplug_ctrl = I915_READ(GEN8_DE_PORT_IMR) & ~hotplug_port;
|
|
|
|
I915_WRITE(GEN8_DE_PORT_IMR, hotplug_ctrl);
|
|
|
|
|
|
|
|
/* Enable DDI hotplug in IER */
|
|
|
|
hotplug_ctrl = I915_READ(GEN8_DE_PORT_IER) | hotplug_port;
|
|
|
|
I915_WRITE(GEN8_DE_PORT_IER, hotplug_ctrl);
|
|
|
|
POSTING_READ(GEN8_DE_PORT_IER);
|
|
|
|
}
|
|
|
|
|
2013-02-09 03:35:15 +08:00
|
|
|
static void ibx_irq_postinstall(struct drm_device *dev)
|
|
|
|
{
|
2014-03-31 19:27:17 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2013-03-27 22:55:01 +08:00
|
|
|
u32 mask;
|
2013-02-28 17:17:12 +08:00
|
|
|
|
2013-05-30 03:43:05 +08:00
|
|
|
if (HAS_PCH_NOP(dev))
|
|
|
|
return;
|
|
|
|
|
2014-04-02 02:37:17 +08:00
|
|
|
if (HAS_PCH_IBX(dev))
|
2014-03-08 03:34:46 +08:00
|
|
|
mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
|
2014-04-02 02:37:17 +08:00
|
|
|
else
|
2014-03-08 03:34:46 +08:00
|
|
|
mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
|
drm/i915: report Gen5+ CPU and PCH FIFO underruns
In this commit we enable both CPU and PCH FIFO underrun reporting and
start reporting them. We follow a few rules:
- after we receive one of these errors, we mask the interrupt, so
we won't get an "interrupt storm" and we also won't flood dmesg;
- at each mode set we enable the interrupts again, so we'll see each
message at most once per mode set;
- in the specific places where we need to ignore the errors, we
completely mask the interrupts.
The downside of this patch is that since we're completely disabling
(masking) the interrupts instead of just not printing error messages,
we will mask more than just what we want on IVB/HSW CPU interrupts
(due to GEN7_ERR_INT) and on CPT/PPT/LPT PCHs (due to SERR_INT). So
when we decide to mask PCH FIFO underruns for pipe A on CPT, we'll
also be masking PCH FIFO underruns for pipe B, because both are
reported by SERR_INT, which has to be either completely enabled or
completely disabled (in othe words, there's no way to disable/enable
specific bits of GEN7_ERR_INT and SERR_INT).
V2: Rename some functions and variables, downgrade messages to
DRM_DEBUG_DRIVER and rebase.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-13 04:57:57 +08:00
|
|
|
|
2014-04-02 02:37:16 +08:00
|
|
|
GEN5_ASSERT_IIR_IS_ZERO(SDEIIR);
|
2013-02-09 03:35:15 +08:00
|
|
|
I915_WRITE(SDEIMR, ~mask);
|
|
|
|
}
|
|
|
|
|
2013-07-13 04:43:26 +08:00
|
|
|
static void gen5_gt_irq_postinstall(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
u32 pm_irqs, gt_irqs;
|
|
|
|
|
|
|
|
pm_irqs = gt_irqs = 0;
|
|
|
|
|
|
|
|
dev_priv->gt_irq_mask = ~0;
|
2013-09-20 02:01:40 +08:00
|
|
|
if (HAS_L3_DPF(dev)) {
|
2013-07-13 04:43:26 +08:00
|
|
|
/* L3 parity interrupt is always unmasked. */
|
2013-09-20 02:13:41 +08:00
|
|
|
dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
|
|
|
|
gt_irqs |= GT_PARITY_ERROR(dev);
|
2013-07-13 04:43:26 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
gt_irqs |= GT_RENDER_USER_INTERRUPT;
|
|
|
|
if (IS_GEN5(dev)) {
|
|
|
|
gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
|
|
|
|
ILK_BSD_USER_INTERRUPT;
|
|
|
|
} else {
|
|
|
|
gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
|
|
|
|
}
|
|
|
|
|
2014-04-02 02:37:15 +08:00
|
|
|
GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
|
2013-07-13 04:43:26 +08:00
|
|
|
|
|
|
|
if (INTEL_INFO(dev)->gen >= 6) {
|
2014-12-16 00:59:27 +08:00
|
|
|
/*
|
|
|
|
* RPS interrupts will get enabled/disabled on demand when RPS
|
|
|
|
* itself is enabled/disabled.
|
|
|
|
*/
|
2013-07-13 04:43:26 +08:00
|
|
|
if (HAS_VEBOX(dev))
|
|
|
|
pm_irqs |= PM_VEBOX_USER_INTERRUPT;
|
|
|
|
|
2013-08-07 05:57:15 +08:00
|
|
|
dev_priv->pm_irq_mask = 0xffffffff;
|
2014-04-02 02:37:15 +08:00
|
|
|
GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs);
|
2013-07-13 04:43:26 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-06-29 04:00:41 +08:00
|
|
|
static int ironlake_irq_postinstall(struct drm_device *dev)
|
2009-06-08 14:40:19 +08:00
|
|
|
{
|
2014-03-31 19:27:17 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2013-07-13 07:01:56 +08:00
|
|
|
u32 display_mask, extra_mask;
|
|
|
|
|
|
|
|
if (INTEL_INFO(dev)->gen >= 7) {
|
|
|
|
display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
|
|
|
|
DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
|
|
|
|
DE_PLANEB_FLIP_DONE_IVB |
|
2014-03-08 03:34:46 +08:00
|
|
|
DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
|
2013-07-13 07:01:56 +08:00
|
|
|
extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
|
2014-03-08 03:34:46 +08:00
|
|
|
DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB);
|
2013-07-13 07:01:56 +08:00
|
|
|
} else {
|
|
|
|
display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
|
|
|
|
DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
|
2013-10-17 04:55:48 +08:00
|
|
|
DE_AUX_CHANNEL_A |
|
|
|
|
DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
|
|
|
|
DE_POISON);
|
2014-03-08 03:34:46 +08:00
|
|
|
extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
|
|
|
|
DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN;
|
2013-07-13 07:01:56 +08:00
|
|
|
}
|
2009-06-08 14:40:19 +08:00
|
|
|
|
2010-12-04 19:30:53 +08:00
|
|
|
dev_priv->irq_mask = ~display_mask;
|
2009-06-08 14:40:19 +08:00
|
|
|
|
2014-04-02 02:37:27 +08:00
|
|
|
I915_WRITE(HWSTAM, 0xeffe);
|
|
|
|
|
2014-04-02 02:37:22 +08:00
|
|
|
ibx_irq_pre_postinstall(dev);
|
|
|
|
|
2014-04-02 02:37:15 +08:00
|
|
|
GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
|
2009-06-08 14:40:19 +08:00
|
|
|
|
2013-07-13 04:43:26 +08:00
|
|
|
gen5_gt_irq_postinstall(dev);
|
2009-06-08 14:40:19 +08:00
|
|
|
|
2013-02-09 03:35:15 +08:00
|
|
|
ibx_irq_postinstall(dev);
|
2011-09-20 04:31:02 +08:00
|
|
|
|
2010-01-30 03:27:07 +08:00
|
|
|
if (IS_IRONLAKE_M(dev)) {
|
2013-06-27 19:44:59 +08:00
|
|
|
/* Enable PCU event interrupts
|
|
|
|
*
|
|
|
|
* spinlocking not required here for correctness since interrupt
|
2013-06-27 19:44:58 +08:00
|
|
|
* setup is guaranteed to run in single-threaded context. But we
|
|
|
|
* need it to make the assert_spin_locked happy. */
|
2014-09-15 20:55:27 +08:00
|
|
|
spin_lock_irq(&dev_priv->irq_lock);
|
2010-01-30 03:27:07 +08:00
|
|
|
ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
|
2014-09-15 20:55:27 +08:00
|
|
|
spin_unlock_irq(&dev_priv->irq_lock);
|
2010-01-30 03:27:07 +08:00
|
|
|
}
|
|
|
|
|
2009-06-08 14:40:19 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-03-05 01:23:07 +08:00
|
|
|
static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
u32 pipestat_mask;
|
|
|
|
u32 iir_mask;
|
2014-10-31 01:42:57 +08:00
|
|
|
enum pipe pipe;
|
2014-03-05 01:23:07 +08:00
|
|
|
|
|
|
|
pipestat_mask = PIPESTAT_INT_STATUS_MASK |
|
|
|
|
PIPE_FIFO_UNDERRUN_STATUS;
|
|
|
|
|
2014-10-31 01:42:57 +08:00
|
|
|
for_each_pipe(dev_priv, pipe)
|
|
|
|
I915_WRITE(PIPESTAT(pipe), pipestat_mask);
|
2014-03-05 01:23:07 +08:00
|
|
|
POSTING_READ(PIPESTAT(PIPE_A));
|
|
|
|
|
|
|
|
pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
|
|
|
|
PIPE_CRC_DONE_INTERRUPT_STATUS;
|
|
|
|
|
2014-10-31 01:42:57 +08:00
|
|
|
i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
|
|
|
|
for_each_pipe(dev_priv, pipe)
|
|
|
|
i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
|
2014-03-05 01:23:07 +08:00
|
|
|
|
|
|
|
iir_mask = I915_DISPLAY_PORT_INTERRUPT |
|
|
|
|
I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
|
|
|
|
I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
|
2014-10-31 01:42:57 +08:00
|
|
|
if (IS_CHERRYVIEW(dev_priv))
|
|
|
|
iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
|
2014-03-05 01:23:07 +08:00
|
|
|
dev_priv->irq_mask &= ~iir_mask;
|
|
|
|
|
|
|
|
I915_WRITE(VLV_IIR, iir_mask);
|
|
|
|
I915_WRITE(VLV_IIR, iir_mask);
|
|
|
|
I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
|
2014-10-31 01:42:54 +08:00
|
|
|
I915_WRITE(VLV_IMR, dev_priv->irq_mask);
|
|
|
|
POSTING_READ(VLV_IMR);
|
2014-03-05 01:23:07 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
u32 pipestat_mask;
|
|
|
|
u32 iir_mask;
|
2014-10-31 01:42:57 +08:00
|
|
|
enum pipe pipe;
|
2014-03-05 01:23:07 +08:00
|
|
|
|
|
|
|
iir_mask = I915_DISPLAY_PORT_INTERRUPT |
|
|
|
|
I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
|
2014-03-11 01:44:48 +08:00
|
|
|
I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
|
2014-10-31 01:42:57 +08:00
|
|
|
if (IS_CHERRYVIEW(dev_priv))
|
|
|
|
iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
|
2014-03-05 01:23:07 +08:00
|
|
|
|
|
|
|
dev_priv->irq_mask |= iir_mask;
|
|
|
|
I915_WRITE(VLV_IMR, dev_priv->irq_mask);
|
2014-10-31 01:42:54 +08:00
|
|
|
I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
|
2014-03-05 01:23:07 +08:00
|
|
|
I915_WRITE(VLV_IIR, iir_mask);
|
|
|
|
I915_WRITE(VLV_IIR, iir_mask);
|
|
|
|
POSTING_READ(VLV_IIR);
|
|
|
|
|
|
|
|
pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
|
|
|
|
PIPE_CRC_DONE_INTERRUPT_STATUS;
|
|
|
|
|
2014-10-31 01:42:57 +08:00
|
|
|
i915_disable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
|
|
|
|
for_each_pipe(dev_priv, pipe)
|
|
|
|
i915_disable_pipestat(dev_priv, pipe, pipestat_mask);
|
2014-03-05 01:23:07 +08:00
|
|
|
|
|
|
|
pipestat_mask = PIPESTAT_INT_STATUS_MASK |
|
|
|
|
PIPE_FIFO_UNDERRUN_STATUS;
|
2014-10-31 01:42:57 +08:00
|
|
|
|
|
|
|
for_each_pipe(dev_priv, pipe)
|
|
|
|
I915_WRITE(PIPESTAT(pipe), pipestat_mask);
|
2014-03-05 01:23:07 +08:00
|
|
|
POSTING_READ(PIPESTAT(PIPE_A));
|
|
|
|
}
|
|
|
|
|
|
|
|
void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
assert_spin_locked(&dev_priv->irq_lock);
|
|
|
|
|
|
|
|
if (dev_priv->display_irqs_enabled)
|
|
|
|
return;
|
|
|
|
|
|
|
|
dev_priv->display_irqs_enabled = true;
|
|
|
|
|
2014-09-08 20:21:09 +08:00
|
|
|
if (intel_irqs_enabled(dev_priv))
|
2014-03-05 01:23:07 +08:00
|
|
|
valleyview_display_irqs_install(dev_priv);
|
|
|
|
}
|
|
|
|
|
|
|
|
void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
assert_spin_locked(&dev_priv->irq_lock);
|
|
|
|
|
|
|
|
if (!dev_priv->display_irqs_enabled)
|
|
|
|
return;
|
|
|
|
|
|
|
|
dev_priv->display_irqs_enabled = false;
|
|
|
|
|
2014-09-08 20:21:09 +08:00
|
|
|
if (intel_irqs_enabled(dev_priv))
|
2014-03-05 01:23:07 +08:00
|
|
|
valleyview_display_irqs_uninstall(dev_priv);
|
|
|
|
}
|
|
|
|
|
2014-10-31 01:43:00 +08:00
|
|
|
static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
|
2012-03-29 04:39:38 +08:00
|
|
|
{
|
2014-03-05 01:23:07 +08:00
|
|
|
dev_priv->irq_mask = ~0;
|
2012-03-29 04:39:38 +08:00
|
|
|
|
2012-12-11 21:05:07 +08:00
|
|
|
I915_WRITE(PORT_HOTPLUG_EN, 0);
|
|
|
|
POSTING_READ(PORT_HOTPLUG_EN);
|
|
|
|
|
2012-03-29 04:39:38 +08:00
|
|
|
I915_WRITE(VLV_IIR, 0xffffffff);
|
2014-10-31 01:42:54 +08:00
|
|
|
I915_WRITE(VLV_IIR, 0xffffffff);
|
|
|
|
I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
|
|
|
|
I915_WRITE(VLV_IMR, dev_priv->irq_mask);
|
|
|
|
POSTING_READ(VLV_IMR);
|
2012-03-29 04:39:38 +08:00
|
|
|
|
2013-06-27 23:52:10 +08:00
|
|
|
/* Interrupt setup is already guaranteed to be single-threaded, this is
|
|
|
|
* just to make the assert_spin_locked check happy. */
|
2014-09-15 20:55:27 +08:00
|
|
|
spin_lock_irq(&dev_priv->irq_lock);
|
2014-03-05 01:23:07 +08:00
|
|
|
if (dev_priv->display_irqs_enabled)
|
|
|
|
valleyview_display_irqs_install(dev_priv);
|
2014-09-15 20:55:27 +08:00
|
|
|
spin_unlock_irq(&dev_priv->irq_lock);
|
2014-10-31 01:43:00 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static int valleyview_irq_postinstall(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
|
|
|
|
vlv_display_irq_postinstall(dev_priv);
|
2012-03-29 04:39:38 +08:00
|
|
|
|
2013-07-13 04:43:26 +08:00
|
|
|
gen5_gt_irq_postinstall(dev);
|
2012-03-29 04:39:38 +08:00
|
|
|
|
|
|
|
/* ack & enable invalid PTE error interrupts */
|
|
|
|
#if 0 /* FIXME: add support to irq handler for checking these bits */
|
|
|
|
I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
|
|
|
|
I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
|
|
|
|
#endif
|
|
|
|
|
|
|
|
I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
|
2012-12-11 21:05:07 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 12:07:09 +08:00
|
|
|
static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
/* These are interrupts we'll toggle with the ring mask register */
|
|
|
|
uint32_t gt_interrupts[] = {
|
|
|
|
GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
|
2014-07-25 00:04:31 +08:00
|
|
|
GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 12:07:09 +08:00
|
|
|
GT_RENDER_L3_PARITY_ERROR_INTERRUPT |
|
2014-07-25 00:04:31 +08:00
|
|
|
GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT |
|
|
|
|
GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 12:07:09 +08:00
|
|
|
GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
|
2014-07-25 00:04:31 +08:00
|
|
|
GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
|
|
|
|
GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT |
|
|
|
|
GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 12:07:09 +08:00
|
|
|
0,
|
2014-07-25 00:04:31 +08:00
|
|
|
GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT |
|
|
|
|
GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 12:07:09 +08:00
|
|
|
};
|
|
|
|
|
2014-05-16 01:58:08 +08:00
|
|
|
dev_priv->pm_irq_mask = 0xffffffff;
|
2014-08-22 11:02:40 +08:00
|
|
|
GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
|
|
|
|
GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
|
2014-12-16 00:59:27 +08:00
|
|
|
/*
|
|
|
|
* RPS interrupts will get enabled/disabled on demand when RPS itself
|
|
|
|
* is enabled/disabled.
|
|
|
|
*/
|
|
|
|
GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_irq_mask, 0);
|
2014-08-22 11:02:40 +08:00
|
|
|
GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 12:07:09 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
2014-03-21 04:45:01 +08:00
|
|
|
uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
|
|
|
|
uint32_t de_pipe_enables;
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 12:07:09 +08:00
|
|
|
int pipe;
|
2014-08-22 20:10:43 +08:00
|
|
|
u32 de_port_en = GEN8_AUX_CHANNEL_A;
|
2014-03-21 04:45:01 +08:00
|
|
|
|
2014-11-14 01:51:48 +08:00
|
|
|
if (IS_GEN9(dev_priv)) {
|
2014-03-21 04:45:01 +08:00
|
|
|
de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE |
|
|
|
|
GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
|
2014-08-22 20:10:43 +08:00
|
|
|
de_port_en |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
|
2014-11-14 01:51:48 +08:00
|
|
|
GEN9_AUX_CHANNEL_D;
|
2014-08-22 20:10:43 +08:00
|
|
|
|
|
|
|
if (IS_BROXTON(dev_priv))
|
|
|
|
de_port_en |= BXT_DE_PORT_GMBUS;
|
2014-11-14 01:51:48 +08:00
|
|
|
} else
|
2014-03-21 04:45:01 +08:00
|
|
|
de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
|
|
|
|
GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
|
|
|
|
|
|
|
|
de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
|
|
|
|
GEN8_PIPE_FIFO_UNDERRUN;
|
|
|
|
|
2013-11-07 22:31:52 +08:00
|
|
|
dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
|
|
|
|
dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
|
|
|
|
dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 12:07:09 +08:00
|
|
|
|
2014-08-18 20:49:10 +08:00
|
|
|
for_each_pipe(dev_priv, pipe)
|
2014-09-30 16:56:39 +08:00
|
|
|
if (intel_display_power_is_enabled(dev_priv,
|
2014-07-04 22:50:29 +08:00
|
|
|
POWER_DOMAIN_PIPE(pipe)))
|
|
|
|
GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
|
|
|
|
dev_priv->de_irq_mask[pipe],
|
|
|
|
de_pipe_enables);
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 12:07:09 +08:00
|
|
|
|
2014-08-22 20:10:43 +08:00
|
|
|
GEN5_IRQ_INIT(GEN8_DE_PORT_, ~de_port_en, de_port_en);
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 12:07:09 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static int gen8_irq_postinstall(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
|
2014-08-22 20:10:42 +08:00
|
|
|
if (HAS_PCH_SPLIT(dev))
|
|
|
|
ibx_irq_pre_postinstall(dev);
|
2014-04-02 02:37:22 +08:00
|
|
|
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 12:07:09 +08:00
|
|
|
gen8_gt_irq_postinstall(dev_priv);
|
|
|
|
gen8_de_irq_postinstall(dev_priv);
|
|
|
|
|
2014-08-22 20:10:42 +08:00
|
|
|
if (HAS_PCH_SPLIT(dev))
|
|
|
|
ibx_irq_postinstall(dev);
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 12:07:09 +08:00
|
|
|
|
|
|
|
I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
|
|
|
|
POSTING_READ(GEN8_MASTER_IRQ);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-04-10 01:40:52 +08:00
|
|
|
static int cherryview_irq_postinstall(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
|
2014-10-31 01:43:02 +08:00
|
|
|
vlv_display_irq_postinstall(dev_priv);
|
2014-04-10 01:40:52 +08:00
|
|
|
|
|
|
|
gen8_gt_irq_postinstall(dev_priv);
|
|
|
|
|
|
|
|
I915_WRITE(GEN8_MASTER_IRQ, MASTER_INTERRUPT_ENABLE);
|
|
|
|
POSTING_READ(GEN8_MASTER_IRQ);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 12:07:09 +08:00
|
|
|
static void gen8_irq_uninstall(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
|
|
|
|
if (!dev_priv)
|
|
|
|
return;
|
|
|
|
|
2014-04-02 02:37:26 +08:00
|
|
|
gen8_irq_reset(dev);
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 12:07:09 +08:00
|
|
|
}
|
|
|
|
|
2014-10-31 01:42:59 +08:00
|
|
|
static void vlv_display_irq_uninstall(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
/* Interrupt setup is already guaranteed to be single-threaded, this is
|
|
|
|
* just to make the assert_spin_locked check happy. */
|
|
|
|
spin_lock_irq(&dev_priv->irq_lock);
|
|
|
|
if (dev_priv->display_irqs_enabled)
|
|
|
|
valleyview_display_irqs_uninstall(dev_priv);
|
|
|
|
spin_unlock_irq(&dev_priv->irq_lock);
|
|
|
|
|
|
|
|
vlv_display_irq_reset(dev_priv);
|
|
|
|
|
2014-11-20 22:05:55 +08:00
|
|
|
dev_priv->irq_mask = ~0;
|
2014-10-31 01:42:59 +08:00
|
|
|
}
|
|
|
|
|
2012-03-29 04:39:38 +08:00
|
|
|
static void valleyview_irq_uninstall(struct drm_device *dev)
|
|
|
|
{
|
2014-03-31 19:27:17 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2012-03-29 04:39:38 +08:00
|
|
|
|
|
|
|
if (!dev_priv)
|
|
|
|
return;
|
|
|
|
|
2014-04-15 01:24:23 +08:00
|
|
|
I915_WRITE(VLV_MASTER_IER, 0);
|
|
|
|
|
2014-10-31 01:42:56 +08:00
|
|
|
gen5_gt_irq_reset(dev);
|
|
|
|
|
2012-03-29 04:39:38 +08:00
|
|
|
I915_WRITE(HWSTAM, 0xffffffff);
|
2014-03-05 01:23:07 +08:00
|
|
|
|
2014-10-31 01:42:59 +08:00
|
|
|
vlv_display_irq_uninstall(dev_priv);
|
2012-03-29 04:39:38 +08:00
|
|
|
}
|
|
|
|
|
2014-04-10 01:40:52 +08:00
|
|
|
static void cherryview_irq_uninstall(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
|
|
|
|
if (!dev_priv)
|
|
|
|
return;
|
|
|
|
|
|
|
|
I915_WRITE(GEN8_MASTER_IRQ, 0);
|
|
|
|
POSTING_READ(GEN8_MASTER_IRQ);
|
|
|
|
|
2014-10-31 01:42:52 +08:00
|
|
|
gen8_gt_irq_reset(dev_priv);
|
2014-04-10 01:40:52 +08:00
|
|
|
|
2014-10-31 01:42:52 +08:00
|
|
|
GEN5_IRQ_RESET(GEN8_PCU_);
|
2014-04-10 01:40:52 +08:00
|
|
|
|
2014-10-31 01:43:02 +08:00
|
|
|
vlv_display_irq_uninstall(dev_priv);
|
2014-04-10 01:40:52 +08:00
|
|
|
}
|
|
|
|
|
2011-06-29 04:00:41 +08:00
|
|
|
static void ironlake_irq_uninstall(struct drm_device *dev)
|
2009-06-08 14:40:19 +08:00
|
|
|
{
|
2014-03-31 19:27:17 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2011-04-08 04:53:55 +08:00
|
|
|
|
|
|
|
if (!dev_priv)
|
|
|
|
return;
|
|
|
|
|
2014-04-02 02:37:25 +08:00
|
|
|
ironlake_irq_reset(dev);
|
2009-06-08 14:40:19 +08:00
|
|
|
}
|
|
|
|
|
2012-04-25 05:59:44 +08:00
|
|
|
static void i8xx_irq_preinstall(struct drm_device * dev)
|
2005-04-17 06:20:36 +08:00
|
|
|
{
|
2014-03-31 19:27:17 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2011-02-08 04:26:52 +08:00
|
|
|
int pipe;
|
2006-02-18 12:17:04 +08:00
|
|
|
|
2014-08-18 20:49:10 +08:00
|
|
|
for_each_pipe(dev_priv, pipe)
|
2011-02-08 04:26:52 +08:00
|
|
|
I915_WRITE(PIPESTAT(pipe), 0);
|
2012-04-25 05:59:44 +08:00
|
|
|
I915_WRITE16(IMR, 0xffff);
|
|
|
|
I915_WRITE16(IER, 0x0);
|
|
|
|
POSTING_READ16(IER);
|
2012-04-23 04:13:57 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static int i8xx_irq_postinstall(struct drm_device *dev)
|
|
|
|
{
|
2014-03-31 19:27:17 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2012-04-23 04:13:57 +08:00
|
|
|
|
|
|
|
I915_WRITE16(EMR,
|
|
|
|
~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
|
|
|
|
|
|
|
|
/* Unmask the interrupts that we always want on. */
|
|
|
|
dev_priv->irq_mask =
|
|
|
|
~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
|
|
|
|
I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
|
|
|
|
I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
|
2015-04-01 19:43:46 +08:00
|
|
|
I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
|
2012-04-23 04:13:57 +08:00
|
|
|
I915_WRITE16(IMR, dev_priv->irq_mask);
|
|
|
|
|
|
|
|
I915_WRITE16(IER,
|
|
|
|
I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
|
|
|
|
I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
|
|
|
|
I915_USER_INTERRUPT);
|
|
|
|
POSTING_READ16(IER);
|
|
|
|
|
2013-10-17 04:55:56 +08:00
|
|
|
/* Interrupt setup is already guaranteed to be single-threaded, this is
|
|
|
|
* just to make the assert_spin_locked check happy. */
|
2014-09-15 20:55:27 +08:00
|
|
|
spin_lock_irq(&dev_priv->irq_lock);
|
2014-02-11 00:42:47 +08:00
|
|
|
i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
|
|
|
|
i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
|
2014-09-15 20:55:27 +08:00
|
|
|
spin_unlock_irq(&dev_priv->irq_lock);
|
2013-10-17 04:55:56 +08:00
|
|
|
|
2012-04-23 04:13:57 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2013-02-20 05:16:44 +08:00
|
|
|
/*
|
|
|
|
* Returns true when a page flip has completed.
|
|
|
|
*/
|
|
|
|
static bool i8xx_handle_vblank(struct drm_device *dev,
|
2013-11-28 23:30:01 +08:00
|
|
|
int plane, int pipe, u32 iir)
|
2013-02-20 05:16:44 +08:00
|
|
|
{
|
2014-03-31 19:27:17 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2013-11-28 23:30:01 +08:00
|
|
|
u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
|
2013-02-20 05:16:44 +08:00
|
|
|
|
2014-04-29 18:35:46 +08:00
|
|
|
if (!intel_pipe_handle_vblank(dev, pipe))
|
2013-02-20 05:16:44 +08:00
|
|
|
return false;
|
|
|
|
|
|
|
|
if ((iir & flip_pending) == 0)
|
drm/i915: Check for a stalled page flip after each vblank
Long ago, back in the racy haydays of 915gm interrupt handling, page
flips would occasionally go astray and leave the hardware stuck, and the
display not updating. This annoyed people who relied on their systems
being able to display continuously updating information 24/7, and so
some code to detect when the driver missed the page flip completion
signal was added. Until recently, it was presumed that the interrupt
handling was now flawless, but once again Simon Farnsworth has found a
system whose display will stall. Reinstate the pageflip stall detection,
which works by checking to see if the hardware has been updated to the
new framebuffer address following each vblank. If the hardware is
scanning out from the new framebuffer, but we still think the flip is
pending, then we kick our driver into submision.
This is a continuation of the effort started with
commit 4e5359cd053bfb7d8dabe4a63624a5726848ffbc
Author: Simon Farnsworth <simon.farnsworth@onelan.co.uk>
Date: Wed Sep 1 17:47:52 2010 +0100
drm/i915: Avoid pageflipping freeze when we miss the flip prepare interrupt
This now includes a belt-and-braces approach to make sure the driver
(or the hardware) doesn't miss an interrupt and cause us to stop
updating the display should the unthinkable happen and the pageflip fail - i.e.
that the user is able to continue submitting flips.
v2: Cleanup, refactor, and rename
v3: Only start counting vblanks after the flip command has been seen by
the hardware.
v4: Record the seqno after we touch the ring, or else there may be no
seqno allocated yet.
v5: Rebase on mmio-flip.
v6: Rebase, rebase.
Reported-by: Simon Farnsworth <simon@farnz.org.uk>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75502
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> [v4]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-05 14:13:24 +08:00
|
|
|
goto check_page_flip;
|
2013-02-20 05:16:44 +08:00
|
|
|
|
|
|
|
/* We detect FlipDone by looking for the change in PendingFlip from '1'
|
|
|
|
* to '0' on the following vblank, i.e. IIR has the Pendingflip
|
|
|
|
* asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
|
|
|
|
* the flip is completed (no longer pending). Since this doesn't raise
|
|
|
|
* an interrupt per se, we watch for the change at vblank.
|
|
|
|
*/
|
|
|
|
if (I915_READ16(ISR) & flip_pending)
|
drm/i915: Check for a stalled page flip after each vblank
Long ago, back in the racy haydays of 915gm interrupt handling, page
flips would occasionally go astray and leave the hardware stuck, and the
display not updating. This annoyed people who relied on their systems
being able to display continuously updating information 24/7, and so
some code to detect when the driver missed the page flip completion
signal was added. Until recently, it was presumed that the interrupt
handling was now flawless, but once again Simon Farnsworth has found a
system whose display will stall. Reinstate the pageflip stall detection,
which works by checking to see if the hardware has been updated to the
new framebuffer address following each vblank. If the hardware is
scanning out from the new framebuffer, but we still think the flip is
pending, then we kick our driver into submision.
This is a continuation of the effort started with
commit 4e5359cd053bfb7d8dabe4a63624a5726848ffbc
Author: Simon Farnsworth <simon.farnsworth@onelan.co.uk>
Date: Wed Sep 1 17:47:52 2010 +0100
drm/i915: Avoid pageflipping freeze when we miss the flip prepare interrupt
This now includes a belt-and-braces approach to make sure the driver
(or the hardware) doesn't miss an interrupt and cause us to stop
updating the display should the unthinkable happen and the pageflip fail - i.e.
that the user is able to continue submitting flips.
v2: Cleanup, refactor, and rename
v3: Only start counting vblanks after the flip command has been seen by
the hardware.
v4: Record the seqno after we touch the ring, or else there may be no
seqno allocated yet.
v5: Rebase on mmio-flip.
v6: Rebase, rebase.
Reported-by: Simon Farnsworth <simon@farnz.org.uk>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75502
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> [v4]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-05 14:13:24 +08:00
|
|
|
goto check_page_flip;
|
2013-02-20 05:16:44 +08:00
|
|
|
|
2014-12-18 05:08:03 +08:00
|
|
|
intel_prepare_page_flip(dev, plane);
|
2013-02-20 05:16:44 +08:00
|
|
|
intel_finish_page_flip(dev, pipe);
|
|
|
|
return true;
|
drm/i915: Check for a stalled page flip after each vblank
Long ago, back in the racy haydays of 915gm interrupt handling, page
flips would occasionally go astray and leave the hardware stuck, and the
display not updating. This annoyed people who relied on their systems
being able to display continuously updating information 24/7, and so
some code to detect when the driver missed the page flip completion
signal was added. Until recently, it was presumed that the interrupt
handling was now flawless, but once again Simon Farnsworth has found a
system whose display will stall. Reinstate the pageflip stall detection,
which works by checking to see if the hardware has been updated to the
new framebuffer address following each vblank. If the hardware is
scanning out from the new framebuffer, but we still think the flip is
pending, then we kick our driver into submision.
This is a continuation of the effort started with
commit 4e5359cd053bfb7d8dabe4a63624a5726848ffbc
Author: Simon Farnsworth <simon.farnsworth@onelan.co.uk>
Date: Wed Sep 1 17:47:52 2010 +0100
drm/i915: Avoid pageflipping freeze when we miss the flip prepare interrupt
This now includes a belt-and-braces approach to make sure the driver
(or the hardware) doesn't miss an interrupt and cause us to stop
updating the display should the unthinkable happen and the pageflip fail - i.e.
that the user is able to continue submitting flips.
v2: Cleanup, refactor, and rename
v3: Only start counting vblanks after the flip command has been seen by
the hardware.
v4: Record the seqno after we touch the ring, or else there may be no
seqno allocated yet.
v5: Rebase on mmio-flip.
v6: Rebase, rebase.
Reported-by: Simon Farnsworth <simon@farnz.org.uk>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75502
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> [v4]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-05 14:13:24 +08:00
|
|
|
|
|
|
|
check_page_flip:
|
|
|
|
intel_check_page_flip(dev, pipe);
|
|
|
|
return false;
|
2013-02-20 05:16:44 +08:00
|
|
|
}
|
|
|
|
|
2012-10-02 21:10:55 +08:00
|
|
|
static irqreturn_t i8xx_irq_handler(int irq, void *arg)
|
2012-04-23 04:13:57 +08:00
|
|
|
{
|
2014-05-13 01:17:55 +08:00
|
|
|
struct drm_device *dev = arg;
|
2014-03-31 19:27:17 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2012-04-23 04:13:57 +08:00
|
|
|
u16 iir, new_iir;
|
|
|
|
u32 pipe_stats[2];
|
|
|
|
int pipe;
|
|
|
|
u16 flip_mask =
|
|
|
|
I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
|
|
|
|
I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
|
|
|
|
|
2015-02-24 17:14:30 +08:00
|
|
|
if (!intel_irqs_enabled(dev_priv))
|
|
|
|
return IRQ_NONE;
|
|
|
|
|
2012-04-23 04:13:57 +08:00
|
|
|
iir = I915_READ16(IIR);
|
|
|
|
if (iir == 0)
|
|
|
|
return IRQ_NONE;
|
|
|
|
|
|
|
|
while (iir & ~flip_mask) {
|
|
|
|
/* Can't rely on pipestat interrupt bit in iir as it might
|
|
|
|
* have been cleared after the pipestat interrupt was received.
|
|
|
|
* It doesn't set the bit in iir again, but it still produces
|
|
|
|
* interrupts (for non-MSI).
|
|
|
|
*/
|
2014-09-15 20:55:28 +08:00
|
|
|
spin_lock(&dev_priv->irq_lock);
|
2012-04-23 04:13:57 +08:00
|
|
|
if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
|
2014-11-04 22:52:22 +08:00
|
|
|
DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
|
2012-04-23 04:13:57 +08:00
|
|
|
|
2014-08-18 20:49:10 +08:00
|
|
|
for_each_pipe(dev_priv, pipe) {
|
2012-04-23 04:13:57 +08:00
|
|
|
int reg = PIPESTAT(pipe);
|
|
|
|
pipe_stats[pipe] = I915_READ(reg);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Clear the PIPE*STAT regs before the IIR
|
|
|
|
*/
|
2014-01-17 17:44:31 +08:00
|
|
|
if (pipe_stats[pipe] & 0x8000ffff)
|
2012-04-23 04:13:57 +08:00
|
|
|
I915_WRITE(reg, pipe_stats[pipe]);
|
|
|
|
}
|
2014-09-15 20:55:28 +08:00
|
|
|
spin_unlock(&dev_priv->irq_lock);
|
2012-04-23 04:13:57 +08:00
|
|
|
|
|
|
|
I915_WRITE16(IIR, iir & ~flip_mask);
|
|
|
|
new_iir = I915_READ16(IIR); /* Flush posted writes */
|
|
|
|
|
|
|
|
if (iir & I915_USER_INTERRUPT)
|
2015-04-07 23:21:05 +08:00
|
|
|
notify_ring(&dev_priv->ring[RCS]);
|
2012-04-23 04:13:57 +08:00
|
|
|
|
2014-08-18 20:49:10 +08:00
|
|
|
for_each_pipe(dev_priv, pipe) {
|
2013-11-28 23:30:01 +08:00
|
|
|
int plane = pipe;
|
2014-01-10 15:50:12 +08:00
|
|
|
if (HAS_FBC(dev))
|
2013-11-28 23:30:01 +08:00
|
|
|
plane = !plane;
|
|
|
|
|
2013-10-17 04:55:55 +08:00
|
|
|
if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
|
2013-11-28 23:30:01 +08:00
|
|
|
i8xx_handle_vblank(dev, plane, pipe, iir))
|
|
|
|
flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
|
2012-04-23 04:13:57 +08:00
|
|
|
|
2013-10-17 04:55:55 +08:00
|
|
|
if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
|
2013-10-18 22:37:07 +08:00
|
|
|
i9xx_pipe_crc_irq_handler(dev, pipe);
|
2014-01-17 17:44:31 +08:00
|
|
|
|
2014-09-30 16:56:48 +08:00
|
|
|
if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
|
|
|
|
intel_cpu_fifo_underrun_irq_handler(dev_priv,
|
|
|
|
pipe);
|
2013-10-17 04:55:55 +08:00
|
|
|
}
|
2012-04-23 04:13:57 +08:00
|
|
|
|
|
|
|
iir = new_iir;
|
|
|
|
}
|
|
|
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void i8xx_irq_uninstall(struct drm_device * dev)
|
|
|
|
{
|
2014-03-31 19:27:17 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2012-04-23 04:13:57 +08:00
|
|
|
int pipe;
|
|
|
|
|
2014-08-18 20:49:10 +08:00
|
|
|
for_each_pipe(dev_priv, pipe) {
|
2012-04-23 04:13:57 +08:00
|
|
|
/* Clear enable bits; then clear status bits */
|
|
|
|
I915_WRITE(PIPESTAT(pipe), 0);
|
|
|
|
I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
|
|
|
|
}
|
|
|
|
I915_WRITE16(IMR, 0xffff);
|
|
|
|
I915_WRITE16(IER, 0x0);
|
|
|
|
I915_WRITE16(IIR, I915_READ16(IIR));
|
|
|
|
}
|
|
|
|
|
2012-04-25 05:59:44 +08:00
|
|
|
static void i915_irq_preinstall(struct drm_device * dev)
|
|
|
|
{
|
2014-03-31 19:27:17 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2012-04-25 05:59:44 +08:00
|
|
|
int pipe;
|
|
|
|
|
|
|
|
if (I915_HAS_HOTPLUG(dev)) {
|
|
|
|
I915_WRITE(PORT_HOTPLUG_EN, 0);
|
|
|
|
I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
|
|
|
|
}
|
|
|
|
|
2012-04-25 05:59:48 +08:00
|
|
|
I915_WRITE16(HWSTAM, 0xeffe);
|
2014-08-18 20:49:10 +08:00
|
|
|
for_each_pipe(dev_priv, pipe)
|
2012-04-25 05:59:44 +08:00
|
|
|
I915_WRITE(PIPESTAT(pipe), 0);
|
|
|
|
I915_WRITE(IMR, 0xffffffff);
|
|
|
|
I915_WRITE(IER, 0x0);
|
|
|
|
POSTING_READ(IER);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int i915_irq_postinstall(struct drm_device *dev)
|
|
|
|
{
|
2014-03-31 19:27:17 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2012-04-25 05:59:50 +08:00
|
|
|
u32 enable_mask;
|
2012-04-25 05:59:44 +08:00
|
|
|
|
2012-04-25 05:59:50 +08:00
|
|
|
I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
|
|
|
|
|
|
|
|
/* Unmask the interrupts that we always want on. */
|
|
|
|
dev_priv->irq_mask =
|
|
|
|
~(I915_ASLE_INTERRUPT |
|
|
|
|
I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
|
|
|
|
I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
|
|
|
|
I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
|
2015-04-01 19:43:46 +08:00
|
|
|
I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
|
2012-04-25 05:59:50 +08:00
|
|
|
|
|
|
|
enable_mask =
|
|
|
|
I915_ASLE_INTERRUPT |
|
|
|
|
I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
|
|
|
|
I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
|
|
|
|
I915_USER_INTERRUPT;
|
|
|
|
|
2012-04-25 05:59:44 +08:00
|
|
|
if (I915_HAS_HOTPLUG(dev)) {
|
2012-12-11 21:05:07 +08:00
|
|
|
I915_WRITE(PORT_HOTPLUG_EN, 0);
|
|
|
|
POSTING_READ(PORT_HOTPLUG_EN);
|
|
|
|
|
2012-04-25 05:59:44 +08:00
|
|
|
/* Enable in IER... */
|
|
|
|
enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
|
|
|
|
/* and unmask in IMR */
|
|
|
|
dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
|
|
|
|
}
|
|
|
|
|
|
|
|
I915_WRITE(IMR, dev_priv->irq_mask);
|
|
|
|
I915_WRITE(IER, enable_mask);
|
|
|
|
POSTING_READ(IER);
|
|
|
|
|
2013-04-29 18:02:54 +08:00
|
|
|
i915_enable_asle_pipestat(dev);
|
2012-12-11 21:05:07 +08:00
|
|
|
|
2013-10-17 04:55:56 +08:00
|
|
|
/* Interrupt setup is already guaranteed to be single-threaded, this is
|
|
|
|
* just to make the assert_spin_locked check happy. */
|
2014-09-15 20:55:27 +08:00
|
|
|
spin_lock_irq(&dev_priv->irq_lock);
|
2014-02-11 00:42:47 +08:00
|
|
|
i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
|
|
|
|
i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
|
2014-09-15 20:55:27 +08:00
|
|
|
spin_unlock_irq(&dev_priv->irq_lock);
|
2013-10-17 04:55:56 +08:00
|
|
|
|
2012-12-11 21:05:07 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2013-02-20 05:16:44 +08:00
|
|
|
/*
|
|
|
|
* Returns true when a page flip has completed.
|
|
|
|
*/
|
|
|
|
static bool i915_handle_vblank(struct drm_device *dev,
|
|
|
|
int plane, int pipe, u32 iir)
|
|
|
|
{
|
2014-03-31 19:27:17 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2013-02-20 05:16:44 +08:00
|
|
|
u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
|
|
|
|
|
2014-04-29 18:35:46 +08:00
|
|
|
if (!intel_pipe_handle_vblank(dev, pipe))
|
2013-02-20 05:16:44 +08:00
|
|
|
return false;
|
|
|
|
|
|
|
|
if ((iir & flip_pending) == 0)
|
drm/i915: Check for a stalled page flip after each vblank
Long ago, back in the racy haydays of 915gm interrupt handling, page
flips would occasionally go astray and leave the hardware stuck, and the
display not updating. This annoyed people who relied on their systems
being able to display continuously updating information 24/7, and so
some code to detect when the driver missed the page flip completion
signal was added. Until recently, it was presumed that the interrupt
handling was now flawless, but once again Simon Farnsworth has found a
system whose display will stall. Reinstate the pageflip stall detection,
which works by checking to see if the hardware has been updated to the
new framebuffer address following each vblank. If the hardware is
scanning out from the new framebuffer, but we still think the flip is
pending, then we kick our driver into submision.
This is a continuation of the effort started with
commit 4e5359cd053bfb7d8dabe4a63624a5726848ffbc
Author: Simon Farnsworth <simon.farnsworth@onelan.co.uk>
Date: Wed Sep 1 17:47:52 2010 +0100
drm/i915: Avoid pageflipping freeze when we miss the flip prepare interrupt
This now includes a belt-and-braces approach to make sure the driver
(or the hardware) doesn't miss an interrupt and cause us to stop
updating the display should the unthinkable happen and the pageflip fail - i.e.
that the user is able to continue submitting flips.
v2: Cleanup, refactor, and rename
v3: Only start counting vblanks after the flip command has been seen by
the hardware.
v4: Record the seqno after we touch the ring, or else there may be no
seqno allocated yet.
v5: Rebase on mmio-flip.
v6: Rebase, rebase.
Reported-by: Simon Farnsworth <simon@farnz.org.uk>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75502
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> [v4]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-05 14:13:24 +08:00
|
|
|
goto check_page_flip;
|
2013-02-20 05:16:44 +08:00
|
|
|
|
|
|
|
/* We detect FlipDone by looking for the change in PendingFlip from '1'
|
|
|
|
* to '0' on the following vblank, i.e. IIR has the Pendingflip
|
|
|
|
* asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
|
|
|
|
* the flip is completed (no longer pending). Since this doesn't raise
|
|
|
|
* an interrupt per se, we watch for the change at vblank.
|
|
|
|
*/
|
|
|
|
if (I915_READ(ISR) & flip_pending)
|
drm/i915: Check for a stalled page flip after each vblank
Long ago, back in the racy haydays of 915gm interrupt handling, page
flips would occasionally go astray and leave the hardware stuck, and the
display not updating. This annoyed people who relied on their systems
being able to display continuously updating information 24/7, and so
some code to detect when the driver missed the page flip completion
signal was added. Until recently, it was presumed that the interrupt
handling was now flawless, but once again Simon Farnsworth has found a
system whose display will stall. Reinstate the pageflip stall detection,
which works by checking to see if the hardware has been updated to the
new framebuffer address following each vblank. If the hardware is
scanning out from the new framebuffer, but we still think the flip is
pending, then we kick our driver into submision.
This is a continuation of the effort started with
commit 4e5359cd053bfb7d8dabe4a63624a5726848ffbc
Author: Simon Farnsworth <simon.farnsworth@onelan.co.uk>
Date: Wed Sep 1 17:47:52 2010 +0100
drm/i915: Avoid pageflipping freeze when we miss the flip prepare interrupt
This now includes a belt-and-braces approach to make sure the driver
(or the hardware) doesn't miss an interrupt and cause us to stop
updating the display should the unthinkable happen and the pageflip fail - i.e.
that the user is able to continue submitting flips.
v2: Cleanup, refactor, and rename
v3: Only start counting vblanks after the flip command has been seen by
the hardware.
v4: Record the seqno after we touch the ring, or else there may be no
seqno allocated yet.
v5: Rebase on mmio-flip.
v6: Rebase, rebase.
Reported-by: Simon Farnsworth <simon@farnz.org.uk>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75502
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> [v4]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-05 14:13:24 +08:00
|
|
|
goto check_page_flip;
|
2013-02-20 05:16:44 +08:00
|
|
|
|
2014-12-18 05:08:03 +08:00
|
|
|
intel_prepare_page_flip(dev, plane);
|
2013-02-20 05:16:44 +08:00
|
|
|
intel_finish_page_flip(dev, pipe);
|
|
|
|
return true;
|
drm/i915: Check for a stalled page flip after each vblank
Long ago, back in the racy haydays of 915gm interrupt handling, page
flips would occasionally go astray and leave the hardware stuck, and the
display not updating. This annoyed people who relied on their systems
being able to display continuously updating information 24/7, and so
some code to detect when the driver missed the page flip completion
signal was added. Until recently, it was presumed that the interrupt
handling was now flawless, but once again Simon Farnsworth has found a
system whose display will stall. Reinstate the pageflip stall detection,
which works by checking to see if the hardware has been updated to the
new framebuffer address following each vblank. If the hardware is
scanning out from the new framebuffer, but we still think the flip is
pending, then we kick our driver into submision.
This is a continuation of the effort started with
commit 4e5359cd053bfb7d8dabe4a63624a5726848ffbc
Author: Simon Farnsworth <simon.farnsworth@onelan.co.uk>
Date: Wed Sep 1 17:47:52 2010 +0100
drm/i915: Avoid pageflipping freeze when we miss the flip prepare interrupt
This now includes a belt-and-braces approach to make sure the driver
(or the hardware) doesn't miss an interrupt and cause us to stop
updating the display should the unthinkable happen and the pageflip fail - i.e.
that the user is able to continue submitting flips.
v2: Cleanup, refactor, and rename
v3: Only start counting vblanks after the flip command has been seen by
the hardware.
v4: Record the seqno after we touch the ring, or else there may be no
seqno allocated yet.
v5: Rebase on mmio-flip.
v6: Rebase, rebase.
Reported-by: Simon Farnsworth <simon@farnz.org.uk>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75502
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> [v4]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-05 14:13:24 +08:00
|
|
|
|
|
|
|
check_page_flip:
|
|
|
|
intel_check_page_flip(dev, pipe);
|
|
|
|
return false;
|
2013-02-20 05:16:44 +08:00
|
|
|
}
|
|
|
|
|
2012-10-02 21:10:55 +08:00
|
|
|
static irqreturn_t i915_irq_handler(int irq, void *arg)
|
2012-04-25 05:59:44 +08:00
|
|
|
{
|
2014-05-13 01:17:55 +08:00
|
|
|
struct drm_device *dev = arg;
|
2014-03-31 19:27:17 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2012-04-25 05:59:47 +08:00
|
|
|
u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
|
2012-04-25 05:59:50 +08:00
|
|
|
u32 flip_mask =
|
|
|
|
I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
|
|
|
|
I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
|
|
|
|
int pipe, ret = IRQ_NONE;
|
2012-04-25 05:59:44 +08:00
|
|
|
|
2015-02-24 17:14:30 +08:00
|
|
|
if (!intel_irqs_enabled(dev_priv))
|
|
|
|
return IRQ_NONE;
|
|
|
|
|
2012-04-25 05:59:44 +08:00
|
|
|
iir = I915_READ(IIR);
|
2012-04-25 05:59:50 +08:00
|
|
|
do {
|
|
|
|
bool irq_received = (iir & ~flip_mask) != 0;
|
2012-04-25 05:59:47 +08:00
|
|
|
bool blc_event = false;
|
2012-04-25 05:59:44 +08:00
|
|
|
|
|
|
|
/* Can't rely on pipestat interrupt bit in iir as it might
|
|
|
|
* have been cleared after the pipestat interrupt was received.
|
|
|
|
* It doesn't set the bit in iir again, but it still produces
|
|
|
|
* interrupts (for non-MSI).
|
|
|
|
*/
|
2014-09-15 20:55:28 +08:00
|
|
|
spin_lock(&dev_priv->irq_lock);
|
2012-04-25 05:59:44 +08:00
|
|
|
if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
|
2014-11-04 22:52:22 +08:00
|
|
|
DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
|
2012-04-25 05:59:44 +08:00
|
|
|
|
2014-08-18 20:49:10 +08:00
|
|
|
for_each_pipe(dev_priv, pipe) {
|
2012-04-25 05:59:44 +08:00
|
|
|
int reg = PIPESTAT(pipe);
|
|
|
|
pipe_stats[pipe] = I915_READ(reg);
|
|
|
|
|
2012-04-25 05:59:50 +08:00
|
|
|
/* Clear the PIPE*STAT regs before the IIR */
|
2012-04-25 05:59:44 +08:00
|
|
|
if (pipe_stats[pipe] & 0x8000ffff) {
|
|
|
|
I915_WRITE(reg, pipe_stats[pipe]);
|
2012-04-25 05:59:50 +08:00
|
|
|
irq_received = true;
|
2012-04-25 05:59:44 +08:00
|
|
|
}
|
|
|
|
}
|
2014-09-15 20:55:28 +08:00
|
|
|
spin_unlock(&dev_priv->irq_lock);
|
2012-04-25 05:59:44 +08:00
|
|
|
|
|
|
|
if (!irq_received)
|
|
|
|
break;
|
|
|
|
|
|
|
|
/* Consume port. Then clear IIR or we'll miss events */
|
2014-04-01 15:54:36 +08:00
|
|
|
if (I915_HAS_HOTPLUG(dev) &&
|
|
|
|
iir & I915_DISPLAY_PORT_INTERRUPT)
|
|
|
|
i9xx_hpd_irq_handler(dev);
|
2012-04-25 05:59:44 +08:00
|
|
|
|
2012-04-25 05:59:50 +08:00
|
|
|
I915_WRITE(IIR, iir & ~flip_mask);
|
2012-04-25 05:59:44 +08:00
|
|
|
new_iir = I915_READ(IIR); /* Flush posted writes */
|
|
|
|
|
|
|
|
if (iir & I915_USER_INTERRUPT)
|
2015-04-07 23:21:05 +08:00
|
|
|
notify_ring(&dev_priv->ring[RCS]);
|
2012-04-25 05:59:44 +08:00
|
|
|
|
2014-08-18 20:49:10 +08:00
|
|
|
for_each_pipe(dev_priv, pipe) {
|
2012-04-25 05:59:50 +08:00
|
|
|
int plane = pipe;
|
2014-01-10 15:50:12 +08:00
|
|
|
if (HAS_FBC(dev))
|
2012-04-25 05:59:50 +08:00
|
|
|
plane = !plane;
|
2013-02-20 05:16:44 +08:00
|
|
|
|
2012-04-25 05:59:47 +08:00
|
|
|
if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
|
2013-02-20 05:16:44 +08:00
|
|
|
i915_handle_vblank(dev, plane, pipe, iir))
|
|
|
|
flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
|
2012-04-25 05:59:44 +08:00
|
|
|
|
|
|
|
if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
|
|
|
|
blc_event = true;
|
2013-10-17 04:55:55 +08:00
|
|
|
|
|
|
|
if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
|
2013-10-18 22:37:07 +08:00
|
|
|
i9xx_pipe_crc_irq_handler(dev, pipe);
|
2014-01-17 17:44:31 +08:00
|
|
|
|
2014-09-30 16:56:48 +08:00
|
|
|
if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
|
|
|
|
intel_cpu_fifo_underrun_irq_handler(dev_priv,
|
|
|
|
pipe);
|
2012-04-25 05:59:44 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
if (blc_event || (iir & I915_ASLE_INTERRUPT))
|
|
|
|
intel_opregion_asle_intr(dev);
|
|
|
|
|
|
|
|
/* With MSI, interrupts are only generated when iir
|
|
|
|
* transitions from zero to nonzero. If another bit got
|
|
|
|
* set while we were handling the existing iir bits, then
|
|
|
|
* we would never get another interrupt.
|
|
|
|
*
|
|
|
|
* This is fine on non-MSI as well, as if we hit this path
|
|
|
|
* we avoid exiting the interrupt handler only to generate
|
|
|
|
* another one.
|
|
|
|
*
|
|
|
|
* Note that for MSI this could cause a stray interrupt report
|
|
|
|
* if an interrupt landed in the time between writing IIR and
|
|
|
|
* the posting read. This should be rare enough to never
|
|
|
|
* trigger the 99% of 100,000 interrupts test for disabling
|
|
|
|
* stray interrupts.
|
|
|
|
*/
|
2012-04-25 05:59:50 +08:00
|
|
|
ret = IRQ_HANDLED;
|
2012-04-25 05:59:44 +08:00
|
|
|
iir = new_iir;
|
2012-04-25 05:59:50 +08:00
|
|
|
} while (iir & ~flip_mask);
|
2012-04-25 05:59:44 +08:00
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void i915_irq_uninstall(struct drm_device * dev)
|
|
|
|
{
|
2014-03-31 19:27:17 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2012-04-25 05:59:44 +08:00
|
|
|
int pipe;
|
|
|
|
|
|
|
|
if (I915_HAS_HOTPLUG(dev)) {
|
|
|
|
I915_WRITE(PORT_HOTPLUG_EN, 0);
|
|
|
|
I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
|
|
|
|
}
|
|
|
|
|
2012-04-25 05:59:48 +08:00
|
|
|
I915_WRITE16(HWSTAM, 0xffff);
|
2014-08-18 20:49:10 +08:00
|
|
|
for_each_pipe(dev_priv, pipe) {
|
2012-04-25 05:59:49 +08:00
|
|
|
/* Clear enable bits; then clear status bits */
|
2012-04-25 05:59:44 +08:00
|
|
|
I915_WRITE(PIPESTAT(pipe), 0);
|
2012-04-25 05:59:49 +08:00
|
|
|
I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
|
|
|
|
}
|
2012-04-25 05:59:44 +08:00
|
|
|
I915_WRITE(IMR, 0xffffffff);
|
|
|
|
I915_WRITE(IER, 0x0);
|
|
|
|
|
|
|
|
I915_WRITE(IIR, I915_READ(IIR));
|
|
|
|
}
|
|
|
|
|
|
|
|
static void i965_irq_preinstall(struct drm_device * dev)
|
|
|
|
{
|
2014-03-31 19:27:17 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2012-04-25 05:59:44 +08:00
|
|
|
int pipe;
|
|
|
|
|
2012-05-12 01:01:31 +08:00
|
|
|
I915_WRITE(PORT_HOTPLUG_EN, 0);
|
|
|
|
I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
|
2012-04-25 05:59:44 +08:00
|
|
|
|
|
|
|
I915_WRITE(HWSTAM, 0xeffe);
|
2014-08-18 20:49:10 +08:00
|
|
|
for_each_pipe(dev_priv, pipe)
|
2012-04-25 05:59:44 +08:00
|
|
|
I915_WRITE(PIPESTAT(pipe), 0);
|
|
|
|
I915_WRITE(IMR, 0xffffffff);
|
|
|
|
I915_WRITE(IER, 0x0);
|
|
|
|
POSTING_READ(IER);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int i965_irq_postinstall(struct drm_device *dev)
|
|
|
|
{
|
2014-03-31 19:27:17 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2012-04-25 05:59:51 +08:00
|
|
|
u32 enable_mask;
|
2012-04-25 05:59:44 +08:00
|
|
|
u32 error_mask;
|
|
|
|
|
|
|
|
/* Unmask the interrupts that we always want on. */
|
2012-04-25 05:59:51 +08:00
|
|
|
dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
|
2012-05-12 01:01:31 +08:00
|
|
|
I915_DISPLAY_PORT_INTERRUPT |
|
2012-04-25 05:59:51 +08:00
|
|
|
I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
|
|
|
|
I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
|
|
|
|
I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
|
|
|
|
I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
|
|
|
|
I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
|
|
|
|
|
|
|
|
enable_mask = ~dev_priv->irq_mask;
|
2013-02-19 21:16:39 +08:00
|
|
|
enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
|
|
|
|
I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
|
2012-04-25 05:59:51 +08:00
|
|
|
enable_mask |= I915_USER_INTERRUPT;
|
|
|
|
|
|
|
|
if (IS_G4X(dev))
|
|
|
|
enable_mask |= I915_BSD_USER_INTERRUPT;
|
2012-04-25 05:59:44 +08:00
|
|
|
|
2013-06-27 23:52:10 +08:00
|
|
|
/* Interrupt setup is already guaranteed to be single-threaded, this is
|
|
|
|
* just to make the assert_spin_locked check happy. */
|
2014-09-15 20:55:27 +08:00
|
|
|
spin_lock_irq(&dev_priv->irq_lock);
|
2014-02-11 00:42:47 +08:00
|
|
|
i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
|
|
|
|
i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
|
|
|
|
i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
|
2014-09-15 20:55:27 +08:00
|
|
|
spin_unlock_irq(&dev_priv->irq_lock);
|
2012-04-25 05:59:44 +08:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Enable some error detection, note the instruction error mask
|
|
|
|
* bit is reserved, so we leave it masked.
|
|
|
|
*/
|
|
|
|
if (IS_G4X(dev)) {
|
|
|
|
error_mask = ~(GM45_ERROR_PAGE_TABLE |
|
|
|
|
GM45_ERROR_MEM_PRIV |
|
|
|
|
GM45_ERROR_CP_PRIV |
|
|
|
|
I915_ERROR_MEMORY_REFRESH);
|
|
|
|
} else {
|
|
|
|
error_mask = ~(I915_ERROR_PAGE_TABLE |
|
|
|
|
I915_ERROR_MEMORY_REFRESH);
|
|
|
|
}
|
|
|
|
I915_WRITE(EMR, error_mask);
|
|
|
|
|
|
|
|
I915_WRITE(IMR, dev_priv->irq_mask);
|
|
|
|
I915_WRITE(IER, enable_mask);
|
|
|
|
POSTING_READ(IER);
|
|
|
|
|
2012-12-11 21:05:07 +08:00
|
|
|
I915_WRITE(PORT_HOTPLUG_EN, 0);
|
|
|
|
POSTING_READ(PORT_HOTPLUG_EN);
|
|
|
|
|
2013-04-29 18:02:54 +08:00
|
|
|
i915_enable_asle_pipestat(dev);
|
2012-12-11 21:05:07 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2013-02-26 01:06:51 +08:00
|
|
|
static void i915_hpd_irq_setup(struct drm_device *dev)
|
2012-12-11 21:05:07 +08:00
|
|
|
{
|
2014-03-31 19:27:17 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2013-04-16 19:36:57 +08:00
|
|
|
struct intel_encoder *intel_encoder;
|
2012-12-11 21:05:07 +08:00
|
|
|
u32 hotplug_en;
|
|
|
|
|
2013-06-27 23:52:15 +08:00
|
|
|
assert_spin_locked(&dev_priv->irq_lock);
|
|
|
|
|
2015-01-09 20:21:13 +08:00
|
|
|
hotplug_en = I915_READ(PORT_HOTPLUG_EN);
|
|
|
|
hotplug_en &= ~HOTPLUG_INT_EN_MASK;
|
|
|
|
/* Note HDMI and DP share hotplug bits */
|
|
|
|
/* enable bits are the same for all generations */
|
|
|
|
for_each_intel_encoder(dev, intel_encoder)
|
2015-05-27 20:03:42 +08:00
|
|
|
if (dev_priv->hotplug.stats[intel_encoder->hpd_pin].state == HPD_ENABLED)
|
2015-01-09 20:21:13 +08:00
|
|
|
hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
|
|
|
|
/* Programming the CRT detection parameters tends
|
|
|
|
to generate a spurious hotplug event about three
|
|
|
|
seconds later. So just do it once.
|
|
|
|
*/
|
|
|
|
if (IS_G4X(dev))
|
|
|
|
hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
|
|
|
|
hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
|
|
|
|
hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
|
|
|
|
|
|
|
|
/* Ignore TV since it's buggy */
|
|
|
|
I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
|
2012-04-25 05:59:44 +08:00
|
|
|
}
|
|
|
|
|
2012-10-02 21:10:55 +08:00
|
|
|
static irqreturn_t i965_irq_handler(int irq, void *arg)
|
2012-04-25 05:59:44 +08:00
|
|
|
{
|
2014-05-13 01:17:55 +08:00
|
|
|
struct drm_device *dev = arg;
|
2014-03-31 19:27:17 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2012-04-25 05:59:44 +08:00
|
|
|
u32 iir, new_iir;
|
|
|
|
u32 pipe_stats[I915_MAX_PIPES];
|
|
|
|
int ret = IRQ_NONE, pipe;
|
2013-02-19 21:16:39 +08:00
|
|
|
u32 flip_mask =
|
|
|
|
I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
|
|
|
|
I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
|
2012-04-25 05:59:44 +08:00
|
|
|
|
2015-02-24 17:14:30 +08:00
|
|
|
if (!intel_irqs_enabled(dev_priv))
|
|
|
|
return IRQ_NONE;
|
|
|
|
|
2012-04-25 05:59:44 +08:00
|
|
|
iir = I915_READ(IIR);
|
|
|
|
|
|
|
|
for (;;) {
|
2014-01-17 17:35:15 +08:00
|
|
|
bool irq_received = (iir & ~flip_mask) != 0;
|
2012-04-25 05:59:46 +08:00
|
|
|
bool blc_event = false;
|
|
|
|
|
2012-04-25 05:59:44 +08:00
|
|
|
/* Can't rely on pipestat interrupt bit in iir as it might
|
|
|
|
* have been cleared after the pipestat interrupt was received.
|
|
|
|
* It doesn't set the bit in iir again, but it still produces
|
|
|
|
* interrupts (for non-MSI).
|
|
|
|
*/
|
2014-09-15 20:55:28 +08:00
|
|
|
spin_lock(&dev_priv->irq_lock);
|
2012-04-25 05:59:44 +08:00
|
|
|
if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
|
2014-11-04 22:52:22 +08:00
|
|
|
DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
|
2012-04-25 05:59:44 +08:00
|
|
|
|
2014-08-18 20:49:10 +08:00
|
|
|
for_each_pipe(dev_priv, pipe) {
|
2012-04-25 05:59:44 +08:00
|
|
|
int reg = PIPESTAT(pipe);
|
|
|
|
pipe_stats[pipe] = I915_READ(reg);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Clear the PIPE*STAT regs before the IIR
|
|
|
|
*/
|
|
|
|
if (pipe_stats[pipe] & 0x8000ffff) {
|
|
|
|
I915_WRITE(reg, pipe_stats[pipe]);
|
2014-01-17 17:35:15 +08:00
|
|
|
irq_received = true;
|
2012-04-25 05:59:44 +08:00
|
|
|
}
|
|
|
|
}
|
2014-09-15 20:55:28 +08:00
|
|
|
spin_unlock(&dev_priv->irq_lock);
|
2012-04-25 05:59:44 +08:00
|
|
|
|
|
|
|
if (!irq_received)
|
|
|
|
break;
|
|
|
|
|
|
|
|
ret = IRQ_HANDLED;
|
|
|
|
|
|
|
|
/* Consume port. Then clear IIR or we'll miss events */
|
2014-04-01 15:54:36 +08:00
|
|
|
if (iir & I915_DISPLAY_PORT_INTERRUPT)
|
|
|
|
i9xx_hpd_irq_handler(dev);
|
2012-04-25 05:59:44 +08:00
|
|
|
|
2013-02-19 21:16:39 +08:00
|
|
|
I915_WRITE(IIR, iir & ~flip_mask);
|
2012-04-25 05:59:44 +08:00
|
|
|
new_iir = I915_READ(IIR); /* Flush posted writes */
|
|
|
|
|
|
|
|
if (iir & I915_USER_INTERRUPT)
|
2015-04-07 23:21:05 +08:00
|
|
|
notify_ring(&dev_priv->ring[RCS]);
|
2012-04-25 05:59:44 +08:00
|
|
|
if (iir & I915_BSD_USER_INTERRUPT)
|
2015-04-07 23:21:05 +08:00
|
|
|
notify_ring(&dev_priv->ring[VCS]);
|
2012-04-25 05:59:44 +08:00
|
|
|
|
2014-08-18 20:49:10 +08:00
|
|
|
for_each_pipe(dev_priv, pipe) {
|
2012-04-25 05:59:46 +08:00
|
|
|
if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
|
2013-02-20 05:16:44 +08:00
|
|
|
i915_handle_vblank(dev, pipe, pipe, iir))
|
|
|
|
flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
|
2012-04-25 05:59:44 +08:00
|
|
|
|
|
|
|
if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
|
|
|
|
blc_event = true;
|
2013-10-17 04:55:55 +08:00
|
|
|
|
|
|
|
if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
|
2013-10-18 22:37:07 +08:00
|
|
|
i9xx_pipe_crc_irq_handler(dev, pipe);
|
2012-04-25 05:59:44 +08:00
|
|
|
|
2014-09-30 16:56:48 +08:00
|
|
|
if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
|
|
|
|
intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
|
2014-01-17 17:44:31 +08:00
|
|
|
}
|
2012-04-25 05:59:44 +08:00
|
|
|
|
|
|
|
if (blc_event || (iir & I915_ASLE_INTERRUPT))
|
|
|
|
intel_opregion_asle_intr(dev);
|
|
|
|
|
2012-12-01 20:53:44 +08:00
|
|
|
if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
|
|
|
|
gmbus_irq_handler(dev);
|
|
|
|
|
2012-04-25 05:59:44 +08:00
|
|
|
/* With MSI, interrupts are only generated when iir
|
|
|
|
* transitions from zero to nonzero. If another bit got
|
|
|
|
* set while we were handling the existing iir bits, then
|
|
|
|
* we would never get another interrupt.
|
|
|
|
*
|
|
|
|
* This is fine on non-MSI as well, as if we hit this path
|
|
|
|
* we avoid exiting the interrupt handler only to generate
|
|
|
|
* another one.
|
|
|
|
*
|
|
|
|
* Note that for MSI this could cause a stray interrupt report
|
|
|
|
* if an interrupt landed in the time between writing IIR and
|
|
|
|
* the posting read. This should be rare enough to never
|
|
|
|
* trigger the 99% of 100,000 interrupts test for disabling
|
|
|
|
* stray interrupts.
|
|
|
|
*/
|
|
|
|
iir = new_iir;
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void i965_irq_uninstall(struct drm_device * dev)
|
|
|
|
{
|
2014-03-31 19:27:17 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2012-04-25 05:59:44 +08:00
|
|
|
int pipe;
|
|
|
|
|
|
|
|
if (!dev_priv)
|
|
|
|
return;
|
|
|
|
|
2012-05-12 01:01:31 +08:00
|
|
|
I915_WRITE(PORT_HOTPLUG_EN, 0);
|
|
|
|
I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
|
2012-04-25 05:59:44 +08:00
|
|
|
|
|
|
|
I915_WRITE(HWSTAM, 0xffffffff);
|
2014-08-18 20:49:10 +08:00
|
|
|
for_each_pipe(dev_priv, pipe)
|
2012-04-25 05:59:44 +08:00
|
|
|
I915_WRITE(PIPESTAT(pipe), 0);
|
|
|
|
I915_WRITE(IMR, 0xffffffff);
|
|
|
|
I915_WRITE(IER, 0x0);
|
|
|
|
|
2014-08-18 20:49:10 +08:00
|
|
|
for_each_pipe(dev_priv, pipe)
|
2012-04-25 05:59:44 +08:00
|
|
|
I915_WRITE(PIPESTAT(pipe),
|
|
|
|
I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
|
|
|
|
I915_WRITE(IIR, I915_READ(IIR));
|
|
|
|
}
|
|
|
|
|
2014-09-15 20:55:26 +08:00
|
|
|
static void intel_hpd_irq_reenable_work(struct work_struct *work)
|
2013-04-16 19:36:58 +08:00
|
|
|
{
|
2014-08-18 20:37:02 +08:00
|
|
|
struct drm_i915_private *dev_priv =
|
|
|
|
container_of(work, typeof(*dev_priv),
|
2015-05-27 20:03:42 +08:00
|
|
|
hotplug.reenable_work.work);
|
2013-04-16 19:36:58 +08:00
|
|
|
struct drm_device *dev = dev_priv->dev;
|
|
|
|
struct drm_mode_config *mode_config = &dev->mode_config;
|
|
|
|
int i;
|
|
|
|
|
2014-08-18 20:37:02 +08:00
|
|
|
intel_runtime_pm_get(dev_priv);
|
|
|
|
|
2014-09-15 20:55:26 +08:00
|
|
|
spin_lock_irq(&dev_priv->irq_lock);
|
2015-05-28 20:43:48 +08:00
|
|
|
for_each_hpd_pin(i) {
|
2013-04-16 19:36:58 +08:00
|
|
|
struct drm_connector *connector;
|
|
|
|
|
2015-05-27 20:03:42 +08:00
|
|
|
if (dev_priv->hotplug.stats[i].state != HPD_DISABLED)
|
2013-04-16 19:36:58 +08:00
|
|
|
continue;
|
|
|
|
|
2015-05-27 20:03:42 +08:00
|
|
|
dev_priv->hotplug.stats[i].state = HPD_ENABLED;
|
2013-04-16 19:36:58 +08:00
|
|
|
|
|
|
|
list_for_each_entry(connector, &mode_config->connector_list, head) {
|
|
|
|
struct intel_connector *intel_connector = to_intel_connector(connector);
|
|
|
|
|
|
|
|
if (intel_connector->encoder->hpd_pin == i) {
|
|
|
|
if (connector->polled != intel_connector->polled)
|
|
|
|
DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
|
2014-06-03 19:56:17 +08:00
|
|
|
connector->name);
|
2013-04-16 19:36:58 +08:00
|
|
|
connector->polled = intel_connector->polled;
|
|
|
|
if (!connector->polled)
|
|
|
|
connector->polled = DRM_CONNECTOR_POLL_HPD;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (dev_priv->display.hpd_irq_setup)
|
|
|
|
dev_priv->display.hpd_irq_setup(dev);
|
2014-09-15 20:55:26 +08:00
|
|
|
spin_unlock_irq(&dev_priv->irq_lock);
|
2014-08-18 20:37:02 +08:00
|
|
|
|
|
|
|
intel_runtime_pm_put(dev_priv);
|
2013-04-16 19:36:58 +08:00
|
|
|
}
|
|
|
|
|
2014-09-30 16:56:45 +08:00
|
|
|
/**
|
|
|
|
* intel_irq_init - initializes irq support
|
|
|
|
* @dev_priv: i915 device instance
|
|
|
|
*
|
|
|
|
* This function initializes all the irq support including work items, timers
|
|
|
|
* and all the vtables. It does not setup the interrupt itself though.
|
|
|
|
*/
|
2014-09-30 16:56:44 +08:00
|
|
|
void intel_irq_init(struct drm_i915_private *dev_priv)
|
2011-06-29 04:00:41 +08:00
|
|
|
{
|
2014-09-30 16:56:44 +08:00
|
|
|
struct drm_device *dev = dev_priv->dev;
|
2012-04-25 05:59:41 +08:00
|
|
|
|
2015-05-27 20:03:42 +08:00
|
|
|
INIT_WORK(&dev_priv->hotplug.hotplug_work, i915_hotplug_work_func);
|
|
|
|
INIT_WORK(&dev_priv->hotplug.dig_port_work, i915_digport_work_func);
|
2012-08-09 05:35:35 +08:00
|
|
|
INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
|
2012-11-03 02:55:07 +08:00
|
|
|
INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
|
2012-04-25 05:59:41 +08:00
|
|
|
|
2014-03-15 22:53:22 +08:00
|
|
|
/* Let's track the enabled rps events */
|
2014-09-30 16:56:44 +08:00
|
|
|
if (IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
|
2014-08-29 19:14:07 +08:00
|
|
|
/* WaGsvRC0ResidencyMethod:vlv */
|
2015-03-18 17:48:23 +08:00
|
|
|
dev_priv->pm_rps_events = GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED;
|
2014-07-04 05:33:01 +08:00
|
|
|
else
|
|
|
|
dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
|
2014-03-15 22:53:22 +08:00
|
|
|
|
2015-01-27 00:03:03 +08:00
|
|
|
INIT_DELAYED_WORK(&dev_priv->gpu_error.hangcheck_work,
|
|
|
|
i915_hangcheck_elapsed);
|
2015-05-27 20:03:42 +08:00
|
|
|
INIT_DELAYED_WORK(&dev_priv->hotplug.reenable_work,
|
2014-09-15 20:55:26 +08:00
|
|
|
intel_hpd_irq_reenable_work);
|
2012-12-02 04:03:21 +08:00
|
|
|
|
2012-12-08 20:48:13 +08:00
|
|
|
pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
|
drm/i915: irq-drive the dp aux communication
At least on the platforms that have a dp aux irq and also have it
enabled - vlvhsw should have one, too. But I don't have a machine to
test this on. Judging from docs there's no dp aux interrupt for gm45.
Also, I only have an ivb cpu edp machine, so the dp aux A code for
snb/ilk is untested.
For dpcd probing when nothing is connected it slashes about 5ms of cpu
time (cpu time is now negligible), which agrees with 3 * 5 400 usec
timeouts.
A previous version of this patch increases the time required to go
through the dp_detect cycle (which includes reading the edid) from
around 33 ms to around 40 ms. Experiments indicated that this is
purely due to the irq latency - the hw doesn't allow us to queue up
dp aux transactions and hence irq latency directly affects throughput.
gmbus is much better, there we have a 8 byte buffer, and we get the
irq once another 4 bytes can be queued up.
But by using the pm_qos interface to request the lowest possible cpu
wake-up latency this slowdown completely disappeared.
Since all our output detection logic is single-threaded with the
mode_config mutex right now anyway, I've decide not ot play fancy and
to just reuse the gmbus wait queue. But this would definitely prep the
way to run dp detection on different ports in parallel
v2: Add a timeout for dp aux transfers when using interrupts - the hw
_does_ prevent this with the hw-based 400 usec timeout, but if the
irq somehow doesn't arrive we're screwed. Lesson learned while
developing this ;-)
v3: While at it also convert the busy-loop to wait_for_atomic, so that
we don't run the risk of an infinite loop any more.
v4: Ensure we have the smallest possible irq latency by using the
pm_qos interface.
v5: Add a comment to the code to explain why we frob pm_qos. Suggested
by Chris Wilson.
v6: Disable dp irq for vlv, that's easier than trying to get at docs
and hw.
v7: Squash in a fix for Haswell that Paulo Zanoni tracked down - the
dp aux registers aren't at a fixed offset any more, but can be on the
PCH while the DP port is on the cpu die.
Reviewed-by: Imre Deak <imre.deak@intel.com> (v6)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-12-01 20:53:48 +08:00
|
|
|
|
2014-09-30 16:56:44 +08:00
|
|
|
if (IS_GEN2(dev_priv)) {
|
2013-10-12 02:52:44 +08:00
|
|
|
dev->max_vblank_count = 0;
|
|
|
|
dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
|
2014-09-30 16:56:44 +08:00
|
|
|
} else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) {
|
2011-06-29 04:00:41 +08:00
|
|
|
dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
|
|
|
|
dev->driver->get_vblank_counter = gm45_get_vblank_counter;
|
2013-09-26 00:55:26 +08:00
|
|
|
} else {
|
|
|
|
dev->driver->get_vblank_counter = i915_get_vblank_counter;
|
|
|
|
dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
|
2011-06-29 04:00:41 +08:00
|
|
|
}
|
|
|
|
|
2014-08-06 19:49:55 +08:00
|
|
|
/*
|
|
|
|
* Opt out of the vblank disable timer on everything except gen2.
|
|
|
|
* Gen2 doesn't have a hardware frame counter and so depends on
|
|
|
|
* vblank interrupts to produce sane vblank seuquence numbers.
|
|
|
|
*/
|
2014-09-30 16:56:44 +08:00
|
|
|
if (!IS_GEN2(dev_priv))
|
2014-08-06 19:49:55 +08:00
|
|
|
dev->vblank_disable_immediate = true;
|
|
|
|
|
2015-02-14 04:03:44 +08:00
|
|
|
dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
|
|
|
|
dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
|
2011-06-29 04:00:41 +08:00
|
|
|
|
2014-09-30 16:56:44 +08:00
|
|
|
if (IS_CHERRYVIEW(dev_priv)) {
|
2014-04-10 01:40:52 +08:00
|
|
|
dev->driver->irq_handler = cherryview_irq_handler;
|
|
|
|
dev->driver->irq_preinstall = cherryview_irq_preinstall;
|
|
|
|
dev->driver->irq_postinstall = cherryview_irq_postinstall;
|
|
|
|
dev->driver->irq_uninstall = cherryview_irq_uninstall;
|
|
|
|
dev->driver->enable_vblank = valleyview_enable_vblank;
|
|
|
|
dev->driver->disable_vblank = valleyview_disable_vblank;
|
|
|
|
dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
|
2014-09-30 16:56:44 +08:00
|
|
|
} else if (IS_VALLEYVIEW(dev_priv)) {
|
2012-03-29 04:39:38 +08:00
|
|
|
dev->driver->irq_handler = valleyview_irq_handler;
|
|
|
|
dev->driver->irq_preinstall = valleyview_irq_preinstall;
|
|
|
|
dev->driver->irq_postinstall = valleyview_irq_postinstall;
|
|
|
|
dev->driver->irq_uninstall = valleyview_irq_uninstall;
|
|
|
|
dev->driver->enable_vblank = valleyview_enable_vblank;
|
|
|
|
dev->driver->disable_vblank = valleyview_disable_vblank;
|
2013-02-26 01:06:48 +08:00
|
|
|
dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
|
2014-09-30 16:56:44 +08:00
|
|
|
} else if (INTEL_INFO(dev_priv)->gen >= 8) {
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 12:07:09 +08:00
|
|
|
dev->driver->irq_handler = gen8_irq_handler;
|
2014-05-22 23:56:34 +08:00
|
|
|
dev->driver->irq_preinstall = gen8_irq_reset;
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 12:07:09 +08:00
|
|
|
dev->driver->irq_postinstall = gen8_irq_postinstall;
|
|
|
|
dev->driver->irq_uninstall = gen8_irq_uninstall;
|
|
|
|
dev->driver->enable_vblank = gen8_enable_vblank;
|
|
|
|
dev->driver->disable_vblank = gen8_disable_vblank;
|
2015-03-27 20:54:14 +08:00
|
|
|
if (HAS_PCH_SPLIT(dev))
|
|
|
|
dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
|
|
|
|
else
|
|
|
|
dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
|
2011-06-29 04:00:41 +08:00
|
|
|
} else if (HAS_PCH_SPLIT(dev)) {
|
|
|
|
dev->driver->irq_handler = ironlake_irq_handler;
|
2014-05-22 23:56:34 +08:00
|
|
|
dev->driver->irq_preinstall = ironlake_irq_reset;
|
2011-06-29 04:00:41 +08:00
|
|
|
dev->driver->irq_postinstall = ironlake_irq_postinstall;
|
|
|
|
dev->driver->irq_uninstall = ironlake_irq_uninstall;
|
|
|
|
dev->driver->enable_vblank = ironlake_enable_vblank;
|
|
|
|
dev->driver->disable_vblank = ironlake_disable_vblank;
|
2013-03-27 22:55:01 +08:00
|
|
|
dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
|
2011-06-29 04:00:41 +08:00
|
|
|
} else {
|
2014-09-30 16:56:44 +08:00
|
|
|
if (INTEL_INFO(dev_priv)->gen == 2) {
|
2012-04-23 04:13:57 +08:00
|
|
|
dev->driver->irq_preinstall = i8xx_irq_preinstall;
|
|
|
|
dev->driver->irq_postinstall = i8xx_irq_postinstall;
|
|
|
|
dev->driver->irq_handler = i8xx_irq_handler;
|
|
|
|
dev->driver->irq_uninstall = i8xx_irq_uninstall;
|
2014-09-30 16:56:44 +08:00
|
|
|
} else if (INTEL_INFO(dev_priv)->gen == 3) {
|
2012-04-25 05:59:44 +08:00
|
|
|
dev->driver->irq_preinstall = i915_irq_preinstall;
|
|
|
|
dev->driver->irq_postinstall = i915_irq_postinstall;
|
|
|
|
dev->driver->irq_uninstall = i915_irq_uninstall;
|
|
|
|
dev->driver->irq_handler = i915_irq_handler;
|
2012-04-23 04:13:57 +08:00
|
|
|
} else {
|
2012-04-25 05:59:44 +08:00
|
|
|
dev->driver->irq_preinstall = i965_irq_preinstall;
|
|
|
|
dev->driver->irq_postinstall = i965_irq_postinstall;
|
|
|
|
dev->driver->irq_uninstall = i965_irq_uninstall;
|
|
|
|
dev->driver->irq_handler = i965_irq_handler;
|
2012-04-23 04:13:57 +08:00
|
|
|
}
|
2015-01-09 20:21:13 +08:00
|
|
|
if (I915_HAS_HOTPLUG(dev_priv))
|
|
|
|
dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
|
2011-06-29 04:00:41 +08:00
|
|
|
dev->driver->enable_vblank = i915_enable_vblank;
|
|
|
|
dev->driver->disable_vblank = i915_disable_vblank;
|
|
|
|
}
|
|
|
|
}
|
2012-12-11 21:05:07 +08:00
|
|
|
|
2014-09-30 16:56:45 +08:00
|
|
|
/**
|
|
|
|
* intel_hpd_init - initializes and enables hpd support
|
|
|
|
* @dev_priv: i915 device instance
|
|
|
|
*
|
|
|
|
* This function enables the hotplug support. It requires that interrupts have
|
|
|
|
* already been enabled with intel_irq_init_hw(). From this point on hotplug and
|
|
|
|
* poll request can run concurrently to other code, so locking rules must be
|
|
|
|
* obeyed.
|
|
|
|
*
|
|
|
|
* This is a separate step from interrupt enabling to simplify the locking rules
|
|
|
|
* in the driver load and resume code.
|
|
|
|
*/
|
2014-09-30 16:56:44 +08:00
|
|
|
void intel_hpd_init(struct drm_i915_private *dev_priv)
|
2012-12-11 21:05:07 +08:00
|
|
|
{
|
2014-09-30 16:56:44 +08:00
|
|
|
struct drm_device *dev = dev_priv->dev;
|
2013-04-16 19:36:55 +08:00
|
|
|
struct drm_mode_config *mode_config = &dev->mode_config;
|
|
|
|
struct drm_connector *connector;
|
|
|
|
int i;
|
2012-12-11 21:05:07 +08:00
|
|
|
|
2015-05-28 20:43:48 +08:00
|
|
|
for_each_hpd_pin(i) {
|
2015-05-27 20:03:42 +08:00
|
|
|
dev_priv->hotplug.stats[i].count = 0;
|
|
|
|
dev_priv->hotplug.stats[i].state = HPD_ENABLED;
|
2013-04-16 19:36:55 +08:00
|
|
|
}
|
|
|
|
list_for_each_entry(connector, &mode_config->connector_list, head) {
|
|
|
|
struct intel_connector *intel_connector = to_intel_connector(connector);
|
|
|
|
connector->polled = intel_connector->polled;
|
2014-05-02 12:02:48 +08:00
|
|
|
if (connector->encoder && !connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
|
|
|
|
connector->polled = DRM_CONNECTOR_POLL_HPD;
|
|
|
|
if (intel_connector->mst_port)
|
2013-04-16 19:36:55 +08:00
|
|
|
connector->polled = DRM_CONNECTOR_POLL_HPD;
|
|
|
|
}
|
2013-06-27 23:52:15 +08:00
|
|
|
|
|
|
|
/* Interrupt setup is already guaranteed to be single-threaded, this is
|
|
|
|
* just to make the assert_spin_locked checks happy. */
|
2014-09-15 20:55:27 +08:00
|
|
|
spin_lock_irq(&dev_priv->irq_lock);
|
2012-12-11 21:05:07 +08:00
|
|
|
if (dev_priv->display.hpd_irq_setup)
|
|
|
|
dev_priv->display.hpd_irq_setup(dev);
|
2014-09-15 20:55:27 +08:00
|
|
|
spin_unlock_irq(&dev_priv->irq_lock);
|
2012-12-11 21:05:07 +08:00
|
|
|
}
|
2013-08-20 00:18:09 +08:00
|
|
|
|
2014-09-30 16:56:45 +08:00
|
|
|
/**
|
|
|
|
* intel_irq_install - enables the hardware interrupt
|
|
|
|
* @dev_priv: i915 device instance
|
|
|
|
*
|
|
|
|
* This function enables the hardware interrupt handling, but leaves the hotplug
|
|
|
|
* handling still disabled. It is called after intel_irq_init().
|
|
|
|
*
|
|
|
|
* In the driver load and resume code we need working interrupts in a few places
|
|
|
|
* but don't want to deal with the hassle of concurrent probe and hotplug
|
|
|
|
* workers. Hence the split into this two-stage approach.
|
|
|
|
*/
|
2014-09-30 16:56:43 +08:00
|
|
|
int intel_irq_install(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
/*
|
|
|
|
* We enable some interrupt sources in our postinstall hooks, so mark
|
|
|
|
* interrupts as enabled _before_ actually enabling them to avoid
|
|
|
|
* special cases in our ordering checks.
|
|
|
|
*/
|
|
|
|
dev_priv->pm.irqs_enabled = true;
|
|
|
|
|
|
|
|
return drm_irq_install(dev_priv->dev, dev_priv->dev->pdev->irq);
|
|
|
|
}
|
|
|
|
|
2014-09-30 16:56:45 +08:00
|
|
|
/**
|
|
|
|
* intel_irq_uninstall - finilizes all irq handling
|
|
|
|
* @dev_priv: i915 device instance
|
|
|
|
*
|
|
|
|
* This stops interrupt and hotplug handling and unregisters and frees all
|
|
|
|
* resources acquired in the init functions.
|
|
|
|
*/
|
2014-09-30 16:56:43 +08:00
|
|
|
void intel_irq_uninstall(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
drm_irq_uninstall(dev_priv->dev);
|
|
|
|
intel_hpd_cancel_work(dev_priv);
|
|
|
|
dev_priv->pm.irqs_enabled = false;
|
|
|
|
}
|
|
|
|
|
2014-09-30 16:56:45 +08:00
|
|
|
/**
|
|
|
|
* intel_runtime_pm_disable_interrupts - runtime interrupt disabling
|
|
|
|
* @dev_priv: i915 device instance
|
|
|
|
*
|
|
|
|
* This function is used to disable interrupts at runtime, both in the runtime
|
|
|
|
* pm and the system suspend/resume code.
|
|
|
|
*/
|
2014-09-30 16:56:44 +08:00
|
|
|
void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
|
2013-08-20 00:18:09 +08:00
|
|
|
{
|
2014-09-30 16:56:44 +08:00
|
|
|
dev_priv->dev->driver->irq_uninstall(dev_priv->dev);
|
2014-09-30 16:56:43 +08:00
|
|
|
dev_priv->pm.irqs_enabled = false;
|
2015-02-24 17:14:30 +08:00
|
|
|
synchronize_irq(dev_priv->dev->irq);
|
2013-08-20 00:18:09 +08:00
|
|
|
}
|
|
|
|
|
2014-09-30 16:56:45 +08:00
|
|
|
/**
|
|
|
|
* intel_runtime_pm_enable_interrupts - runtime interrupt enabling
|
|
|
|
* @dev_priv: i915 device instance
|
|
|
|
*
|
|
|
|
* This function is used to enable interrupts at runtime, both in the runtime
|
|
|
|
* pm and the system suspend/resume code.
|
|
|
|
*/
|
2014-09-30 16:56:44 +08:00
|
|
|
void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
|
2013-08-20 00:18:09 +08:00
|
|
|
{
|
2014-09-30 16:56:43 +08:00
|
|
|
dev_priv->pm.irqs_enabled = true;
|
2014-09-30 16:56:44 +08:00
|
|
|
dev_priv->dev->driver->irq_preinstall(dev_priv->dev);
|
|
|
|
dev_priv->dev->driver->irq_postinstall(dev_priv->dev);
|
2013-08-20 00:18:09 +08:00
|
|
|
}
|