riscv: Introduce alternative mechanism to apply errata solution
Introduce the "alternative" mechanism from ARM64 and x86 to apply the CPU
vendors' errata solution at runtime. The main purpose of this patch is
to provide a framework. Therefore, the implementation is quite basic for
now so that some scenarios could not use this schemei, such as patching
code to a module, relocating the patching code and heterogeneous CPU
topology.
Users could use the macro ALTERNATIVE to apply an errata to the existing
code flow. In the macro ALTERNATIVE, users need to specify the manufacturer
information(vendorid, archid, and impid) for this errata. Therefore, kernel
will know this errata is suitable for which CPU core. During the booting
procedure, kernel will select the errata required by the CPU core and then
patch it. It means that the kernel only applies the errata to the specified
CPU core. In this case, the vendor's errata does not affect each other at
runtime. The above patching procedure only occurs during the booting phase,
so we only take the overhead of the "alternative" mechanism once.
This "alternative" mechanism is enabled by default to ensure that all
required errata will be applied. However, users can disable this feature by
the Kconfig "CONFIG_RISCV_ERRATA_ALTERNATIVE".
Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2021-03-22 22:26:03 +08:00
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menu "CPU errata selection"
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2021-03-22 22:26:04 +08:00
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config ERRATA_SIFIVE
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bool "SiFive errata"
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2022-05-12 03:29:10 +08:00
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depends on !XIP_KERNEL
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select RISCV_ALTERNATIVE
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2021-03-22 22:26:04 +08:00
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help
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All SiFive errata Kconfig depend on this Kconfig. Disabling
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this Kconfig will disable all SiFive errata. Please say "Y"
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here if your platform uses SiFive CPU cores.
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Otherwise, please say "N" here to avoid unnecessary overhead.
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2021-03-22 22:26:05 +08:00
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config ERRATA_SIFIVE_CIP_453
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bool "Apply SiFive errata CIP-453"
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2021-04-29 15:58:36 +08:00
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depends on ERRATA_SIFIVE && 64BIT
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2021-03-22 22:26:05 +08:00
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default y
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help
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This will apply the SiFive CIP-453 errata to add sign extension
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to the $badaddr when exception type is instruction page fault
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and instruction access fault.
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If you don't know what to do here, say "Y".
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2021-03-22 22:26:06 +08:00
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config ERRATA_SIFIVE_CIP_1200
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bool "Apply SiFive errata CIP-1200"
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2021-04-29 15:58:36 +08:00
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depends on ERRATA_SIFIVE && 64BIT
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2021-03-22 22:26:06 +08:00
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default y
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help
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This will apply the SiFive CIP-1200 errata to repalce all
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"sfence.vma addr" with "sfence.vma" to ensure that the addr
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has been flushed from TLB.
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If you don't know what to do here, say "Y".
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2022-05-12 03:29:21 +08:00
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config ERRATA_THEAD
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bool "T-HEAD errata"
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2022-05-27 04:56:45 +08:00
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depends on !XIP_KERNEL
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2022-05-12 03:29:21 +08:00
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select RISCV_ALTERNATIVE
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help
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All T-HEAD errata Kconfig depend on this Kconfig. Disabling
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this Kconfig will disable all T-HEAD errata. Please say "Y"
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here if your platform uses T-HEAD CPU cores.
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Otherwise, please say "N" here to avoid unnecessary overhead.
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config ERRATA_THEAD_PBMT
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bool "Apply T-Head memory type errata"
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2022-09-07 23:49:32 +08:00
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depends on ERRATA_THEAD && 64BIT && MMU
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2022-05-12 03:29:21 +08:00
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select RISCV_ALTERNATIVE_EARLY
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default y
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help
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This will apply the memory type errata to handle the non-standard
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memory type bits in page-table-entries on T-Head SoCs.
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If you don't know what to do here, say "Y".
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2022-07-07 07:15:36 +08:00
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config ERRATA_THEAD_CMO
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bool "Apply T-Head cache management errata"
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2022-09-07 23:49:32 +08:00
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depends on ERRATA_THEAD && MMU
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2022-07-07 07:15:36 +08:00
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select RISCV_DMA_NONCOHERENT
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default y
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help
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This will apply the cache management errata to handle the
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non-standard handling on non-coherent operations on T-Head SoCs.
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If you don't know what to do here, say "Y".
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2022-10-12 07:18:41 +08:00
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config ERRATA_THEAD_PMU
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bool "Apply T-Head PMU errata"
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depends on ERRATA_THEAD && RISCV_PMU_SBI
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default y
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help
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The T-Head C9xx cores implement a PMU overflow extension very
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similar to the core SSCOFPMF extension.
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This will apply the overflow errata to handle the non-standard
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behaviour via the regular SBI PMU driver and interface.
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If you don't know what to do here, say "Y".
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2022-05-20 20:02:31 +08:00
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endmenu # "CPU errata selection"
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