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linux/arch/arm/mach-zynq/common.h

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ARM: Xilinx: Adding Xilinx board support The 1st board support is minimal to get a system up and running on the Xilinx platform. This platform reuses the clock implementation from plat-versatile, and it depends entirely on CONFIG_OF support. There is only one board support file which obtains all device information from a device tree dtb file which is passed to the kernel at boot time. Signed-off-by: John Linn <john.linn@xilinx.com>
2011-06-21 01:47:27 +08:00
/*
* This file contains common function prototypes to avoid externs
* in the c files.
*
* Copyright (C) 2011 Xilinx
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __MACH_ZYNQ_COMMON_H__
#define __MACH_ZYNQ_COMMON_H__
arm: zynq: Invalidate L1 in secondary boot During boot, Linux initiates a clean-invalidate operation only, resulting in faulty data to be written to the memory system during resume. Therefore invalidate the L1 in the secondary boot path to avoid these issues. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-11-01 00:10:15 +08:00
void zynq_secondary_startup(void);
arm: zynq: Move slcr initialization to separate file Create separate slcr driver instead of polluting common code. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-03-27 19:37:53 +08:00
extern int zynq_slcr_init(void);
ARM: zynq: Split slcr in two parts Split the slcr into an early part for unlocking and cpu starting and a later syscon driver. Also add "syscon" compatible property for slcr. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-11-26 22:41:31 +08:00
extern int zynq_early_slcr_init(void);
arm: zynq: Add support for system reset Do system reset via slcr registers. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-03-20 18:42:15 +08:00
extern void zynq_slcr_system_reset(void);
arm: zynq: Add smp support Zynq is dual core Cortex A9 which starts always at zero. Using simple trampoline ensure long jump to secondary_startup code. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
2013-03-20 20:50:12 +08:00
extern void zynq_slcr_cpu_stop(int cpu);
extern void zynq_slcr_cpu_start(int cpu);
ARM: zynq: Add support for SOC_BUS Provide information through SOC_BUS to user space. Silicon revision is provided through devcfg device. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-07-31 15:19:59 +08:00
extern u32 zynq_slcr_get_device_id(void);
arm: zynq: Add smp support Zynq is dual core Cortex A9 which starts always at zero. Using simple trampoline ensure long jump to secondary_startup code. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
2013-03-20 20:50:12 +08:00
#ifdef CONFIG_SMP
extern void secondary_startup(void);
extern char zynq_secondary_trampoline;
extern char zynq_secondary_trampoline_jump;
extern char zynq_secondary_trampoline_end;
arm: delete __cpuinit/__CPUINIT usage from all ARM users The __cpuinit type of throwaway sections might have made sense some time ago when RAM was more constrained, but now the savings do not offset the cost and complications. For example, the fix in commit 5e427ec2d0 ("x86: Fix bit corruption at CPU resume time") is a good example of the nasty type of bugs that can be created with improper use of the various __init prefixes. After a discussion on LKML[1] it was decided that cpuinit should go the way of devinit and be phased out. Once all the users are gone, we can then finally remove the macros themselves from linux/init.h. Note that some harmless section mismatch warnings may result, since notify_cpu_starting() and cpu_up() are arch independent (kernel/cpu.c) and are flagged as __cpuinit -- so if we remove the __cpuinit from the arch specific callers, we will also get section mismatch warnings. As an intermediate step, we intend to turn the linux/init.h cpuinit related content into no-ops as early as possible, since that will get rid of these warnings. In any case, they are temporary and harmless. This removes all the ARM uses of the __cpuinit macros from C code, and all __CPUINIT from assembly code. It also had two ".previous" section statements that were paired off against __CPUINIT (aka .section ".cpuinit.text") that also get removed here. [1] https://lkml.org/lkml/2013/5/20/589 Cc: Russell King <linux@arm.linux.org.uk> Cc: Will Deacon <will.deacon@arm.com> Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
2013-06-18 03:43:14 +08:00
extern int zynq_cpun_start(u32 address, int cpu);
arm: zynq: Add smp support Zynq is dual core Cortex A9 which starts always at zero. Using simple trampoline ensure long jump to secondary_startup code. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
2013-03-20 20:50:12 +08:00
extern struct smp_operations zynq_smp_ops __initdata;
#endif
arm: zynq: Move slcr initialization to separate file Create separate slcr driver instead of polluting common code. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-03-27 19:37:53 +08:00
arm: zynq: Load scu baseaddress at run time Use Cortex a9 cp15 to read scu baseaddress. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-03-20 18:11:43 +08:00
extern void __iomem *zynq_scu_base;
arm: zynq: Add hotplug support Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-03-20 20:56:15 +08:00
/* Hotplug */
extern void zynq_platform_cpu_die(unsigned int cpu);
ARM: zynq: PM: Enable DDR clock stop The DDR controller can detect idle periods and leverage low power features clock stop. When new requests occur, the DDRC resumes normal operation. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-09-03 05:19:09 +08:00
void zynq_pm_late_init(void);
ARM: zynq: PM: Enable A9 internal clock gating feature Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-09-03 05:19:06 +08:00
static inline void zynq_core_pm_init(void)
{
/* A9 clock gating */
asm volatile ("mrc p15, 0, r12, c15, c0, 0\n"
"orr r12, r12, #1\n"
"mcr p15, 0, r12, c15, c0, 0\n"
: /* no outputs */
: /* no inputs */
: "r12");
}
ARM: Xilinx: Adding Xilinx board support The 1st board support is minimal to get a system up and running on the Xilinx platform. This platform reuses the clock implementation from plat-versatile, and it depends entirely on CONFIG_OF support. There is only one board support file which obtains all device information from a device tree dtb file which is passed to the kernel at boot time. Signed-off-by: John Linn <john.linn@xilinx.com>
2011-06-21 01:47:27 +08:00
#endif
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