2021-02-17 12:09:51 +08:00
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* Copyright(c) 2020 Intel Corporation. */
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#ifndef __CXL_H__
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#define __CXL_H__
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2021-06-16 07:18:17 +08:00
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#include <linux/libnvdimm.h>
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2021-02-17 12:09:51 +08:00
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#include <linux/bitfield.h>
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#include <linux/bitops.h>
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#include <linux/io.h>
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2021-06-10 00:01:35 +08:00
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/**
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* DOC: cxl objects
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*
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* The CXL core objects like ports, decoders, and regions are shared
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* between the subsystem drivers cxl_acpi, cxl_pci, and core drivers
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* (port-driver, region-driver, nvdimm object-drivers... etc).
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*/
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2022-02-02 04:24:30 +08:00
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/* CXL 2.0 8.2.4 CXL Component Register Layout and Definition */
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#define CXL_COMPONENT_REG_BLOCK_SIZE SZ_64K
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2021-05-28 08:49:22 +08:00
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/* CXL 2.0 8.2.5 CXL.cache and CXL.mem Registers*/
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#define CXL_CM_OFFSET 0x1000
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#define CXL_CM_CAP_HDR_OFFSET 0x0
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#define CXL_CM_CAP_HDR_ID_MASK GENMASK(15, 0)
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#define CM_CAP_HDR_CAP_ID 1
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#define CXL_CM_CAP_HDR_VERSION_MASK GENMASK(19, 16)
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#define CM_CAP_HDR_CAP_VERSION 1
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#define CXL_CM_CAP_HDR_CACHE_MEM_VERSION_MASK GENMASK(23, 20)
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#define CM_CAP_HDR_CACHE_MEM_VERSION 1
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#define CXL_CM_CAP_HDR_ARRAY_SIZE_MASK GENMASK(31, 24)
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#define CXL_CM_CAP_PTR_MASK GENMASK(31, 20)
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#define CXL_CM_CAP_CAP_ID_HDM 0x5
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#define CXL_CM_CAP_CAP_HDM_VERSION 1
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/* HDM decoders CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure */
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#define CXL_HDM_DECODER_CAP_OFFSET 0x0
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#define CXL_HDM_DECODER_COUNT_MASK GENMASK(3, 0)
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#define CXL_HDM_DECODER_TARGET_COUNT_MASK GENMASK(7, 4)
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2022-02-02 04:24:30 +08:00
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#define CXL_HDM_DECODER_INTERLEAVE_11_8 BIT(8)
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#define CXL_HDM_DECODER_INTERLEAVE_14_12 BIT(9)
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#define CXL_HDM_DECODER_CTRL_OFFSET 0x4
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#define CXL_HDM_DECODER_ENABLE BIT(1)
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#define CXL_HDM_DECODER0_BASE_LOW_OFFSET(i) (0x20 * (i) + 0x10)
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#define CXL_HDM_DECODER0_BASE_HIGH_OFFSET(i) (0x20 * (i) + 0x14)
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#define CXL_HDM_DECODER0_SIZE_LOW_OFFSET(i) (0x20 * (i) + 0x18)
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#define CXL_HDM_DECODER0_SIZE_HIGH_OFFSET(i) (0x20 * (i) + 0x1c)
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#define CXL_HDM_DECODER0_CTRL_OFFSET(i) (0x20 * (i) + 0x20)
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#define CXL_HDM_DECODER0_CTRL_IG_MASK GENMASK(3, 0)
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#define CXL_HDM_DECODER0_CTRL_IW_MASK GENMASK(7, 4)
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#define CXL_HDM_DECODER0_CTRL_LOCK BIT(8)
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#define CXL_HDM_DECODER0_CTRL_COMMIT BIT(9)
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#define CXL_HDM_DECODER0_CTRL_COMMITTED BIT(10)
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#define CXL_HDM_DECODER0_CTRL_TYPE BIT(12)
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#define CXL_HDM_DECODER0_TL_LOW(i) (0x20 * (i) + 0x24)
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#define CXL_HDM_DECODER0_TL_HIGH(i) (0x20 * (i) + 0x28)
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2022-07-22 08:19:12 +08:00
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#define CXL_HDM_DECODER0_SKIP_LOW(i) CXL_HDM_DECODER0_TL_LOW(i)
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#define CXL_HDM_DECODER0_SKIP_HIGH(i) CXL_HDM_DECODER0_TL_HIGH(i)
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2021-05-28 08:49:22 +08:00
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2021-06-12 03:01:11 +08:00
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static inline int cxl_hdm_decoder_count(u32 cap_hdr)
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{
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int val = FIELD_GET(CXL_HDM_DECODER_COUNT_MASK, cap_hdr);
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return val ? val * 2 : 1;
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}
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2022-05-23 08:04:27 +08:00
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/* Encode defined in CXL 2.0 8.2.5.12.7 HDM Decoder Control Register */
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static inline int cxl_to_granularity(u16 ig, unsigned int *val)
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{
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if (ig > 6)
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return -EINVAL;
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*val = 256 << ig;
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return 0;
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}
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/* Encode defined in CXL ECN "3, 6, 12 and 16-way memory Interleaving" */
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static inline int cxl_to_ways(u8 eniw, unsigned int *val)
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{
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switch (eniw) {
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case 0 ... 4:
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*val = 1 << eniw;
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break;
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case 8 ... 10:
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*val = 3 << (eniw - 8);
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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2021-02-17 12:09:51 +08:00
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/* CXL 2.0 8.2.8.1 Device Capabilities Array Register */
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#define CXLDEV_CAP_ARRAY_OFFSET 0x0
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#define CXLDEV_CAP_ARRAY_CAP_ID 0
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#define CXLDEV_CAP_ARRAY_ID_MASK GENMASK_ULL(15, 0)
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#define CXLDEV_CAP_ARRAY_COUNT_MASK GENMASK_ULL(47, 32)
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/* CXL 2.0 8.2.8.2 CXL Device Capability Header Register */
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#define CXLDEV_CAP_HDR_CAP_ID_MASK GENMASK(15, 0)
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/* CXL 2.0 8.2.8.2.1 CXL Device Capabilities */
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#define CXLDEV_CAP_CAP_ID_DEVICE_STATUS 0x1
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#define CXLDEV_CAP_CAP_ID_PRIMARY_MAILBOX 0x2
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#define CXLDEV_CAP_CAP_ID_SECONDARY_MAILBOX 0x3
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#define CXLDEV_CAP_CAP_ID_MEMDEV 0x4000
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/* CXL 2.0 8.2.8.4 Mailbox Registers */
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#define CXLDEV_MBOX_CAPS_OFFSET 0x00
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#define CXLDEV_MBOX_CAP_PAYLOAD_SIZE_MASK GENMASK(4, 0)
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#define CXLDEV_MBOX_CTRL_OFFSET 0x04
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#define CXLDEV_MBOX_CTRL_DOORBELL BIT(0)
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#define CXLDEV_MBOX_CMD_OFFSET 0x08
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#define CXLDEV_MBOX_CMD_COMMAND_OPCODE_MASK GENMASK_ULL(15, 0)
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#define CXLDEV_MBOX_CMD_PAYLOAD_LENGTH_MASK GENMASK_ULL(36, 16)
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#define CXLDEV_MBOX_STATUS_OFFSET 0x10
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#define CXLDEV_MBOX_STATUS_RET_CODE_MASK GENMASK_ULL(47, 32)
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#define CXLDEV_MBOX_BG_CMD_STATUS_OFFSET 0x18
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#define CXLDEV_MBOX_PAYLOAD_OFFSET 0x20
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cxl/mem: Introduce 'struct cxl_regs' for "composable" CXL devices
CXL MMIO register blocks are organized by device type and capabilities.
There are Component registers, Device registers (yes, an ambiguous
name), and Memory Device registers (a specific extension of Device
registers).
It is possible for a given device instance (endpoint or port) to
implement register sets from multiple of the above categories.
The driver code that enumerates and maps the registers is type specific
so it is useful to have a dedicated type and helpers for each block
type.
At the same time, once the registers are mapped the origin type does not
matter. It is overly pedantic to reference the register block type in
code that is using the registers.
In preparation for the endpoint driver to incorporate Component registers
into its MMIO operations reorganize the registers to allow typed
enumeration + mapping, but anonymous usage. With the end state of
'struct cxl_regs' to be:
struct cxl_regs {
union {
struct {
CXL_DEVICE_REGS();
};
struct cxl_device_regs device_regs;
};
union {
struct {
CXL_COMPONENT_REGS();
};
struct cxl_component_regs component_regs;
};
};
With this arrangement the driver can share component init code with
ports, but when using the registers it can directly reference the
component register block type by name without the 'component_regs'
prefix.
So, map + enumerate can be shared across drivers of different CXL
classes e.g.:
void cxl_setup_device_regs(struct device *dev, void __iomem *base,
struct cxl_device_regs *regs);
void cxl_setup_component_regs(struct device *dev, void __iomem *base,
struct cxl_component_regs *regs);
...while inline usage in the driver need not indicate where the
registers came from:
readl(cxlm->regs.mbox + MBOX_OFFSET);
readl(cxlm->regs.hdm + HDM_OFFSET);
...instead of:
readl(cxlm->regs.device_regs.mbox + MBOX_OFFSET);
readl(cxlm->regs.component_regs.hdm + HDM_OFFSET);
This complexity of the definition in .h yields improvement in code
readability in .c while maintaining type-safety for organization of
setup code. It prepares the implementation to maintain organization in
the face of CXL devices that compose register interfaces consisting of
multiple types.
Given that this new container is named 'regs' rename the common register
base pointer @base, and fixup the kernel-doc for the missing @cxlmd
description.
Reviewed-by: Ben Widawsky <ben.widawsky@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Christoph Hellwig <hch@lst.de>
Link: https://lore.kernel.org/r/162096971451.1865304.13540251513463515153.stgit@dwillia2-desk3.amr.corp.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2021-05-14 13:21:54 +08:00
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/*
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2021-07-31 11:25:50 +08:00
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* Using struct_group() allows for per register-block-type helper routines,
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* without requiring block-type agnostic code to include the prefix.
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cxl/mem: Introduce 'struct cxl_regs' for "composable" CXL devices
CXL MMIO register blocks are organized by device type and capabilities.
There are Component registers, Device registers (yes, an ambiguous
name), and Memory Device registers (a specific extension of Device
registers).
It is possible for a given device instance (endpoint or port) to
implement register sets from multiple of the above categories.
The driver code that enumerates and maps the registers is type specific
so it is useful to have a dedicated type and helpers for each block
type.
At the same time, once the registers are mapped the origin type does not
matter. It is overly pedantic to reference the register block type in
code that is using the registers.
In preparation for the endpoint driver to incorporate Component registers
into its MMIO operations reorganize the registers to allow typed
enumeration + mapping, but anonymous usage. With the end state of
'struct cxl_regs' to be:
struct cxl_regs {
union {
struct {
CXL_DEVICE_REGS();
};
struct cxl_device_regs device_regs;
};
union {
struct {
CXL_COMPONENT_REGS();
};
struct cxl_component_regs component_regs;
};
};
With this arrangement the driver can share component init code with
ports, but when using the registers it can directly reference the
component register block type by name without the 'component_regs'
prefix.
So, map + enumerate can be shared across drivers of different CXL
classes e.g.:
void cxl_setup_device_regs(struct device *dev, void __iomem *base,
struct cxl_device_regs *regs);
void cxl_setup_component_regs(struct device *dev, void __iomem *base,
struct cxl_component_regs *regs);
...while inline usage in the driver need not indicate where the
registers came from:
readl(cxlm->regs.mbox + MBOX_OFFSET);
readl(cxlm->regs.hdm + HDM_OFFSET);
...instead of:
readl(cxlm->regs.device_regs.mbox + MBOX_OFFSET);
readl(cxlm->regs.component_regs.hdm + HDM_OFFSET);
This complexity of the definition in .h yields improvement in code
readability in .c while maintaining type-safety for organization of
setup code. It prepares the implementation to maintain organization in
the face of CXL devices that compose register interfaces consisting of
multiple types.
Given that this new container is named 'regs' rename the common register
base pointer @base, and fixup the kernel-doc for the missing @cxlmd
description.
Reviewed-by: Ben Widawsky <ben.widawsky@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Christoph Hellwig <hch@lst.de>
Link: https://lore.kernel.org/r/162096971451.1865304.13540251513463515153.stgit@dwillia2-desk3.amr.corp.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2021-05-14 13:21:54 +08:00
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*/
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struct cxl_regs {
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2021-07-31 11:25:50 +08:00
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/*
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* Common set of CXL Component register block base pointers
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* @hdm_decoder: CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure
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*/
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struct_group_tagged(cxl_component_regs, component,
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void __iomem *hdm_decoder;
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);
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/*
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* Common set of CXL Device register block base pointers
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* @status: CXL 2.0 8.2.8.3 Device Status Registers
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* @mbox: CXL 2.0 8.2.8.4 Mailbox Registers
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* @memdev: CXL 2.0 8.2.8.5 Memory Device Registers
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*/
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struct_group_tagged(cxl_device_regs, device_regs,
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void __iomem *status, *mbox, *memdev;
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);
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cxl/mem: Introduce 'struct cxl_regs' for "composable" CXL devices
CXL MMIO register blocks are organized by device type and capabilities.
There are Component registers, Device registers (yes, an ambiguous
name), and Memory Device registers (a specific extension of Device
registers).
It is possible for a given device instance (endpoint or port) to
implement register sets from multiple of the above categories.
The driver code that enumerates and maps the registers is type specific
so it is useful to have a dedicated type and helpers for each block
type.
At the same time, once the registers are mapped the origin type does not
matter. It is overly pedantic to reference the register block type in
code that is using the registers.
In preparation for the endpoint driver to incorporate Component registers
into its MMIO operations reorganize the registers to allow typed
enumeration + mapping, but anonymous usage. With the end state of
'struct cxl_regs' to be:
struct cxl_regs {
union {
struct {
CXL_DEVICE_REGS();
};
struct cxl_device_regs device_regs;
};
union {
struct {
CXL_COMPONENT_REGS();
};
struct cxl_component_regs component_regs;
};
};
With this arrangement the driver can share component init code with
ports, but when using the registers it can directly reference the
component register block type by name without the 'component_regs'
prefix.
So, map + enumerate can be shared across drivers of different CXL
classes e.g.:
void cxl_setup_device_regs(struct device *dev, void __iomem *base,
struct cxl_device_regs *regs);
void cxl_setup_component_regs(struct device *dev, void __iomem *base,
struct cxl_component_regs *regs);
...while inline usage in the driver need not indicate where the
registers came from:
readl(cxlm->regs.mbox + MBOX_OFFSET);
readl(cxlm->regs.hdm + HDM_OFFSET);
...instead of:
readl(cxlm->regs.device_regs.mbox + MBOX_OFFSET);
readl(cxlm->regs.component_regs.hdm + HDM_OFFSET);
This complexity of the definition in .h yields improvement in code
readability in .c while maintaining type-safety for organization of
setup code. It prepares the implementation to maintain organization in
the face of CXL devices that compose register interfaces consisting of
multiple types.
Given that this new container is named 'regs' rename the common register
base pointer @base, and fixup the kernel-doc for the missing @cxlmd
description.
Reviewed-by: Ben Widawsky <ben.widawsky@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Christoph Hellwig <hch@lst.de>
Link: https://lore.kernel.org/r/162096971451.1865304.13540251513463515153.stgit@dwillia2-desk3.amr.corp.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2021-05-14 13:21:54 +08:00
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};
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2021-06-04 08:50:36 +08:00
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struct cxl_reg_map {
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bool valid;
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unsigned long offset;
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unsigned long size;
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};
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2021-05-28 08:49:22 +08:00
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struct cxl_component_reg_map {
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struct cxl_reg_map hdm_decoder;
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};
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2021-06-04 08:50:36 +08:00
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struct cxl_device_reg_map {
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struct cxl_reg_map status;
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struct cxl_reg_map mbox;
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struct cxl_reg_map memdev;
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};
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2021-10-16 05:57:27 +08:00
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/**
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* struct cxl_register_map - DVSEC harvested register block mapping parameters
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* @base: virtual base of the register-block-BAR + @block_offset
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* @block_offset: offset to start of register block in @barno
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* @reg_type: see enum cxl_regloc_type
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* @barno: PCI BAR number containing the register block
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* @component_map: cxl_reg_map for component registers
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* @device_map: cxl_reg_maps for device registers
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*/
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2021-06-04 08:50:36 +08:00
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struct cxl_register_map {
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2021-10-16 05:57:27 +08:00
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void __iomem *base;
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2021-06-04 08:50:36 +08:00
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u64 block_offset;
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u8 reg_type;
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u8 barno;
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union {
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2021-05-28 08:49:22 +08:00
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struct cxl_component_reg_map component_map;
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2021-06-04 08:50:36 +08:00
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struct cxl_device_reg_map device_map;
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};
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};
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2021-05-28 08:49:22 +08:00
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void cxl_probe_component_regs(struct device *dev, void __iomem *base,
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struct cxl_component_reg_map *map);
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2021-06-04 08:50:36 +08:00
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void cxl_probe_device_regs(struct device *dev, void __iomem *base,
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struct cxl_device_reg_map *map);
|
2021-05-28 08:49:22 +08:00
|
|
|
int cxl_map_component_regs(struct pci_dev *pdev,
|
|
|
|
|
struct cxl_component_regs *regs,
|
|
|
|
|
struct cxl_register_map *map);
|
2021-06-04 08:50:36 +08:00
|
|
|
int cxl_map_device_regs(struct pci_dev *pdev,
|
|
|
|
|
struct cxl_device_regs *regs,
|
|
|
|
|
struct cxl_register_map *map);
|
2021-05-14 13:22:05 +08:00
|
|
|
|
2022-01-24 08:29:10 +08:00
|
|
|
enum cxl_regloc_type;
|
|
|
|
|
int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type,
|
|
|
|
|
struct cxl_register_map *map);
|
2022-02-02 05:07:51 +08:00
|
|
|
void __iomem *devm_cxl_iomap_block(struct device *dev, resource_size_t addr,
|
|
|
|
|
resource_size_t length);
|
2022-01-24 08:29:10 +08:00
|
|
|
|
2021-06-10 00:01:35 +08:00
|
|
|
#define CXL_RESOURCE_NONE ((resource_size_t) -1)
|
2021-06-10 00:01:46 +08:00
|
|
|
#define CXL_TARGET_STRLEN 20
|
2021-06-10 00:01:35 +08:00
|
|
|
|
2021-06-10 00:43:29 +08:00
|
|
|
/*
|
|
|
|
|
* cxl_decoder flags that define the type of memory / devices this
|
|
|
|
|
* decoder supports as well as configuration lock status See "CXL 2.0
|
|
|
|
|
* 8.2.5.12.7 CXL HDM Decoder 0 Control Register" for details.
|
|
|
|
|
*/
|
|
|
|
|
#define CXL_DECODER_F_RAM BIT(0)
|
|
|
|
|
#define CXL_DECODER_F_PMEM BIT(1)
|
|
|
|
|
#define CXL_DECODER_F_TYPE2 BIT(2)
|
|
|
|
|
#define CXL_DECODER_F_TYPE3 BIT(3)
|
|
|
|
|
#define CXL_DECODER_F_LOCK BIT(4)
|
2022-02-02 04:24:30 +08:00
|
|
|
#define CXL_DECODER_F_ENABLE BIT(5)
|
|
|
|
|
#define CXL_DECODER_F_MASK GENMASK(5, 0)
|
2021-06-10 00:43:29 +08:00
|
|
|
|
|
|
|
|
enum cxl_decoder_type {
|
|
|
|
|
CXL_DECODER_ACCELERATOR = 2,
|
|
|
|
|
CXL_DECODER_EXPANDER = 3,
|
|
|
|
|
};
|
|
|
|
|
|
cxl/bus: Populate the target list at decoder create
As found by cxl_test, the implementation populated the target_list for
the single dport exceptional case, it missed populating the target_list
for the typical multi-dport case. Root decoders always know their target
list at the beginning of time, and even switch-level decoders should
have a target list of one or more zeros by default, depending on the
interleave-ways setting.
Walk the hosting port's dport list and populate based on the passed in
map.
Move devm_cxl_add_passthrough_decoder() out of line now that it does the
work of generating a target_map.
Before:
$ cat /sys/bus/cxl/devices/root2/decoder*/target_list
0
0
After:
$ cat /sys/bus/cxl/devices/root2/decoder*/target_list
0
0,1,2,3
0
0,1,2,3
Where root2 is a CXL topology root object generated by 'cxl_test'.
Acked-by: Ben Widawsky <ben.widawsky@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/163116439000.2460985.11713777051267946018.stgit@dwillia2-desk3.amr.corp.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2021-09-09 13:13:10 +08:00
|
|
|
/*
|
|
|
|
|
* Current specification goes up to 8, double that seems a reasonable
|
|
|
|
|
* software max for the foreseeable future
|
|
|
|
|
*/
|
|
|
|
|
#define CXL_DECODER_MAX_INTERLEAVE 16
|
|
|
|
|
|
2021-06-10 00:43:29 +08:00
|
|
|
/**
|
2022-05-19 08:52:23 +08:00
|
|
|
* struct cxl_decoder - Common CXL HDM Decoder Attributes
|
2021-06-10 00:43:29 +08:00
|
|
|
* @dev: this decoder's device
|
|
|
|
|
* @id: kernel device name id
|
2022-05-19 08:55:13 +08:00
|
|
|
* @hpa_range: Host physical address range mapped by this decoder
|
2021-06-10 00:43:29 +08:00
|
|
|
* @interleave_ways: number of cxl_dports in this decode
|
|
|
|
|
* @interleave_granularity: data stride per dport
|
|
|
|
|
* @target_type: accelerator vs expander (type2 vs type3) selector
|
|
|
|
|
* @flags: memory type capabilities and locking
|
|
|
|
|
*/
|
|
|
|
|
struct cxl_decoder {
|
|
|
|
|
struct device dev;
|
|
|
|
|
int id;
|
2022-05-19 09:02:39 +08:00
|
|
|
struct range hpa_range;
|
2021-06-10 00:43:29 +08:00
|
|
|
int interleave_ways;
|
|
|
|
|
int interleave_granularity;
|
|
|
|
|
enum cxl_decoder_type target_type;
|
|
|
|
|
unsigned long flags;
|
2022-05-19 08:52:23 +08:00
|
|
|
};
|
|
|
|
|
|
2022-05-24 03:15:35 +08:00
|
|
|
enum cxl_decoder_mode {
|
|
|
|
|
CXL_DECODER_NONE,
|
|
|
|
|
CXL_DECODER_RAM,
|
|
|
|
|
CXL_DECODER_PMEM,
|
|
|
|
|
CXL_DECODER_MIXED,
|
|
|
|
|
};
|
|
|
|
|
|
2022-05-22 07:24:14 +08:00
|
|
|
/**
|
|
|
|
|
* struct cxl_endpoint_decoder - Endpoint / SPA to DPA decoder
|
|
|
|
|
* @cxld: base cxl_decoder_object
|
|
|
|
|
* @dpa_res: actively claimed DPA span of this decoder
|
|
|
|
|
* @skip: offset into @dpa_res where @cxld.hpa_range maps
|
2022-05-24 03:15:35 +08:00
|
|
|
* @mode: which memory type / access-mode-partition this decoder targets
|
2022-05-22 07:24:14 +08:00
|
|
|
*/
|
|
|
|
|
struct cxl_endpoint_decoder {
|
|
|
|
|
struct cxl_decoder cxld;
|
|
|
|
|
struct resource *dpa_res;
|
|
|
|
|
resource_size_t skip;
|
2022-05-24 03:15:35 +08:00
|
|
|
enum cxl_decoder_mode mode;
|
2022-05-22 07:24:14 +08:00
|
|
|
};
|
|
|
|
|
|
2022-05-19 08:52:23 +08:00
|
|
|
/**
|
|
|
|
|
* struct cxl_switch_decoder - Switch specific CXL HDM Decoder
|
|
|
|
|
* @cxld: base cxl_decoder object
|
|
|
|
|
* @target_lock: coordinate coherent reads of the target list
|
|
|
|
|
* @nr_targets: number of elements in @target
|
|
|
|
|
* @target: active ordered target list in current decoder configuration
|
|
|
|
|
*
|
|
|
|
|
* The 'switch' decoder type represents the decoder instances of cxl_port's that
|
|
|
|
|
* route from the root of a CXL memory decode topology to the endpoints. They
|
|
|
|
|
* come in two flavors, root-level decoders, statically defined by platform
|
|
|
|
|
* firmware, and mid-level decoders, where interleave-granularity,
|
|
|
|
|
* interleave-width, and the target list are mutable.
|
|
|
|
|
*/
|
|
|
|
|
struct cxl_switch_decoder {
|
|
|
|
|
struct cxl_decoder cxld;
|
2022-02-01 07:35:18 +08:00
|
|
|
seqlock_t target_lock;
|
2021-12-11 05:36:27 +08:00
|
|
|
int nr_targets;
|
2021-06-10 00:43:29 +08:00
|
|
|
struct cxl_dport *target[];
|
|
|
|
|
};
|
|
|
|
|
|
2021-06-16 07:18:17 +08:00
|
|
|
|
2022-07-13 09:38:26 +08:00
|
|
|
/**
|
|
|
|
|
* struct cxl_root_decoder - Static platform CXL address decoder
|
|
|
|
|
* @res: host / parent resource for region allocations
|
|
|
|
|
* @cxlsd: base cxl switch decoder
|
|
|
|
|
*/
|
|
|
|
|
struct cxl_root_decoder {
|
|
|
|
|
struct resource *res;
|
|
|
|
|
struct cxl_switch_decoder cxlsd;
|
|
|
|
|
};
|
|
|
|
|
|
2021-11-12 02:19:05 +08:00
|
|
|
/**
|
|
|
|
|
* enum cxl_nvdimm_brige_state - state machine for managing bus rescans
|
|
|
|
|
* @CXL_NVB_NEW: Set at bridge create and after cxl_pmem_wq is destroyed
|
|
|
|
|
* @CXL_NVB_DEAD: Set at brige unregistration to preclude async probing
|
|
|
|
|
* @CXL_NVB_ONLINE: Target state after successful ->probe()
|
|
|
|
|
* @CXL_NVB_OFFLINE: Target state after ->remove() or failed ->probe()
|
|
|
|
|
*/
|
2021-06-16 07:18:17 +08:00
|
|
|
enum cxl_nvdimm_brige_state {
|
|
|
|
|
CXL_NVB_NEW,
|
|
|
|
|
CXL_NVB_DEAD,
|
|
|
|
|
CXL_NVB_ONLINE,
|
|
|
|
|
CXL_NVB_OFFLINE,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
struct cxl_nvdimm_bridge {
|
2021-09-15 03:08:40 +08:00
|
|
|
int id;
|
2021-06-16 07:18:17 +08:00
|
|
|
struct device dev;
|
|
|
|
|
struct cxl_port *port;
|
|
|
|
|
struct nvdimm_bus *nvdimm_bus;
|
|
|
|
|
struct nvdimm_bus_descriptor nd_desc;
|
|
|
|
|
struct work_struct state_work;
|
|
|
|
|
enum cxl_nvdimm_brige_state state;
|
|
|
|
|
};
|
|
|
|
|
|
2021-06-16 07:36:31 +08:00
|
|
|
struct cxl_nvdimm {
|
|
|
|
|
struct device dev;
|
|
|
|
|
struct cxl_memdev *cxlmd;
|
|
|
|
|
};
|
|
|
|
|
|
2021-06-10 00:01:35 +08:00
|
|
|
/**
|
|
|
|
|
* struct cxl_port - logical collection of upstream port devices and
|
|
|
|
|
* downstream port devices to construct a CXL memory
|
|
|
|
|
* decode hierarchy.
|
|
|
|
|
* @dev: this port's device
|
|
|
|
|
* @uport: PCI or platform device implementing the upstream port capability
|
2022-06-02 03:49:32 +08:00
|
|
|
* @host_bridge: Shortcut to the platform attach point for this port
|
2021-06-10 00:01:35 +08:00
|
|
|
* @id: id for port device-name
|
2021-06-10 00:01:46 +08:00
|
|
|
* @dports: cxl_dport instances referenced by decoders
|
2022-02-04 23:08:40 +08:00
|
|
|
* @endpoints: cxl_ep instances, endpoints that are a descendant of this port
|
2022-05-28 01:57:01 +08:00
|
|
|
* @parent_dport: dport that points to this port in the parent
|
2021-06-10 00:43:29 +08:00
|
|
|
* @decoder_ida: allocator for decoder ids
|
2022-05-25 03:04:58 +08:00
|
|
|
* @hdm_end: track last allocated HDM decoder instance for allocation ordering
|
2021-06-10 00:01:35 +08:00
|
|
|
* @component_reg_phys: component register capability base address (optional)
|
2022-02-04 23:08:40 +08:00
|
|
|
* @dead: last ep has been removed, force port re-creation
|
2022-01-24 08:29:53 +08:00
|
|
|
* @depth: How deep this port is relative to the root. depth 0 is the root.
|
2022-07-20 04:52:49 +08:00
|
|
|
* @cdat: Cached CDAT data
|
|
|
|
|
* @cdat_available: Should a CDAT attribute be available in sysfs
|
2021-06-10 00:01:35 +08:00
|
|
|
*/
|
|
|
|
|
struct cxl_port {
|
|
|
|
|
struct device dev;
|
|
|
|
|
struct device *uport;
|
2022-06-02 03:49:32 +08:00
|
|
|
struct device *host_bridge;
|
2021-06-10 00:01:35 +08:00
|
|
|
int id;
|
2022-05-28 11:51:19 +08:00
|
|
|
struct xarray dports;
|
2022-05-28 01:58:26 +08:00
|
|
|
struct xarray endpoints;
|
2022-05-28 01:57:01 +08:00
|
|
|
struct cxl_dport *parent_dport;
|
2021-06-10 00:43:29 +08:00
|
|
|
struct ida decoder_ida;
|
2022-05-25 03:04:58 +08:00
|
|
|
int hdm_end;
|
2021-06-10 00:01:35 +08:00
|
|
|
resource_size_t component_reg_phys;
|
2022-02-04 23:08:40 +08:00
|
|
|
bool dead;
|
2022-01-24 08:29:53 +08:00
|
|
|
unsigned int depth;
|
2022-07-20 04:52:49 +08:00
|
|
|
struct cxl_cdat {
|
|
|
|
|
void *table;
|
|
|
|
|
size_t length;
|
|
|
|
|
} cdat;
|
|
|
|
|
bool cdat_available;
|
2021-06-10 00:01:35 +08:00
|
|
|
};
|
|
|
|
|
|
2022-05-28 11:51:19 +08:00
|
|
|
static inline struct cxl_dport *
|
|
|
|
|
cxl_find_dport_by_dev(struct cxl_port *port, const struct device *dport_dev)
|
|
|
|
|
{
|
|
|
|
|
return xa_load(&port->dports, (unsigned long)dport_dev);
|
|
|
|
|
}
|
|
|
|
|
|
2021-06-10 00:01:46 +08:00
|
|
|
/**
|
|
|
|
|
* struct cxl_dport - CXL downstream port
|
|
|
|
|
* @dport: PCI bridge or firmware device representing the downstream link
|
|
|
|
|
* @port_id: unique hardware identifier for dport in decoder target list
|
|
|
|
|
* @component_reg_phys: downstream port component registers
|
|
|
|
|
* @port: reference to cxl_port that contains this downstream port
|
|
|
|
|
*/
|
|
|
|
|
struct cxl_dport {
|
|
|
|
|
struct device *dport;
|
|
|
|
|
int port_id;
|
|
|
|
|
resource_size_t component_reg_phys;
|
|
|
|
|
struct cxl_port *port;
|
|
|
|
|
};
|
|
|
|
|
|
2022-02-04 23:08:40 +08:00
|
|
|
/**
|
|
|
|
|
* struct cxl_ep - track an endpoint's interest in a port
|
|
|
|
|
* @ep: device that hosts a generic CXL endpoint (expander or accelerator)
|
2022-05-27 15:56:59 +08:00
|
|
|
* @dport: which dport routes to this endpoint on @port
|
2022-06-08 01:35:39 +08:00
|
|
|
* @next: cxl switch port across the link attached to @dport NULL if
|
|
|
|
|
* attached to an endpoint
|
2022-02-04 23:08:40 +08:00
|
|
|
*/
|
|
|
|
|
struct cxl_ep {
|
|
|
|
|
struct device *ep;
|
2022-05-27 15:56:59 +08:00
|
|
|
struct cxl_dport *dport;
|
2022-06-08 01:35:39 +08:00
|
|
|
struct cxl_port *next;
|
2022-02-04 23:08:40 +08:00
|
|
|
};
|
|
|
|
|
|
2022-02-01 05:33:13 +08:00
|
|
|
/*
|
|
|
|
|
* The platform firmware device hosting the root is also the top of the
|
|
|
|
|
* CXL port topology. All other CXL ports have another CXL port as their
|
|
|
|
|
* parent and their ->uport / host device is out-of-line of the port
|
|
|
|
|
* ancestry.
|
|
|
|
|
*/
|
|
|
|
|
static inline bool is_cxl_root(struct cxl_port *port)
|
|
|
|
|
{
|
|
|
|
|
return port->uport == port->dev.parent;
|
|
|
|
|
}
|
|
|
|
|
|
2022-02-01 03:50:09 +08:00
|
|
|
bool is_cxl_port(struct device *dev);
|
2021-06-10 00:01:35 +08:00
|
|
|
struct cxl_port *to_cxl_port(struct device *dev);
|
2022-02-01 10:10:04 +08:00
|
|
|
struct pci_bus;
|
2022-02-01 00:44:52 +08:00
|
|
|
int devm_cxl_register_pci_bus(struct device *host, struct device *uport,
|
|
|
|
|
struct pci_bus *bus);
|
|
|
|
|
struct pci_bus *cxl_port_to_pci_bus(struct cxl_port *port);
|
2021-06-10 00:01:35 +08:00
|
|
|
struct cxl_port *devm_cxl_add_port(struct device *host, struct device *uport,
|
|
|
|
|
resource_size_t component_reg_phys,
|
2022-05-28 01:57:01 +08:00
|
|
|
struct cxl_dport *parent_dport);
|
2022-06-08 01:35:39 +08:00
|
|
|
int devm_cxl_add_endpoint(struct cxl_memdev *cxlmd,
|
|
|
|
|
struct cxl_dport *parent_dport);
|
2022-02-01 08:34:40 +08:00
|
|
|
struct cxl_port *find_cxl_root(struct device *dev);
|
2022-02-04 23:08:40 +08:00
|
|
|
int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd);
|
2022-02-04 23:18:31 +08:00
|
|
|
int cxl_bus_rescan(void);
|
2022-05-28 01:57:01 +08:00
|
|
|
struct cxl_port *cxl_mem_find_port(struct cxl_memdev *cxlmd,
|
|
|
|
|
struct cxl_dport **dport);
|
2022-02-04 23:18:31 +08:00
|
|
|
bool schedule_cxl_memdev_detach(struct cxl_memdev *cxlmd);
|
2022-02-04 23:08:40 +08:00
|
|
|
|
2022-02-02 05:23:14 +08:00
|
|
|
struct cxl_dport *devm_cxl_add_dport(struct cxl_port *port,
|
2022-02-01 10:10:04 +08:00
|
|
|
struct device *dport, int port_id,
|
|
|
|
|
resource_size_t component_reg_phys);
|
2022-02-04 23:08:40 +08:00
|
|
|
|
2021-06-10 00:43:29 +08:00
|
|
|
struct cxl_decoder *to_cxl_decoder(struct device *dev);
|
2022-07-13 09:38:26 +08:00
|
|
|
struct cxl_root_decoder *to_cxl_root_decoder(struct device *dev);
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2022-05-22 07:24:14 +08:00
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struct cxl_endpoint_decoder *to_cxl_endpoint_decoder(struct device *dev);
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2021-06-16 07:18:17 +08:00
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bool is_root_decoder(struct device *dev);
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2022-03-05 05:36:45 +08:00
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bool is_endpoint_decoder(struct device *dev);
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2022-07-13 09:38:26 +08:00
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struct cxl_root_decoder *cxl_root_decoder_alloc(struct cxl_port *port,
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unsigned int nr_targets);
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2022-05-19 08:52:23 +08:00
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struct cxl_switch_decoder *cxl_switch_decoder_alloc(struct cxl_port *port,
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unsigned int nr_targets);
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2021-09-22 03:22:16 +08:00
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int cxl_decoder_add(struct cxl_decoder *cxld, int *target_map);
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2022-05-22 07:24:14 +08:00
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struct cxl_endpoint_decoder *cxl_endpoint_decoder_alloc(struct cxl_port *port);
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2022-02-02 04:24:30 +08:00
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int cxl_decoder_add_locked(struct cxl_decoder *cxld, int *target_map);
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2021-09-22 03:22:16 +08:00
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int cxl_decoder_autoremove(struct device *host, struct cxl_decoder *cxld);
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2022-02-04 23:18:31 +08:00
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int cxl_endpoint_autoremove(struct cxl_memdev *cxlmd, struct cxl_port *endpoint);
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2022-02-02 04:24:30 +08:00
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struct cxl_hdm;
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2022-02-02 05:23:14 +08:00
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struct cxl_hdm *devm_cxl_setup_hdm(struct cxl_port *port);
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int devm_cxl_enumerate_decoders(struct cxl_hdm *cxlhdm);
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int devm_cxl_add_passthrough_decoder(struct cxl_port *port);
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2021-06-10 00:43:29 +08:00
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2021-02-17 12:09:52 +08:00
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extern struct bus_type cxl_bus_type;
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2021-06-16 07:18:11 +08:00
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struct cxl_driver {
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const char *name;
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int (*probe)(struct device *dev);
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void (*remove)(struct device *dev);
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struct device_driver drv;
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int id;
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};
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static inline struct cxl_driver *to_cxl_drv(struct device_driver *drv)
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{
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return container_of(drv, struct cxl_driver, drv);
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}
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int __cxl_driver_register(struct cxl_driver *cxl_drv, struct module *owner,
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const char *modname);
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#define cxl_driver_register(x) __cxl_driver_register(x, THIS_MODULE, KBUILD_MODNAME)
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void cxl_driver_unregister(struct cxl_driver *cxl_drv);
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|
2022-01-24 08:29:15 +08:00
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#define module_cxl_driver(__cxl_driver) \
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module_driver(__cxl_driver, cxl_driver_register, cxl_driver_unregister)
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|
2021-06-16 07:36:31 +08:00
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#define CXL_DEVICE_NVDIMM_BRIDGE 1
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#define CXL_DEVICE_NVDIMM 2
|
2022-02-02 05:07:51 +08:00
|
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#define CXL_DEVICE_PORT 3
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#define CXL_DEVICE_ROOT 4
|
2022-02-04 23:18:31 +08:00
|
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#define CXL_DEVICE_MEMORY_EXPANDER 5
|
2021-06-16 07:18:17 +08:00
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|
|
2021-06-16 07:18:11 +08:00
|
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|
#define MODULE_ALIAS_CXL(type) MODULE_ALIAS("cxl:t" __stringify(type) "*")
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|
#define CXL_MODALIAS_FMT "cxl:t%d"
|
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|
|
|
|
2021-06-16 07:18:17 +08:00
|
|
|
struct cxl_nvdimm_bridge *to_cxl_nvdimm_bridge(struct device *dev);
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|
|
struct cxl_nvdimm_bridge *devm_cxl_add_nvdimm_bridge(struct device *host,
|
|
|
|
|
struct cxl_port *port);
|
2021-06-16 07:36:31 +08:00
|
|
|
struct cxl_nvdimm *to_cxl_nvdimm(struct device *dev);
|
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|
|
|
bool is_cxl_nvdimm(struct device *dev);
|
2021-11-12 02:19:05 +08:00
|
|
|
bool is_cxl_nvdimm_bridge(struct device *dev);
|
2021-06-16 07:36:31 +08:00
|
|
|
int devm_cxl_add_nvdimm(struct device *host, struct cxl_memdev *cxlmd);
|
2021-09-09 13:13:21 +08:00
|
|
|
struct cxl_nvdimm_bridge *cxl_find_nvdimm_bridge(struct cxl_nvdimm *cxl_nvd);
|
2021-09-15 03:14:22 +08:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Unit test builds overrides this to __weak, find the 'strong' version
|
|
|
|
|
* of these symbols in tools/testing/cxl/.
|
|
|
|
|
*/
|
|
|
|
|
#ifndef __mock
|
|
|
|
|
#define __mock static
|
|
|
|
|
#endif
|
2022-02-01 03:50:09 +08:00
|
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|
2021-02-17 12:09:51 +08:00
|
|
|
#endif /* __CXL_H__ */
|
