2022-02-28 10:09:06 +08:00
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2021 NXP
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*
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* Peng Fan <peng.fan@nxp.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/errno.h>
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#include <linux/export.h>
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#include <linux/io.h>
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2022-08-30 11:31:32 +08:00
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#include <linux/iopoll.h>
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2022-02-28 10:09:06 +08:00
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#include <linux/slab.h>
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#include "clk.h"
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2022-08-30 11:31:32 +08:00
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#define TIMEOUT_US 500U
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2022-02-28 10:09:06 +08:00
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#define CCM_DIV_SHIFT 0
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#define CCM_DIV_WIDTH 8
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#define CCM_MUX_SHIFT 8
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#define CCM_MUX_MASK 3
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#define CCM_OFF_SHIFT 24
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2022-08-30 11:31:32 +08:00
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#define CCM_BUSY_SHIFT 28
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2022-02-28 10:09:06 +08:00
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2022-08-30 11:31:32 +08:00
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#define STAT_OFFSET 0x4
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2022-02-28 10:09:06 +08:00
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#define AUTHEN_OFFSET 0x30
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#define TZ_NS_SHIFT 9
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#define TZ_NS_MASK BIT(9)
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2022-08-30 11:31:33 +08:00
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#define WHITE_LIST_SHIFT 16
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2022-08-30 11:31:32 +08:00
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static int imx93_clk_composite_wait_ready(struct clk_hw *hw, void __iomem *reg)
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{
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int ret;
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u32 val;
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ret = readl_poll_timeout_atomic(reg + STAT_OFFSET, val, !(val & BIT(CCM_BUSY_SHIFT)),
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0, TIMEOUT_US);
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if (ret)
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pr_err("Slice[%s] busy timeout\n", clk_hw_get_name(hw));
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return ret;
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}
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static void imx93_clk_composite_gate_endisable(struct clk_hw *hw, int enable)
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{
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struct clk_gate *gate = to_clk_gate(hw);
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unsigned long flags;
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u32 reg;
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if (gate->lock)
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spin_lock_irqsave(gate->lock, flags);
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reg = readl(gate->reg);
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if (enable)
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reg &= ~BIT(gate->bit_idx);
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else
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reg |= BIT(gate->bit_idx);
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writel(reg, gate->reg);
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imx93_clk_composite_wait_ready(hw, gate->reg);
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if (gate->lock)
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spin_unlock_irqrestore(gate->lock, flags);
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}
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static int imx93_clk_composite_gate_enable(struct clk_hw *hw)
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{
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imx93_clk_composite_gate_endisable(hw, 1);
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return 0;
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}
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static void imx93_clk_composite_gate_disable(struct clk_hw *hw)
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{
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imx93_clk_composite_gate_endisable(hw, 0);
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}
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static const struct clk_ops imx93_clk_composite_gate_ops = {
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.enable = imx93_clk_composite_gate_enable,
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.disable = imx93_clk_composite_gate_disable,
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.is_enabled = clk_gate_is_enabled,
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};
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static unsigned long
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imx93_clk_composite_divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
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{
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return clk_divider_ops.recalc_rate(hw, parent_rate);
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}
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static long
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imx93_clk_composite_divider_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate)
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{
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return clk_divider_ops.round_rate(hw, rate, prate);
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}
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static int
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imx93_clk_composite_divider_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
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{
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return clk_divider_ops.determine_rate(hw, req);
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}
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static int imx93_clk_composite_divider_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_divider *divider = to_clk_divider(hw);
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int value;
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unsigned long flags = 0;
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u32 val;
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int ret;
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value = divider_get_val(rate, parent_rate, divider->table, divider->width, divider->flags);
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if (value < 0)
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return value;
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if (divider->lock)
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spin_lock_irqsave(divider->lock, flags);
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val = readl(divider->reg);
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val &= ~(clk_div_mask(divider->width) << divider->shift);
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val |= (u32)value << divider->shift;
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writel(val, divider->reg);
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ret = imx93_clk_composite_wait_ready(hw, divider->reg);
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if (divider->lock)
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spin_unlock_irqrestore(divider->lock, flags);
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return ret;
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}
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static const struct clk_ops imx93_clk_composite_divider_ops = {
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.recalc_rate = imx93_clk_composite_divider_recalc_rate,
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.round_rate = imx93_clk_composite_divider_round_rate,
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.determine_rate = imx93_clk_composite_divider_determine_rate,
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.set_rate = imx93_clk_composite_divider_set_rate,
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};
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static u8 imx93_clk_composite_mux_get_parent(struct clk_hw *hw)
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{
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return clk_mux_ops.get_parent(hw);
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}
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static int imx93_clk_composite_mux_set_parent(struct clk_hw *hw, u8 index)
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{
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struct clk_mux *mux = to_clk_mux(hw);
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u32 val = clk_mux_index_to_val(mux->table, mux->flags, index);
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unsigned long flags = 0;
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u32 reg;
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int ret;
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if (mux->lock)
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spin_lock_irqsave(mux->lock, flags);
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reg = readl(mux->reg);
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reg &= ~(mux->mask << mux->shift);
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val = val << mux->shift;
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reg |= val;
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writel(reg, mux->reg);
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ret = imx93_clk_composite_wait_ready(hw, mux->reg);
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if (mux->lock)
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spin_unlock_irqrestore(mux->lock, flags);
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return ret;
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}
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static int
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imx93_clk_composite_mux_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
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{
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return clk_mux_ops.determine_rate(hw, req);
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}
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static const struct clk_ops imx93_clk_composite_mux_ops = {
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.get_parent = imx93_clk_composite_mux_get_parent,
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.set_parent = imx93_clk_composite_mux_set_parent,
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.determine_rate = imx93_clk_composite_mux_determine_rate,
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};
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2022-02-28 10:09:06 +08:00
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struct clk_hw *imx93_clk_composite_flags(const char *name, const char * const *parent_names,
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2022-08-30 11:31:33 +08:00
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int num_parents, void __iomem *reg, u32 domain_id,
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2022-02-28 10:09:06 +08:00
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unsigned long flags)
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{
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struct clk_hw *hw = ERR_PTR(-ENOMEM), *mux_hw;
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struct clk_hw *div_hw, *gate_hw;
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struct clk_divider *div = NULL;
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struct clk_gate *gate = NULL;
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struct clk_mux *mux = NULL;
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bool clk_ro = false;
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2022-08-30 11:31:33 +08:00
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u32 authen;
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2022-02-28 10:09:06 +08:00
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mux = kzalloc(sizeof(*mux), GFP_KERNEL);
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if (!mux)
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goto fail;
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mux_hw = &mux->hw;
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mux->reg = reg;
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mux->shift = CCM_MUX_SHIFT;
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mux->mask = CCM_MUX_MASK;
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mux->lock = &imx_ccm_lock;
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div = kzalloc(sizeof(*div), GFP_KERNEL);
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if (!div)
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goto fail;
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div_hw = &div->hw;
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div->reg = reg;
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div->shift = CCM_DIV_SHIFT;
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div->width = CCM_DIV_WIDTH;
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div->lock = &imx_ccm_lock;
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div->flags = CLK_DIVIDER_ROUND_CLOSEST;
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2022-08-30 11:31:33 +08:00
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authen = readl(reg + AUTHEN_OFFSET);
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if (!(authen & TZ_NS_MASK) || !(authen & BIT(WHITE_LIST_SHIFT + domain_id)))
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2022-02-28 10:09:06 +08:00
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clk_ro = true;
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if (clk_ro) {
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hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
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mux_hw, &clk_mux_ro_ops, div_hw,
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&clk_divider_ro_ops, NULL, NULL, flags);
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} else {
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gate = kzalloc(sizeof(*gate), GFP_KERNEL);
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if (!gate)
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goto fail;
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gate_hw = &gate->hw;
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gate->reg = reg;
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gate->bit_idx = CCM_OFF_SHIFT;
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gate->lock = &imx_ccm_lock;
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gate->flags = CLK_GATE_SET_TO_DISABLE;
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hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
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2022-08-30 11:31:32 +08:00
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mux_hw, &imx93_clk_composite_mux_ops, div_hw,
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&imx93_clk_composite_divider_ops, gate_hw,
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&imx93_clk_composite_gate_ops,
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flags | CLK_SET_RATE_NO_REPARENT);
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2022-02-28 10:09:06 +08:00
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}
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if (IS_ERR(hw))
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goto fail;
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return hw;
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fail:
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kfree(gate);
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kfree(div);
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kfree(mux);
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return ERR_CAST(hw);
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}
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EXPORT_SYMBOL_GPL(imx93_clk_composite_flags);
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