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linux/arch/arm64/tools/sysreg

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arm64: Add sysreg header generation scripting The arm64 kernel requires some metadata for each system register it may need to access. Currently we have: * A SYS_<regname> definition which sorresponds to a sys_reg() macro. This is used both to look up a sysreg by encoding (e.g. in KVM), and also to generate code to access a sysreg where the assembler is unaware of the specific sysreg encoding. Where assemblers support the S3_<op1>_C<crn>_C<crm>_<op2> syntax for system registers, we could use this rather than manually assembling the instructions. However, we don't have consistent definitions for these and we currently still need to handle toolchains that lack this feature. * A set of <regname>_<fieldname>_SHIFT and <regname>_<fieldname>_MASK definitions, which can be used to extract fields from the register, or to construct a register from a set of fields. These do not follow the convention used by <linux/bitfield.h>, and the masks are not shifted into place, preventing their use in FIELD_PREP() and FIELD_GET(). We require the SHIFT definitions for inline assembly (and WIDTH definitions would be helpful for UBFX/SBFX), so we cannot only define a shifted MASK. Defining a SHIFT, WIDTH, shifted MASK and unshifted MASK is tedious and error-prone and life is much easier when they can be relied up to exist when writing code. * A set of <regname>_<fieldname>_<valname> definitions for each enumerated value a field may hold. These are used when identifying the presence of features. Atop of this, other code has to build up metadata at runtime (e.g. the sets of RES0/RES1 bits in a register). This patch adds scripting so that we can have an easier-to-manage canonical representation of this metadata, from which we can generate all the definitions necessary for various use-cases, e.g. | #define REG_ID_AA64ISAR0_EL1 S3_0_C0_C6_0 | #define SYS_ID_AA64ISAR0_EL1 sys_reg(3, 0, 0, 6, 0) | #define SYS_ID_AA64ISAR0_EL1_Op0 3 | #define SYS_ID_AA64ISAR0_EL1_Op1 0 | #define SYS_ID_AA64ISAR0_EL1_CRn 0 | #define SYS_ID_AA64ISAR0_EL1_CRm 6 | #define SYS_ID_AA64ISAR0_EL1_Op2 0 | #define ID_AA64ISAR0_EL1_RNDR GENMASK(63, 60) | #define ID_AA64ISAR0_EL1_RNDR_MASK GENMASK(63, 60) | #define ID_AA64ISAR0_EL1_RNDR_SHIFT 60 | #define ID_AA64ISAR0_EL1_RNDR_WIDTH 4 | #define ID_AA64ISAR0_EL1_RNDR_NI UL(0b0000) | #define ID_AA64ISAR0_EL1_RNDR_IMP UL(0b0001) The script requires that all bits in the register be specified and that there be no overlapping fields. This helps the script spot errors in the input but means that the few registers which change layout at runtime depending on things like virtualisation settings will need some manual handling. No actual register conversions are done here but a header for the register data with some documention of the format is provided. For cases where multiple registers share a layout (eg, when identical controls are provided at multiple ELs) the register fields can be defined once and referenced from the actual registers, currently we do not generate actual defines for the individual registers. At the moment this is only intended to express metadata from the architecture, and does not handle policy imposed by the kernel, such as values exposed to userspace or VMs. In future this could be extended to express such information. This script was mostly written by Mark Rutland but has been extended by Mark Brown to improve validation of input and better integrate with the kernel. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Co-Developed-by: Mark Brown <broonie@kernel.org> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220503170233.507788-9-broonie@kernel.org Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2022-05-04 01:02:29 +08:00
# SPDX-License-Identifier: GPL-2.0-only
#
# System register metadata
# Each System register is described by a Sysreg block:
# Sysreg <name> <op0> <op1> <crn> <crm> <op2>
# <field>
# ...
# EndSysreg
# Within a Sysreg block, each field can be described as one of:
# Res0 <msb>[:<lsb>]
# Res1 <msb>[:<lsb>]
# Field <msb>[:<lsb>] <name>
# Enum <msb>[:<lsb>] <name>
# <enumval> <enumname>
# ...
# EndEnum
# Alternatively if multiple registers share the same layout then
# a SysregFields block can be used to describe the shared layout
# SysregFields <fieldsname>
# <field>
# ...
# EndSysregFields
# and referenced from within the Sysreg:
# Sysreg <name> <op0> <op1> <crn> <crm> <op2>
# Fields <fieldsname>
# EndSysreg
# For ID registers we adopt a few conventions for translating the
# language in the ARM into defines:
#
# NI - Not implemented
# IMP - Implemented
#
# In general it is recommended that new enumeration items be named for the
# feature that introduces them (eg, FEAT_LS64_ACCDATA introduces enumeration
# item ACCDATA) though it may be more taseful to do something else.
arm64/sysreg: Convert ID_AA64PFR0_EL1 to automatic generation Automatically generate the constants for ID_AA64PFR0_EL1 as per DDI0487I.a, no functional changes. The generic defines for the ELx fields are left in place as they remain useful. Signed-off-by: Mark Brown <broonie@kernel.org> Reviewed-by: Kristina Martsenko <kristina.martsenko@arm.com> Link: https://lore.kernel.org/r/20220905225425.1871461-25-broonie@kernel.org Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2022-09-06 06:54:21 +08:00
Sysreg ID_AA64PFR0_EL1 3 0 0 4 0
Enum 63:60 CSV3
0b0000 NI
0b0001 IMP
EndEnum
Enum 59:56 CSV2
0b0000 NI
0b0001 IMP
0b0010 CSV2_2
0b0011 CSV2_3
EndEnum
Enum 55:52 RME
0b0000 NI
0b0001 IMP
EndEnum
Enum 51:48 DIT
0b0000 NI
0b0001 IMP
EndEnum
Enum 47:44 AMU
0b0000 NI
0b0001 IMP
0b0010 V1P1
EndEnum
Enum 43:40 MPAM
0b0000 0
0b0001 1
EndEnum
Enum 39:36 SEL2
0b0000 NI
0b0001 IMP
EndEnum
Enum 35:32 SVE
0b0000 NI
0b0001 IMP
EndEnum
Enum 31:28 RAS
0b0000 NI
0b0001 IMP
0b0010 V1P1
EndEnum
Enum 27:24 GIC
0b0000 NI
0b0001 IMP
0b0010 V4P1
EndEnum
Enum 23:20 AdvSIMD
0b0000 IMP
0b0001 FP16
0b1111 NI
EndEnum
Enum 19:16 FP
0b0000 IMP
0b0001 FP16
0b1111 NI
EndEnum
Enum 15:12 EL3
0b0000 NI
0b0001 IMP
0b0010 AARCH32
EndEnum
Enum 11:8 EL2
0b0000 NI
0b0001 IMP
0b0010 AARCH32
EndEnum
Enum 7:4 EL1
0b0001 IMP
0b0010 AARCH32
EndEnum
Enum 3:0 EL0
0b0001 IMP
0b0010 AARCH32
EndEnum
EndSysreg
arm64/sysreg: Convert ID_AA64PFR1_EL1 to automatic generation Convert ID_AA64PFR1_EL1 to be automatically generated as per DDI04187H.a, no functional changes. Signed-off-by: Mark Brown <broonie@kernel.org> Reviewed-by: Kristina Martsenko <kristina.martsenko@arm.com> Link: https://lore.kernel.org/r/20220905225425.1871461-26-broonie@kernel.org Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2022-09-06 06:54:22 +08:00
Sysreg ID_AA64PFR1_EL1 3 0 0 4 1
Res0 63:40
Enum 39:36 NMI
0b0000 NI
0b0001 IMP
EndEnum
Enum 35:32 CSV2_frac
0b0000 NI
0b0001 CSV2_1p1
0b0010 CSV2_1p2
EndEnum
Enum 31:28 RNDR_trap
0b0000 NI
0b0001 IMP
EndEnum
Enum 27:24 SME
0b0000 NI
0b0001 IMP
EndEnum
Res0 23:20
Enum 19:16 MPAM_frac
0b0000 MINOR_0
0b0001 MINOR_1
EndEnum
Enum 15:12 RAS_frac
0b0000 NI
0b0001 RASv1p1
EndEnum
Enum 11:8 MTE
0b0000 NI
0b0001 IMP
0b0010 MTE2
0b0011 MTE3
EndEnum
Enum 7:4 SSBS
0b0000 NI
0b0001 IMP
0b0010 SSBS2
EndEnum
Enum 3:0 BT
0b0000 NI
0b0001 IMP
EndEnum
EndSysreg
arm64/sysreg: Convert ID_AA64ZFR0_EL1 to automatic generation Convert ID_AA64ZFR0_EL1 to automatic register generation as per DDI0487H.a, no functional changes. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-29-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05 01:03:02 +08:00
Sysreg ID_AA64ZFR0_EL1 3 0 0 4 4
Res0 63:60
Enum 59:56 F64MM
0b0000 NI
0b0001 IMP
EndEnum
Enum 55:52 F32MM
0b0000 NI
0b0001 IMP
EndEnum
Res0 51:48
Enum 47:44 I8MM
0b0000 NI
0b0001 IMP
EndEnum
Enum 43:40 SM4
0b0000 NI
0b0001 IMP
EndEnum
Res0 39:36
Enum 35:32 SHA3
0b0000 NI
0b0001 IMP
EndEnum
Res0 31:24
Enum 23:20 BF16
0b0000 NI
0b0001 IMP
0b0010 EBF16
EndEnum
Enum 19:16 BitPerm
0b0000 NI
0b0001 IMP
EndEnum
Res0 15:8
Enum 7:4 AES
0b0000 NI
0b0001 IMP
0b0010 PMULL128
EndEnum
Enum 3:0 SVEver
0b0000 IMP
0b0001 SVE2
EndEnum
EndSysreg
arm64/sysreg: Convert ID_AA64SMFR0_EL1 to automatic generation Convert ID_AA64SMFR0_EL1 to automatic register generation as per DDI0487H.a, no functional change. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-28-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05 01:03:01 +08:00
Sysreg ID_AA64SMFR0_EL1 3 0 0 4 5
Enum 63 FA64
0b0 NI
0b1 IMP
EndEnum
Res0 62:60
arm64/sysreg: Describe ID_AA64SMFR0_EL1.SMEVer as an enumeration As with the corresponding SVE field ID_AA64ZFR0_EL1.SVEVer and other ID register fields the SMEVer field should be identified as an enumeration but it is currently described as a plain field (most likely due to there presently being only one possible value). Update it to be an enumeration as one would expect. No functional change. Signed-off-by: Mark Brown <broonie@kernel.org> Reviewed-by: Kristina Martsenko <kristina.martsenko@arm.com> Link: https://lore.kernel.org/r/20220905225425.1871461-3-broonie@kernel.org Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2022-09-06 06:53:59 +08:00
Enum 59:56 SMEver
0b0000 IMP
EndEnum
arm64/sysreg: Convert ID_AA64SMFR0_EL1 to automatic generation Convert ID_AA64SMFR0_EL1 to automatic register generation as per DDI0487H.a, no functional change. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-28-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05 01:03:01 +08:00
Enum 55:52 I16I64
0b0000 NI
0b1111 IMP
EndEnum
Res0 51:49
Enum 48 F64F64
0b0 NI
0b1 IMP
EndEnum
Res0 47:40
Enum 39:36 I8I32
0b0000 NI
0b1111 IMP
EndEnum
Enum 35 F16F32
0b0 NI
0b1 IMP
EndEnum
Enum 34 B16F32
0b0 NI
0b1 IMP
EndEnum
Res0 33
Enum 32 F32F32
0b0 NI
0b1 IMP
EndEnum
Res0 31:0
EndSysreg
arm64/sysreg: Generate definitions for ID_AA64ISAR0_EL1 Remove the manual definitions for ID_AA64ISAR0_EL1 in favour of automatic generation. There should be no functional change. The only notable change is that 27:24 TME is defined rather than RES0 reflecting DDI0487H.a. Signed-off-by: Mark Brown <broonie@kernel.org> Acked-by: Mark Rutland <mark.rutland@arm.com> Link: https://lore.kernel.org/r/20220503170233.507788-11-broonie@kernel.org Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2022-05-04 01:02:31 +08:00
Sysreg ID_AA64ISAR0_EL1 3 0 0 6 0
Enum 63:60 RNDR
0b0000 NI
0b0001 IMP
EndEnum
Enum 59:56 TLB
0b0000 NI
0b0001 OS
0b0010 RANGE
EndEnum
Enum 55:52 TS
0b0000 NI
0b0001 FLAGM
0b0010 FLAGM2
EndEnum
Enum 51:48 FHM
0b0000 NI
0b0001 IMP
EndEnum
Enum 47:44 DP
0b0000 NI
0b0001 IMP
EndEnum
Enum 43:40 SM4
0b0000 NI
0b0001 IMP
EndEnum
Enum 39:36 SM3
0b0000 NI
0b0001 IMP
EndEnum
Enum 35:32 SHA3
0b0000 NI
0b0001 IMP
EndEnum
Enum 31:28 RDM
0b0000 NI
0b0001 IMP
EndEnum
Enum 27:24 TME
0b0000 NI
0b0001 IMP
EndEnum
Enum 23:20 ATOMIC
0b0000 NI
0b0010 IMP
EndEnum
Enum 19:16 CRC32
0b0000 NI
0b0001 IMP
EndEnum
Enum 15:12 SHA2
0b0000 NI
0b0001 SHA256
0b0010 SHA512
EndEnum
Enum 11:8 SHA1
0b0000 NI
0b0001 IMP
EndEnum
Enum 7:4 AES
0b0000 NI
0b0001 AES
0b0010 PMULL
EndEnum
Res0 3:0
EndSysreg
arm64/sysreg: Generate definitions for TTBRn_EL1 Automatically generate definitions for accessing the TTBRn_EL1 registers, no functional change. Signed-off-by: Mark Brown <broonie@kernel.org> Acked-by: Mark Rutland <mark.rutland@arm.com> Link: https://lore.kernel.org/r/20220503170233.507788-12-broonie@kernel.org Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2022-05-04 01:02:32 +08:00
arm64/sysreg: Convert ID_AA64ISAR1_EL1 to automatic generation Automatically generate defines for ID_AA64ISAR1_EL1, using the definitions in DDI0487H.a. No functional changes. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-21-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05 01:02:54 +08:00
Sysreg ID_AA64ISAR1_EL1 3 0 0 6 1
Enum 63:60 LS64
0b0000 NI
0b0001 LS64
0b0010 LS64_V
0b0011 LS64_ACCDATA
EndEnum
Enum 59:56 XS
0b0000 NI
0b0001 IMP
EndEnum
Enum 55:52 I8MM
0b0000 NI
0b0001 IMP
EndEnum
Enum 51:48 DGH
0b0000 NI
0b0001 IMP
EndEnum
Enum 47:44 BF16
0b0000 NI
0b0001 IMP
0b0010 EBF16
EndEnum
Enum 43:40 SPECRES
0b0000 NI
0b0001 IMP
EndEnum
Enum 39:36 SB
0b0000 NI
0b0001 IMP
EndEnum
Enum 35:32 FRINTTS
0b0000 NI
0b0001 IMP
EndEnum
Enum 31:28 GPI
0b0000 NI
0b0001 IMP
EndEnum
Enum 27:24 GPA
0b0000 NI
0b0001 IMP
EndEnum
Enum 23:20 LRCPC
0b0000 NI
0b0001 IMP
0b0010 LRCPC2
EndEnum
Enum 19:16 FCMA
0b0000 NI
0b0001 IMP
EndEnum
Enum 15:12 JSCVT
0b0000 NI
0b0001 IMP
EndEnum
Enum 11:8 API
0b0000 NI
0b0001 PAuth
0b0010 EPAC
0b0011 PAuth2
0b0100 FPAC
0b0101 FPACCOMBINE
EndEnum
Enum 7:4 APA
0b0000 NI
0b0001 PAuth
0b0010 EPAC
0b0011 PAuth2
0b0100 FPAC
0b0101 FPACCOMBINE
EndEnum
Enum 3:0 DPB
0b0000 NI
0b0001 IMP
0b0010 DPB2
EndEnum
EndSysreg
arm64/sysreg: Convert ID_AA64ISAR2_EL1 to automatic generation Automatically generate defines for ID_AA64ISAR2_EL1, using the definitions in DDI0487H.a. No functional changes. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-22-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05 01:02:55 +08:00
Sysreg ID_AA64ISAR2_EL1 3 0 0 6 2
Res0 63:28
Enum 27:24 PAC_frac
0b0000 NI
0b0001 IMP
EndEnum
Enum 23:20 BC
0b0000 NI
0b0001 IMP
EndEnum
Enum 19:16 MOPS
0b0000 NI
0b0001 IMP
EndEnum
Enum 15:12 APA3
0b0000 NI
0b0001 PAuth
0b0010 EPAC
0b0011 PAuth2
0b0100 FPAC
0b0101 FPACCOMBINE
EndEnum
Enum 11:8 GPA3
0b0000 NI
arm64/sysreg: Convert ID_AA64ISAR1_EL1 to automatic generation Automatically generate defines for ID_AA64ISAR1_EL1, using the definitions in DDI0487H.a. No functional changes. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-21-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05 01:02:54 +08:00
0b0001 IMP
EndEnum
arm64/sysreg: Convert ID_AA64ISAR2_EL1 to automatic generation Automatically generate defines for ID_AA64ISAR2_EL1, using the definitions in DDI0487H.a. No functional changes. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-22-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05 01:02:55 +08:00
Enum 7:4 RPRES
0b0000 NI
0b0001 IMP
EndEnum
Enum 3:0 WFxT
0b0000 NI
0b0010 IMP
EndEnum
arm64/sysreg: Convert ID_AA64ISAR1_EL1 to automatic generation Automatically generate defines for ID_AA64ISAR1_EL1, using the definitions in DDI0487H.a. No functional changes. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-21-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05 01:02:54 +08:00
EndSysreg
arm64/sysreg: Convert ID_AA64MMFR0_EL1 to automatic generation Automatically generate most of the defines for ID_AA64MMFR0_EL1 mostly as per DDI0487H.a. Due to the large amount of MixedCase in this register which isn't really consistent with either the kernel style or the majority of the architecture the use of upper case is preserved. We also leave in place a number of min/max/default value definitions which don't flow from the architecture definitions. No functional changes. Signed-off-by: Mark Brown <broonie@kernel.org> Reviewed-by: Kristina Martsenko <kristina.martsenko@arm.com> Link: https://lore.kernel.org/r/20220905225425.1871461-22-broonie@kernel.org Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2022-09-06 06:54:18 +08:00
Sysreg ID_AA64MMFR0_EL1 3 0 0 7 0
Enum 63:60 ECV
0b0000 NI
0b0001 IMP
0b0010 CNTPOFF
EndEnum
Enum 59:56 FGT
0b0000 NI
0b0001 IMP
EndEnum
Res0 55:48
Enum 47:44 EXS
0b0000 NI
0b0001 IMP
EndEnum
Enum 43:40 TGRAN4_2
0b0000 TGRAN4
0b0001 NI
0b0010 IMP
0b0011 52_BIT
EndEnum
Enum 39:36 TGRAN64_2
0b0000 TGRAN64
0b0001 NI
0b0010 IMP
EndEnum
Enum 35:32 TGRAN16_2
0b0000 TGRAN16
0b0001 NI
0b0010 IMP
0b0011 52_BIT
EndEnum
Enum 31:28 TGRAN4
0b0000 IMP
0b0001 52_BIT
0b1111 NI
EndEnum
Enum 27:24 TGRAN64
0b0000 IMP
0b1111 NI
EndEnum
Enum 23:20 TGRAN16
0b0000 NI
0b0001 IMP
0b0010 52_BIT
EndEnum
Enum 19:16 BIGENDEL0
0b0000 NI
0b0001 IMP
EndEnum
Enum 15:12 SNSMEM
0b0000 NI
0b0001 IMP
EndEnum
Enum 11:8 BIGEND
0b0000 NI
0b0001 IMP
EndEnum
Enum 7:4 ASIDBITS
0b0000 8
0b0010 16
EndEnum
Enum 3:0 PARANGE
0b0000 32
0b0001 36
0b0010 40
0b0011 42
0b0100 44
0b0101 48
0b0110 52
EndEnum
EndSysreg
arm64/sysreg: Convert ID_AA64MMFR1_EL1 to automatic generation Convert ID_AA64MMFR1_EL1 to be automatically generated as per DDI0487H.a plus ECBHB which was RES0 in DDI0487H.a but has been subsequently defined and is already present in mainline. No functional changes. Signed-off-by: Kristina Martsenko <kristina.martsenko@arm.com> Signed-off-by: Mark Brown <broonie@kernel.org> Reviewed-by: Kristina Martsenko <kristina.martsenko@arm.com> Link: https://lore.kernel.org/r/20220905225425.1871461-23-broonie@kernel.org Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2022-09-06 06:54:19 +08:00
Sysreg ID_AA64MMFR1_EL1 3 0 0 7 1
Enum 63:60 ECBHB
0b0000 NI
0b0001 IMP
EndEnum
Enum 59:56 CMOW
0b0000 NI
0b0001 IMP
EndEnum
Enum 55:52 TIDCP1
0b0000 NI
0b0001 IMP
EndEnum
Enum 51:48 nTLBPA
0b0000 NI
0b0001 IMP
EndEnum
Enum 47:44 AFP
0b0000 NI
0b0001 IMP
EndEnum
Enum 43:40 HCX
0b0000 NI
0b0001 IMP
EndEnum
Enum 39:36 ETS
0b0000 NI
0b0001 IMP
EndEnum
Enum 35:32 TWED
0b0000 NI
0b0001 IMP
EndEnum
Enum 31:28 XNX
0b0000 NI
0b0001 IMP
EndEnum
Enum 27:24 SpecSEI
0b0000 NI
0b0001 IMP
EndEnum
Enum 23:20 PAN
0b0000 NI
0b0001 IMP
0b0010 PAN2
0b0011 PAN3
EndEnum
Enum 19:16 LO
0b0000 NI
0b0001 IMP
EndEnum
Enum 15:12 HPDS
0b0000 NI
0b0001 IMP
0b0010 HPDS2
EndEnum
Enum 11:8 VH
0b0000 NI
0b0001 IMP
EndEnum
Enum 7:4 VMIDBits
0b0000 8
0b0010 16
EndEnum
Enum 3:0 HAFDBS
0b0000 NI
0b0001 AF
0b0010 DBM
EndEnum
EndSysreg
arm64/sysreg: Convert ID_AA64MMFR2_EL1 to automatic generation Convert ID_AA64MMFR2_EL1 defines to automatic generation as per DDI0487H.a, no functional changes. Signed-off-by: Mark Brown <broonie@kernel.org> Reviewed-by: Kristina Martsenko <kristina.martsenko@arm.com> Link: https://lore.kernel.org/r/20220905225425.1871461-24-broonie@kernel.org Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2022-09-06 06:54:20 +08:00
Sysreg ID_AA64MMFR2_EL1 3 0 0 7 2
Enum 63:60 E0PD
0b0000 NI
0b0001 IMP
EndEnum
Enum 59:56 EVT
0b0000 NI
0b0001 IMP
0b0010 TTLBxS
EndEnum
Enum 55:52 BBM
0b0000 0
0b0001 1
0b0010 2
EndEnum
Enum 51:48 TTL
0b0000 NI
0b0001 IMP
EndEnum
Res0 47:44
Enum 43:40 FWB
0b0000 NI
0b0001 IMP
EndEnum
Enum 39:36 IDS
0b0000 0x0
0b0001 0x18
EndEnum
Enum 35:32 AT
0b0000 NI
0b0001 IMP
EndEnum
Enum 31:28 ST
0b0000 39
0b0001 48_47
EndEnum
Enum 27:24 NV
0b0000 NI
0b0001 IMP
0b0010 NV2
EndEnum
Enum 23:20 CCIDX
0b0000 32
0b0001 64
EndEnum
Enum 19:16 VARange
0b0000 48
0b0001 52
EndEnum
Enum 15:12 IESB
0b0000 NI
0b0001 IMP
EndEnum
Enum 11:8 LSM
0b0000 NI
0b0001 IMP
EndEnum
Enum 7:4 UAO
0b0000 NI
0b0001 IMP
EndEnum
Enum 3:0 CnP
0b0000 NI
0b0001 IMP
EndEnum
EndSysreg
arm64/sysreg: Generate definitions for SCTLR_EL1 Automatically generate register definitions for SCTLR_EL1. No functional change. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220503170233.507788-13-broonie@kernel.org [catalin.marinas@arm.com: fix the SCTLR_EL1 encoding] Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2022-05-04 01:02:33 +08:00
Sysreg SCTLR_EL1 3 0 1 0 0
Field 63 TIDCP
Field 62 SPINMASK
Field 61 NMI
Field 60 EnTP2
Res0 59:58
Field 57 EPAN
Field 56 EnALS
Field 55 EnAS0
Field 54 EnASR
Field 53 TME
Field 52 TME0
Field 51 TMT
Field 50 TMT0
Field 49:46 TWEDEL
Field 45 TWEDEn
Field 44 DSSBS
Field 43 ATA
Field 42 ATA0
Enum 41:40 TCF
0b00 NONE
0b01 SYNC
0b10 ASYNC
0b11 ASYMM
EndEnum
Enum 39:38 TCF0
0b00 NONE
0b01 SYNC
0b10 ASYNC
0b11 ASYMM
EndEnum
Field 37 ITFSB
Field 36 BT1
Field 35 BT0
Res0 34
Field 33 MSCEn
Field 32 CMOW
Field 31 EnIA
Field 30 EnIB
Field 29 LSMAOE
Field 28 nTLSMD
Field 27 EnDA
Field 26 UCI
Field 25 EE
Field 24 E0E
Field 23 SPAN
Field 22 EIS
Field 21 IESB
Field 20 TSCXT
Field 19 WXN
Field 18 nTWE
Res0 17
Field 16 nTWI
Field 15 UCT
Field 14 DZE
Field 13 EnDB
Field 12 I
Field 11 EOS
Field 10 EnRCTX
Field 9 UMA
Field 8 SED
Field 7 ITD
Field 6 nAA
Field 5 CP15BEN
Field 4 SA0
Field 3 SA
Field 2 C
Field 1 A
Field 0 M
EndSysreg
arm64/sysreg: Generate definitions for CPACR_ELx Convert the CPACR system register definitions to be automatically generated using the definitions in DDI0487H.a. The kernel does have some additional definitions for subfields of SMEN, FPEN and ZEN which are not identified as distinct subfields in the architecture so the definitions are not updated as part of this patch. No functional change. Signed-off-by: Mark Brown <broonie@kernel.org> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Link: https://lore.kernel.org/r/20220520161639.324236-4-broonie@kernel.org Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2022-05-21 00:16:35 +08:00
SysregFields CPACR_ELx
Res0 63:29
Field 28 TTA
Res0 27:26
Field 25:24 SMEN
Res0 23:22
Field 21:20 FPEN
Res0 19:18
Field 17:16 ZEN
Res0 15:0
EndSysregFields
Sysreg CPACR_EL1 3 0 1 0 2
Fields CPACR_ELx
EndSysreg
arm64/sme: Generate SMPRI_EL1 definitions Convert SMPRI_EL1 to be generated. No functional change. Signed-off-by: Mark Brown <broonie@kernel.org> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Link: https://lore.kernel.org/r/20220510161208.631259-11-broonie@kernel.org Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2022-05-11 00:12:06 +08:00
Sysreg SMPRI_EL1 3 0 1 2 4
Res0 63:4
Field 3:0 PRIORITY
EndSysreg
arm64/sve: Generate ZCR definitions Convert the various ZCR instances to automatic generation, no functional changes expected. Signed-off-by: Mark Brown <broonie@kernel.org> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Link: https://lore.kernel.org/r/20220510161208.631259-13-broonie@kernel.org Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2022-05-11 00:12:08 +08:00
SysregFields ZCR_ELx
Res0 63:9
Raz 8:4
Field 3:0 LEN
EndSysregFields
Sysreg ZCR_EL1 3 0 1 2 0
Fields ZCR_ELx
EndSysreg
arm64/sme: Automatically generate defines for SMCR Convert SMCR to use the register definition code, no functional change. Signed-off-by: Mark Brown <broonie@kernel.org> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Link: https://lore.kernel.org/r/20220510161208.631259-8-broonie@kernel.org Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2022-05-11 00:12:03 +08:00
SysregFields SMCR_ELx
Res0 63:32
Field 31 FA64
Res0 30:9
Raz 8:4
Field 3:0 LEN
EndSysregFields
Sysreg SMCR_EL1 3 0 1 2 6
Fields SMCR_ELx
EndSysreg
arm64/sysreg: Generate definitions for FAR_ELx Convert FAR_ELx to automatic register generation as per DDI0487H.a. In the architecture these registers have a single field "named" as "Faulting Virtual Address for synchronous exceptions taken to ELx" occupying the entire register, in order to fit in with the requirement to describe the contents of the register I have created a single field named ADDR. No functional change. Signed-off-by: Mark Brown <broonie@kernel.org> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Link: https://lore.kernel.org/r/20220520161639.324236-7-broonie@kernel.org Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2022-05-21 00:16:38 +08:00
Sysreg FAR_EL1 3 0 6 0 0
Field 63:0 ADDR
EndSysreg
arm64/sysreg: Generate definitions for CONTEXTIDR_ELx Convert the various CONTEXTIDR_ELx register definitions to be automatically generated following the definitions in DDI0487H.a. No functional change. Signed-off-by: Mark Brown <broonie@kernel.org> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Link: https://lore.kernel.org/r/20220520161639.324236-3-broonie@kernel.org Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2022-05-21 00:16:34 +08:00
SysregFields CONTEXTIDR_ELx
Res0 63:32
Field 31:0 PROCID
EndSysregFields
Sysreg CONTEXTIDR_EL1 3 0 13 0 1
Fields CONTEXTIDR_ELx
EndSysreg
arm64/sysreg: Convert TIPDR_EL1 to automatic generation Convert TPIDR_EL1 to automatic generation as per DDI0487H.a, no functional changes. Signed-off-by: Mark Brown <broonie@kernel.org> Reviewed-by: Kristina Martsenko <kristina.martsenko@arm.com> Link: https://lore.kernel.org/r/20220905225425.1871461-27-broonie@kernel.org Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2022-09-06 06:54:23 +08:00
Sysreg TPIDR_EL1 3 0 13 0 4
Field 63:0 ThreadID
EndSysreg
arm64/sysreg: Generate definitions for CLIDR_EL1 Convert CLIDR_EL1 to be automatically generated with definition as per DDI0487H.a. No functional change. Signed-off-by: Mark Brown <broonie@kernel.org> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Link: https://lore.kernel.org/r/20220520161639.324236-2-broonie@kernel.org Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2022-05-21 00:16:33 +08:00
Sysreg CLIDR_EL1 3 1 0 0 1
Res0 63:47
Field 46:33 Ttypen
Field 32:30 ICB
Field 29:27 LoUU
Field 26:24 LoC
Field 23:21 LoUIS
Field 20:18 Ctype7
Field 17:15 Ctype6
Field 14:12 Ctype5
Field 11:9 Ctype4
Field 8:6 Ctype3
Field 5:3 Ctype2
Field 2:0 Ctype1
EndSysreg
arm64/sysreg: Convert GMID to automatic generation Automatically generate the register definitions for GMID as per DDI0487H.a, no functional change. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-20-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05 01:02:53 +08:00
Sysreg GMID_EL1 3 1 0 0 4
Res0 63:4
Field 3:0 BS
EndSysreg
arm64/sme: Automatically generate SMIDR_EL1 defines Automatically generate the defines for SMIDR_EL1, no functional change. Signed-off-by: Mark Brown <broonie@kernel.org> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Link: https://lore.kernel.org/r/20220510161208.631259-9-broonie@kernel.org Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2022-05-11 00:12:04 +08:00
Sysreg SMIDR_EL1 3 1 0 0 6
Res0 63:32
Field 31:24 IMPLEMENTER
Field 23:16 REVISION
Field 15 SMPS
Res0 14:12
Field 11:0 AFFINITY
EndSysreg
arm64/sysreg: Generate definitions for CSSELR_EL1 Convert CSSELR_EL1 to automatic generation as per DDI0487H.a, no functional change. Signed-off-by: Mark Brown <broonie@kernel.org> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Link: https://lore.kernel.org/r/20220520161639.324236-5-broonie@kernel.org Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2022-05-21 00:16:36 +08:00
Sysreg CSSELR_EL1 3 2 0 0 0
Res0 63:5
Field 4 TnD
Field 3:1 Level
Field 0 InD
EndSysreg
arm64/sysreg: Convert CTR_EL0 to automatic generation Convert CTR_EL0 to automatic register generation as per DDI0487H.a, no functional change. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-18-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05 01:02:51 +08:00
Sysreg CTR_EL0 3 3 0 0 1
Res0 63:38
Field 37:32 TminLine
Res1 31
Res0 30
Field 29 DIC
Field 28 IDC
Field 27:24 CWG
Field 23:20 ERG
Field 19:16 DminLine
Enum 15:14 L1Ip
0b00 VPIPT
# This is named as AIVIVT in the ARM but documented as reserved
0b01 RESERVED
0b10 VIPT
0b11 PIPT
EndEnum
Res0 13:4
Field 3:0 IminLine
EndSysreg
arm64/sysreg: Convert DCZID_EL0 to automatic generation Convert DCZID_EL0 to automatic register generation as per DDI0487H.a, no functional change. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-19-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05 01:02:52 +08:00
Sysreg DCZID_EL0 3 3 0 0 7
Res0 63:5
Field 4 DZP
Field 3:0 BS
EndSysreg
arm64/sme: Generate defintions for SVCR Convert SVCR to automatic generation, no functional change. Signed-off-by: Mark Brown <broonie@kernel.org> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Link: https://lore.kernel.org/r/20220510161208.631259-12-broonie@kernel.org Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2022-05-11 00:12:07 +08:00
Sysreg SVCR 3 3 4 2 2
Res0 63:2
Field 1 ZA
Field 0 SM
EndSysreg
arm64/sve: Generate ZCR definitions Convert the various ZCR instances to automatic generation, no functional changes expected. Signed-off-by: Mark Brown <broonie@kernel.org> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Link: https://lore.kernel.org/r/20220510161208.631259-13-broonie@kernel.org Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2022-05-11 00:12:08 +08:00
Sysreg ZCR_EL2 3 4 1 2 0
Fields ZCR_ELx
EndSysreg
arm64/sysreg: Convert HCRX_EL2 to automatic generation Convert HCRX_EL2 to be automatically generated as per DDI04187H.a, n functional changes. Signed-off-by: Mark Brown <broonie@kernel.org> Reviewed-by: Kristina Martsenko <kristina.martsenko@arm.com> Link: https://lore.kernel.org/r/20220905225425.1871461-21-broonie@kernel.org Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2022-09-06 06:54:17 +08:00
Sysreg HCRX_EL2 3 4 1 2 2
Res0 63:12
Field 11 MSCEn
Field 10 MCE2
Field 9 CMOW
Field 8 VFNMI
Field 7 VINMI
Field 6 TALLINT
Field 5 SMPME
Field 4 FGTnXS
Field 3 FnXS
Field 2 EnASR
Field 1 EnALS
Field 0 EnAS0
EndSysreg
arm64/sme: Automatically generate SMPRIMAP_EL2 definitions No functional change should be seen from converting SMPRIMAP_EL2 to be generated. Signed-off-by: Mark Brown <broonie@kernel.org> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Link: https://lore.kernel.org/r/20220510161208.631259-10-broonie@kernel.org Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2022-05-11 00:12:05 +08:00
Sysreg SMPRIMAP_EL2 3 4 1 2 5
Field 63:60 P15
Field 59:56 P14
Field 55:52 P13
Field 51:48 P12
Field 47:44 P11
Field 43:40 P10
Field 39:36 F9
Field 35:32 P8
Field 31:28 P7
Field 27:24 P6
Field 23:20 P5
Field 19:16 P4
Field 15:12 P3
Field 11:8 P2
Field 7:4 P1
Field 3:0 P0
EndSysreg
arm64/sme: Automatically generate defines for SMCR Convert SMCR to use the register definition code, no functional change. Signed-off-by: Mark Brown <broonie@kernel.org> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Link: https://lore.kernel.org/r/20220510161208.631259-8-broonie@kernel.org Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2022-05-11 00:12:03 +08:00
Sysreg SMCR_EL2 3 4 1 2 6
Fields SMCR_ELx
EndSysreg
arm64/sysreg: Generate definitions for DACR32_EL2 Convert DACR32_EL2 to automatic register generation as per DDI0487H.a, no functional change. Signed-off-by: Mark Brown <broonie@kernel.org> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Link: https://lore.kernel.org/r/20220520161639.324236-6-broonie@kernel.org Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2022-05-21 00:16:37 +08:00
Sysreg DACR32_EL2 3 4 3 0 0
Res0 63:32
Field 31:30 D15
Field 29:28 D14
Field 27:26 D13
Field 25:24 D12
Field 23:22 D11
Field 21:20 D10
Field 19:18 D9
Field 17:16 D8
Field 15:14 D7
Field 13:12 D6
Field 11:10 D5
Field 9:8 D4
Field 7:6 D3
Field 5:4 D2
Field 3:2 D1
Field 1:0 D0
EndSysreg
arm64/sysreg: Generate definitions for FAR_ELx Convert FAR_ELx to automatic register generation as per DDI0487H.a. In the architecture these registers have a single field "named" as "Faulting Virtual Address for synchronous exceptions taken to ELx" occupying the entire register, in order to fit in with the requirement to describe the contents of the register I have created a single field named ADDR. No functional change. Signed-off-by: Mark Brown <broonie@kernel.org> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Link: https://lore.kernel.org/r/20220520161639.324236-7-broonie@kernel.org Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2022-05-21 00:16:38 +08:00
Sysreg FAR_EL2 3 4 6 0 0
Field 63:0 ADDR
EndSysreg
arm64/sysreg: Generate definitions for CONTEXTIDR_ELx Convert the various CONTEXTIDR_ELx register definitions to be automatically generated following the definitions in DDI0487H.a. No functional change. Signed-off-by: Mark Brown <broonie@kernel.org> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Link: https://lore.kernel.org/r/20220520161639.324236-3-broonie@kernel.org Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2022-05-21 00:16:34 +08:00
Sysreg CONTEXTIDR_EL2 3 4 13 0 1
Fields CONTEXTIDR_ELx
EndSysreg
arm64/sysreg: Generate definitions for CPACR_ELx Convert the CPACR system register definitions to be automatically generated using the definitions in DDI0487H.a. The kernel does have some additional definitions for subfields of SMEN, FPEN and ZEN which are not identified as distinct subfields in the architecture so the definitions are not updated as part of this patch. No functional change. Signed-off-by: Mark Brown <broonie@kernel.org> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Link: https://lore.kernel.org/r/20220520161639.324236-4-broonie@kernel.org Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2022-05-21 00:16:35 +08:00
Sysreg CPACR_EL12 3 5 1 0 2
Fields CPACR_ELx
EndSysreg
arm64/sve: Generate ZCR definitions Convert the various ZCR instances to automatic generation, no functional changes expected. Signed-off-by: Mark Brown <broonie@kernel.org> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Link: https://lore.kernel.org/r/20220510161208.631259-13-broonie@kernel.org Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2022-05-11 00:12:08 +08:00
Sysreg ZCR_EL12 3 5 1 2 0
Fields ZCR_ELx
EndSysreg
arm64/sme: Automatically generate defines for SMCR Convert SMCR to use the register definition code, no functional change. Signed-off-by: Mark Brown <broonie@kernel.org> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Link: https://lore.kernel.org/r/20220510161208.631259-8-broonie@kernel.org Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2022-05-11 00:12:03 +08:00
Sysreg SMCR_EL12 3 5 1 2 6
Fields SMCR_ELx
EndSysreg
arm64/sysreg: Generate definitions for FAR_ELx Convert FAR_ELx to automatic register generation as per DDI0487H.a. In the architecture these registers have a single field "named" as "Faulting Virtual Address for synchronous exceptions taken to ELx" occupying the entire register, in order to fit in with the requirement to describe the contents of the register I have created a single field named ADDR. No functional change. Signed-off-by: Mark Brown <broonie@kernel.org> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Link: https://lore.kernel.org/r/20220520161639.324236-7-broonie@kernel.org Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2022-05-21 00:16:38 +08:00
Sysreg FAR_EL12 3 5 6 0 0
Field 63:0 ADDR
EndSysreg
arm64/sysreg: Generate definitions for CONTEXTIDR_ELx Convert the various CONTEXTIDR_ELx register definitions to be automatically generated following the definitions in DDI0487H.a. No functional change. Signed-off-by: Mark Brown <broonie@kernel.org> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Link: https://lore.kernel.org/r/20220520161639.324236-3-broonie@kernel.org Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2022-05-21 00:16:34 +08:00
Sysreg CONTEXTIDR_EL12 3 5 13 0 1
Fields CONTEXTIDR_ELx
EndSysreg
arm64/sysreg: Generate definitions for TTBRn_EL1 Automatically generate definitions for accessing the TTBRn_EL1 registers, no functional change. Signed-off-by: Mark Brown <broonie@kernel.org> Acked-by: Mark Rutland <mark.rutland@arm.com> Link: https://lore.kernel.org/r/20220503170233.507788-12-broonie@kernel.org Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2022-05-04 01:02:32 +08:00
SysregFields TTBRx_EL1
Field 63:48 ASID
Field 47:1 BADDR
Field 0 CnP
EndSysregFields
Sysreg TTBR0_EL1 3 0 2 0 0
Fields TTBRx_EL1
EndSysreg
Sysreg TTBR1_EL1 3 0 2 0 1
Fields TTBRx_EL1
EndSysreg
arm64/sysreg: Convert LORSA_EL1 to automatic generation Convert LORSA_EL1 to automatic register generation as per DDI0487H.a, no functional changes. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-23-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05 01:02:56 +08:00
Sysreg LORSA_EL1 3 0 10 4 0
Res0 63:52
Field 51:16 SA
Res0 15:1
Field 0 Valid
EndSysreg
arm64/sysreg: Convert LOREA_EL1 to automatic generation Convert LOREA_EL1 to automatic register generation as per DDI0487H.a, no functional changes. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-24-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05 01:02:57 +08:00
Sysreg LOREA_EL1 3 0 10 4 1
Res0 63:52
Field 51:48 EA_51_48
Field 47:16 EA_47_16
Res0 15:0
EndSysreg
arm64/sysreg: Convert LORN_EL1 to automatic generation Convert LORN_EL1 to automatic register generation as per DDI0487H.a, no functional changes. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-25-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05 01:02:58 +08:00
Sysreg LORN_EL1 3 0 10 4 2
Res0 63:8
Field 7:0 Num
EndSysreg
arm64/sysreg: Convert LORC_EL1 to automatic generation Convert LORC_EL1 to automatic register generation as per DDI0487H.a, no functional changes. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-26-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05 01:02:59 +08:00
Sysreg LORC_EL1 3 0 10 4 3
Res0 63:10
Field 9:2 DS
Res0 1
Field 0 EN
EndSysreg
arm64/sysreg: Convert LORID_EL1 to automatic generation Convert LORID_EL1 to automatic register generation as per DDI0487H.a, no functional changes. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-27-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05 01:03:00 +08:00
Sysreg LORID_EL1 3 0 10 4 7
Res0 63:24
Field 23:16 LD
Res0 15:8
Field 7:0 LR
EndSysreg
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