2019-05-19 20:07:45 +08:00
|
|
|
# SPDX-License-Identifier: GPL-2.0-only
|
2013-10-12 07:54:56 +08:00
|
|
|
#
|
|
|
|
|
# Generic power capping sysfs interface configuration
|
|
|
|
|
#
|
|
|
|
|
|
|
|
|
|
menuconfig POWERCAP
|
|
|
|
|
bool "Generic powercap sysfs driver"
|
|
|
|
|
help
|
|
|
|
|
The power capping sysfs interface allows kernel subsystems to expose power
|
|
|
|
|
capping settings to user space in a consistent way. Usually, it consists
|
|
|
|
|
of multiple control types that determine which settings may be exposed and
|
|
|
|
|
power zones representing parts of the system that can be subject to power
|
|
|
|
|
capping.
|
|
|
|
|
|
|
|
|
|
If you want this code to be compiled in, say Y here.
|
|
|
|
|
|
|
|
|
|
if POWERCAP
|
|
|
|
|
# Client driver configurations go here.
|
2019-07-10 21:44:30 +08:00
|
|
|
config INTEL_RAPL_CORE
|
|
|
|
|
tristate
|
2023-06-06 22:00:00 +08:00
|
|
|
depends on PCI
|
|
|
|
|
select IOSF_MBI
|
2019-07-10 21:44:30 +08:00
|
|
|
|
PowerCap: Introduce Intel RAPL power capping driver
The Intel Running Average Power Limit (RAPL) technology provides platform
software with the ability to monitor, control, and get notifications on
power usage.
This feature is present in all Sandy Bridge and later Intel processors.
Newer models allow more fine grained controls to be applied. In RAPL,
power control is divided into domains, which include package, DRAM
controller, CPU core (Power Plane 0), graphics uncore (power plane 1), etc.
The purpose of this driver is to expose the RAPL settings to userspace.
Overall, RAPL fits in the new powercap class driver in that platform
level power capping controls are exposed via this generic interface.
This driver is based on an earlier patch from Zhang Rui.
However, while the previous work was mainly focused on thermal monitoring
the focus here is on the usability from user space perspective.
References: https://lkml.org/lkml/2011/5/26/93
Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
Reviewed-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2013-10-18 01:28:35 +08:00
|
|
|
config INTEL_RAPL
|
2019-07-10 21:44:30 +08:00
|
|
|
tristate "Intel RAPL Support via MSR Interface"
|
2023-06-06 22:00:00 +08:00
|
|
|
depends on X86 && PCI
|
2019-07-10 21:44:30 +08:00
|
|
|
select INTEL_RAPL_CORE
|
2020-06-14 00:50:22 +08:00
|
|
|
help
|
PowerCap: Introduce Intel RAPL power capping driver
The Intel Running Average Power Limit (RAPL) technology provides platform
software with the ability to monitor, control, and get notifications on
power usage.
This feature is present in all Sandy Bridge and later Intel processors.
Newer models allow more fine grained controls to be applied. In RAPL,
power control is divided into domains, which include package, DRAM
controller, CPU core (Power Plane 0), graphics uncore (power plane 1), etc.
The purpose of this driver is to expose the RAPL settings to userspace.
Overall, RAPL fits in the new powercap class driver in that platform
level power capping controls are exposed via this generic interface.
This driver is based on an earlier patch from Zhang Rui.
However, while the previous work was mainly focused on thermal monitoring
the focus here is on the usability from user space perspective.
References: https://lkml.org/lkml/2011/5/26/93
Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
Reviewed-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2013-10-18 01:28:35 +08:00
|
|
|
This enables support for the Intel Running Average Power Limit (RAPL)
|
2019-07-10 21:44:30 +08:00
|
|
|
technology via MSR interface, which allows power limits to be enforced
|
|
|
|
|
and monitored on modern Intel processors (Sandy Bridge and later).
|
PowerCap: Introduce Intel RAPL power capping driver
The Intel Running Average Power Limit (RAPL) technology provides platform
software with the ability to monitor, control, and get notifications on
power usage.
This feature is present in all Sandy Bridge and later Intel processors.
Newer models allow more fine grained controls to be applied. In RAPL,
power control is divided into domains, which include package, DRAM
controller, CPU core (Power Plane 0), graphics uncore (power plane 1), etc.
The purpose of this driver is to expose the RAPL settings to userspace.
Overall, RAPL fits in the new powercap class driver in that platform
level power capping controls are exposed via this generic interface.
This driver is based on an earlier patch from Zhang Rui.
However, while the previous work was mainly focused on thermal monitoring
the focus here is on the usability from user space perspective.
References: https://lkml.org/lkml/2011/5/26/93
Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
Reviewed-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2013-10-18 01:28:35 +08:00
|
|
|
|
|
|
|
|
In RAPL, the platform level settings are divided into domains for
|
|
|
|
|
fine grained control. These domains include processor package, DRAM
|
2020-10-18 23:21:06 +08:00
|
|
|
controller, CPU core (Power Plane 0), graphics uncore (Power Plane
|
PowerCap: Introduce Intel RAPL power capping driver
The Intel Running Average Power Limit (RAPL) technology provides platform
software with the ability to monitor, control, and get notifications on
power usage.
This feature is present in all Sandy Bridge and later Intel processors.
Newer models allow more fine grained controls to be applied. In RAPL,
power control is divided into domains, which include package, DRAM
controller, CPU core (Power Plane 0), graphics uncore (power plane 1), etc.
The purpose of this driver is to expose the RAPL settings to userspace.
Overall, RAPL fits in the new powercap class driver in that platform
level power capping controls are exposed via this generic interface.
This driver is based on an earlier patch from Zhang Rui.
However, while the previous work was mainly focused on thermal monitoring
the focus here is on the usability from user space perspective.
References: https://lkml.org/lkml/2011/5/26/93
Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
Reviewed-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2013-10-18 01:28:35 +08:00
|
|
|
1), etc.
|
2013-10-12 07:54:56 +08:00
|
|
|
|
powercap: intel_rapl: Introduce RAPL TPMI interface driver
The TPMI (Topology Aware Register and PM Capsule Interface) provides a
flexible, extendable and PCIe enumerable MMIO interface for PM features.
Intel RAPL (Running Average Power Limit) is one of the features that
benefit from this. Using TPMI Interface has advantage over traditional MSR
(Model Specific Register) interface, where a thread needs to be scheduled
on the target CPU to read or write. Also the RAPL features vary between
CPU models, and hence lot of model specific code. Here TPMI provides an
architectural interface by providing hierarchical tables and fields,
which will not need any model specific implementation.
TPMI interface uses a PCI VSEC structure to expose the location of MMIO
interface for PM feature enumeration and control.
The Intel VSEC driver parses VSEC structures present in the PCI
configuration space of the given device and creates an auxiliary device
object for each of them. In particular, it creates an auxiliary device
object representing TPMI that can be bound to by an auxiliary driver.
Then the TPMI enumeration driver binds to the TPMI auxiliary device
object created by the Intel VSEC driver, parses the PM Feature Structure
(PFS) present in the TPMI MMIO region and creates device nodes for PM
features described in the PFS.
This RAPL TPMI Interface driver binds the RAPL auxiliary device created
by the TPMI enumeration driver and expose the RAPL control to userspace
via powercap sysfs class.
RAPL TPMI details are published in the following document:
https://github.com/intel/tpmi_power_management/blob/main/RAPL_TPMI_public_disclosure_FINAL.docx
Note, for now, the RAPL TPMI Interface and RAPL MSR Interface cannot
co-exists on the same platform (RAPL TPMI Interface is not supported on
any platforms in the CPU model list for RAPL MSR Interface). Thus
register the RAPL TPMI powercap control type with name "intel-rapl",
the same as RAPL MSR Interface, so that it is transparent to userspace.
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Tested-by: Wang Wendy <wendy.wang@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2023-04-19 10:44:19 +08:00
|
|
|
config INTEL_RAPL_TPMI
|
|
|
|
|
tristate "Intel RAPL Support via TPMI Interface"
|
|
|
|
|
depends on X86
|
|
|
|
|
depends on INTEL_TPMI
|
|
|
|
|
select INTEL_RAPL_CORE
|
|
|
|
|
help
|
|
|
|
|
This enables support for the Intel Running Average Power Limit (RAPL)
|
|
|
|
|
technology via TPMI interface, which allows power limits to be enforced
|
|
|
|
|
and monitored.
|
|
|
|
|
|
|
|
|
|
In RAPL, the platform level settings are divided into domains for
|
|
|
|
|
fine grained control. These domains include processor package, DRAM
|
|
|
|
|
controller, platform, etc.
|
|
|
|
|
|
2018-06-26 18:53:29 +08:00
|
|
|
config IDLE_INJECT
|
|
|
|
|
bool "Idle injection framework"
|
|
|
|
|
depends on CPU_IDLE
|
|
|
|
|
default n
|
|
|
|
|
help
|
|
|
|
|
This enables support for the idle injection framework. It
|
|
|
|
|
provides a way to force idle periods on a set of specified
|
|
|
|
|
CPUs for power capping. Idle period can be injected
|
|
|
|
|
synchronously on a set of specified CPUs or alternatively
|
|
|
|
|
on a per CPU basis.
|
2020-12-09 00:41:44 +08:00
|
|
|
|
2022-10-14 01:46:12 +08:00
|
|
|
config ARM_SCMI_POWERCAP
|
|
|
|
|
tristate "ARM SCMI Powercap driver"
|
|
|
|
|
depends on ARM_SCMI_PROTOCOL
|
|
|
|
|
help
|
|
|
|
|
This enables support for the ARM Powercap based on ARM SCMI
|
|
|
|
|
Powercap protocol.
|
|
|
|
|
|
|
|
|
|
ARM SCMI Powercap protocol allows power limits to be enforced
|
|
|
|
|
and monitored against the SCMI Powercap domains advertised as
|
|
|
|
|
available by the SCMI platform firmware.
|
|
|
|
|
|
|
|
|
|
When compiled as module it will be called arm_scmi_powercap.ko.
|
|
|
|
|
|
2020-12-09 00:41:44 +08:00
|
|
|
config DTPM
|
2021-02-25 02:30:22 +08:00
|
|
|
bool "Power capping for Dynamic Thermal Power Management (EXPERIMENTAL)"
|
2022-01-29 00:35:34 +08:00
|
|
|
depends on OF
|
2020-12-09 00:41:44 +08:00
|
|
|
help
|
|
|
|
|
This enables support for the power capping for the dynamic
|
|
|
|
|
thermal power management userspace engine.
|
2020-12-09 00:41:45 +08:00
|
|
|
|
|
|
|
|
config DTPM_CPU
|
|
|
|
|
bool "Add CPU power capping based on the energy model"
|
|
|
|
|
depends on DTPM && ENERGY_MODEL
|
|
|
|
|
help
|
|
|
|
|
This enables support for CPU power limitation based on
|
|
|
|
|
energy model.
|
2022-01-29 00:35:36 +08:00
|
|
|
|
|
|
|
|
config DTPM_DEVFREQ
|
|
|
|
|
bool "Add device power capping based on the energy model"
|
|
|
|
|
depends on DTPM && ENERGY_MODEL
|
|
|
|
|
help
|
|
|
|
|
This enables support for device power limitation based on
|
|
|
|
|
energy model.
|
2013-10-12 07:54:56 +08:00
|
|
|
endif
|
