2011-06-07 23:02:55 +08:00
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/*
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* Copyright 2010-2011 Calxeda, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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2012-08-21 18:31:06 +08:00
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#include <linux/dma-mapping.h>
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2011-06-07 23:02:55 +08:00
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#include <linux/io.h>
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#include <linux/irq.h>
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2012-11-06 06:18:28 +08:00
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#include <linux/irqchip.h>
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2011-06-07 23:02:55 +08:00
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#include <linux/irqdomain.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/of_address.h>
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2011-06-06 19:35:46 +08:00
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#include <linux/smp.h>
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2012-08-21 18:31:06 +08:00
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#include <linux/amba/bus.h>
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2011-06-07 23:02:55 +08:00
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2012-10-26 01:19:52 +08:00
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#include <asm/arch_timer.h>
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2011-06-07 23:02:55 +08:00
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#include <asm/cacheflush.h>
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2012-01-20 19:01:12 +08:00
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#include <asm/smp_plat.h>
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2012-01-11 03:44:19 +08:00
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#include <asm/smp_twd.h>
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2011-06-07 23:02:55 +08:00
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#include <asm/hardware/arm_timer.h>
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#include <asm/hardware/timer-sp.h>
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#include <asm/hardware/cache-l2x0.h>
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#include <asm/mach/arch.h>
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2012-10-28 04:38:22 +08:00
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#include <asm/mach/map.h>
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2011-06-07 23:02:55 +08:00
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#include <asm/mach/time.h>
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#include "core.h"
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#include "sysregs.h"
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void __iomem *sregs_base;
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2012-10-26 01:13:47 +08:00
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void __iomem *scu_base_addr;
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2011-06-07 23:02:55 +08:00
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static void __init highbank_scu_map_io(void)
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{
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unsigned long base;
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/* Get SCU base */
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asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base));
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2012-10-26 01:13:47 +08:00
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scu_base_addr = ioremap(base, SZ_4K);
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2011-06-07 23:02:55 +08:00
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}
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#define HB_JUMP_TABLE_PHYS(cpu) (0x40 + (0x10 * (cpu)))
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#define HB_JUMP_TABLE_VIRT(cpu) phys_to_virt(HB_JUMP_TABLE_PHYS(cpu))
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void highbank_set_cpu_jump(int cpu, void *jump_addr)
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{
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2011-06-06 19:35:46 +08:00
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cpu = cpu_logical_map(cpu);
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2012-01-10 05:41:58 +08:00
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writel(virt_to_phys(jump_addr), HB_JUMP_TABLE_VIRT(cpu));
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2011-06-07 23:02:55 +08:00
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__cpuc_flush_dcache_area(HB_JUMP_TABLE_VIRT(cpu), 16);
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outer_clean_range(HB_JUMP_TABLE_PHYS(cpu),
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HB_JUMP_TABLE_PHYS(cpu) + 15);
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}
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2012-06-07 06:20:10 +08:00
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#ifdef CONFIG_CACHE_L2X0
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static void highbank_l2x0_disable(void)
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{
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/* Disable PL310 L2 Cache controller */
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highbank_smc1(0x102, 0x0);
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}
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#endif
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2011-06-07 23:02:55 +08:00
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static void __init highbank_init_irq(void)
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{
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2012-11-06 06:18:28 +08:00
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irqchip_init();
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2012-06-07 06:20:10 +08:00
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2012-10-26 01:13:47 +08:00
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if (of_find_compatible_node(NULL, NULL, "arm,cortex-a9"))
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highbank_scu_map_io();
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2012-06-07 06:20:10 +08:00
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#ifdef CONFIG_CACHE_L2X0
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/* Enable PL310 L2 Cache controller */
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highbank_smc1(0x102, 0x1);
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2011-06-07 23:02:55 +08:00
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l2x0_of_init(0, ~0UL);
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2012-06-07 06:20:10 +08:00
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outer_cache.disable = highbank_l2x0_disable;
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#endif
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2011-06-07 23:02:55 +08:00
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}
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2012-03-14 07:19:19 +08:00
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static struct clk_lookup lookup = {
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.dev_id = "sp804",
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.con_id = NULL,
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};
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2011-06-07 23:02:55 +08:00
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static void __init highbank_timer_init(void)
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{
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int irq;
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struct device_node *np;
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void __iomem *timer_base;
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/* Map system registers */
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np = of_find_compatible_node(NULL, NULL, "calxeda,hb-sregs");
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sregs_base = of_iomap(np, 0);
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WARN_ON(!sregs_base);
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np = of_find_compatible_node(NULL, NULL, "arm,sp804");
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timer_base = of_iomap(np, 0);
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WARN_ON(!timer_base);
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irq = irq_of_parse_and_map(np, 0);
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highbank_clocks_init();
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2012-03-14 07:19:19 +08:00
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lookup.clk = of_clk_get(np, 0);
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clkdev_add(&lookup);
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2011-06-07 23:02:55 +08:00
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2012-01-16 22:06:09 +08:00
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sp804_clocksource_and_sched_clock_init(timer_base + 0x20, "timer1");
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2011-06-07 23:02:55 +08:00
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sp804_clockevents_init(timer_base, irq, "timer0");
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2012-01-11 03:44:19 +08:00
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twd_local_timer_of_register();
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2012-10-26 01:19:52 +08:00
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arch_timer_of_register();
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arch_timer_sched_clock_init();
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2011-06-07 23:02:55 +08:00
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}
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static struct sys_timer highbank_timer = {
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.init = highbank_timer_init,
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};
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static void highbank_power_off(void)
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{
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2012-12-31 00:15:04 +08:00
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highbank_set_pwr_shutdown();
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2011-06-07 23:02:55 +08:00
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while (1)
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cpu_do_idle();
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}
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2012-08-21 18:31:06 +08:00
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static int highbank_platform_notifier(struct notifier_block *nb,
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unsigned long event, void *__dev)
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{
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struct resource *res;
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int reg = -1;
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struct device *dev = __dev;
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if (event != BUS_NOTIFY_ADD_DEVICE)
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return NOTIFY_DONE;
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if (of_device_is_compatible(dev->of_node, "calxeda,hb-ahci"))
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reg = 0xc;
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else if (of_device_is_compatible(dev->of_node, "calxeda,hb-sdhci"))
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reg = 0x18;
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else if (of_device_is_compatible(dev->of_node, "arm,pl330"))
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reg = 0x20;
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else if (of_device_is_compatible(dev->of_node, "calxeda,hb-xgmac")) {
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res = platform_get_resource(to_platform_device(dev),
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IORESOURCE_MEM, 0);
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if (res) {
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if (res->start == 0xfff50000)
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reg = 0;
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else if (res->start == 0xfff51000)
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reg = 4;
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}
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}
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if (reg < 0)
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return NOTIFY_DONE;
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if (of_property_read_bool(dev->of_node, "dma-coherent")) {
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writel(0xff31, sregs_base + reg);
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set_dma_ops(dev, &arm_coherent_dma_ops);
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} else
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writel(0, sregs_base + reg);
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return NOTIFY_OK;
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}
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static struct notifier_block highbank_amba_nb = {
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.notifier_call = highbank_platform_notifier,
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};
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static struct notifier_block highbank_platform_nb = {
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.notifier_call = highbank_platform_notifier,
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};
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2011-06-07 23:02:55 +08:00
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static void __init highbank_init(void)
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{
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pm_power_off = highbank_power_off;
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2012-09-17 22:55:12 +08:00
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highbank_pm_init();
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2011-06-07 23:02:55 +08:00
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2012-08-21 18:31:06 +08:00
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bus_register_notifier(&platform_bus_type, &highbank_platform_nb);
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bus_register_notifier(&amba_bustype, &highbank_amba_nb);
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2011-06-07 23:02:55 +08:00
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of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
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}
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static const char *highbank_match[] __initconst = {
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"calxeda,highbank",
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2012-10-26 01:19:52 +08:00
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"calxeda,ecx-2000",
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2011-06-07 23:02:55 +08:00
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NULL,
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};
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DT_MACHINE_START(HIGHBANK, "Highbank")
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2012-09-05 22:36:18 +08:00
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.smp = smp_ops(highbank_smp_ops),
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2012-10-28 04:38:22 +08:00
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.map_io = debug_ll_io_init,
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2011-06-07 23:02:55 +08:00
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.init_irq = highbank_init_irq,
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.timer = &highbank_timer,
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.init_machine = highbank_init,
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.dt_compat = highbank_match,
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2011-11-05 19:16:05 +08:00
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.restart = highbank_restart,
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2011-06-07 23:02:55 +08:00
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MACHINE_END
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