2010-08-19 19:36:01 +08:00
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/*
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2010-12-08 22:13:28 +08:00
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* Copyright (C) STMicroelectronics 2009
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* Copyright (C) ST-Ericsson SA 2010
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2010-08-19 19:36:01 +08:00
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*
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2010-12-08 22:13:28 +08:00
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* Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
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* Author: Sundar Iyer <sundar.iyer@stericsson.com>
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*
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* License Terms: GNU General Public License v2
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*
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* PRCM Unit registers
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2010-08-19 19:36:01 +08:00
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*/
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2011-08-12 16:27:20 +08:00
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2011-05-16 06:15:05 +08:00
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#ifndef __DB8500_PRCMU_REGS_H
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#define __DB8500_PRCMU_REGS_H
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2010-12-08 22:13:28 +08:00
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2010-08-19 19:36:01 +08:00
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#include <mach/hardware.h>
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2011-05-16 06:15:05 +08:00
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#define BITS(_start, _end) ((BIT(_end) - BIT(_start)) + BIT(_end))
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2011-08-12 16:27:20 +08:00
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#define PRCM_SVACLK_MGT_OFF 0x008
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#define PRCM_SIACLK_MGT_OFF 0x00C
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#define PRCM_SGACLK_MGT_OFF 0x014
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#define PRCM_UARTCLK_MGT_OFF 0x018
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#define PRCM_MSP02CLK_MGT_OFF 0x01C
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#define PRCM_I2CCLK_MGT_OFF 0x020
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#define PRCM_SDMMCCLK_MGT_OFF 0x024
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#define PRCM_SLIMCLK_MGT_OFF 0x028
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#define PRCM_PER1CLK_MGT_OFF 0x02C
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#define PRCM_PER2CLK_MGT_OFF 0x030
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#define PRCM_PER3CLK_MGT_OFF 0x034
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#define PRCM_PER5CLK_MGT_OFF 0x038
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#define PRCM_PER6CLK_MGT_OFF 0x03C
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#define PRCM_PER7CLK_MGT_OFF 0x040
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#define PRCM_PWMCLK_MGT_OFF 0x044 /* for DB5500 */
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#define PRCM_IRDACLK_MGT_OFF 0x048 /* for DB5500 */
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#define PRCM_IRRCCLK_MGT_OFF 0x04C /* for DB5500 */
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#define PRCM_LCDCLK_MGT_OFF 0x044
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#define PRCM_BMLCLK_MGT_OFF 0x04C
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#define PRCM_HSITXCLK_MGT_OFF 0x050
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#define PRCM_HSIRXCLK_MGT_OFF 0x054
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#define PRCM_HDMICLK_MGT_OFF 0x058
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#define PRCM_APEATCLK_MGT_OFF 0x05C
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#define PRCM_APETRACECLK_MGT_OFF 0x060
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#define PRCM_MCDECLK_MGT_OFF 0x064
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#define PRCM_IPI2CCLK_MGT_OFF 0x068
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#define PRCM_DSIALTCLK_MGT_OFF 0x06C
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#define PRCM_DMACLK_MGT_OFF 0x074
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#define PRCM_B2R2CLK_MGT_OFF 0x078
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#define PRCM_TVCLK_MGT_OFF 0x07C
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#define PRCM_UNIPROCLK_MGT_OFF 0x278
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#define PRCM_SSPCLK_MGT_OFF 0x280
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#define PRCM_RNGCLK_MGT_OFF 0x284
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#define PRCM_UICCCLK_MGT_OFF 0x27C
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#define PRCM_MSP1CLK_MGT_OFF 0x288
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#define PRCM_ARM_PLLDIVPS (_PRCMU_BASE + 0x118)
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#define PRCM_ARM_PLLDIVPS_ARM_BRM_RATE 0x3f
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#define PRCM_ARM_PLLDIVPS_MAX_MASK 0xf
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#define PRCM_PLLARM_LOCKP (_PRCMU_BASE + 0x0a8)
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#define PRCM_PLLARM_LOCKP_PRCM_PLLARM_LOCKP3 0x2
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#define PRCM_ARM_CHGCLKREQ (_PRCMU_BASE + 0x114)
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#define PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ 0x1
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#define PRCM_PLLARM_ENABLE (_PRCMU_BASE + 0x98)
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#define PRCM_PLLARM_ENABLE_PRCM_PLLARM_ENABLE 0x1
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#define PRCM_PLLARM_ENABLE_PRCM_PLLARM_COUNTON 0x100
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#define PRCM_ARMCLKFIX_MGT (_PRCMU_BASE + 0x0)
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#define PRCM_A9PL_FORCE_CLKEN (_PRCMU_BASE + 0x19C)
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#define PRCM_A9_RESETN_CLR (_PRCMU_BASE + 0x1f4)
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#define PRCM_A9_RESETN_SET (_PRCMU_BASE + 0x1f0)
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#define PRCM_ARM_LS_CLAMP (_PRCMU_BASE + 0x30c)
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#define PRCM_SRAM_A9 (_PRCMU_BASE + 0x308)
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#define PRCM_A9PL_FORCE_CLKEN_PRCM_A9PL_FORCE_CLKEN BIT(0)
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#define PRCM_A9PL_FORCE_CLKEN_PRCM_A9AXI_FORCE_CLKEN BIT(1)
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2010-08-19 19:36:01 +08:00
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/* ARM WFI Standby signal register */
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2011-08-12 16:27:20 +08:00
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#define PRCM_ARM_WFI_STANDBY (_PRCMU_BASE + 0x130)
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#define PRCM_IOCR (_PRCMU_BASE + 0x310)
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#define PRCM_IOCR_IOFORCE 0x1
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2010-08-19 19:36:01 +08:00
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/* CPU mailbox registers */
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2011-08-12 16:27:20 +08:00
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#define PRCM_MBOX_CPU_VAL (_PRCMU_BASE + 0x0fc)
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#define PRCM_MBOX_CPU_SET (_PRCMU_BASE + 0x100)
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#define PRCM_MBOX_CPU_CLR (_PRCMU_BASE + 0x104)
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2010-08-19 19:36:01 +08:00
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/* Dual A9 core interrupt management unit registers */
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2011-08-12 16:27:20 +08:00
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#define PRCM_A9_MASK_REQ (_PRCMU_BASE + 0x328)
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#define PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ 0x1
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#define PRCM_A9_MASK_ACK (_PRCMU_BASE + 0x32c)
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#define PRCM_ARMITMSK31TO0 (_PRCMU_BASE + 0x11c)
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#define PRCM_ARMITMSK63TO32 (_PRCMU_BASE + 0x120)
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#define PRCM_ARMITMSK95TO64 (_PRCMU_BASE + 0x124)
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#define PRCM_ARMITMSK127TO96 (_PRCMU_BASE + 0x128)
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#define PRCM_POWER_STATE_VAL (_PRCMU_BASE + 0x25C)
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#define PRCM_ARMITVAL31TO0 (_PRCMU_BASE + 0x260)
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#define PRCM_ARMITVAL63TO32 (_PRCMU_BASE + 0x264)
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#define PRCM_ARMITVAL95TO64 (_PRCMU_BASE + 0x268)
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#define PRCM_ARMITVAL127TO96 (_PRCMU_BASE + 0x26C)
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#define PRCM_HOSTACCESS_REQ (_PRCMU_BASE + 0x334)
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#define PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ 0x1
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#define ARM_WAKEUP_MODEM 0x1
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#define PRCM_ARM_IT1_CLR (_PRCMU_BASE + 0x48C)
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#define PRCM_ARM_IT1_VAL (_PRCMU_BASE + 0x494)
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#define PRCM_HOLD_EVT (_PRCMU_BASE + 0x174)
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#define PRCM_MOD_AWAKE_STATUS (_PRCMU_BASE + 0x4A0)
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#define PRCM_MOD_AWAKE_STATUS_PRCM_MOD_COREPD_AWAKE BIT(0)
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#define PRCM_MOD_AWAKE_STATUS_PRCM_MOD_AAPD_AWAKE BIT(1)
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#define PRCM_MOD_AWAKE_STATUS_PRCM_MOD_VMODEM_OFF_ISO BIT(2)
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#define PRCM_ITSTATUS0 (_PRCMU_BASE + 0x148)
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#define PRCM_ITSTATUS1 (_PRCMU_BASE + 0x150)
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#define PRCM_ITSTATUS2 (_PRCMU_BASE + 0x158)
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#define PRCM_ITSTATUS3 (_PRCMU_BASE + 0x160)
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#define PRCM_ITSTATUS4 (_PRCMU_BASE + 0x168)
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#define PRCM_ITSTATUS5 (_PRCMU_BASE + 0x484)
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#define PRCM_ITCLEAR5 (_PRCMU_BASE + 0x488)
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#define PRCM_ARMIT_MASKXP70_IT (_PRCMU_BASE + 0x1018)
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2010-08-19 19:36:01 +08:00
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/* System reset register */
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2011-08-12 16:27:20 +08:00
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#define PRCM_APE_SOFTRST (_PRCMU_BASE + 0x228)
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2010-08-19 19:36:01 +08:00
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/* Level shifter and clamp control registers */
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2011-08-12 16:27:20 +08:00
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#define PRCM_MMIP_LS_CLAMP_SET (_PRCMU_BASE + 0x420)
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#define PRCM_MMIP_LS_CLAMP_CLR (_PRCMU_BASE + 0x424)
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/* PRCMU clock/PLL/reset registers */
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#define PRCM_PLLDSI_FREQ (_PRCMU_BASE + 0x500)
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#define PRCM_PLLDSI_ENABLE (_PRCMU_BASE + 0x504)
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#define PRCM_PLLDSI_LOCKP (_PRCMU_BASE + 0x508)
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#define PRCM_LCDCLK_MGT (_PRCMU_BASE + PRCM_LCDCLK_MGT_OFF)
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#define PRCM_MCDECLK_MGT (_PRCMU_BASE + PRCM_MCDECLK_MGT_OFF)
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#define PRCM_HDMICLK_MGT (_PRCMU_BASE + PRCM_HDMICLK_MGT_OFF)
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#define PRCM_TVCLK_MGT (_PRCMU_BASE + PRCM_TVCLK_MGT_OFF)
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#define PRCM_DSI_PLLOUT_SEL (_PRCMU_BASE + 0x530)
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#define PRCM_DSITVCLK_DIV (_PRCMU_BASE + 0x52C)
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#define PRCM_PLLDSI_LOCKP (_PRCMU_BASE + 0x508)
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#define PRCM_APE_RESETN_SET (_PRCMU_BASE + 0x1E4)
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#define PRCM_APE_RESETN_CLR (_PRCMU_BASE + 0x1E8)
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#define PRCM_CLKOCR (_PRCMU_BASE + 0x1CC)
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#define PRCM_CLKOCR_CLKOUT0_REF_CLK (1 << 0)
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#define PRCM_CLKOCR_CLKOUT0_MASK BITS(0, 13)
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#define PRCM_CLKOCR_CLKOUT1_REF_CLK (1 << 16)
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#define PRCM_CLKOCR_CLKOUT1_MASK BITS(16, 29)
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/* ePOD and memory power signal control registers */
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#define PRCM_EPOD_C_SET (_PRCMU_BASE + 0x410)
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#define PRCM_SRAM_LS_SLEEP (_PRCMU_BASE + 0x304)
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/* Debug power control unit registers */
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#define PRCM_POWER_STATE_SET (_PRCMU_BASE + 0x254)
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/* Miscellaneous unit registers */
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#define PRCM_DSI_SW_RESET (_PRCMU_BASE + 0x324)
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#define PRCM_GPIOCR (_PRCMU_BASE + 0x138)
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#define PRCM_GPIOCR_DBG_STM_MOD_CMD1 0x800
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#define PRCM_GPIOCR_DBG_UARTMOD_CMD0 0x1
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2011-05-16 06:15:05 +08:00
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/* PRCMU HW semaphore */
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2011-08-12 16:27:20 +08:00
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#define PRCM_SEM (_PRCMU_BASE + 0x400)
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2011-05-16 06:15:05 +08:00
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#define PRCM_SEM_PRCM_SEM BIT(0)
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2010-08-19 19:36:01 +08:00
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2011-08-12 16:27:20 +08:00
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#define PRCM_TCR (_PRCMU_BASE + 0x1C8)
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#define PRCM_TCR_TENSEL_MASK BITS(0, 7)
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#define PRCM_TCR_STOP_TIMERS BIT(16)
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#define PRCM_TCR_DOZE_MODE BIT(17)
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2011-05-16 06:15:05 +08:00
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#define PRCM_CLKOCR_CLKODIV0_SHIFT 0
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#define PRCM_CLKOCR_CLKODIV0_MASK BITS(0, 5)
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#define PRCM_CLKOCR_CLKOSEL0_SHIFT 6
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#define PRCM_CLKOCR_CLKOSEL0_MASK BITS(6, 8)
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#define PRCM_CLKOCR_CLKODIV1_SHIFT 16
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#define PRCM_CLKOCR_CLKODIV1_MASK BITS(16, 21)
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#define PRCM_CLKOCR_CLKOSEL1_SHIFT 22
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#define PRCM_CLKOCR_CLKOSEL1_MASK BITS(22, 24)
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#define PRCM_CLKOCR_CLK1TYPE BIT(28)
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#define PRCM_CLK_MGT_CLKPLLDIV_MASK BITS(0, 4)
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#define PRCM_CLK_MGT_CLKPLLSW_MASK BITS(5, 7)
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#define PRCM_CLK_MGT_CLKEN BIT(8)
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2010-08-19 19:36:01 +08:00
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2011-08-12 16:27:20 +08:00
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/* GPIOCR register */
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#define PRCM_GPIOCR_SPI2_SELECT BIT(23)
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2010-08-19 19:36:01 +08:00
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2011-08-12 16:27:20 +08:00
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#define PRCM_DDR_SUBSYS_APE_MINBW (_PRCMU_BASE + 0x438)
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#define PRCM_CGATING_BYPASS (_PRCMU_BASE + 0x134)
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#define PRCM_CGATING_BYPASS_ICN2 BIT(6)
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2010-08-19 19:36:01 +08:00
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/* Miscellaneous unit registers */
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2011-08-12 16:27:20 +08:00
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#define PRCM_RESOUTN_SET (_PRCMU_BASE + 0x214)
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#define PRCM_RESOUTN_CLR (_PRCMU_BASE + 0x218)
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2011-05-16 06:15:05 +08:00
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2011-08-12 16:27:20 +08:00
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/* System reset register */
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#define PRCM_APE_SOFTRST (_PRCMU_BASE + 0x228)
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2010-08-19 19:36:01 +08:00
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2011-05-16 06:15:05 +08:00
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#endif /* __DB8500_PRCMU_REGS_H */
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