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treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 18 Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 or at your option any later version this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program see the file copying if not write to the free software foundation 675 mass ave cambridge ma 02139 usa extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 52 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Jilayne Lovejoy <opensource@jilayne.com> Reviewed-by: Steve Winslow <swinslow@gmail.com> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190519154042.342335923@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-19 21:51:48 +08:00
// SPDX-License-Identifier: GPL-2.0-or-later
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 06:20:36 +08:00
/*
* ahci.c - AHCI SATA support
*
libata: update "Maintained by:" tags Jeff moved on to a greener pasture. s/Maintained by: Jeff Garzik/Maintained by: Tejun Heo/g Signed-off-by: Tejun Heo <tj@kernel.org> Cc: Jeff Garzik <jgarzik@pobox.com>
2013-05-15 02:09:50 +08:00
* Maintained by: Tejun Heo <tj@kernel.org>
[libata] license change, other bits - changes license of all code from OSL+GPL to plain ole GPL - except for NVIDIA, who hasn't yet responded about sata_nv - copyright holders were already contacted privately - adds info in each driver about where hardware/protocol docs may be obtained - where I have made major contributions, updated copyright dates
2005-08-29 08:18:39 +08:00
* Please ALWAYS copy linux-ide@vger.kernel.org
* on emails.
*
* Copyright 2004-2005 Red Hat, Inc.
*
* libata documentation is available via 'make {ps|pdf}docs',
ata: update references for libata documentation The libata documentation is now using ReST. Update references to it to point to the new place. Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
2017-05-14 22:52:56 +08:00
* as Documentation/driver-api/libata.rst
[libata] license change, other bits - changes license of all code from OSL+GPL to plain ole GPL - except for NVIDIA, who hasn't yet responded about sata_nv - copyright holders were already contacted privately - adds info in each driver about where hardware/protocol docs may be obtained - where I have made major contributions, updated copyright dates
2005-08-29 08:18:39 +08:00
*
* AHCI hardware documentation:
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 06:20:36 +08:00
* http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
[libata] license change, other bits - changes license of all code from OSL+GPL to plain ole GPL - except for NVIDIA, who hasn't yet responded about sata_nv - copyright holders were already contacted privately - adds info in each driver about where hardware/protocol docs may be obtained - where I have made major contributions, updated copyright dates
2005-08-29 08:18:39 +08:00
* http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 06:20:36 +08:00
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
[PATCH] drivers/scsi/ahci: add #include req'd for the DMA_{64,32}BIT_MASK constants The previous patch did not compile cleanly on all architectures so here's a fixed one which #includes <linux/dma-mapping.h>. Use the DMA_{64,32}BIT_MASK constants from dma-mapping.h when calling pci_set_dma_mask() or pci_set_consistent_dma_mask() This patch includes dma-mapping.h explicitly because it caused errors on some architectures otherwise. See http://marc.theaimsgroup.com/?t=108001993000001&r=1&w=2 for details Signed-off-by: Tobias Klauser <tklauser@nuerscht.ch> Signed-off-by: Domen Puncer <domen@coderock.org> diff -puN drivers/scsi/ahci.c~dma_mask-drivers_scsi_ahci drivers/scsi/ahci.c
2005-04-08 15:53:06 +08:00
#include <linux/dma-mapping.h>
[libata] use dev_printk() throughout drivers A few drivers were not following the standard meme of printing out their driver name and version at module load time; this is fixed as well.
2005-10-31 03:39:11 +08:00
#include <linux/device.h>
ahci: ahci: implement workaround for ASUS P5W-DH Deluxe ahci_broken_hardreset(), take #2 P5W-DH Deluxe has ICH9 which doesn't have PMP support but SIMG 4726 hardwired to the second port of AHCI controller at PCI device 1f.2. The 4726 doesn't work as PMP but as a storage processor which can do hardware RAID on downstream ports. When no device is attached to the downstream port of the 4726, pseudo ATA device for configuration appears. Unfortunately, ATA emulation on the device is very lousy and causes long hang during boot. This patch implements workaround for the board. If the mainboard is P5W-DH Deluxe (matched using DMI), only hardreset is used on the second port of AHCI controller @ 1f.2 and the hardreset doesn't depend on receiving the first FIS and just proceed to IDENTIFY. This workaround fixes bugzilla #8923. http://bugzilla.kernel.org/show_bug.cgi?id=8923 Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-10-25 13:59:16 +08:00
#include <linux/dmi.h>
include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h percpu.h is included by sched.h and module.h and thus ends up being included when building most .c files. percpu.h includes slab.h which in turn includes gfp.h making everything defined by the two files universally available and complicating inclusion dependencies. percpu.h -> slab.h dependency is about to be removed. Prepare for this change by updating users of gfp and slab facilities include those headers directly instead of assuming availability. As this conversion needs to touch large number of source files, the following script is used as the basis of conversion. http://userweb.kernel.org/~tj/misc/slabh-sweep.py The script does the followings. * Scan files for gfp and slab usages and update includes such that only the necessary includes are there. ie. if only gfp is used, gfp.h, if slab is used, slab.h. * When the script inserts a new include, it looks at the include blocks and try to put the new include such that its order conforms to its surrounding. It's put in the include block which contains core kernel includes, in the same order that the rest are ordered - alphabetical, Christmas tree, rev-Xmas-tree or at the end if there doesn't seem to be any matching order. * If the script can't find a place to put a new include (mostly because the file doesn't have fitting include block), it prints out an error message indicating which .h file needs to be added to the file. The conversion was done in the following steps. 1. The initial automatic conversion of all .c files updated slightly over 4000 files, deleting around 700 includes and adding ~480 gfp.h and ~3000 slab.h inclusions. The script emitted errors for ~400 files. 2. Each error was manually checked. Some didn't need the inclusion, some needed manual addition while adding it to implementation .h or embedding .c file was more appropriate for others. This step added inclusions to around 150 files. 3. The script was run again and the output was compared to the edits from #2 to make sure no file was left behind. 4. Several build tests were done and a couple of problems were fixed. e.g. lib/decompress_*.c used malloc/free() wrappers around slab APIs requiring slab.h to be added manually. 5. The script was run on all .h files but without automatically editing them as sprinkling gfp.h and slab.h inclusions around .h files could easily lead to inclusion dependency hell. Most gfp.h inclusion directives were ignored as stuff from gfp.h was usually wildly available and often used in preprocessor macros. Each slab.h inclusion directive was examined and added manually as necessary. 6. percpu.h was updated not to include slab.h. 7. Build test were done on the following configurations and failures were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my distributed build env didn't work with gcov compiles) and a few more options had to be turned off depending on archs to make things build (like ipr on powerpc/64 which failed due to missing writeq). * x86 and x86_64 UP and SMP allmodconfig and a custom test config. * powerpc and powerpc64 SMP allmodconfig * sparc and sparc64 SMP allmodconfig * ia64 SMP allmodconfig * s390 SMP allmodconfig * alpha SMP allmodconfig * um on x86_64 SMP allmodconfig 8. percpu.h modifications were reverted so that it could be applied as a separate patch and serve as bisection point. Given the fact that I had only a couple of failures from tests on step 6, I'm fairly confident about the coverage of this conversion patch. If there is a breakage, it's likely to be something in one of the arch headers which should be easily discoverable easily on most builds of the specific arch. Signed-off-by: Tejun Heo <tj@kernel.org> Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org> Cc: Ingo Molnar <mingo@redhat.com> Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 16:04:11 +08:00
#include <linux/gfp.h>
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 06:20:36 +08:00
#include <scsi/scsi_host.h>
[libata] eliminate use of drivers/scsi/scsi.h compatibility header/defines
2005-11-07 13:59:37 +08:00
#include <scsi/scsi_cmnd.h>
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 06:20:36 +08:00
#include <linux/libata.h>
ahci: warn about remapped NVMe devices Some Intel ahci implementations have a completely broken remapping mode where they hide one or more NVMe devices behind the bar of an AHCI device. Intel refuses to let the OS reprogram the BIOS to switch out of this mode at runtime, and so far we're not come up with another good way to undo the mess that the Chipset people created. So for now the only thing we can do is to alert users about this situation and switch to the faster and much saner so called "AHCI" mode insted of the RAID mode in the BIOS so that the BIOS does not hide the NVMe devices from us. The sitation is even worse as at least one vendor (thanks a lot Lenovo..) has started hardcoding their BIOS into the "RAID" mode even for laptops that don't use AHCI _at all_ and just have a single NVMe device. For now there is an unspported Linux-only BIOS that undoes this braindamage, but we'll have to see if things are getting better or worse from here. Based on an earlier patch from Dan Williams <dan.j.williams@intel.com>. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Tejun Heo <tj@kernel.org>
2016-12-03 02:31:03 +08:00
#include <linux/ahci-remap.h>
#include <linux/io-64-nonatomic-lo-hi.h>
ahci: Move generic code into libahci This patch should contain no functional changes, just moves code around. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-03-28 12:22:14 +08:00
#include "ahci.h"
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 06:20:36 +08:00
#define DRV_NAME "ahci"
ahci: implement PMP support Implement AHCI PMP support. ahci only supports command based switching. Also, for some reason, NCQ over PMP doesn't work now. Other than that, everything works. Tested on ICH9R, JMB360/363 + SIMG3726, 4726 and 5744. Signed-off-by: Tejun Heo <htejun@gmail.com> Cc: Forrest Zhao <forrest.zhao@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-09-23 12:19:54 +08:00
#define DRV_VERSION "3.0"
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 06:20:36 +08:00
enum {
ahci: support the STA2X11 I/O Hub The AHCI controller found in the STA2X11 chip uses BAR number 0 instead of 5. Also, the chip's fixup code sets a special DMA mask for all of its PCI functions, and the mask must be preserved here. Signed-off-by: Alessandro Rubini <rubini@gnudd.com> Acked-by: Giancarlo Asnaghi <giancarlo.asnaghi@st.com> Cc: Alan Cox <alan@linux.intel.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2012-01-06 20:33:39 +08:00
AHCI_PCI_BAR_STA2X11 = 0,
ahci: Add support for Cavium's ThunderX host controller This patch adds support for Cavium's ThunderX host controller. The controller resides on the SoC and is a AHCI compatible SATA controller with one port, compliant with Serial ATA 3.1 and AHCI Revision 1.31. There can exists multiple SATA controllers on the SoC. The controller depends on MSI-X support since the PCI ECAM controller on the SoC does not implement MSI nor lagacy intx interrupt support. Thus, during device initialization, if MSI fails MSI-X will be used to enable the device's interrupts. The controller uses non-standard BAR0 for its register range. The already existing device lookup (vendor and device id) that is already implemented for other host controllers is used to change the PCI BAR. Signed-off-by: Robert Richter <rrichter@cavium.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2015-06-06 01:49:26 +08:00
AHCI_PCI_BAR_CAVIUM = 0,
AHCI: Add support for Loongson 7A1000 SATA controller Loongson 7A1000 SATA controller uses BAR0 as the base address register. Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn> Signed-off-by: Jens Axboe <axboe@kernel.dk>
2020-03-10 20:50:08 +08:00
AHCI_PCI_BAR_LOONGSON = 0,
[libata] ahci: Add support for Enmotus Bobcat device. Silicon does not support standard AHCI BAR assignment. Add vendor/device exception to force BAR 2. Signed-off-by: Hugh Daschbach <hugh.daschbach@enmotus.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2013-01-05 06:39:09 +08:00
AHCI_PCI_BAR_ENMOTUS = 2,
ahci: Add support for Cavium's fifth generation SATA controller This patch adds support for Cavium's fifth generation SATA controller. It is an on-chip controller and complies with AHCI 1.3.1. As the controller uses 64-bit addresses it cannot use the standard AHCI BAR5 and so uses BAR4. Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2017-10-11 13:37:51 +08:00
AHCI_PCI_BAR_CAVIUM_GEN5 = 4,
ahci: support the STA2X11 I/O Hub The AHCI controller found in the STA2X11 chip uses BAR number 0 instead of 5. Also, the chip's fixup code sets a special DMA mask for all of its PCI functions, and the mask must be preserved here. Signed-off-by: Alessandro Rubini <rubini@gnudd.com> Acked-by: Giancarlo Asnaghi <giancarlo.asnaghi@st.com> Cc: Alan Cox <alan@linux.intel.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2012-01-06 20:33:39 +08:00
AHCI_PCI_BAR_STANDARD = 5,
ahci: clean up board IDs ahci over time has grown a number of board IDs and it's a bit of mess right now. Clean it up such that, * board_id_* now live in a separate enum board_ids and numbers are assigned automatically. * Board IDs assigned to features are separated from the ones assigned to specific implementations and both are ordered alphabetically. * For NV MCPs, define per-generation alias board_ids and assign matching aliases in the pci id table. This makes mcp_linux, 67-73 use board_ahci_mcp65 instead of board_ahci_yesncq. Both are identical in content. * Kill now unused board_ahci_nopmp and board_ahci_yesncq. This patch doesn't cause any functional change but will make future changes to board_ids and quirks much less painful. Signed-off-by: Tejun Heo <tj@kernel.org> Cc: Peer Chen <pchen@nvidia.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-03-29 09:32:39 +08:00
};
enum board_ids {
/* board IDs by feature in alphabetical order */
board_ahci,
ahci: add 43-bit DMA address quirk for ASMedia ASM1061 controllers With one of the on-board ASM1061 AHCI controllers (1b21:0612) on an ASUSTeK Pro WS WRX80E-SAGE SE WIFI mainboard, a controller hang was observed that was immediately preceded by the following kernel messages: ahci 0000:28:00.0: Using 64-bit DMA addresses ahci 0000:28:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0035 address=0x7fffff00000 flags=0x0000] ahci 0000:28:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0035 address=0x7fffff00300 flags=0x0000] ahci 0000:28:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0035 address=0x7fffff00380 flags=0x0000] ahci 0000:28:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0035 address=0x7fffff00400 flags=0x0000] ahci 0000:28:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0035 address=0x7fffff00680 flags=0x0000] ahci 0000:28:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0035 address=0x7fffff00700 flags=0x0000] The first message is produced by code in drivers/iommu/dma-iommu.c which is accompanied by the following comment that seems to apply: /* * Try to use all the 32-bit PCI addresses first. The original SAC vs. * DAC reasoning loses relevance with PCIe, but enough hardware and * firmware bugs are still lurking out there that it's safest not to * venture into the 64-bit space until necessary. * * If your device goes wrong after seeing the notice then likely either * its driver is not setting DMA masks accurately, the hardware has * some inherent bug in handling >32-bit addresses, or not all the * expected address bits are wired up between the device and the IOMMU. */ Asking the ASM1061 on a discrete PCIe card to DMA from I/O virtual address 0xffffffff00000000 produces the following I/O page faults: vfio-pci 0000:07:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0021 address=0x7ff00000000 flags=0x0010] vfio-pci 0000:07:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0021 address=0x7ff00000500 flags=0x0010] Note that the upper 21 bits of the logged DMA address are zero. (When asking a different PCIe device in the same PCIe slot to DMA to the same I/O virtual address, we do see all the upper 32 bits of the DMA address as 1, so this is not an issue with the chipset or IOMMU configuration on the test system.) Also, hacking libahci to always set the upper 21 bits of all DMA addresses to 1 produces no discernible effect on the behavior of the ASM1061, and mkfs/mount/scrub/etc work as without this hack. This all strongly suggests that the ASM1061 has a 43 bit DMA address limit, and this commit therefore adds a quirk to deal with this limit. This issue probably applies to (some of) the other supported ASMedia parts as well, but we limit it to the PCI IDs known to refer to ASM1061 parts, as that's the only part we know for sure to be affected by this issue at this point. Link: https://lore.kernel.org/linux-ide/ZaZ2PIpEId-rl6jv@wantstofly.org/ Signed-off-by: Lennert Buytenhek <kernel@wantstofly.org> [cassel: drop date from error messages in commit log] Signed-off-by: Niklas Cassel <cassel@kernel.org>
2024-01-25 23:04:01 +08:00
board_ahci_43bit_dma,
ahci: clean up board IDs ahci over time has grown a number of board IDs and it's a bit of mess right now. Clean it up such that, * board_id_* now live in a separate enum board_ids and numbers are assigned automatically. * Board IDs assigned to features are separated from the ones assigned to specific implementations and both are ordered alphabetically. * For NV MCPs, define per-generation alias board_ids and assign matching aliases in the pci id table. This makes mcp_linux, 67-73 use board_ahci_mcp65 instead of board_ahci_yesncq. Both are identical in content. * Kill now unused board_ahci_nopmp and board_ahci_yesncq. This patch doesn't cause any functional change but will make future changes to board_ids and quirks much less painful. Signed-off-by: Tejun Heo <tj@kernel.org> Cc: Peer Chen <pchen@nvidia.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-03-29 09:32:39 +08:00
board_ahci_ign_iferr,
ata: ahci: Rename board_ahci_mobile This board definition was originally created for mobile devices to designate default link power managmeent policy to influence runtime power consumption. As this is interesting for more than just mobile designs, rename the board to `board_ahci_low_power` to make it clear it is about default policy. Reviewed-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Paul Menzel <pmenzel@molgen.mpg.de> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
2022-02-26 01:23:17 +08:00
board_ahci_low_power,
ata: ahci: Add support for AMD A85 FCH (Hudson D4) Add support for the AMD A85 FCH (Hudson D4) AHCI adapter. Since this adapter does not require the default 200 ms debounce delay in sata_link_resume(), create a new board board_ahci_no_debounce_delay with the link flag ATA_LFLAG_NO_DEBOUNCE_DELAY, and, for now, configure the AMD A85 FCH (Hudson D4) to use it. On the ASUS F2A85-M PRO it reduces the Linux kernel boot time by the expected 200 ms from 787 ms to 585 ms. Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Cc: Tejun Heo <tj@kernel.org> Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
2022-01-05 23:36:18 +08:00
board_ahci_no_debounce_delay,
ahci: disable MSI instead of NCQ on Samsung pci-e SSDs on macbooks Samsung pci-e SSDs on macbooks failed miserably on NCQ commands, so 67809f85d31e ("ahci: disable NCQ on Samsung pci-e SSDs on macbooks") disabled NCQ on them. It turns out that NCQ is fine as long as MSI is not used, so let's turn off MSI and leave NCQ on. Signed-off-by: Tejun Heo <tj@kernel.org> Link: https://bugzilla.kernel.org/show_bug.cgi?id=60731 Tested-by: <dorin@i51.org> Tested-by: Imre Kaloz <kaloz@openwrt.org> Cc: stable@vger.kernel.org Fixes: 67809f85d31e ("ahci: disable NCQ on Samsung pci-e SSDs on macbooks")
2014-10-27 22:22:56 +08:00
board_ahci_nomsi,
ahci: disable NCQ on Samsung pci-e SSDs on macbooks Samsung's pci-e SSDs with device ID 0x1600 which are found on some macbooks time out on NCQ commands. Blacklist NCQ on the device so that the affected machines can at least boot. Original-patch-by: Levente Kurusa <levex@linux.com> Signed-off-by: Tejun Heo <tj@kernel.org> Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=60731 Cc: stable@vger.kernel.org
2014-02-18 23:22:17 +08:00
board_ahci_noncq,
ahci: clean up board IDs ahci over time has grown a number of board IDs and it's a bit of mess right now. Clean it up such that, * board_id_* now live in a separate enum board_ids and numbers are assigned automatically. * Board IDs assigned to features are separated from the ones assigned to specific implementations and both are ordered alphabetically. * For NV MCPs, define per-generation alias board_ids and assign matching aliases in the pci id table. This makes mcp_linux, 67-73 use board_ahci_mcp65 instead of board_ahci_yesncq. Both are identical in content. * Kill now unused board_ahci_nopmp and board_ahci_yesncq. This patch doesn't cause any functional change but will make future changes to board_ids and quirks much less painful. Signed-off-by: Tejun Heo <tj@kernel.org> Cc: Peer Chen <pchen@nvidia.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-03-29 09:32:39 +08:00
board_ahci_nosntf,
ahci: add HFLAG_YES_FBS and apply it to 88SE9128 88SE9128 can do FBS and sets it in HOST_CAP but forgets to set FBSCP in PORT_CMD. Implement AHCI_HFLAG_YES_FBS and apply it to 88SE9128. Signed-off-by: Tejun Heo <tj@kernel.org> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-07-24 22:53:48 +08:00
board_ahci_yes_fbs,
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 06:20:36 +08:00
ahci: clean up board IDs ahci over time has grown a number of board IDs and it's a bit of mess right now. Clean it up such that, * board_id_* now live in a separate enum board_ids and numbers are assigned automatically. * Board IDs assigned to features are separated from the ones assigned to specific implementations and both are ordered alphabetically. * For NV MCPs, define per-generation alias board_ids and assign matching aliases in the pci id table. This makes mcp_linux, 67-73 use board_ahci_mcp65 instead of board_ahci_yesncq. Both are identical in content. * Kill now unused board_ahci_nopmp and board_ahci_yesncq. This patch doesn't cause any functional change but will make future changes to board_ids and quirks much less painful. Signed-off-by: Tejun Heo <tj@kernel.org> Cc: Peer Chen <pchen@nvidia.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-03-29 09:32:39 +08:00
/* board IDs for specific chipsets in alphabetical order */
ahci: Add support for Amazon's Annapurna Labs SATA controller This patch adds basic support for Amazon's Annapurna Labs SATA controller. Signed-off-by: Hanna Hawa <hhhawa@amazon.com> Signed-off-by: Jens Axboe <axboe@kernel.dk>
2019-10-17 22:46:53 +08:00
board_ahci_al,
ahci: avoton port-disable reset-quirk Avoton AHCI occasionally sees drive probe timeouts at driver load time. When this happens SCR_STATUS indicates device detected, but no D2H FIS reception. Reset the internal link state machines by bouncing port-enable in the PCS register when this occurs. Cc: <stable@vger.kernel.org> Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2015-05-09 03:23:55 +08:00
board_ahci_avn,
ahci: clean up board IDs ahci over time has grown a number of board IDs and it's a bit of mess right now. Clean it up such that, * board_id_* now live in a separate enum board_ids and numbers are assigned automatically. * Board IDs assigned to features are separated from the ones assigned to specific implementations and both are ordered alphabetically. * For NV MCPs, define per-generation alias board_ids and assign matching aliases in the pci id table. This makes mcp_linux, 67-73 use board_ahci_mcp65 instead of board_ahci_yesncq. Both are identical in content. * Kill now unused board_ahci_nopmp and board_ahci_yesncq. This patch doesn't cause any functional change but will make future changes to board_ids and quirks much less painful. Signed-off-by: Tejun Heo <tj@kernel.org> Cc: Peer Chen <pchen@nvidia.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-03-29 09:32:39 +08:00
board_ahci_mcp65,
ahci: implement AHCI_HFLAG_NO_FPDMA_AA and update NV quirks It turns out different generations of MCPs have differing quirks. * MCP 65-73 : FPDMA AA broken, lies about PMP support, forgets to report NCQ * MCP 77-79 : FPDMA AA broken, lies about PMP support * MCP 89 : FPDMA AA broken Instead of turngin off FPDMA AA on all NVIDIAs, implement HFLAG_NO_FPDMA_AA, define additional board IDs and apply necessary quirks. This fixes bko#15481 and the list of quirks is verified by Peer Chen. http://bugzilla.kernel.org/show_bug.cgi?id=15481 Signed-off-by: Tejun Heo <tj@kernel.org> Cc: Peer Chen <pchen@nvidia.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-03-30 09:28:32 +08:00
board_ahci_mcp77,
board_ahci_mcp89,
ahci: clean up board IDs ahci over time has grown a number of board IDs and it's a bit of mess right now. Clean it up such that, * board_id_* now live in a separate enum board_ids and numbers are assigned automatically. * Board IDs assigned to features are separated from the ones assigned to specific implementations and both are ordered alphabetically. * For NV MCPs, define per-generation alias board_ids and assign matching aliases in the pci id table. This makes mcp_linux, 67-73 use board_ahci_mcp65 instead of board_ahci_yesncq. Both are identical in content. * Kill now unused board_ahci_nopmp and board_ahci_yesncq. This patch doesn't cause any functional change but will make future changes to board_ids and quirks much less painful. Signed-off-by: Tejun Heo <tj@kernel.org> Cc: Peer Chen <pchen@nvidia.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-03-29 09:32:39 +08:00
board_ahci_mv,
board_ahci_sb600,
board_ahci_sb700, /* for SB700 and SB800 */
board_ahci_vt8251,
libata/ahci: Drop PCS quirk for Denverton and beyond The Linux ahci driver has historically implemented a configuration fixup for platforms / platform-firmware that fails to enable the ports prior to OS hand-off at boot. The fixup was originally implemented way back before ahci moved from drivers/scsi/ to drivers/ata/, and was updated in 2007 via commit 49f290903935 "ahci: update PCS programming". The quirk sets a port-enable bitmap in the PCS register at offset 0x92. This quirk could be applied generically up until the arrival of the Denverton (DNV) platform. The DNV AHCI controller architecture supports more than 6 ports and along with that the PCS register location and format were updated to allow for more possible ports in the bitmap. DNV AHCI expands the register to 32-bits and moves it to offset 0x94. As it stands there are no known problem reports with existing Linux trying to set bits at offset 0x92 which indicates that the quirk is not applicable. Likely it is not applicable on a wider range of platforms, but it is difficult to discern which platforms if any still depend on the quirk. Rather than try to fix the PCS quirk to consider the DNV register layout instead require explicit opt-in. The assumption is that the OS driver need not touch this register, and platforms can be added with a new boad_ahci_pcs7 board-id when / if problematic platforms are found in the future. The logic in ahci_intel_pcs_quirk() looks for all Intel AHCI instances with "legacy" board-ids and otherwise skips the quirk if the board was matched by class-code. Reported-by: Stephen Douthit <stephend@silicom-usa.com> Cc: Christoph Hellwig <hch@infradead.org> Reviewed-by: Stephen Douthit <stephend@silicom-usa.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Jens Axboe <axboe@kernel.dk>
2019-08-30 07:30:34 +08:00
/*
* board IDs for Intel chipsets that support more than 6 ports
* *and* end up needing the PCS quirk.
*/
board_ahci_pcs7,
ahci: clean up board IDs ahci over time has grown a number of board IDs and it's a bit of mess right now. Clean it up such that, * board_id_* now live in a separate enum board_ids and numbers are assigned automatically. * Board IDs assigned to features are separated from the ones assigned to specific implementations and both are ordered alphabetically. * For NV MCPs, define per-generation alias board_ids and assign matching aliases in the pci id table. This makes mcp_linux, 67-73 use board_ahci_mcp65 instead of board_ahci_yesncq. Both are identical in content. * Kill now unused board_ahci_nopmp and board_ahci_yesncq. This patch doesn't cause any functional change but will make future changes to board_ids and quirks much less painful. Signed-off-by: Tejun Heo <tj@kernel.org> Cc: Peer Chen <pchen@nvidia.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-03-29 09:32:39 +08:00
/* aliases */
board_ahci_mcp_linux = board_ahci_mcp65,
board_ahci_mcp67 = board_ahci_mcp65,
board_ahci_mcp73 = board_ahci_mcp65,
ahci: implement AHCI_HFLAG_NO_FPDMA_AA and update NV quirks It turns out different generations of MCPs have differing quirks. * MCP 65-73 : FPDMA AA broken, lies about PMP support, forgets to report NCQ * MCP 77-79 : FPDMA AA broken, lies about PMP support * MCP 89 : FPDMA AA broken Instead of turngin off FPDMA AA on all NVIDIAs, implement HFLAG_NO_FPDMA_AA, define additional board IDs and apply necessary quirks. This fixes bko#15481 and the list of quirks is verified by Peer Chen. http://bugzilla.kernel.org/show_bug.cgi?id=15481 Signed-off-by: Tejun Heo <tj@kernel.org> Cc: Peer Chen <pchen@nvidia.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-03-30 09:28:32 +08:00
board_ahci_mcp79 = board_ahci_mcp77,
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 06:20:36 +08:00
};
[libata] checkpatch-inspired cleanups Tackle the relatively sane complaints of checkpatch --file. The vast majority is indentation and whitespace changes, the rest are * #include fixes * printk KERN_xxx prefix addition * BSS/initializer cleanups Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2007-10-19 18:42:56 +08:00
static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
ahci: Add runtime PM support for the host controller This patch adds runtime PM support for the AHCI host controller driver so that the host controller is powered down when all SATA ports are runtime suspended. Powering down the AHCI host controller can reduce power consumption and possibly allow the CPU to enter lower power idle states (S0ix) during runtime. Runtime PM is blocked by default and needs to be unblocked from userspace as needed (via power/* sysfs nodes). Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2016-02-18 16:54:17 +08:00
static void ahci_remove_one(struct pci_dev *dev);
ata: ahci: Add shutdown to freeze hardware resources of ahci device_shutdown() called from reboot or power_shutdown expect all devices to be shutdown. Same is true for even ahci pci driver. As no ahci shutdown function is implemented, the ata subsystem always remains alive with DMA & interrupt support. File system related calls should not be honored after device_shutdown(). So defining ahci pci driver shutdown to freeze hardware (mask interrupt, stop DMA engine and free DMA resources). Signed-off-by: Prabhakar Kushwaha <pkushwaha@marvell.com> Signed-off-by: Jens Axboe <axboe@kernel.dk>
2020-01-25 11:37:29 +08:00
static void ahci_shutdown_one(struct pci_dev *dev);
ata: ahci: Fix PCS quirk application for suspend Since kernel 5.3.4 my laptop (ICH8M controller) does not see Kingston SV300S37A60G SSD disk connected into a SATA connector on wake from suspend. The problem was introduced in c312ef176399 ("libata/ahci: Drop PCS quirk for Denverton and beyond"): the quirk is not applied on wake from suspend as it originally was. It is worth to mention the commit contained another bug: the quirk is not applied at all to controllers which require it. The fix commit 09d6ac8dc51a ("libata/ahci: Fix PCS quirk application") landed in 5.3.8. So testing my patch anywhere between commits c312ef176399 and 09d6ac8dc51a is pointless. Not all disks trigger the problem. For example nothing bad happens with Western Digital WD5000LPCX HDD. Test hardware: - Acer 5920G with ICH8M SATA controller - sda: some SATA HDD connnected into the DVD drive IDE port with a SATA-IDE caddy. It is a boot disk - sdb: Kingston SV300S37A60G SSD connected into the only SATA port Sample "dmesg --notime | grep -E '^(sd |ata)'" output on wake: sd 0:0:0:0: [sda] Starting disk sd 2:0:0:0: [sdb] Starting disk ata4: SATA link down (SStatus 4 SControl 300) ata3: SATA link down (SStatus 4 SControl 300) ata1.00: ACPI cmd ef/03:0c:00:00:00:a0 (SET FEATURES) filtered out ata1.00: ACPI cmd ef/03:42:00:00:00:a0 (SET FEATURES) filtered out ata1: FORCE: cable set to 80c ata5: SATA link down (SStatus 0 SControl 300) ata3: SATA link down (SStatus 4 SControl 300) ata3: SATA link down (SStatus 4 SControl 300) ata3.00: disabled sd 2:0:0:0: rejecting I/O to offline device ata3.00: detaching (SCSI 2:0:0:0) sd 2:0:0:0: [sdb] Start/Stop Unit failed: Result: hostbyte=DID_NO_CONNECT driverbyte=DRIVER_OK sd 2:0:0:0: [sdb] Synchronizing SCSI cache sd 2:0:0:0: [sdb] Synchronize Cache(10) failed: Result: hostbyte=DID_BAD_TARGET driverbyte=DRIVER_OK sd 2:0:0:0: [sdb] Stopping disk sd 2:0:0:0: [sdb] Start/Stop Unit failed: Result: hostbyte=DID_BAD_TARGET driverbyte=DRIVER_OK Commit c312ef176399 dropped ahci_pci_reset_controller() which internally calls ahci_reset_controller() and applies the PCS quirk if needed after that. It was called each time a reset was required instead of just ahci_reset_controller(). This patch puts the function back in place. Fixes: c312ef176399 ("libata/ahci: Drop PCS quirk for Denverton and beyond") Signed-off-by: Adam Vodopjan <grozzly@protonmail.com> Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
2022-12-09 17:26:34 +08:00
static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv);
libata: make reset related methods proper port operations Currently reset methods are not specified directly in the ata_port_operations table. If a LLD wants to use custom reset methods, it should construct and use a error_handler which uses those reset methods. It's done this way for two reasons. First, the ops table already contained too many methods and adding four more of them would noticeably increase the amount of necessary boilerplate code all over low level drivers. Second, as ->error_handler uses those reset methods, it can get confusing. ie. By overriding ->error_handler, those reset ops can be made useless making layering a bit hazy. Now that ops table uses inheritance, the first problem doesn't exist anymore. The second isn't completely solved but is relieved by providing default values - most drivers can just override what it has implemented and don't have to concern itself about higher level callbacks. In fact, there currently is no driver which actually modifies error handling behavior. Drivers which override ->error_handler just wraps the standard error handler only to prepare the controller for EH. I don't think making ops layering strict has any noticeable benefit. This patch makes ->prereset, ->softreset, ->hardreset, ->postreset and their PMP counterparts propoer ops. Default ops are provided in the base ops tables and drivers are converted to override individual reset methods instead of creating custom error_handler. * ata_std_error_handler() doesn't use sata_std_hardreset() if SCRs aren't accessible. sata_promise doesn't need to use separate error_handlers for PATA and SATA anymore. * softreset is broken for sata_inic162x and sata_sx4. As libata now always prefers hardreset, this doesn't really matter but the ops are forced to NULL using ATA_OP_NULL for documentation purpose. * pata_hpt374 needs to use different prereset for the first and second PCI functions. This used to be done by branching from hpt374_error_handler(). The proper way to do this is to use separate ops and port_info tables for each function. Converted. Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-03-25 11:22:50 +08:00
static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
unsigned long deadline);
ahci: avoton port-disable reset-quirk Avoton AHCI occasionally sees drive probe timeouts at driver load time. When this happens SCR_STATUS indicates device detected, but no D2H FIS reception. Reset the internal link state machines by bouncing port-enable in the PCS register when this occurs. Cc: <stable@vger.kernel.org> Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2015-05-09 03:23:55 +08:00
static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
unsigned long deadline);
ahci: mcp89: enter AHCI mode under Apple BIOS emulation Apple's BIOS emulation forcibly disables MCP89 AHCI, eg. on Macbook7,1. We can re-enable it, replacing the previous workaround of using ata_generic. tj: whitespace adjustments, dropped inline from is_mcp89_apple() Signed-off-by: James Laird <jhl@mafipulation.org> Signed-off-by: Tejun Heo <tj@kernel.org>
2013-11-19 08:06:38 +08:00
static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
static bool is_mcp89_apple(struct pci_dev *pdev);
libata: make reset related methods proper port operations Currently reset methods are not specified directly in the ata_port_operations table. If a LLD wants to use custom reset methods, it should construct and use a error_handler which uses those reset methods. It's done this way for two reasons. First, the ops table already contained too many methods and adding four more of them would noticeably increase the amount of necessary boilerplate code all over low level drivers. Second, as ->error_handler uses those reset methods, it can get confusing. ie. By overriding ->error_handler, those reset ops can be made useless making layering a bit hazy. Now that ops table uses inheritance, the first problem doesn't exist anymore. The second isn't completely solved but is relieved by providing default values - most drivers can just override what it has implemented and don't have to concern itself about higher level callbacks. In fact, there currently is no driver which actually modifies error handling behavior. Drivers which override ->error_handler just wraps the standard error handler only to prepare the controller for EH. I don't think making ops layering strict has any noticeable benefit. This patch makes ->prereset, ->softreset, ->hardreset, ->postreset and their PMP counterparts propoer ops. Default ops are provided in the base ops tables and drivers are converted to override individual reset methods instead of creating custom error_handler. * ata_std_error_handler() doesn't use sata_std_hardreset() if SCRs aren't accessible. sata_promise doesn't need to use separate error_handlers for PATA and SATA anymore. * softreset is broken for sata_inic162x and sata_sx4. As libata now always prefers hardreset, this doesn't really matter but the ops are forced to NULL using ATA_OP_NULL for documentation purpose. * pata_hpt374 needs to use different prereset for the first and second PCI functions. This used to be done by branching from hpt374_error_handler(). The proper way to do this is to use separate ops and port_info tables for each function. Converted. Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-03-25 11:22:50 +08:00
static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
unsigned long deadline);
ahci: Add runtime PM support for the host controller This patch adds runtime PM support for the AHCI host controller driver so that the host controller is powered down when all SATA ports are runtime suspended. Powering down the AHCI host controller can reduce power consumption and possibly allow the CPU to enter lower power idle states (S0ix) during runtime. Runtime PM is blocked by default and needs to be unblocked from userspace as needed (via power/* sysfs nodes). Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2016-02-18 16:54:17 +08:00
#ifdef CONFIG_PM
static int ahci_pci_device_runtime_suspend(struct device *dev);
static int ahci_pci_device_runtime_resume(struct device *dev);
ahci: Convert driver to use modern PM hooks In order to add support for runtime PM to the ahci driver we first need to convert the driver to use modern non-legacy system suspend hooks. There should be no functional changes. tj: Updated .driver.pm init for older compilers as suggested by Andy and Chrsitoph. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Cc: Andy Shevchenko <andy.shevchenko@gmail.com> Cc: Christoph Hellwig <hch@infradead.org> Signed-off-by: Tejun Heo <tj@kernel.org>
2016-02-18 16:54:15 +08:00
#ifdef CONFIG_PM_SLEEP
static int ahci_pci_device_suspend(struct device *dev);
static int ahci_pci_device_resume(struct device *dev);
libata: add missing CONFIG_PM in LLDs Add missing #ifdef CONFIG_PM conditionals around all PM related parts in libata LLDs. Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-03-02 16:31:26 +08:00
#endif
ahci: Add runtime PM support for the host controller This patch adds runtime PM support for the AHCI host controller driver so that the host controller is powered down when all SATA ports are runtime suspended. Powering down the AHCI host controller can reduce power consumption and possibly allow the CPU to enter lower power idle states (S0ix) during runtime. Runtime PM is blocked by default and needs to be unblocked from userspace as needed (via power/* sysfs nodes). Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2016-02-18 16:54:17 +08:00
#endif /* CONFIG_PM */
[PATCH] ahci: update ahci-vt8251 reset sequence ahci-vt8251 * requires hardreset after PHY status change * doesn't clear BSY on signature FIS after hardreset * needs SError cleared for the port to operate after hardreset This patch implements ahci_vt8251_hardreset() and sets ATA_FLAG_HRST_TO_RESUME to handle the above behaviors. This fixes EH including hotplug on vt8251. Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2006-11-01 17:00:24 +08:00
scsi: ata: Declare SCSI host templates const Make it explicit that ATA host templates are not modified. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Damien Le Moal <damien.lemoal@opensource.wdc.com> Reviewed-by: Serge Semin <fancer.lancer@gmail.com> (for DWC AHCI SATA) Reviewed-by: John Garry <john.g.garry@oracle.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> (for Tegra) Cc: Christoph Hellwig <hch@lst.de> Cc: Ming Lei <ming.lei@redhat.com> Cc: Hannes Reinecke <hare@suse.de> Cc: John Garry <john.g.garry@oracle.com> Cc: Mike Christie <michael.christie@oracle.com> Signed-off-by: Bart Van Assche <bvanassche@acm.org> Link: https://lore.kernel.org/r/20230322195515.1267197-5-bvanassche@acm.org Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2023-03-23 03:53:59 +08:00
static const struct scsi_host_template ahci_sht = {
ahci: fix module refcount breakage introduced by libahci split libata depends on scsi_host_template for module reference counting and sht's should be owned by each low level driver. During libahci split, the sht was left with libahci.ko leaving the actual low level drivers not reference counted. This made ahci and ahci_platform always unloadable even while they're being actively used. Fix it by defining AHCI_SHT() macro in ahci.h and defining a sht for each low level ahci driver. stable: only applicable to 2.6.35. Signed-off-by: Tejun Heo <tj@kernel.org> Reported-by: Pedro Francisco <pedrogfrancisco@gmail.com> Tested-by: Michael Tokarev <mjt@tls.msk.ru> Cc: stable@kernel.org Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-09-21 15:25:48 +08:00
AHCI_SHT("ahci"),
};
libata: implement and use ops inheritance libata lets low level drivers build ata_port_operations table and register it with libata core layer. This allows low level drivers high level of flexibility but also burdens them with lots of boilerplate entries. This becomes worse for drivers which support related similar controllers which differ slightly. They share most of the operations except for a few. However, the driver still needs to list all operations for each variant. This results in large number of duplicate entries, which is not only inefficient but also error-prone as it becomes very difficult to tell what the actual differences are. This duplicate boilerplates all over the low level drivers also make updating the core layer exteremely difficult and error-prone. When compounded with multi-branched development model, it ends up accumulating inconsistencies over time. Some of those inconsistencies cause immediate problems and fixed. Others just remain there dormant making maintenance increasingly difficult. To rectify the problem, this patch implements ata_port_operations inheritance. To allow LLDs to easily re-use their own ops tables overriding only specific methods, this patch implements poor man's class inheritance. An ops table has ->inherits field which can be set to any ops table as long as it doesn't create a loop. When the host is started, the inheritance chain is followed and any operation which isn't specified is taken from the nearest ancestor which has it specified. This operation is called finalization and done only once per an ops table and the LLD doesn't have to do anything special about it other than making the ops table non-const such that libata can update it. libata provides four base ops tables lower drivers can inherit from - base, sata, pmp, sff and bmdma. To avoid overriding these ops accidentaly, these ops are declared const and LLDs should always inherit these instead of using them directly. After finalization, all the ops table are identical before and after the patch except for setting .irq_handler to ata_interrupt in drivers which didn't use to. The .irq_handler doesn't have any actual effect and the field will soon be removed by later patch. * sata_sx4 is still using old style EH and currently doesn't take advantage of ops inheritance. Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-03-25 11:22:49 +08:00
static struct ata_port_operations ahci_vt8251_ops = {
.inherits = &ahci_ops,
libata: make reset related methods proper port operations Currently reset methods are not specified directly in the ata_port_operations table. If a LLD wants to use custom reset methods, it should construct and use a error_handler which uses those reset methods. It's done this way for two reasons. First, the ops table already contained too many methods and adding four more of them would noticeably increase the amount of necessary boilerplate code all over low level drivers. Second, as ->error_handler uses those reset methods, it can get confusing. ie. By overriding ->error_handler, those reset ops can be made useless making layering a bit hazy. Now that ops table uses inheritance, the first problem doesn't exist anymore. The second isn't completely solved but is relieved by providing default values - most drivers can just override what it has implemented and don't have to concern itself about higher level callbacks. In fact, there currently is no driver which actually modifies error handling behavior. Drivers which override ->error_handler just wraps the standard error handler only to prepare the controller for EH. I don't think making ops layering strict has any noticeable benefit. This patch makes ->prereset, ->softreset, ->hardreset, ->postreset and their PMP counterparts propoer ops. Default ops are provided in the base ops tables and drivers are converted to override individual reset methods instead of creating custom error_handler. * ata_std_error_handler() doesn't use sata_std_hardreset() if SCRs aren't accessible. sata_promise doesn't need to use separate error_handlers for PATA and SATA anymore. * softreset is broken for sata_inic162x and sata_sx4. As libata now always prefers hardreset, this doesn't really matter but the ops are forced to NULL using ATA_OP_NULL for documentation purpose. * pata_hpt374 needs to use different prereset for the first and second PCI functions. This used to be done by branching from hpt374_error_handler(). The proper way to do this is to use separate ops and port_info tables for each function. Converted. Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-03-25 11:22:50 +08:00
.hardreset = ahci_vt8251_hardreset,
libata: implement and use ops inheritance libata lets low level drivers build ata_port_operations table and register it with libata core layer. This allows low level drivers high level of flexibility but also burdens them with lots of boilerplate entries. This becomes worse for drivers which support related similar controllers which differ slightly. They share most of the operations except for a few. However, the driver still needs to list all operations for each variant. This results in large number of duplicate entries, which is not only inefficient but also error-prone as it becomes very difficult to tell what the actual differences are. This duplicate boilerplates all over the low level drivers also make updating the core layer exteremely difficult and error-prone. When compounded with multi-branched development model, it ends up accumulating inconsistencies over time. Some of those inconsistencies cause immediate problems and fixed. Others just remain there dormant making maintenance increasingly difficult. To rectify the problem, this patch implements ata_port_operations inheritance. To allow LLDs to easily re-use their own ops tables overriding only specific methods, this patch implements poor man's class inheritance. An ops table has ->inherits field which can be set to any ops table as long as it doesn't create a loop. When the host is started, the inheritance chain is followed and any operation which isn't specified is taken from the nearest ancestor which has it specified. This operation is called finalization and done only once per an ops table and the LLD doesn't have to do anything special about it other than making the ops table non-const such that libata can update it. libata provides four base ops tables lower drivers can inherit from - base, sata, pmp, sff and bmdma. To avoid overriding these ops accidentaly, these ops are declared const and LLDs should always inherit these instead of using them directly. After finalization, all the ops table are identical before and after the patch except for setting .irq_handler to ata_interrupt in drivers which didn't use to. The .irq_handler doesn't have any actual effect and the field will soon be removed by later patch. * sata_sx4 is still using old style EH and currently doesn't take advantage of ops inheritance. Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-03-25 11:22:49 +08:00
};
ahci: ahci: implement workaround for ASUS P5W-DH Deluxe ahci_broken_hardreset(), take #2 P5W-DH Deluxe has ICH9 which doesn't have PMP support but SIMG 4726 hardwired to the second port of AHCI controller at PCI device 1f.2. The 4726 doesn't work as PMP but as a storage processor which can do hardware RAID on downstream ports. When no device is attached to the downstream port of the 4726, pseudo ATA device for configuration appears. Unfortunately, ATA emulation on the device is very lousy and causes long hang during boot. This patch implements workaround for the board. If the mainboard is P5W-DH Deluxe (matched using DMI), only hardreset is used on the second port of AHCI controller @ 1f.2 and the hardreset doesn't depend on receiving the first FIS and just proceed to IDENTIFY. This workaround fixes bugzilla #8923. http://bugzilla.kernel.org/show_bug.cgi?id=8923 Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-10-25 13:59:16 +08:00
libata: implement and use ops inheritance libata lets low level drivers build ata_port_operations table and register it with libata core layer. This allows low level drivers high level of flexibility but also burdens them with lots of boilerplate entries. This becomes worse for drivers which support related similar controllers which differ slightly. They share most of the operations except for a few. However, the driver still needs to list all operations for each variant. This results in large number of duplicate entries, which is not only inefficient but also error-prone as it becomes very difficult to tell what the actual differences are. This duplicate boilerplates all over the low level drivers also make updating the core layer exteremely difficult and error-prone. When compounded with multi-branched development model, it ends up accumulating inconsistencies over time. Some of those inconsistencies cause immediate problems and fixed. Others just remain there dormant making maintenance increasingly difficult. To rectify the problem, this patch implements ata_port_operations inheritance. To allow LLDs to easily re-use their own ops tables overriding only specific methods, this patch implements poor man's class inheritance. An ops table has ->inherits field which can be set to any ops table as long as it doesn't create a loop. When the host is started, the inheritance chain is followed and any operation which isn't specified is taken from the nearest ancestor which has it specified. This operation is called finalization and done only once per an ops table and the LLD doesn't have to do anything special about it other than making the ops table non-const such that libata can update it. libata provides four base ops tables lower drivers can inherit from - base, sata, pmp, sff and bmdma. To avoid overriding these ops accidentaly, these ops are declared const and LLDs should always inherit these instead of using them directly. After finalization, all the ops table are identical before and after the patch except for setting .irq_handler to ata_interrupt in drivers which didn't use to. The .irq_handler doesn't have any actual effect and the field will soon be removed by later patch. * sata_sx4 is still using old style EH and currently doesn't take advantage of ops inheritance. Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-03-25 11:22:49 +08:00
static struct ata_port_operations ahci_p5wdh_ops = {
.inherits = &ahci_ops,
libata: make reset related methods proper port operations Currently reset methods are not specified directly in the ata_port_operations table. If a LLD wants to use custom reset methods, it should construct and use a error_handler which uses those reset methods. It's done this way for two reasons. First, the ops table already contained too many methods and adding four more of them would noticeably increase the amount of necessary boilerplate code all over low level drivers. Second, as ->error_handler uses those reset methods, it can get confusing. ie. By overriding ->error_handler, those reset ops can be made useless making layering a bit hazy. Now that ops table uses inheritance, the first problem doesn't exist anymore. The second isn't completely solved but is relieved by providing default values - most drivers can just override what it has implemented and don't have to concern itself about higher level callbacks. In fact, there currently is no driver which actually modifies error handling behavior. Drivers which override ->error_handler just wraps the standard error handler only to prepare the controller for EH. I don't think making ops layering strict has any noticeable benefit. This patch makes ->prereset, ->softreset, ->hardreset, ->postreset and their PMP counterparts propoer ops. Default ops are provided in the base ops tables and drivers are converted to override individual reset methods instead of creating custom error_handler. * ata_std_error_handler() doesn't use sata_std_hardreset() if SCRs aren't accessible. sata_promise doesn't need to use separate error_handlers for PATA and SATA anymore. * softreset is broken for sata_inic162x and sata_sx4. As libata now always prefers hardreset, this doesn't really matter but the ops are forced to NULL using ATA_OP_NULL for documentation purpose. * pata_hpt374 needs to use different prereset for the first and second PCI functions. This used to be done by branching from hpt374_error_handler(). The proper way to do this is to use separate ops and port_info tables for each function. Converted. Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-03-25 11:22:50 +08:00
.hardreset = ahci_p5wdh_hardreset,
ahci: ahci: implement workaround for ASUS P5W-DH Deluxe ahci_broken_hardreset(), take #2 P5W-DH Deluxe has ICH9 which doesn't have PMP support but SIMG 4726 hardwired to the second port of AHCI controller at PCI device 1f.2. The 4726 doesn't work as PMP but as a storage processor which can do hardware RAID on downstream ports. When no device is attached to the downstream port of the 4726, pseudo ATA device for configuration appears. Unfortunately, ATA emulation on the device is very lousy and causes long hang during boot. This patch implements workaround for the board. If the mainboard is P5W-DH Deluxe (matched using DMI), only hardreset is used on the second port of AHCI controller @ 1f.2 and the hardreset doesn't depend on receiving the first FIS and just proceed to IDENTIFY. This workaround fixes bugzilla #8923. http://bugzilla.kernel.org/show_bug.cgi?id=8923 Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-10-25 13:59:16 +08:00
};
ahci: avoton port-disable reset-quirk Avoton AHCI occasionally sees drive probe timeouts at driver load time. When this happens SCR_STATUS indicates device detected, but no D2H FIS reception. Reset the internal link state machines by bouncing port-enable in the PCS register when this occurs. Cc: <stable@vger.kernel.org> Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2015-05-09 03:23:55 +08:00
static struct ata_port_operations ahci_avn_ops = {
.inherits = &ahci_ops,
.hardreset = ahci_avn_hardreset,
};
[PATCH] mark several libata datastructures const Hi, the patch below marks several libata (and libata-driver) structures const so that they end up in the .rodata segment and don't false-share cachelines with things that get dirtied often. Signed-off-by: Arjan van de Ven <arjan@infradead.org> Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
2005-11-28 17:06:23 +08:00
static const struct ata_port_info ahci_port_info[] = {
ahci: clean up board IDs ahci over time has grown a number of board IDs and it's a bit of mess right now. Clean it up such that, * board_id_* now live in a separate enum board_ids and numbers are assigned automatically. * Board IDs assigned to features are separated from the ones assigned to specific implementations and both are ordered alphabetically. * For NV MCPs, define per-generation alias board_ids and assign matching aliases in the pci id table. This makes mcp_linux, 67-73 use board_ahci_mcp65 instead of board_ahci_yesncq. Both are identical in content. * Kill now unused board_ahci_nopmp and board_ahci_yesncq. This patch doesn't cause any functional change but will make future changes to board_ids and quirks much less painful. Signed-off-by: Tejun Heo <tj@kernel.org> Cc: Peer Chen <pchen@nvidia.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-03-29 09:32:39 +08:00
/* by features */
ahci, trivial: fixed coding style issues related to braces Fixed coding style issues related to braces found by checkpatch.pl in drivers/ata/ahci.c Signed-off-by: Jeffrin Jose <ahiliation@yahoo.co.in> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2012-06-05 04:03:37 +08:00
[board_ahci] = {
ahci: consolidate common port flags Consolidate common port flags into AHCI_FLAG_COMMON. Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-04-23 01:41:05 +08:00
.flags = AHCI_FLAG_COMMON,
[libata] convert drivers to use ata.h mode mask defines No functional changes in this patch. Signed-off-by: Erik Inge Bolsø <knan-lkml@anduin.net> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-03-15 04:38:24 +08:00
.pio_mask = ATA_PIO4,
[libata] Clean up driver udma_mask initializers * Use ATA_UDMA* * Remove FIXME notations that once served to remind us to verify that these were indeed the correct UDMA masks. They are. Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-07-08 13:13:16 +08:00
.udma_mask = ATA_UDMA6,
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 06:20:36 +08:00
.port_ops = &ahci_ops,
},
ahci: add 43-bit DMA address quirk for ASMedia ASM1061 controllers With one of the on-board ASM1061 AHCI controllers (1b21:0612) on an ASUSTeK Pro WS WRX80E-SAGE SE WIFI mainboard, a controller hang was observed that was immediately preceded by the following kernel messages: ahci 0000:28:00.0: Using 64-bit DMA addresses ahci 0000:28:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0035 address=0x7fffff00000 flags=0x0000] ahci 0000:28:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0035 address=0x7fffff00300 flags=0x0000] ahci 0000:28:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0035 address=0x7fffff00380 flags=0x0000] ahci 0000:28:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0035 address=0x7fffff00400 flags=0x0000] ahci 0000:28:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0035 address=0x7fffff00680 flags=0x0000] ahci 0000:28:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0035 address=0x7fffff00700 flags=0x0000] The first message is produced by code in drivers/iommu/dma-iommu.c which is accompanied by the following comment that seems to apply: /* * Try to use all the 32-bit PCI addresses first. The original SAC vs. * DAC reasoning loses relevance with PCIe, but enough hardware and * firmware bugs are still lurking out there that it's safest not to * venture into the 64-bit space until necessary. * * If your device goes wrong after seeing the notice then likely either * its driver is not setting DMA masks accurately, the hardware has * some inherent bug in handling >32-bit addresses, or not all the * expected address bits are wired up between the device and the IOMMU. */ Asking the ASM1061 on a discrete PCIe card to DMA from I/O virtual address 0xffffffff00000000 produces the following I/O page faults: vfio-pci 0000:07:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0021 address=0x7ff00000000 flags=0x0010] vfio-pci 0000:07:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0021 address=0x7ff00000500 flags=0x0010] Note that the upper 21 bits of the logged DMA address are zero. (When asking a different PCIe device in the same PCIe slot to DMA to the same I/O virtual address, we do see all the upper 32 bits of the DMA address as 1, so this is not an issue with the chipset or IOMMU configuration on the test system.) Also, hacking libahci to always set the upper 21 bits of all DMA addresses to 1 produces no discernible effect on the behavior of the ASM1061, and mkfs/mount/scrub/etc work as without this hack. This all strongly suggests that the ASM1061 has a 43 bit DMA address limit, and this commit therefore adds a quirk to deal with this limit. This issue probably applies to (some of) the other supported ASMedia parts as well, but we limit it to the PCI IDs known to refer to ASM1061 parts, as that's the only part we know for sure to be affected by this issue at this point. Link: https://lore.kernel.org/linux-ide/ZaZ2PIpEId-rl6jv@wantstofly.org/ Signed-off-by: Lennert Buytenhek <kernel@wantstofly.org> [cassel: drop date from error messages in commit log] Signed-off-by: Niklas Cassel <cassel@kernel.org>
2024-01-25 23:04:01 +08:00
[board_ahci_43bit_dma] = {
AHCI_HFLAGS (AHCI_HFLAG_43BIT_ONLY),
.flags = AHCI_FLAG_COMMON,
.pio_mask = ATA_PIO4,
.udma_mask = ATA_UDMA6,
.port_ops = &ahci_ops,
},
ahci, trivial: fixed coding style issues related to braces Fixed coding style issues related to braces found by checkpatch.pl in drivers/ata/ahci.c Signed-off-by: Jeffrin Jose <ahiliation@yahoo.co.in> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2012-06-05 04:03:37 +08:00
[board_ahci_ign_iferr] = {
ahci: clean up board IDs ahci over time has grown a number of board IDs and it's a bit of mess right now. Clean it up such that, * board_id_* now live in a separate enum board_ids and numbers are assigned automatically. * Board IDs assigned to features are separated from the ones assigned to specific implementations and both are ordered alphabetically. * For NV MCPs, define per-generation alias board_ids and assign matching aliases in the pci id table. This makes mcp_linux, 67-73 use board_ahci_mcp65 instead of board_ahci_yesncq. Both are identical in content. * Kill now unused board_ahci_nopmp and board_ahci_yesncq. This patch doesn't cause any functional change but will make future changes to board_ids and quirks much less painful. Signed-off-by: Tejun Heo <tj@kernel.org> Cc: Peer Chen <pchen@nvidia.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-03-29 09:32:39 +08:00
AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
ahci: move host flags over to pi.private_data Private pi.flags area is full and we need more private flags. Move host private flags over to pi.private_data. During initialization, these flags are copied to hpriv->flags. Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-09-23 12:19:55 +08:00
.flags = AHCI_FLAG_COMMON,
[libata] convert drivers to use ata.h mode mask defines No functional changes in this patch. Signed-off-by: Erik Inge Bolsø <knan-lkml@anduin.net> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-03-15 04:38:24 +08:00
.pio_mask = ATA_PIO4,
[libata] Clean up driver udma_mask initializers * Use ATA_UDMA* * Remove FIXME notations that once served to remind us to verify that these were indeed the correct UDMA masks. They are. Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-07-08 13:13:16 +08:00
.udma_mask = ATA_UDMA6,
ahci: clean up board IDs ahci over time has grown a number of board IDs and it's a bit of mess right now. Clean it up such that, * board_id_* now live in a separate enum board_ids and numbers are assigned automatically. * Board IDs assigned to features are separated from the ones assigned to specific implementations and both are ordered alphabetically. * For NV MCPs, define per-generation alias board_ids and assign matching aliases in the pci id table. This makes mcp_linux, 67-73 use board_ahci_mcp65 instead of board_ahci_yesncq. Both are identical in content. * Kill now unused board_ahci_nopmp and board_ahci_yesncq. This patch doesn't cause any functional change but will make future changes to board_ids and quirks much less painful. Signed-off-by: Tejun Heo <tj@kernel.org> Cc: Peer Chen <pchen@nvidia.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-03-29 09:32:39 +08:00
.port_ops = &ahci_ops,
[PATCH] ahci: add support for VIA VT8251 Adds AHCI support for the VIA VT8251. Includes a workaround for a hardware bug which requires a Command List Override before softreset. Signed-off-by: Bastiaan Jacques <b.jacques@planet.nl> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2006-04-17 20:17:59 +08:00
},
ata: ahci: Rename board_ahci_mobile This board definition was originally created for mobile devices to designate default link power managmeent policy to influence runtime power consumption. As this is interesting for more than just mobile designs, rename the board to `board_ahci_low_power` to make it clear it is about default policy. Reviewed-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Paul Menzel <pmenzel@molgen.mpg.de> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
2022-02-26 01:23:17 +08:00
[board_ahci_low_power] = {
ata: ahci: Rename `AHCI_HFLAG_IS_MOBILE` `AHCI_HFLAG_IS_MOBILE` designates that a chipset should be using the default link power management policy from a kernel configuration item. As desktop chipsets may also be interested in this default policy configuration, rename the flag to `AHCI_HFLAG_USE_LPM_POLICY` to more accurately reflect that a chipset doesn't have to be mobile to adopt it. Reviewed-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Paul Menzel <pmenzel@molgen.mpg.de> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
2022-02-26 01:23:18 +08:00
AHCI_HFLAGS (AHCI_HFLAG_USE_LPM_POLICY),
ahci: Allow setting a default LPM policy for mobile chipsets On many laptops setting a different LPM policy then unknown / max_performance can lead to power-savings of 1.0 - 1.5 Watts (when idle). Modern ultrabooks idle around 6W (at 50% screen brightness), 1.0 - 1.5W is a significant chunk of this. There are some performance / latency costs to enabling LPM by default, so it is desirable to make it possible to set a different LPM policy for mobile / laptop variants of chipsets / "South Bridges" vs their desktop / server counterparts. Also enabling LPM by default is not entirely without risk of regressions. At least min_power is known to cause issues with some disks, including some reports of data corruption. This commits adds a new ahci.mobile_lpm_policy kernel cmdline option, which defaults to a new SATA_MOBILE_LPM_POLICY Kconfig option so that Linux distributions can choose to set a LPM policy for mobile chipsets by default. The reason to have both a kernel cmdline option and a Kconfig default value for it, is to allow easy overriding of the default to allow trouble-shooting without needing to rebuild the kernel. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2017-12-12 00:52:16 +08:00
.flags = AHCI_FLAG_COMMON,
.pio_mask = ATA_PIO4,
.udma_mask = ATA_UDMA6,
.port_ops = &ahci_ops,
},
ata: ahci: Add support for AMD A85 FCH (Hudson D4) Add support for the AMD A85 FCH (Hudson D4) AHCI adapter. Since this adapter does not require the default 200 ms debounce delay in sata_link_resume(), create a new board board_ahci_no_debounce_delay with the link flag ATA_LFLAG_NO_DEBOUNCE_DELAY, and, for now, configure the AMD A85 FCH (Hudson D4) to use it. On the ASUS F2A85-M PRO it reduces the Linux kernel boot time by the expected 200 ms from 787 ms to 585 ms. Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Cc: Tejun Heo <tj@kernel.org> Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
2022-01-05 23:36:18 +08:00
[board_ahci_no_debounce_delay] = {
.flags = AHCI_FLAG_COMMON,
.link_flags = ATA_LFLAG_NO_DEBOUNCE_DELAY,
.pio_mask = ATA_PIO4,
.udma_mask = ATA_UDMA6,
.port_ops = &ahci_ops,
},
ahci: disable MSI instead of NCQ on Samsung pci-e SSDs on macbooks Samsung pci-e SSDs on macbooks failed miserably on NCQ commands, so 67809f85d31e ("ahci: disable NCQ on Samsung pci-e SSDs on macbooks") disabled NCQ on them. It turns out that NCQ is fine as long as MSI is not used, so let's turn off MSI and leave NCQ on. Signed-off-by: Tejun Heo <tj@kernel.org> Link: https://bugzilla.kernel.org/show_bug.cgi?id=60731 Tested-by: <dorin@i51.org> Tested-by: Imre Kaloz <kaloz@openwrt.org> Cc: stable@vger.kernel.org Fixes: 67809f85d31e ("ahci: disable NCQ on Samsung pci-e SSDs on macbooks")
2014-10-27 22:22:56 +08:00
[board_ahci_nomsi] = {
AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
.flags = AHCI_FLAG_COMMON,
.pio_mask = ATA_PIO4,
.udma_mask = ATA_UDMA6,
.port_ops = &ahci_ops,
},
ahci: disable NCQ on Samsung pci-e SSDs on macbooks Samsung's pci-e SSDs with device ID 0x1600 which are found on some macbooks time out on NCQ commands. Blacklist NCQ on the device so that the affected machines can at least boot. Original-patch-by: Levente Kurusa <levex@linux.com> Signed-off-by: Tejun Heo <tj@kernel.org> Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=60731 Cc: stable@vger.kernel.org
2014-02-18 23:22:17 +08:00
[board_ahci_noncq] = {
AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
.flags = AHCI_FLAG_COMMON,
.pio_mask = ATA_PIO4,
.udma_mask = ATA_UDMA6,
.port_ops = &ahci_ops,
},
ahci, trivial: fixed coding style issues related to braces Fixed coding style issues related to braces found by checkpatch.pl in drivers/ata/ahci.c Signed-off-by: Jeffrin Jose <ahiliation@yahoo.co.in> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2012-06-05 04:03:37 +08:00
[board_ahci_nosntf] = {
ahci: clean up board IDs ahci over time has grown a number of board IDs and it's a bit of mess right now. Clean it up such that, * board_id_* now live in a separate enum board_ids and numbers are assigned automatically. * Board IDs assigned to features are separated from the ones assigned to specific implementations and both are ordered alphabetically. * For NV MCPs, define per-generation alias board_ids and assign matching aliases in the pci id table. This makes mcp_linux, 67-73 use board_ahci_mcp65 instead of board_ahci_yesncq. Both are identical in content. * Kill now unused board_ahci_nopmp and board_ahci_yesncq. This patch doesn't cause any functional change but will make future changes to board_ids and quirks much less painful. Signed-off-by: Tejun Heo <tj@kernel.org> Cc: Peer Chen <pchen@nvidia.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-03-29 09:32:39 +08:00
AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
ahci: move host flags over to pi.private_data Private pi.flags area is full and we need more private flags. Move host private flags over to pi.private_data. During initialization, these flags are copied to hpriv->flags. Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-09-23 12:19:55 +08:00
.flags = AHCI_FLAG_COMMON,
[libata] convert drivers to use ata.h mode mask defines No functional changes in this patch. Signed-off-by: Erik Inge Bolsø <knan-lkml@anduin.net> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-03-15 04:38:24 +08:00
.pio_mask = ATA_PIO4,
[libata] Clean up driver udma_mask initializers * Use ATA_UDMA* * Remove FIXME notations that once served to remind us to verify that these were indeed the correct UDMA masks. They are. Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-07-08 13:13:16 +08:00
.udma_mask = ATA_UDMA6,
[PATCH] ahci: ignore PORT_IRQ_IF_ERR on JMB controllers JMicron AHCI controllers set PORT_IRQ_IF_ERR on device errors. The IRQ status bit indicates interface error or protocol mismatch and ahci driver interprets it into AC_ERR_ATA_BUS. So, whenever an ATAPI device raises check condition, ahci interprets it as ATA bus error and thus resets it which, in turn, raises check condition thus creating a reset loop and rendering the device unuseable. This patch makes JMB controllers ignore PORT_IRQ_IF_ERR when interpreting error condition. Signed-off-by: Tejun Heo <htejun@gmail.com> Cc: Justin Tsai <justin@jmicron.com>
2006-11-29 10:33:14 +08:00
.port_ops = &ahci_ops,
},
ahci, trivial: fixed coding style issues related to braces Fixed coding style issues related to braces found by checkpatch.pl in drivers/ata/ahci.c Signed-off-by: Jeffrin Jose <ahiliation@yahoo.co.in> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2012-06-05 04:03:37 +08:00
[board_ahci_yes_fbs] = {
ahci: add HFLAG_YES_FBS and apply it to 88SE9128 88SE9128 can do FBS and sets it in HOST_CAP but forgets to set FBSCP in PORT_CMD. Implement AHCI_HFLAG_YES_FBS and apply it to 88SE9128. Signed-off-by: Tejun Heo <tj@kernel.org> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-07-24 22:53:48 +08:00
AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
.flags = AHCI_FLAG_COMMON,
.pio_mask = ATA_PIO4,
.udma_mask = ATA_UDMA6,
.port_ops = &ahci_ops,
},
ahci: clean up board IDs ahci over time has grown a number of board IDs and it's a bit of mess right now. Clean it up such that, * board_id_* now live in a separate enum board_ids and numbers are assigned automatically. * Board IDs assigned to features are separated from the ones assigned to specific implementations and both are ordered alphabetically. * For NV MCPs, define per-generation alias board_ids and assign matching aliases in the pci id table. This makes mcp_linux, 67-73 use board_ahci_mcp65 instead of board_ahci_yesncq. Both are identical in content. * Kill now unused board_ahci_nopmp and board_ahci_yesncq. This patch doesn't cause any functional change but will make future changes to board_ids and quirks much less painful. Signed-off-by: Tejun Heo <tj@kernel.org> Cc: Peer Chen <pchen@nvidia.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-03-29 09:32:39 +08:00
/* by chipsets */
ahci: Add support for Amazon's Annapurna Labs SATA controller This patch adds basic support for Amazon's Annapurna Labs SATA controller. Signed-off-by: Hanna Hawa <hhhawa@amazon.com> Signed-off-by: Jens Axboe <axboe@kernel.dk>
2019-10-17 22:46:53 +08:00
[board_ahci_al] = {
AHCI_HFLAGS (AHCI_HFLAG_NO_PMP | AHCI_HFLAG_NO_MSI),
.flags = AHCI_FLAG_COMMON,
.pio_mask = ATA_PIO4,
.udma_mask = ATA_UDMA6,
.port_ops = &ahci_ops,
},
ahci: avoton port-disable reset-quirk Avoton AHCI occasionally sees drive probe timeouts at driver load time. When this happens SCR_STATUS indicates device detected, but no D2H FIS reception. Reset the internal link state machines by bouncing port-enable in the PCS register when this occurs. Cc: <stable@vger.kernel.org> Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2015-05-09 03:23:55 +08:00
[board_ahci_avn] = {
.flags = AHCI_FLAG_COMMON,
.pio_mask = ATA_PIO4,
.udma_mask = ATA_UDMA6,
.port_ops = &ahci_avn_ops,
},
ahci, trivial: fixed coding style issues related to braces Fixed coding style issues related to braces found by checkpatch.pl in drivers/ata/ahci.c Signed-off-by: Jeffrin Jose <ahiliation@yahoo.co.in> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2012-06-05 04:03:37 +08:00
[board_ahci_mcp65] = {
ahci: implement AHCI_HFLAG_NO_FPDMA_AA and update NV quirks It turns out different generations of MCPs have differing quirks. * MCP 65-73 : FPDMA AA broken, lies about PMP support, forgets to report NCQ * MCP 77-79 : FPDMA AA broken, lies about PMP support * MCP 89 : FPDMA AA broken Instead of turngin off FPDMA AA on all NVIDIAs, implement HFLAG_NO_FPDMA_AA, define additional board IDs and apply necessary quirks. This fixes bko#15481 and the list of quirks is verified by Peer Chen. http://bugzilla.kernel.org/show_bug.cgi?id=15481 Signed-off-by: Tejun Heo <tj@kernel.org> Cc: Peer Chen <pchen@nvidia.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-03-30 09:28:32 +08:00
AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
AHCI_HFLAG_YES_NCQ),
libata: Implement ATA_FLAG_NO_DIPM and apply it to mcp65 NVIDIA mcp65 familiy of controllers cause command timeouts when DIPM is used. Implement ATA_FLAG_NO_DIPM and apply it. This problem was reported by Stefan Bader in the following thread. http://thread.gmane.org/gmane.linux.ide/48841 stable: applicable to 2.6.37 and 38. Signed-off-by: Tejun Heo <tj@kernel.org> Reported-by: Stefan Bader <stefan.bader@canonical.com> Cc: stable@kernel.org Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
2011-03-16 18:14:55 +08:00
.flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
ahci: implement AHCI_HFLAG_NO_FPDMA_AA and update NV quirks It turns out different generations of MCPs have differing quirks. * MCP 65-73 : FPDMA AA broken, lies about PMP support, forgets to report NCQ * MCP 77-79 : FPDMA AA broken, lies about PMP support * MCP 89 : FPDMA AA broken Instead of turngin off FPDMA AA on all NVIDIAs, implement HFLAG_NO_FPDMA_AA, define additional board IDs and apply necessary quirks. This fixes bko#15481 and the list of quirks is verified by Peer Chen. http://bugzilla.kernel.org/show_bug.cgi?id=15481 Signed-off-by: Tejun Heo <tj@kernel.org> Cc: Peer Chen <pchen@nvidia.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-03-30 09:28:32 +08:00
.pio_mask = ATA_PIO4,
.udma_mask = ATA_UDMA6,
.port_ops = &ahci_ops,
},
ahci, trivial: fixed coding style issues related to braces Fixed coding style issues related to braces found by checkpatch.pl in drivers/ata/ahci.c Signed-off-by: Jeffrin Jose <ahiliation@yahoo.co.in> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2012-06-05 04:03:37 +08:00
[board_ahci_mcp77] = {
ahci: implement AHCI_HFLAG_NO_FPDMA_AA and update NV quirks It turns out different generations of MCPs have differing quirks. * MCP 65-73 : FPDMA AA broken, lies about PMP support, forgets to report NCQ * MCP 77-79 : FPDMA AA broken, lies about PMP support * MCP 89 : FPDMA AA broken Instead of turngin off FPDMA AA on all NVIDIAs, implement HFLAG_NO_FPDMA_AA, define additional board IDs and apply necessary quirks. This fixes bko#15481 and the list of quirks is verified by Peer Chen. http://bugzilla.kernel.org/show_bug.cgi?id=15481 Signed-off-by: Tejun Heo <tj@kernel.org> Cc: Peer Chen <pchen@nvidia.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-03-30 09:28:32 +08:00
AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
.flags = AHCI_FLAG_COMMON,
.pio_mask = ATA_PIO4,
.udma_mask = ATA_UDMA6,
.port_ops = &ahci_ops,
},
ahci, trivial: fixed coding style issues related to braces Fixed coding style issues related to braces found by checkpatch.pl in drivers/ata/ahci.c Signed-off-by: Jeffrin Jose <ahiliation@yahoo.co.in> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2012-06-05 04:03:37 +08:00
[board_ahci_mcp89] = {
ahci: implement AHCI_HFLAG_NO_FPDMA_AA and update NV quirks It turns out different generations of MCPs have differing quirks. * MCP 65-73 : FPDMA AA broken, lies about PMP support, forgets to report NCQ * MCP 77-79 : FPDMA AA broken, lies about PMP support * MCP 89 : FPDMA AA broken Instead of turngin off FPDMA AA on all NVIDIAs, implement HFLAG_NO_FPDMA_AA, define additional board IDs and apply necessary quirks. This fixes bko#15481 and the list of quirks is verified by Peer Chen. http://bugzilla.kernel.org/show_bug.cgi?id=15481 Signed-off-by: Tejun Heo <tj@kernel.org> Cc: Peer Chen <pchen@nvidia.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-03-30 09:28:32 +08:00
AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
ahci: move host flags over to pi.private_data Private pi.flags area is full and we need more private flags. Move host private flags over to pi.private_data. During initialization, these flags are copied to hpriv->flags. Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-09-23 12:19:55 +08:00
.flags = AHCI_FLAG_COMMON,
[libata] convert drivers to use ata.h mode mask defines No functional changes in this patch. Signed-off-by: Erik Inge Bolsø <knan-lkml@anduin.net> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-03-15 04:38:24 +08:00
.pio_mask = ATA_PIO4,
[libata] Clean up driver udma_mask initializers * Use ATA_UDMA* * Remove FIXME notations that once served to remind us to verify that these were indeed the correct UDMA masks. They are. Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-07-08 13:13:16 +08:00
.udma_mask = ATA_UDMA6,
ahci: clean up board IDs ahci over time has grown a number of board IDs and it's a bit of mess right now. Clean it up such that, * board_id_* now live in a separate enum board_ids and numbers are assigned automatically. * Board IDs assigned to features are separated from the ones assigned to specific implementations and both are ordered alphabetically. * For NV MCPs, define per-generation alias board_ids and assign matching aliases in the pci id table. This makes mcp_linux, 67-73 use board_ahci_mcp65 instead of board_ahci_yesncq. Both are identical in content. * Kill now unused board_ahci_nopmp and board_ahci_yesncq. This patch doesn't cause any functional change but will make future changes to board_ids and quirks much less painful. Signed-off-by: Tejun Heo <tj@kernel.org> Cc: Peer Chen <pchen@nvidia.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-03-29 09:32:39 +08:00
.port_ops = &ahci_ops,
ahci.c: walkaround for SB600 SATA internal error issue There is a HW issue in ATI SB600 SATA that PxSERR.E should not be set on some conditions, for example, when there is no media in SATA CD/DVD drive or media is not ready, AHCI controller fails to execute ATAPI commands and reports PORT_IRQ_TF_ERR, but ATI SB600 SATA controller sets PxSERR.E at the same time, which is not necessary. This patch is just to ignore the INTERNAL ERROR in such case. Without this patch, ahci error handler will report many errors as below: ----------- cut from dmesg ----------- ata9: soft resetting port ata9: SATA link up 1.5 Gbps (SStatus 113 SControl 300) ata9.00: configured for UDMA/33 ata9: EH complete ata9.00: exception Emask 0x40 SAct 0x0 SErr 0x800 action 0x2 ata9.00: (irq_stat 0x40000001) ata9.00: cmd a0/00:00:00:00:20/00:00:00:00:00/a0 tag 0 cdb 0x0 data 0 res 51/24:03:00:00:20/00:00:00:00:00/a0 Emask 0x40 (internal error) ata9: soft resetting port ata9: SATA link up 1.5 Gbps (SStatus 113 SControl 300) ata9.00: configured for UDMA/33 ata9: EH complete ata9.00: exception Emask 0x40 SAct 0x0 SErr 0x800 action 0x2 ata9.00: (irq_stat 0x40000001) ata9.00: cmd a0/01:00:00:00:00/00:00:00:00:00/a0 tag 0 cdb 0x43 data 12 in res 51/24:03:00:00:00/00:00:00:00:00/a0 Emask 0x40 (internal error) -------- end cut --------- Signed-off-by: Conke Hu <conke.hu@amd.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-03-27 18:33:05 +08:00
},
ahci, trivial: fixed coding style issues related to braces Fixed coding style issues related to braces found by checkpatch.pl in drivers/ata/ahci.c Signed-off-by: Jeffrin Jose <ahiliation@yahoo.co.in> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2012-06-05 04:03:37 +08:00
[board_ahci_mv] = {
ahci: move host flags over to pi.private_data Private pi.flags area is full and we need more private flags. Move host private flags over to pi.private_data. During initialization, these flags are copied to hpriv->flags. Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-09-23 12:19:55 +08:00
AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
ahci: disable PMP for marvell ahcis Marvell ahcis don't play nicely with PMPs. Disable it. Reported by KueiHuan Chen in the following thread. http://thread.gmane.org/gmane.linux.ide/33296 Signed-off-by: Tejun Heo <tj@kernel.org> Cc: KueiHuan Chen <kueihuan.chen@gmail.com> Cc: Mark Lord <mlord@pobox.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2008-08-29 22:03:59 +08:00
AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
libata: remove ATA_FLAG_NO_LEGACY All checks of ATA_FLAG_NO_LEGACY have been removed by the commits c791c30670ea61f19eec390124128bf278e854fe ([libata] minor PCI IDE probe fixes and cleanups) and f0d36efdc624beb3d9e29b9ab9e9537bf0f25d5b (libata: update libata core layer to use devres), so I think it's time to finally get rid of this flag... Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2011-02-05 03:05:48 +08:00
.flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
[libata] convert drivers to use ata.h mode mask defines No functional changes in this patch. Signed-off-by: Erik Inge Bolsø <knan-lkml@anduin.net> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-03-15 04:38:24 +08:00
.pio_mask = ATA_PIO4,
[libata] AHCI: Add support for Marvell AHCI-like chips (initially 6145) Add support for the SATA portion of Marvell's AHCI-compatible chips. The PATA port capability, also available via AHCI, is disabled until support is completed. NCQ and PCI MSI are disabled by default. Marvell says "we use NCQ" in their drivers but "we do not use PCI MSI." Theoretically that implies we need to fix ahci.c to work with Marvell NCQ, but one wonders why Marvell NCQ is any different from other AHCI chips. Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-07-08 14:29:42 +08:00
.udma_mask = ATA_UDMA6,
.port_ops = &ahci_ops,
},
ahci, trivial: fixed coding style issues related to braces Fixed coding style issues related to braces found by checkpatch.pl in drivers/ata/ahci.c Signed-off-by: Jeffrin Jose <ahiliation@yahoo.co.in> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2012-06-05 04:03:37 +08:00
[board_ahci_sb600] = {
ahci: clean up board IDs ahci over time has grown a number of board IDs and it's a bit of mess right now. Clean it up such that, * board_id_* now live in a separate enum board_ids and numbers are assigned automatically. * Board IDs assigned to features are separated from the ones assigned to specific implementations and both are ordered alphabetically. * For NV MCPs, define per-generation alias board_ids and assign matching aliases in the pci id table. This makes mcp_linux, 67-73 use board_ahci_mcp65 instead of board_ahci_yesncq. Both are identical in content. * Kill now unused board_ahci_nopmp and board_ahci_yesncq. This patch doesn't cause any functional change but will make future changes to board_ids and quirks much less painful. Signed-off-by: Tejun Heo <tj@kernel.org> Cc: Peer Chen <pchen@nvidia.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-03-29 09:32:39 +08:00
AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
AHCI_HFLAG_32BIT_ONLY),
[libata] ahci: AMD SB700/SB800 SATA support 64bit DMA SB700 SATA controller can support 64 bit DMA, the previous commit badc2341579511a247f5993865aa68379e283c5c was added with careless reference to SB600, which should be modified by this patch. Signed-off-by: Shane Huang <shane.huang@amd.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2008-02-22 21:00:31 +08:00
.flags = AHCI_FLAG_COMMON,
[libata] convert drivers to use ata.h mode mask defines No functional changes in this patch. Signed-off-by: Erik Inge Bolsø <knan-lkml@anduin.net> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-03-15 04:38:24 +08:00
.pio_mask = ATA_PIO4,
[libata] ahci: AMD SB700/SB800 SATA support 64bit DMA SB700 SATA controller can support 64 bit DMA, the previous commit badc2341579511a247f5993865aa68379e283c5c was added with careless reference to SB600, which should be modified by this patch. Signed-off-by: Shane Huang <shane.huang@amd.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2008-02-22 21:00:31 +08:00
.udma_mask = ATA_UDMA6,
ahci: move ahci_sb600_softreset to libahci.c and rename it ahci_sb600_softreset was in ahci.c. This function is used to fix soft reset failure and renames as ahci_pmp_retry_softreset in libahci.c. Signed-off-by: Yuan-Hsin Chen <yhchen@faraday-tech.com> Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
2011-06-21 17:17:38 +08:00
.port_ops = &ahci_pmp_retry_srst_ops,
[libata] ahci: AMD SB700/SB800 SATA support 64bit DMA SB700 SATA controller can support 64 bit DMA, the previous commit badc2341579511a247f5993865aa68379e283c5c was added with careless reference to SB600, which should be modified by this patch. Signed-off-by: Shane Huang <shane.huang@amd.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2008-02-22 21:00:31 +08:00
},
ahci, trivial: fixed coding style issues related to braces Fixed coding style issues related to braces found by checkpatch.pl in drivers/ata/ahci.c Signed-off-by: Jeffrin Jose <ahiliation@yahoo.co.in> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2012-06-05 04:03:37 +08:00
[board_ahci_sb700] = { /* for SB700 and SB800 */
ahci: clean up board IDs ahci over time has grown a number of board IDs and it's a bit of mess right now. Clean it up such that, * board_id_* now live in a separate enum board_ids and numbers are assigned automatically. * Board IDs assigned to features are separated from the ones assigned to specific implementations and both are ordered alphabetically. * For NV MCPs, define per-generation alias board_ids and assign matching aliases in the pci id table. This makes mcp_linux, 67-73 use board_ahci_mcp65 instead of board_ahci_yesncq. Both are identical in content. * Kill now unused board_ahci_nopmp and board_ahci_yesncq. This patch doesn't cause any functional change but will make future changes to board_ids and quirks much less painful. Signed-off-by: Tejun Heo <tj@kernel.org> Cc: Peer Chen <pchen@nvidia.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-03-29 09:32:39 +08:00
AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
ahci: force CAP_NCQ for earlier NV MCPs Along with MCP65, MCP67 and 73 also don't set CAP_NCQ. Force it. Reported by zaceni@yandex.ru on bko#13014 and confirmed by Peer Chen. Signed-off-by: Tejun Heo <tj@kernel.org> Reported-by: NightFox <zaceni2@yandex.ru> Cc: Peer Chen <pchen@nvidia.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-04-09 05:25:31 +08:00
.flags = AHCI_FLAG_COMMON,
.pio_mask = ATA_PIO4,
.udma_mask = ATA_UDMA6,
ahci: move ahci_sb600_softreset to libahci.c and rename it ahci_sb600_softreset was in ahci.c. This function is used to fix soft reset failure and renames as ahci_pmp_retry_softreset in libahci.c. Signed-off-by: Yuan-Hsin Chen <yhchen@faraday-tech.com> Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
2011-06-21 17:17:38 +08:00
.port_ops = &ahci_pmp_retry_srst_ops,
ahci: force CAP_NCQ for earlier NV MCPs Along with MCP65, MCP67 and 73 also don't set CAP_NCQ. Force it. Reported by zaceni@yandex.ru on bko#13014 and confirmed by Peer Chen. Signed-off-by: Tejun Heo <tj@kernel.org> Reported-by: NightFox <zaceni2@yandex.ru> Cc: Peer Chen <pchen@nvidia.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-04-09 05:25:31 +08:00
},
ahci, trivial: fixed coding style issues related to braces Fixed coding style issues related to braces found by checkpatch.pl in drivers/ata/ahci.c Signed-off-by: Jeffrin Jose <ahiliation@yahoo.co.in> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2012-06-05 04:03:37 +08:00
[board_ahci_vt8251] = {
ahci: clean up board IDs ahci over time has grown a number of board IDs and it's a bit of mess right now. Clean it up such that, * board_id_* now live in a separate enum board_ids and numbers are assigned automatically. * Board IDs assigned to features are separated from the ones assigned to specific implementations and both are ordered alphabetically. * For NV MCPs, define per-generation alias board_ids and assign matching aliases in the pci id table. This makes mcp_linux, 67-73 use board_ahci_mcp65 instead of board_ahci_yesncq. Both are identical in content. * Kill now unused board_ahci_nopmp and board_ahci_yesncq. This patch doesn't cause any functional change but will make future changes to board_ids and quirks much less painful. Signed-off-by: Tejun Heo <tj@kernel.org> Cc: Peer Chen <pchen@nvidia.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-03-29 09:32:39 +08:00
AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
ahci: disable SNotification capability for ich8 I obseved there is a sata_async_notification() for every ahci interrupt. But the async notification does nothing (this is hard disk drive and no pmp). This cause cpu wastes some time on sntf register access. It appears ICH AHCI doesn't support SNotification register, but the controller reports it does. After quirking it, the async notification disappears. PS. it appears all ICH don't support SNotification register from ICH manual, don't know if we need quirk all ICH. I don't have machines with all kinds of ICH. Signed-off-by: Shaohua Li <shaohua.li@intel.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-11-16 09:56:05 +08:00
.flags = AHCI_FLAG_COMMON,
.pio_mask = ATA_PIO4,
.udma_mask = ATA_UDMA6,
ahci: clean up board IDs ahci over time has grown a number of board IDs and it's a bit of mess right now. Clean it up such that, * board_id_* now live in a separate enum board_ids and numbers are assigned automatically. * Board IDs assigned to features are separated from the ones assigned to specific implementations and both are ordered alphabetically. * For NV MCPs, define per-generation alias board_ids and assign matching aliases in the pci id table. This makes mcp_linux, 67-73 use board_ahci_mcp65 instead of board_ahci_yesncq. Both are identical in content. * Kill now unused board_ahci_nopmp and board_ahci_yesncq. This patch doesn't cause any functional change but will make future changes to board_ids and quirks much less painful. Signed-off-by: Tejun Heo <tj@kernel.org> Cc: Peer Chen <pchen@nvidia.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-03-29 09:32:39 +08:00
.port_ops = &ahci_vt8251_ops,
ahci: disable SNotification capability for ich8 I obseved there is a sata_async_notification() for every ahci interrupt. But the async notification does nothing (this is hard disk drive and no pmp). This cause cpu wastes some time on sntf register access. It appears ICH AHCI doesn't support SNotification register, but the controller reports it does. After quirking it, the async notification disappears. PS. it appears all ICH don't support SNotification register from ICH manual, don't know if we need quirk all ICH. I don't have machines with all kinds of ICH. Signed-off-by: Shaohua Li <shaohua.li@intel.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-11-16 09:56:05 +08:00
},
libata/ahci: Drop PCS quirk for Denverton and beyond The Linux ahci driver has historically implemented a configuration fixup for platforms / platform-firmware that fails to enable the ports prior to OS hand-off at boot. The fixup was originally implemented way back before ahci moved from drivers/scsi/ to drivers/ata/, and was updated in 2007 via commit 49f290903935 "ahci: update PCS programming". The quirk sets a port-enable bitmap in the PCS register at offset 0x92. This quirk could be applied generically up until the arrival of the Denverton (DNV) platform. The DNV AHCI controller architecture supports more than 6 ports and along with that the PCS register location and format were updated to allow for more possible ports in the bitmap. DNV AHCI expands the register to 32-bits and moves it to offset 0x94. As it stands there are no known problem reports with existing Linux trying to set bits at offset 0x92 which indicates that the quirk is not applicable. Likely it is not applicable on a wider range of platforms, but it is difficult to discern which platforms if any still depend on the quirk. Rather than try to fix the PCS quirk to consider the DNV register layout instead require explicit opt-in. The assumption is that the OS driver need not touch this register, and platforms can be added with a new boad_ahci_pcs7 board-id when / if problematic platforms are found in the future. The logic in ahci_intel_pcs_quirk() looks for all Intel AHCI instances with "legacy" board-ids and otherwise skips the quirk if the board was matched by class-code. Reported-by: Stephen Douthit <stephend@silicom-usa.com> Cc: Christoph Hellwig <hch@infradead.org> Reviewed-by: Stephen Douthit <stephend@silicom-usa.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Jens Axboe <axboe@kernel.dk>
2019-08-30 07:30:34 +08:00
[board_ahci_pcs7] = {
.flags = AHCI_FLAG_COMMON,
.pio_mask = ATA_PIO4,
.udma_mask = ATA_UDMA6,
.port_ops = &ahci_ops,
},
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 06:20:36 +08:00
};
[libata] constify PCI ID table in several drivers
2005-11-11 00:04:11 +08:00
static const struct pci_device_id ahci_pci_tbl[] = {
[libata] ahci: Add NVIDIA PCI IDs. Based on a patch by Andrew Chew @ NVIDIA. Signed-off-by: Jeff Garzik <jeff@garzik.org>
2006-06-23 11:05:36 +08:00
/* Intel */
ahci: Add Intel Comet Lake PCH-H PCI ID Add Intel Comet Lake PCH-H PCI ID to the list of supported controllers. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Jens Axboe <axboe@kernel.dk>
2020-02-27 22:32:59 +08:00
{ PCI_VDEVICE(INTEL, 0x06d6), board_ahci }, /* Comet Lake PCH-H RAID */
[libata] Use new PCI_VDEVICE() macro to dramatically shorten ID lists Signed-off-by: Jeff Garzik <jeff@garzik.org>
2006-09-28 10:20:11 +08:00
{ PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
{ PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
{ PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
{ PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
{ PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
ahci: make ULi M5288 ignore interface fatal error bit As with JMicron controllers, ULi M5288 sets interface fatal error bit on device error including ATAPI CC. This makes libata hardreset the port on ATAPI CC thus making it impossible to use. Ignore interface fatal error bit on ULi M5288. This fixes bugzilla bug #7837. Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-01-23 14:13:39 +08:00
{ PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
[libata] Use new PCI_VDEVICE() macro to dramatically shorten ID lists Signed-off-by: Jeff Garzik <jeff@garzik.org>
2006-09-28 10:20:11 +08:00
{ PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
{ PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
{ PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
{ PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
ahci: reimplement port_map handling Reimplement port_map handling such that 1. Non-zero PORTS_IMPL value is always examined and used if consistent with cap.n_ports. 2. When PI and cat.n_ports are inconsistent, honor cap.n_ports and force port_map to be ((1 << cap.n_ports) - 1). 3. There were two separate places dealing with port_map. Unify them to one. As all newer ahci chips seem to get PI correct and older ones usually have zero PI. Controllers with holes in PI are very unlikely to screw up PI, so #2 makes more sense than following inconsistent PI. Without this change, not setting ATA_FLAG_HONOR_PI when it's needed results in weird detection failure. This changed logic should be able to handle all known cases correctly automatically. Verified on ICH6 (reports 0 PI), ICH8 (with holes in port_map), ICH9, JMB360 and JMB363. Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-09-03 11:44:57 +08:00
{ PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
ahci: remove duplicated PCI device IDs Intel devices 0x2822, 0x2823, 0x2826 and 0x2827 are already on the list as Lewisburg AHCI/RAID. They use same configuration except 0x2822 which has board_ahci_nosntf (for ICH8). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
2021-09-19 17:43:13 +08:00
{ PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8/Lewisburg RAID*/
ahci: reimplement port_map handling Reimplement port_map handling such that 1. Non-zero PORTS_IMPL value is always examined and used if consistent with cap.n_ports. 2. When PI and cat.n_ports are inconsistent, honor cap.n_ports and force port_map to be ((1 << cap.n_ports) - 1). 3. There were two separate places dealing with port_map. Unify them to one. As all newer ahci chips seem to get PI correct and older ones usually have zero PI. Controllers with holes in PI are very unlikely to screw up PI, so #2 makes more sense than following inconsistent PI. Without this change, not setting ATA_FLAG_HONOR_PI when it's needed results in weird detection failure. This changed logic should be able to handle all known cases correctly automatically. Verified on ICH6 (reports 0 PI), ICH8 (with holes in port_map), ICH9, JMB360 and JMB363. Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-09-03 11:44:57 +08:00
{ PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
{ PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
{ PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
{ PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
{ PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
{ PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
{ PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
{ PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
ata: ahci: Rename board_ahci_mobile This board definition was originally created for mobile devices to designate default link power managmeent policy to influence runtime power consumption. As this is interesting for more than just mobile designs, rename the board to `board_ahci_low_power` to make it clear it is about default policy. Reviewed-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Paul Menzel <pmenzel@molgen.mpg.de> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
2022-02-26 01:23:17 +08:00
{ PCI_VDEVICE(INTEL, 0x2929), board_ahci_low_power }, /* ICH9M */
{ PCI_VDEVICE(INTEL, 0x292a), board_ahci_low_power }, /* ICH9M */
{ PCI_VDEVICE(INTEL, 0x292b), board_ahci_low_power }, /* ICH9M */
{ PCI_VDEVICE(INTEL, 0x292c), board_ahci_low_power }, /* ICH9M */
{ PCI_VDEVICE(INTEL, 0x292f), board_ahci_low_power }, /* ICH9M */
ahci: reimplement port_map handling Reimplement port_map handling such that 1. Non-zero PORTS_IMPL value is always examined and used if consistent with cap.n_ports. 2. When PI and cat.n_ports are inconsistent, honor cap.n_ports and force port_map to be ((1 << cap.n_ports) - 1). 3. There were two separate places dealing with port_map. Unify them to one. As all newer ahci chips seem to get PI correct and older ones usually have zero PI. Controllers with holes in PI are very unlikely to screw up PI, so #2 makes more sense than following inconsistent PI. Without this change, not setting ATA_FLAG_HONOR_PI when it's needed results in weird detection failure. This changed logic should be able to handle all known cases correctly automatically. Verified on ICH6 (reports 0 PI), ICH8 (with holes in port_map), ICH9, JMB360 and JMB363. Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-09-03 11:44:57 +08:00
{ PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
ata: ahci: Rename board_ahci_mobile This board definition was originally created for mobile devices to designate default link power managmeent policy to influence runtime power consumption. As this is interesting for more than just mobile designs, rename the board to `board_ahci_low_power` to make it clear it is about default policy. Reviewed-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Paul Menzel <pmenzel@molgen.mpg.de> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
2022-02-26 01:23:17 +08:00
{ PCI_VDEVICE(INTEL, 0x294e), board_ahci_low_power }, /* ICH9M */
ahci: RAID mode SATA patch for Intel Tolapai Signed-off-by: Jason Gaston <jason.d.gaston@intel.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-09-21 05:35:00 +08:00
{ PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
{ PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
ahci: RAID mode SATA patch for Intel ICH10 DeviceID's This patch adds the Intel ICH10 SATA RAID Controllers DeviceID's. Signed-off-by: Jason Gaston <jason.d.gaston@intel.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2008-01-29 09:34:14 +08:00
{ PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
ahci: add device ID for 82801JI sata controller Add device ID for Intel 82801JI SATA AHCI controller. Signed-off-by: David Milburn <dmilburn@redhat.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-06-26 23:44:11 +08:00
{ PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
ahci: RAID mode SATA patch for Intel ICH10 DeviceID's This patch adds the Intel ICH10 SATA RAID Controllers DeviceID's. Signed-off-by: Jason Gaston <jason.d.gaston@intel.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2008-01-29 09:34:14 +08:00
{ PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
ahci: add device IDs for Ibex Peak ahci controllers Add device IDS for Ibex Peak SATA AHCI Controllers Signed-off-by: Jaroslav Kysela <jkysela@redhat.com> Signed-off-by: David Milburn <dmilburn@redhat.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-07-23 04:15:56 +08:00
{ PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
{ PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
ahci: RAID mode SATA patch for Intel Ibex Peak DeviceIDs Resend with proper whitespace. This patch adds the Intel Ibex Peak (PCH) SATA RAID Controller DeviceIDs. Signed-off-by: Seth Heasley <seth.heasley@intel.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2008-08-12 08:03:09 +08:00
{ PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
ahci: RAID mode SATA patch for Intel Ibex Peak DeviceIDs Add the Intel Ibex Peak (PCH) SATA RAID Controller DeviceIDs. Signed-off-by: Seth Heasley <seth.heasley@intel.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2008-08-28 07:47:22 +08:00
{ PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
ata: ahci: Rename board_ahci_mobile This board definition was originally created for mobile devices to designate default link power managmeent policy to influence runtime power consumption. As this is interesting for more than just mobile designs, rename the board to `board_ahci_low_power` to make it clear it is about default policy. Reviewed-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Paul Menzel <pmenzel@molgen.mpg.de> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
2022-02-26 01:23:17 +08:00
{ PCI_VDEVICE(INTEL, 0x3b29), board_ahci_low_power }, /* PCH M AHCI */
ahci: RAID mode SATA patch for Intel Ibex Peak DeviceIDs Resend with proper whitespace. This patch adds the Intel Ibex Peak (PCH) SATA RAID Controller DeviceIDs. Signed-off-by: Seth Heasley <seth.heasley@intel.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2008-08-12 08:03:09 +08:00
{ PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
ata: ahci: Rename board_ahci_mobile This board definition was originally created for mobile devices to designate default link power managmeent policy to influence runtime power consumption. As this is interesting for more than just mobile designs, rename the board to `board_ahci_low_power` to make it clear it is about default policy. Reviewed-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Paul Menzel <pmenzel@molgen.mpg.de> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
2022-02-26 01:23:17 +08:00
{ PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_low_power }, /* PCH M RAID */
ahci: add device IDs for Ibex Peak ahci controllers Add device IDS for Ibex Peak SATA AHCI Controllers Signed-off-by: Jaroslav Kysela <jkysela@redhat.com> Signed-off-by: David Milburn <dmilburn@redhat.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-07-23 04:15:56 +08:00
{ PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
libata/ahci: Drop PCS quirk for Denverton and beyond The Linux ahci driver has historically implemented a configuration fixup for platforms / platform-firmware that fails to enable the ports prior to OS hand-off at boot. The fixup was originally implemented way back before ahci moved from drivers/scsi/ to drivers/ata/, and was updated in 2007 via commit 49f290903935 "ahci: update PCS programming". The quirk sets a port-enable bitmap in the PCS register at offset 0x92. This quirk could be applied generically up until the arrival of the Denverton (DNV) platform. The DNV AHCI controller architecture supports more than 6 ports and along with that the PCS register location and format were updated to allow for more possible ports in the bitmap. DNV AHCI expands the register to 32-bits and moves it to offset 0x94. As it stands there are no known problem reports with existing Linux trying to set bits at offset 0x92 which indicates that the quirk is not applicable. Likely it is not applicable on a wider range of platforms, but it is difficult to discern which platforms if any still depend on the quirk. Rather than try to fix the PCS quirk to consider the DNV register layout instead require explicit opt-in. The assumption is that the OS driver need not touch this register, and platforms can be added with a new boad_ahci_pcs7 board-id when / if problematic platforms are found in the future. The logic in ahci_intel_pcs_quirk() looks for all Intel AHCI instances with "legacy" board-ids and otherwise skips the quirk if the board was matched by class-code. Reported-by: Stephen Douthit <stephend@silicom-usa.com> Cc: Christoph Hellwig <hch@infradead.org> Reviewed-by: Stephen Douthit <stephend@silicom-usa.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Jens Axboe <axboe@kernel.dk>
2019-08-30 07:30:34 +08:00
{ PCI_VDEVICE(INTEL, 0x19b0), board_ahci_pcs7 }, /* DNV AHCI */
{ PCI_VDEVICE(INTEL, 0x19b1), board_ahci_pcs7 }, /* DNV AHCI */
{ PCI_VDEVICE(INTEL, 0x19b2), board_ahci_pcs7 }, /* DNV AHCI */
{ PCI_VDEVICE(INTEL, 0x19b3), board_ahci_pcs7 }, /* DNV AHCI */
{ PCI_VDEVICE(INTEL, 0x19b4), board_ahci_pcs7 }, /* DNV AHCI */
{ PCI_VDEVICE(INTEL, 0x19b5), board_ahci_pcs7 }, /* DNV AHCI */
{ PCI_VDEVICE(INTEL, 0x19b6), board_ahci_pcs7 }, /* DNV AHCI */
{ PCI_VDEVICE(INTEL, 0x19b7), board_ahci_pcs7 }, /* DNV AHCI */
{ PCI_VDEVICE(INTEL, 0x19bE), board_ahci_pcs7 }, /* DNV AHCI */
{ PCI_VDEVICE(INTEL, 0x19bF), board_ahci_pcs7 }, /* DNV AHCI */
{ PCI_VDEVICE(INTEL, 0x19c0), board_ahci_pcs7 }, /* DNV AHCI */
{ PCI_VDEVICE(INTEL, 0x19c1), board_ahci_pcs7 }, /* DNV AHCI */
{ PCI_VDEVICE(INTEL, 0x19c2), board_ahci_pcs7 }, /* DNV AHCI */
{ PCI_VDEVICE(INTEL, 0x19c3), board_ahci_pcs7 }, /* DNV AHCI */
{ PCI_VDEVICE(INTEL, 0x19c4), board_ahci_pcs7 }, /* DNV AHCI */
{ PCI_VDEVICE(INTEL, 0x19c5), board_ahci_pcs7 }, /* DNV AHCI */
{ PCI_VDEVICE(INTEL, 0x19c6), board_ahci_pcs7 }, /* DNV AHCI */
{ PCI_VDEVICE(INTEL, 0x19c7), board_ahci_pcs7 }, /* DNV AHCI */
{ PCI_VDEVICE(INTEL, 0x19cE), board_ahci_pcs7 }, /* DNV AHCI */
{ PCI_VDEVICE(INTEL, 0x19cF), board_ahci_pcs7 }, /* DNV AHCI */
ahci: AHCI and RAID mode SATA patch for Intel Cougar Point DeviceIDs Signed-off-by: Seth Heasley <seth.heasley@intel.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-01-13 09:00:18 +08:00
{ PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
ata: ahci: Rename board_ahci_mobile This board definition was originally created for mobile devices to designate default link power managmeent policy to influence runtime power consumption. As this is interesting for more than just mobile designs, rename the board to `board_ahci_low_power` to make it clear it is about default policy. Reviewed-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Paul Menzel <pmenzel@molgen.mpg.de> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
2022-02-26 01:23:17 +08:00
{ PCI_VDEVICE(INTEL, 0x1c03), board_ahci_low_power }, /* CPT M AHCI */
ahci: AHCI and RAID mode SATA patch for Intel Cougar Point DeviceIDs Signed-off-by: Seth Heasley <seth.heasley@intel.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-01-13 09:00:18 +08:00
{ PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
ata: ahci: Rename board_ahci_mobile This board definition was originally created for mobile devices to designate default link power managmeent policy to influence runtime power consumption. As this is interesting for more than just mobile designs, rename the board to `board_ahci_low_power` to make it clear it is about default policy. Reviewed-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Paul Menzel <pmenzel@molgen.mpg.de> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
2022-02-26 01:23:17 +08:00
{ PCI_VDEVICE(INTEL, 0x1c05), board_ahci_low_power }, /* CPT M RAID */
ahci: AHCI and RAID mode SATA patch for Intel Cougar Point DeviceIDs Signed-off-by: Seth Heasley <seth.heasley@intel.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-01-13 09:00:18 +08:00
{ PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
{ PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
ahci: AHCI and RAID mode SATA patch for Intel Patsburg DeviceIDs This patch adds the Intel Patsburg (PCH) SATA AHCI and RAID Controller DeviceIDs. Signed-off-by: Seth Heasley <seth.heasley@intel.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-09-10 00:44:56 +08:00
{ PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
{ PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
{ PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
ahci: AHCI mode SATA patch for Intel DH89xxCC DeviceIDs This patch adds the AHCI-mode SATA DeviceID for the Intel DH89xxCC PCH. Signed-off-by: Seth Heasley <seth.heasley@intel.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2011-01-11 04:57:17 +08:00
{ PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
ahci: AHCI-mode SATA patch for Intel Panther Point DeviceIDs The previously submitted patch was word-wrapped. This patch adds the AHCI-mode SATA DeviceIDs for the Intel Panther Point PCH. Signed-off-by: Seth Heasley <seth.heasley@intel.com> Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
2011-04-20 23:45:20 +08:00
{ PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
ata: ahci: Rename board_ahci_mobile This board definition was originally created for mobile devices to designate default link power managmeent policy to influence runtime power consumption. As this is interesting for more than just mobile designs, rename the board to `board_ahci_low_power` to make it clear it is about default policy. Reviewed-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Paul Menzel <pmenzel@molgen.mpg.de> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
2022-02-26 01:23:17 +08:00
{ PCI_VDEVICE(INTEL, 0x1e03), board_ahci_low_power }, /* Panther M AHCI */
ahci: AHCI-mode SATA patch for Intel Panther Point DeviceIDs The previously submitted patch was word-wrapped. This patch adds the AHCI-mode SATA DeviceIDs for the Intel Panther Point PCH. Signed-off-by: Seth Heasley <seth.heasley@intel.com> Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
2011-04-20 23:45:20 +08:00
{ PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
{ PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
{ PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
ata: ahci: Rename board_ahci_mobile This board definition was originally created for mobile devices to designate default link power managmeent policy to influence runtime power consumption. As this is interesting for more than just mobile designs, rename the board to `board_ahci_low_power` to make it clear it is about default policy. Reviewed-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Paul Menzel <pmenzel@molgen.mpg.de> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
2022-02-26 01:23:17 +08:00
{ PCI_VDEVICE(INTEL, 0x1e07), board_ahci_low_power }, /* Panther M RAID */
ahci: RAID-mode SATA patch for Intel Panther Point DeviceIDs This patch adds an additional SATA RAID controller DeviceID for the Intel Panther Point PCH. Signed-off-by: Seth Heasley <seth.heasley@intel.com> Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
2011-07-15 07:50:49 +08:00
{ PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
ahci: AHCI-mode SATA patch for Intel Lynx Point DeviceIDs This patch adds the AHCI-mode SATA DeviceIDs for the Intel Lynx Point PCH. Signed-off-by: Seth Heasley <seth.heasley@intel.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2012-01-24 08:27:30 +08:00
{ PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
ata: ahci: Rename board_ahci_mobile This board definition was originally created for mobile devices to designate default link power managmeent policy to influence runtime power consumption. As this is interesting for more than just mobile designs, rename the board to `board_ahci_low_power` to make it clear it is about default policy. Reviewed-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Paul Menzel <pmenzel@molgen.mpg.de> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
2022-02-26 01:23:17 +08:00
{ PCI_VDEVICE(INTEL, 0x8c03), board_ahci_low_power }, /* Lynx M AHCI */
ahci: AHCI-mode SATA patch for Intel Lynx Point DeviceIDs This patch adds the AHCI-mode SATA DeviceIDs for the Intel Lynx Point PCH. Signed-off-by: Seth Heasley <seth.heasley@intel.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2012-01-24 08:27:30 +08:00
{ PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
ata: ahci: Rename board_ahci_mobile This board definition was originally created for mobile devices to designate default link power managmeent policy to influence runtime power consumption. As this is interesting for more than just mobile designs, rename the board to `board_ahci_low_power` to make it clear it is about default policy. Reviewed-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Paul Menzel <pmenzel@molgen.mpg.de> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
2022-02-26 01:23:17 +08:00
{ PCI_VDEVICE(INTEL, 0x8c05), board_ahci_low_power }, /* Lynx M RAID */
ahci: AHCI-mode SATA patch for Intel Lynx Point DeviceIDs This patch adds the AHCI-mode SATA DeviceIDs for the Intel Lynx Point PCH. Signed-off-by: Seth Heasley <seth.heasley@intel.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2012-01-24 08:27:30 +08:00
{ PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
ata: ahci: Rename board_ahci_mobile This board definition was originally created for mobile devices to designate default link power managmeent policy to influence runtime power consumption. As this is interesting for more than just mobile designs, rename the board to `board_ahci_low_power` to make it clear it is about default policy. Reviewed-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Paul Menzel <pmenzel@molgen.mpg.de> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
2022-02-26 01:23:17 +08:00
{ PCI_VDEVICE(INTEL, 0x8c07), board_ahci_low_power }, /* Lynx M RAID */
ahci: AHCI-mode SATA patch for Intel Lynx Point DeviceIDs This patch adds the AHCI-mode SATA DeviceIDs for the Intel Lynx Point PCH. Signed-off-by: Seth Heasley <seth.heasley@intel.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2012-01-24 08:27:30 +08:00
{ PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
ata: ahci: Rename board_ahci_mobile This board definition was originally created for mobile devices to designate default link power managmeent policy to influence runtime power consumption. As this is interesting for more than just mobile designs, rename the board to `board_ahci_low_power` to make it clear it is about default policy. Reviewed-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Paul Menzel <pmenzel@molgen.mpg.de> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
2022-02-26 01:23:17 +08:00
{ PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_low_power }, /* Lynx M RAID */
{ PCI_VDEVICE(INTEL, 0x9c02), board_ahci_low_power }, /* Lynx LP AHCI */
{ PCI_VDEVICE(INTEL, 0x9c03), board_ahci_low_power }, /* Lynx LP AHCI */
{ PCI_VDEVICE(INTEL, 0x9c04), board_ahci_low_power }, /* Lynx LP RAID */
{ PCI_VDEVICE(INTEL, 0x9c05), board_ahci_low_power }, /* Lynx LP RAID */
{ PCI_VDEVICE(INTEL, 0x9c06), board_ahci_low_power }, /* Lynx LP RAID */
{ PCI_VDEVICE(INTEL, 0x9c07), board_ahci_low_power }, /* Lynx LP RAID */
{ PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_low_power }, /* Lynx LP RAID */
{ PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_low_power }, /* Lynx LP RAID */
{ PCI_VDEVICE(INTEL, 0x9dd3), board_ahci_low_power }, /* Cannon Lake PCH-LP AHCI */
ahci: AHCI-mode SATA patch for Intel Avoton DeviceIDs This patch adds the AHCI and RAID-mode SATA DeviceIDs for the Intel Avoton SOC. Signed-off-by: Seth Heasley <seth.heasley@intel.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2013-01-26 04:01:05 +08:00
{ PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
{ PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
{ PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
{ PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
{ PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
{ PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
{ PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
{ PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
ahci: avoton port-disable reset-quirk Avoton AHCI occasionally sees drive probe timeouts at driver load time. When this happens SCR_STATUS indicates device detected, but no D2H FIS reception. Reset the internal link state machines by bouncing port-enable in the PCS register when this occurs. Cc: <stable@vger.kernel.org> Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2015-05-09 03:23:55 +08:00
{ PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */
{ PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */
{ PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */
{ PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */
{ PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */
{ PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */
{ PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */
{ PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */
ahci: remove duplicated PCI device IDs Intel devices 0x2822, 0x2823, 0x2826 and 0x2827 are already on the list as Lewisburg AHCI/RAID. They use same configuration except 0x2822 which has board_ahci_nosntf (for ICH8). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
2021-09-19 17:43:13 +08:00
{ PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg/Lewisburg AHCI*/
ahci: Add a generic 'controller2' RAID id Intel server platforms that support 'RAID', i.e. have platform firmware support for software-RAID metadata + features that the kernel also understands, maintain the same device-ids for RAID from generation to generation. This is in contrast to client platforms that have tended to roll new device-ids every platform generation. However, even though server platform keep the ids there are still unique device-ids per controller instance. To date there have only been 2 controllers on these platforms, but platforms code named Emmitsburg add a third controller. Add the device-id for this third controller and collect it with the other generic server RAID ids. As mentioned here [1], the pain of continuing add new and different device-ids for RAID mode to this file [2] has been heard. Ideally this device-id would not matter and the class code would remain PCI_CLASS_STORAGE_SATA_AHCI regardless of the RAID mode, but other operating systems depend on the class code *not* being AHCI when the device is in RAID mode. That said, going forward there is little reason for new server RAID ids to be added as they can simply reuse one of the existing ids even for a new controller. Server software RAID features continue to be supported on Linux. Client software RAID features continue to be not supported and the recommendation there remains to set the device to AHCI mode in platform firmware. Link: https://lore.kernel.org/all/8e61fb0104422e8d70701e2ddc7b1ca53f009797.camel@intel.com [1] Link: https://lore.kernel.org/all/20201119165022.GA3582@infradead.org/ [2] Cc: Damien Le Moal <damien.lemoal@opensource.wdc.com> Cc: Christoph Hellwig <hch@lst.de> Cc: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com> Reviewed-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
2022-04-21 11:27:26 +08:00
{ PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* *burg SATA0 'RAID' */
{ PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* *burg SATA1 'RAID' */
{ PCI_VDEVICE(INTEL, 0x282f), board_ahci }, /* *burg SATA2 'RAID' */
ahci: Add Intel Rocket Lake PCH-H RAID PCI IDs Add Intel Rocket Lake PCH-H RAID PCI IDs to the list of supported controllers. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Jens Axboe <axboe@kernel.dk>
2020-10-02 17:40:35 +08:00
{ PCI_VDEVICE(INTEL, 0x43d4), board_ahci }, /* Rocket Lake PCH-H RAID */
{ PCI_VDEVICE(INTEL, 0x43d5), board_ahci }, /* Rocket Lake PCH-H RAID */
{ PCI_VDEVICE(INTEL, 0x43d6), board_ahci }, /* Rocket Lake PCH-H RAID */
{ PCI_VDEVICE(INTEL, 0x43d7), board_ahci }, /* Rocket Lake PCH-H RAID */
ahci: Add Device IDs for Intel Wellsburg PCH This patch adds the AHCI-mode SATA Device IDs for the Intel Wellsburg PCH Signed-off-by: James Ralston <james.d.ralston@intel.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2013-02-09 09:34:47 +08:00
{ PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
{ PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
{ PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
{ PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
{ PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
{ PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
{ PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
{ PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
ahci: AHCI-mode SATA patch for Intel Coleto Creek DeviceIDs This patch adds the AHCI-mode SATA DeviceIDs for the Intel Coleto Creek PCH. Signed-off-by: Seth Heasley <seth.heasley@intel.com> Signed-off-by: Tejun Heo <tj@kernel.org> Cc: stable@vger.kernel.org
2013-06-20 07:36:45 +08:00
{ PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
ata: ahci: Rename board_ahci_mobile This board definition was originally created for mobile devices to designate default link power managmeent policy to influence runtime power consumption. As this is interesting for more than just mobile designs, rename the board to `board_ahci_low_power` to make it clear it is about default policy. Reviewed-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Paul Menzel <pmenzel@molgen.mpg.de> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
2022-02-26 01:23:17 +08:00
{ PCI_VDEVICE(INTEL, 0x9c83), board_ahci_low_power }, /* Wildcat LP AHCI */
{ PCI_VDEVICE(INTEL, 0x9c85), board_ahci_low_power }, /* Wildcat LP RAID */
{ PCI_VDEVICE(INTEL, 0x9c87), board_ahci_low_power }, /* Wildcat LP RAID */
{ PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_low_power }, /* Wildcat LP RAID */
ahci: Add Device IDs for Intel 9 Series PCH This patch adds the AHCI mode SATA Device IDs for the Intel 9 Series PCH. Signed-off-by: James Ralston <james.d.ralston@intel.com> Signed-off-by: Tejun Heo <tj@kernel.org> Cc: stable@vger.kernel.org
2014-08-28 05:29:07 +08:00
{ PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
ata: ahci: Rename board_ahci_mobile This board definition was originally created for mobile devices to designate default link power managmeent policy to influence runtime power consumption. As this is interesting for more than just mobile designs, rename the board to `board_ahci_low_power` to make it clear it is about default policy. Reviewed-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Paul Menzel <pmenzel@molgen.mpg.de> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
2022-02-26 01:23:17 +08:00
{ PCI_VDEVICE(INTEL, 0x8c83), board_ahci_low_power }, /* 9 Series M AHCI */
ahci: Add Device IDs for Intel 9 Series PCH This patch adds the AHCI mode SATA Device IDs for the Intel 9 Series PCH. Signed-off-by: James Ralston <james.d.ralston@intel.com> Signed-off-by: Tejun Heo <tj@kernel.org> Cc: stable@vger.kernel.org
2014-08-28 05:29:07 +08:00
{ PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
ata: ahci: Rename board_ahci_mobile This board definition was originally created for mobile devices to designate default link power managmeent policy to influence runtime power consumption. As this is interesting for more than just mobile designs, rename the board to `board_ahci_low_power` to make it clear it is about default policy. Reviewed-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Paul Menzel <pmenzel@molgen.mpg.de> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
2022-02-26 01:23:17 +08:00
{ PCI_VDEVICE(INTEL, 0x8c85), board_ahci_low_power }, /* 9 Series M RAID */
ahci: Add Device IDs for Intel 9 Series PCH This patch adds the AHCI mode SATA Device IDs for the Intel 9 Series PCH. Signed-off-by: James Ralston <james.d.ralston@intel.com> Signed-off-by: Tejun Heo <tj@kernel.org> Cc: stable@vger.kernel.org
2014-08-28 05:29:07 +08:00
{ PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
ata: ahci: Rename board_ahci_mobile This board definition was originally created for mobile devices to designate default link power managmeent policy to influence runtime power consumption. As this is interesting for more than just mobile designs, rename the board to `board_ahci_low_power` to make it clear it is about default policy. Reviewed-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Paul Menzel <pmenzel@molgen.mpg.de> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
2022-02-26 01:23:17 +08:00
{ PCI_VDEVICE(INTEL, 0x8c87), board_ahci_low_power }, /* 9 Series M RAID */
ahci: Add Device IDs for Intel 9 Series PCH This patch adds the AHCI mode SATA Device IDs for the Intel 9 Series PCH. Signed-off-by: James Ralston <james.d.ralston@intel.com> Signed-off-by: Tejun Heo <tj@kernel.org> Cc: stable@vger.kernel.org
2014-08-28 05:29:07 +08:00
{ PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
ata: ahci: Rename board_ahci_mobile This board definition was originally created for mobile devices to designate default link power managmeent policy to influence runtime power consumption. As this is interesting for more than just mobile designs, rename the board to `board_ahci_low_power` to make it clear it is about default policy. Reviewed-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Paul Menzel <pmenzel@molgen.mpg.de> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
2022-02-26 01:23:17 +08:00
{ PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_low_power }, /* 9 Series M RAID */
{ PCI_VDEVICE(INTEL, 0x9d03), board_ahci_low_power }, /* Sunrise LP AHCI */
{ PCI_VDEVICE(INTEL, 0x9d05), board_ahci_low_power }, /* Sunrise LP RAID */
{ PCI_VDEVICE(INTEL, 0x9d07), board_ahci_low_power }, /* Sunrise LP RAID */
ahci: Add Device ID for Intel Sunrise Point PCH This patch adds missing AHCI RAID SATA Device IDs for the Intel Sunrise Point PCH. Signed-off-by: Nanda Kishore Chinna <nanda_kishore_chinna@dell.com> Signed-off-by: Charles Rose <charles_rose@dell.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2015-11-07 04:18:56 +08:00
{ PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */
ata: ahci: Rename board_ahci_mobile This board definition was originally created for mobile devices to designate default link power managmeent policy to influence runtime power consumption. As this is interesting for more than just mobile designs, rename the board to `board_ahci_low_power` to make it clear it is about default policy. Reviewed-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Paul Menzel <pmenzel@molgen.mpg.de> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
2022-02-26 01:23:17 +08:00
{ PCI_VDEVICE(INTEL, 0xa103), board_ahci_low_power }, /* Sunrise M AHCI */
ahci: Add Device IDs for Intel Sunrise Point PCH This patch adds the AHCI-mode SATA Device IDs for the Intel Sunrise Point PCH. Signed-off-by: James Ralston <james.d.ralston@intel.com> Signed-off-by: Tejun Heo <tj@kernel.org> Cc: stable@vger.kernel.org
2014-10-14 06:16:38 +08:00
{ PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
ahci: Add Device ID for Intel Sunrise Point PCH This patch adds missing AHCI RAID SATA Device IDs for the Intel Sunrise Point PCH. Signed-off-by: Nanda Kishore Chinna <nanda_kishore_chinna@dell.com> Signed-off-by: Charles Rose <charles_rose@dell.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2015-11-07 04:18:56 +08:00
{ PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */
ata: ahci: Rename board_ahci_mobile This board definition was originally created for mobile devices to designate default link power managmeent policy to influence runtime power consumption. As this is interesting for more than just mobile designs, rename the board to `board_ahci_low_power` to make it clear it is about default policy. Reviewed-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Paul Menzel <pmenzel@molgen.mpg.de> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
2022-02-26 01:23:17 +08:00
{ PCI_VDEVICE(INTEL, 0xa107), board_ahci_low_power }, /* Sunrise M RAID */
ahci: Add Device IDs for Intel Sunrise Point PCH This patch adds the AHCI-mode SATA Device IDs for the Intel Sunrise Point PCH. Signed-off-by: James Ralston <james.d.ralston@intel.com> Signed-off-by: Tejun Heo <tj@kernel.org> Cc: stable@vger.kernel.org
2014-10-14 06:16:38 +08:00
{ PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
ahci: Order SATA device IDs for codename Lewisburg This change was to preserve the ascending order of device IDs. There was an exception with the first two Lewisburg device IDs to keep all device IDs of the same kind grouped by code name. Signed-off-by: Alexandra Yates <alexandra.yates@linux.intel.com> signed-off-by: Tejun Heo <tj@kernel.org>
2015-11-17 00:22:16 +08:00
{ PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/
{ PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/
Adding Intel Lewisburg device IDs for SATA This patch complements the list of device IDs previously added for lewisburg sata. Signed-off-by: Alexandra Yates <alexandra.yates@linux.intel.com> Signed-off-by: Tejun Heo <tj@kernel.org> Cc: stable@vger.kernel.org
2016-02-18 11:36:20 +08:00
{ PCI_VDEVICE(INTEL, 0xa1d2), board_ahci }, /* Lewisburg RAID*/
{ PCI_VDEVICE(INTEL, 0xa1d6), board_ahci }, /* Lewisburg RAID*/
ahci: Order SATA device IDs for codename Lewisburg This change was to preserve the ascending order of device IDs. There was an exception with the first two Lewisburg device IDs to keep all device IDs of the same kind grouped by code name. Signed-off-by: Alexandra Yates <alexandra.yates@linux.intel.com> signed-off-by: Tejun Heo <tj@kernel.org>
2015-11-17 00:22:16 +08:00
{ PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/
{ PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/
Adding Intel Lewisburg device IDs for SATA This patch complements the list of device IDs previously added for lewisburg sata. Signed-off-by: Alexandra Yates <alexandra.yates@linux.intel.com> Signed-off-by: Tejun Heo <tj@kernel.org> Cc: stable@vger.kernel.org
2016-02-18 11:36:20 +08:00
{ PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/
{ PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/
ahci: Add Intel Cannon Lake PCH-H PCI ID Add Intel Cannon Lake PCH-H PCI ID to the list of supported controllers. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Tejun Heo <tj@kernel.org> Cc: stable@vger.kernel.org
2018-01-11 20:55:50 +08:00
{ PCI_VDEVICE(INTEL, 0xa356), board_ahci }, /* Cannon Lake PCH-H RAID */
ahci: Add Intel Comet Lake H RAID PCI ID Add the PCI ID to the driver list to support this new device. Cc: stable@vger.kernel.org Signed-off-by: Kai-Heng Feng <kai.heng.feng@canonical.com> Signed-off-by: Jens Axboe <axboe@kernel.dk>
2020-02-27 20:28:22 +08:00
{ PCI_VDEVICE(INTEL, 0x06d7), board_ahci }, /* Comet Lake-H RAID */
ahci: Add Intel Comet Lake PCH-V PCI ID Add Intel Comet Lake PCH-V PCI ID to the list of supported controllers. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Jens Axboe <axboe@kernel.dk>
2020-02-28 18:50:48 +08:00
{ PCI_VDEVICE(INTEL, 0xa386), board_ahci }, /* Comet Lake PCH-V RAID */
ata: ahci: Rename board_ahci_mobile This board definition was originally created for mobile devices to designate default link power managmeent policy to influence runtime power consumption. As this is interesting for more than just mobile designs, rename the board to `board_ahci_low_power` to make it clear it is about default policy. Reviewed-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Paul Menzel <pmenzel@molgen.mpg.de> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
2022-02-26 01:23:17 +08:00
{ PCI_VDEVICE(INTEL, 0x0f22), board_ahci_low_power }, /* Bay Trail AHCI */
{ PCI_VDEVICE(INTEL, 0x0f23), board_ahci_low_power }, /* Bay Trail AHCI */
{ PCI_VDEVICE(INTEL, 0x22a3), board_ahci_low_power }, /* Cherry Tr. AHCI */
{ PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_low_power }, /* ApolloLake AHCI */
{ PCI_VDEVICE(INTEL, 0x34d3), board_ahci_low_power }, /* Ice Lake LP AHCI */
{ PCI_VDEVICE(INTEL, 0x02d3), board_ahci_low_power }, /* Comet Lake PCH-U AHCI */
{ PCI_VDEVICE(INTEL, 0x02d7), board_ahci_low_power }, /* Comet Lake PCH RAID */
ata: ahci: Add Elkhart Lake AHCI controller Elkhart Lake is the successor of Apollo Lake and Gemini Lake. These CPUs and their PCHs are used in mobile and embedded environments. With this patch I suggest that Elkhart Lake SATA controllers [1] should use the default LPM policy for mobile chipsets. The disadvantage of missing hot-plug support with this setting should not be an issue, as those CPUs are used in embedded environments and not in servers with hot-plug backplanes. We discovered that the Elkhart Lake SATA controllers have been missing in ahci.c after a customer reported the throttling of his SATA SSD after a short period of higher I/O. We determined the high temperature of the SSD controller in idle mode as the root cause for that. Depending on the used SSD, we have seen up to 1.8 Watt lower system idle power usage and up to 30°C lower SSD controller temperatures in our tests, when we set med_power_with_dipm manually. I have provided a table showing seven different SATA SSDs from ATP, Intel/Solidigm and Samsung [2]. Intel lists a total of 3 SATA controller IDs (4B60, 4B62, 4B63) in [1] for those mobile PCHs. This commit just adds 0x4b63 as I do not have test systems with 0x4b60 and 0x4b62 SATA controllers. I have tested this patch with a system which uses 0x4b63 as SATA controller. [1] https://sata-io.org/product/8803 [2] https://www.thomas-krenn.com/en/wiki/SATA_Link_Power_Management#Example_LES_v4 Signed-off-by: Werner Fischer <devlists@wefi.net> Cc: stable@vger.kernel.org Signed-off-by: Damien Le Moal <dlemoal@kernel.org>
2023-08-29 19:33:58 +08:00
/* Elkhart Lake IDs 0x4b60 & 0x4b62 https://sata-io.org/product/8803 not tested yet */
{ PCI_VDEVICE(INTEL, 0x4b63), board_ahci_low_power }, /* Elkhart Lake AHCI */
ata: ahci: Add Intel Alder Lake-P AHCI controller to low power chipsets list Intel Alder Lake-P AHCI controller needs to be added to the mobile chipsets list in order to have link power management enabled. Without this the CPU cannot enter lower power C-states making idle power consumption high. Cc: Koba Ko <koba.ko@canonical.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Damien Le Moal <dlemoal@kernel.org>
2023-09-25 16:05:38 +08:00
{ PCI_VDEVICE(INTEL, 0x7ae2), board_ahci_low_power }, /* Alder Lake-P AHCI */
[libata] ahci: Add NVIDIA PCI IDs. Based on a patch by Andrew Chew @ NVIDIA. Signed-off-by: Jeff Garzik <jeff@garzik.org>
2006-06-23 11:05:36 +08:00
ahci/pata_jmicron: match class not function number Make jmiron_ata quirk update pdev->class after programming the device and update ahci and pata_jmicron such that they match class code instead of checking function number manually. For ahci, it matches for vendor and class. For pata_jmicron, it matches vendor, device and class as IDE class isn't as well defined as AHCI class. This makes jmicron device matching more conventional and script friendly. Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-02-26 19:24:03 +08:00
/* JMicron 360/1/3/5/6, match class to avoid IDE function */
{ PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
ahci: Add JMicron 362 device IDs The JMicron JMB362 controller supports AHCI only, but some revisions use the IDE class code. These need to be matched by device ID. These additions have apparently been included by QNAP in their NAS devices using these controllers. References: http://bugs.debian.org/634180 Signed-off-by: Ben Hutchings <ben@decadent.org.uk> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2012-09-10 08:09:04 +08:00
/* JMicron 362B and 362C have an AHCI function with IDE class code */
{ PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
{ PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
PCI: Disable async suspend/resume for JMicron multi-function SATA/AHCI On multi-function JMicron SATA/PATA/AHCI devices, the PATA controller at function 1 doesn't work if it is powered on before the SATA controller at function 0. The result is that PATA doesn't work after resume, and we print messages like this: pata_jmicron 0000:02:00.1: Refused to change power state, currently in D3 irq 17: nobody cared (try booting with the "irqpoll" option) Async resume was introduced in v3.15 by 76569faa62c4 ("PM / sleep: Asynchronous threads for resume_noirq"). Prior to that, we powered on the functions in order, so this problem shouldn't happen. e6b7e41cdd8c ("ata: Disabling the async PM for JMicron chip 363/361") solved the problem for JMicron 361 and 363 devices. With async suspend disabled, we always power on function 0 before function 1. Barto then reported the same problem with a JMicron 368 (see comment #57 in the bugzilla). Rather than extending the blacklist piecemeal, disable async suspend for all JMicron multi-function SATA/PATA/AHCI devices. This quirk could stay in the ahci and pata_jmicron drivers, but it's likely the problem will occur even if pata_jmicron isn't loaded until after the suspend/resume. Making it a PCI quirk ensures that we'll preserve the power-on order even if the drivers aren't loaded. [bhelgaas: changelog, limit to multi-function, limit to IDE/ATA] Link: https://bugzilla.kernel.org/show_bug.cgi?id=81551 Reported-and-tested-by: Barto <mister.freeman@laposte.net> Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: stable@vger.kernel.org # v3.15+
2015-08-25 04:27:11 +08:00
/* May need to update quirk_jmicron_async_suspend() for additions */
[libata] ahci: Add NVIDIA PCI IDs. Based on a patch by Andrew Chew @ NVIDIA. Signed-off-by: Jeff Garzik <jeff@garzik.org>
2006-06-23 11:05:36 +08:00
/* ATI */
ahci.c: remove non-existing SB600 raid id (re-send) SB600 RAID and SB600 SATA is the same controller and share the same PCI ID 0x4380. There is no such PCI ID 0x4381. Signed-off-by: Conke Hu <conke.hu@gmail.com> --------- Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-04-11 18:23:14 +08:00
{ PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
[libata] ahci: AMD SB700/SB800 SATA support 64bit DMA SB700 SATA controller can support 64 bit DMA, the previous commit badc2341579511a247f5993865aa68379e283c5c was added with careless reference to SB600, which should be modified by this patch. Signed-off-by: Shane Huang <shane.huang@amd.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2008-02-22 21:00:31 +08:00
{ PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
{ PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
{ PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
{ PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
{ PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
{ PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
[libata] ahci: Add NVIDIA PCI IDs. Based on a patch by Andrew Chew @ NVIDIA. Signed-off-by: Jeff Garzik <jeff@garzik.org>
2006-06-23 11:05:36 +08:00
ahci: Add support for Amazon's Annapurna Labs SATA controller This patch adds basic support for Amazon's Annapurna Labs SATA controller. Signed-off-by: Hanna Hawa <hhhawa@amazon.com> Signed-off-by: Jens Axboe <axboe@kernel.dk>
2019-10-17 22:46:53 +08:00
/* Amazon's Annapurna Labs support */
{ PCI_DEVICE(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031),
.class = PCI_CLASS_STORAGE_SATA_AHCI,
.class_mask = 0xffffff,
board_ahci_al },
ahci: Add AMD SB900 SATA/IDE controller device IDs Add AMD SB900 SATA/IDE controller device IDs. Signed-off-by: Shane Huang <shane.huang@amd.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-07-29 11:34:49 +08:00
/* AMD */
ahci / atiixp / pci quirks: rename AMD SB900 into Hudson-2 This patch renames the code name SB900 into Hudson-2 Signed-off-by: Shane Huang <shane.huang@amd.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-10-13 11:14:00 +08:00
{ PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
ata: ahci: Add support for AMD A85 FCH (Hudson D4) Add support for the AMD A85 FCH (Hudson D4) AHCI adapter. Since this adapter does not require the default 200 ms debounce delay in sata_link_resume(), create a new board board_ahci_no_debounce_delay with the link flag ATA_LFLAG_NO_DEBOUNCE_DELAY, and, for now, configure the AMD A85 FCH (Hudson D4) to use it. On the ASUS F2A85-M PRO it reduces the Linux kernel boot time by the expected 200 ms from 787 ms to 585 ms. Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Cc: Tejun Heo <tj@kernel.org> Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
2022-01-05 23:36:18 +08:00
{ PCI_VDEVICE(AMD, 0x7801), board_ahci_no_debounce_delay }, /* AMD Hudson-2 (AHCI mode) */
ahci: Add AMD CZ SATA device ID To add AMD CZ SATA controller device ID of IDE mode. [bhelgaas: drop pci_ids.h update] Signed-off-by: Shane Huang <shane.huang@amd.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Tejun Heo <tj@kernel.org> Cc: stable@vger.kernel.org
2013-06-03 18:24:10 +08:00
{ PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
ata: ahci: Rename board_ahci_mobile This board definition was originally created for mobile devices to designate default link power managmeent policy to influence runtime power consumption. As this is interesting for more than just mobile designs, rename the board to `board_ahci_low_power` to make it clear it is about default policy. Reviewed-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Paul Menzel <pmenzel@molgen.mpg.de> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
2022-02-26 01:23:17 +08:00
{ PCI_VDEVICE(AMD, 0x7901), board_ahci_low_power }, /* AMD Green Sardine */
ahci: Add AMD SB900 SATA/IDE controller device IDs Add AMD SB900 SATA/IDE controller device IDs. Signed-off-by: Shane Huang <shane.huang@amd.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-07-29 11:34:49 +08:00
/* AMD is using RAID class only for ahci controllers */
{ PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
ahci: Add support for Dell S140 and later controllers This patch enables support for Dell S140 and later controllers that use Intel's PCHs configured as PCI_CLASS_STORAGE_RAID. Reviewed-by: Mika Westerberg <mika.westerberg@intel.com> Signed-off-by: Charles Rose <charles.rose@dell.com> Link: https://lore.kernel.org/r/20210615190801.1744466-1-charles.rose@dell.com Signed-off-by: Jens Axboe <axboe@kernel.dk>
2021-06-16 03:08:01 +08:00
/* Dell S140/S150 */
{ PCI_VENDOR_ID_INTEL, PCI_ANY_ID, PCI_SUBVENDOR_ID_DELL, PCI_ANY_ID,
PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
ahci: Add AMD SB900 SATA/IDE controller device IDs Add AMD SB900 SATA/IDE controller device IDs. Signed-off-by: Shane Huang <shane.huang@amd.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-07-29 11:34:49 +08:00
[libata] ahci: Add NVIDIA PCI IDs. Based on a patch by Andrew Chew @ NVIDIA. Signed-off-by: Jeff Garzik <jeff@garzik.org>
2006-06-23 11:05:36 +08:00
/* VIA */
[libata] Use new PCI_VDEVICE() macro to dramatically shorten ID lists Signed-off-by: Jeff Garzik <jeff@garzik.org>
2006-09-28 10:20:11 +08:00
{ PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
ahci: add PCI ID for new VIA chip Add PCI ID for new VIA chip. Original patch is from Maarten Vanraes. Signed-off-by: Tejun Heo <htejun@gmail.com> Cc: Maarten Vanraes <maarten.vanraes@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-04-11 16:27:14 +08:00
{ PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
[libata] ahci: Add NVIDIA PCI IDs. Based on a patch by Andrew Chew @ NVIDIA. Signed-off-by: Jeff Garzik <jeff@garzik.org>
2006-06-23 11:05:36 +08:00
/* NVIDIA */
ahci: workarounds for mcp65 MCP65 ahci can do NCQ but doesn't set the CAP bit and rev A0 and A1 can't do MSI but have MSI capability. Implement AHCI_HFLAG_YES_NCQ and apply appropriate workarounds. Signed-off-by: Tejun Heo <htejun@gmail.com> Cc: Peer Chen <pchen@nvidia.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2008-06-09 23:13:04 +08:00
{ PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
{ PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
{ PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
{ PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
{ PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
{ PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
{ PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
{ PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
ahci: clean up board IDs ahci over time has grown a number of board IDs and it's a bit of mess right now. Clean it up such that, * board_id_* now live in a separate enum board_ids and numbers are assigned automatically. * Board IDs assigned to features are separated from the ones assigned to specific implementations and both are ordered alphabetically. * For NV MCPs, define per-generation alias board_ids and assign matching aliases in the pci id table. This makes mcp_linux, 67-73 use board_ahci_mcp65 instead of board_ahci_yesncq. Both are identical in content. * Kill now unused board_ahci_nopmp and board_ahci_yesncq. This patch doesn't cause any functional change but will make future changes to board_ids and quirks much less painful. Signed-off-by: Tejun Heo <tj@kernel.org> Cc: Peer Chen <pchen@nvidia.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-03-29 09:32:39 +08:00
{ PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
{ PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
{ PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
{ PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
{ PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
{ PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
{ PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
{ PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
{ PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
{ PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
{ PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
{ PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
{ PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
{ PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
{ PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
{ PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
{ PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
{ PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
{ PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
{ PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
{ PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
{ PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
{ PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
{ PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
{ PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
{ PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
{ PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
{ PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
{ PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
{ PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
{ PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
{ PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
{ PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
{ PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
{ PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
{ PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
{ PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
{ PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
{ PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
{ PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
{ PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
{ PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
{ PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
{ PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
{ PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
{ PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
{ PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
{ PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
{ PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
{ PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
{ PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
{ PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
{ PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
{ PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
{ PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
{ PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
{ PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
{ PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
{ PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
{ PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
{ PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
{ PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
{ PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
{ PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
{ PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
{ PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
{ PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
{ PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
{ PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
{ PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
{ PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
{ PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
{ PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
{ PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
{ PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
{ PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
[libata] ahci: Add NVIDIA PCI IDs. Based on a patch by Andrew Chew @ NVIDIA. Signed-off-by: Jeff Garzik <jeff@garzik.org>
2006-06-23 11:05:36 +08:00
[libata] ahci: add SiS PCI IDs Signed-off-by: David Wang <touch@sis.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2006-07-29 16:10:14 +08:00
/* SiS */
ahci: sis controllers actually can do PMP SIS controllers were blacklisted for PMP as enabling it made device detection fail whether the device was PMP or not - the natural conclusion was the controller chokes on SRST w/ pmp==15. However, it turned out that the controller just didn't like issuing SRST after hardreset w/o clearing SError first. Interestingly, the SRST itself succeeds but the following commands fail. If SError is cleared between hardreset and SRST, which is the default behavior now, everything works fine and SIS controllers work with PMPs happily. Remove PMP blacklisting for SIS AHCIs. Signed-off-by: Tejun Heo <tj@kernel.org> Cc: Piter PUNK <piterpunk@slackware.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2008-08-01 11:51:43 +08:00
{ PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
{ PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
{ PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
[libata] ahci: add SiS PCI IDs Signed-off-by: David Wang <touch@sis.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2006-07-29 16:10:14 +08:00
ahci: support the STA2X11 I/O Hub The AHCI controller found in the STA2X11 chip uses BAR number 0 instead of 5. Also, the chip's fixup code sets a special DMA mask for all of its PCI functions, and the mask must be preserved here. Signed-off-by: Alessandro Rubini <rubini@gnudd.com> Acked-by: Giancarlo Asnaghi <giancarlo.asnaghi@st.com> Cc: Alan Cox <alan@linux.intel.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2012-01-06 20:33:39 +08:00
/* ST Microelectronics */
{ PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
[libata] AHCI: Add support for Marvell AHCI-like chips (initially 6145) Add support for the SATA portion of Marvell's AHCI-compatible chips. The PATA port capability, also available via AHCI, is disabled until support is completed. NCQ and PCI MSI are disabled by default. Marvell says "we use NCQ" in their drivers but "we do not use PCI MSI." Theoretically that implies we need to fix ahci.c to work with Marvell NCQ, but one wonders why Marvell NCQ is any different from other AHCI chips. Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-07-08 14:29:42 +08:00
/* Marvell */
{ PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
ahci: Add Marvell 6121 SATA support Signed-off-by: Jose Alberto Reguero <jareguero@telefonica.net> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2008-03-14 06:22:24 +08:00
{ PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
ahci: Use PCI_VENDOR_ID_MARVELL_EXT for 0x1b4b With the 0x1b4b vendor ID #define in place, convert hard-coded ID values. Signed-off-by: Myron Stowe <myron.stowe@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jeff Garzik <jgarzik@pobox.com>
2013-04-09 01:32:49 +08:00
{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
ahci: add HFLAG_YES_FBS and apply it to 88SE9128 Commit 5f173107ecad83a50 added HFLAG_YES_FBS workaround for 88SE9128 (1b4b:9123). However, that change inadvertently caused the legacy IDE interface of the controller (with the same pci id) to become associated with the AHCI driver as well, causing the driver to try to bring the interface up in vain. Fix that by matching against class as well. Signed-off-by: Anssi Hannula <anssi.hannula@iki.fi> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2011-01-19 09:03:26 +08:00
.class = PCI_CLASS_STORAGE_SATA_AHCI,
.class_mask = 0xffffff,
ahci: add HFLAG_YES_FBS and apply it to 88SE9128 88SE9128 can do FBS and sets it in HOST_CAP but forgets to set FBSCP in PORT_CMD. Implement AHCI_HFLAG_YES_FBS and apply it to 88SE9128. Signed-off-by: Tejun Heo <tj@kernel.org> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-07-24 22:53:48 +08:00
.driver_data = board_ahci_yes_fbs }, /* 88se9128 */
ahci: Use PCI_VENDOR_ID_MARVELL_EXT for 0x1b4b With the 0x1b4b vendor ID #define in place, convert hard-coded ID values. Signed-off-by: Myron Stowe <myron.stowe@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jeff Garzik <jgarzik@pobox.com>
2013-04-09 01:32:49 +08:00
{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
ahci: recognize Marvell 88se9125 PCIe SATA 6.0 Gb/s controller Recognize Marvell 88SE9125 PCIe SATA 6.0 Gb/s controller. Signed-off-by: Per Jessen <per@computer.org> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2011-02-08 20:54:32 +08:00
.driver_data = board_ahci_yes_fbs }, /* 88se9125 */
ahci: add PCI ID for Marvell 88SE9170 SATA controller This patch adds support for the PCI ID provided by the Marvell 88SE9170 SATA controller. Signed-off-by: Simon Guinot <sguinot@lacie.com> Signed-off-by: Tejun Heo <tj@kernel.org> Cc: stable@vger.kernel.org
2013-12-23 20:24:35 +08:00
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
.driver_data = board_ahci_yes_fbs }, /* 88se9170 */
ahci: Use PCI_VENDOR_ID_MARVELL_EXT for 0x1b4b With the 0x1b4b vendor ID #define in place, convert hard-coded ID values. Signed-off-by: Myron Stowe <myron.stowe@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jeff Garzik <jgarzik@pobox.com>
2013-04-09 01:32:49 +08:00
{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
ahci: Detect Marvell 88SE9172 SATA controller The Marvell 88SE9172 SATA controller (PCI ID 1b4b 917a) already worked once it was detected, but was missing an ahci_pci_tbl entry. Boot tested on a Gigabyte Z68X-UD3H-B3 motherboard. Signed-off-by: Matt Johnson <johnso87@illinois.edu> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2012-04-27 14:42:30 +08:00
.driver_data = board_ahci_yes_fbs }, /* 88se9172 */
ahci: add an observed PCI ID for Marvell 88se9172 SATA controller A third possible PCI ID, as personally observed, and found in the pci.ids list. Signed-off-by: George Spelvin <linux@horizon.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2013-05-29 09:20:35 +08:00
{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
ahci: add pcid for Marvel 0x9182 controller Keystone K2E EVM uses Marvel 0x9182 controller. This requires support for the ID in the ahci driver. Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Tejun Heo <tj@kernel.org> Cc: Santosh Shilimkar <santosh.shilimkar@ti.com> Cc: stable@vger.kernel.org
2014-09-06 01:21:00 +08:00
.driver_data = board_ahci_yes_fbs }, /* 88se9182 */
{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
ahci: add an observed PCI ID for Marvell 88se9172 SATA controller A third possible PCI ID, as personally observed, and found in the pci.ids list. Signed-off-by: George Spelvin <linux@horizon.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2013-05-29 09:20:35 +08:00
.driver_data = board_ahci_yes_fbs }, /* 88se9172 */
ahci: Use PCI_VENDOR_ID_MARVELL_EXT for 0x1b4b With the 0x1b4b vendor ID #define in place, convert hard-coded ID values. Signed-off-by: Myron Stowe <myron.stowe@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jeff Garzik <jgarzik@pobox.com>
2013-04-09 01:32:49 +08:00
{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
ahci: Add alternate identifier for the 88SE9172 This can also appear as 0x9192. Reported in bugzilla and confirmed with the board documentation for these boards. Resolves-bug: https://bugzilla.kernel.org/show_bug.cgi?id=42970 Signed-off-by: Alan Cox <alan@linux.intel.com> Cc: The Stables <stable@vger.kernel.org> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2012-09-04 23:07:18 +08:00
.driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
ahci: add PCI ID for Marvell 88SE91A0 SATA Controller Add support for Marvell Technology Group Ltd. 88SE91A0 SATA 6Gb/s Controller by adding its PCI ID. Signed-off-by: Andreas Schrägle <ajs124.ajs124@gmail.com> Signed-off-by: Tejun Heo <tj@kernel.org> Cc: stable@vger.kernel.org
2014-05-24 22:35:43 +08:00
{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
.driver_data = board_ahci_yes_fbs },
ahci: Add Marvell 88se91a2 device id Add device id for Marvell 88se91a2 Signed-off-by: Johannes Thumshirn <jthumshirn@suse.de> Signed-off-by: Tejun Heo <tj@kernel.org>
2015-10-20 15:31:22 +08:00
{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */
.driver_data = board_ahci_yes_fbs },
ahci: Use PCI_VENDOR_ID_MARVELL_EXT for 0x1b4b With the 0x1b4b vendor ID #define in place, convert hard-coded ID values. Signed-off-by: Myron Stowe <myron.stowe@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jeff Garzik <jgarzik@pobox.com>
2013-04-09 01:32:49 +08:00
{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
ahci: add another PCI ID for marvell 1b4b:91a3 seems to be another PCI ID for marvell ahci. Add it. Reported and tested in the following thread. http://thread.gmane.org/gmane.linux.kernel/1068354 Signed-off-by: Tejun Heo <tj@kernel.org> Reported-by: Borislav Petkov <bp@alien8.de> Reported-by: Alessandro Tagliapietra <tagliapietra.alessandro@gmail.com> Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
2010-11-29 22:57:14 +08:00
.driver_data = board_ahci_yes_fbs },
ahci: add Marvell 9230 to the AHCI PCI device list Tested with a DAWICONTROL DC-624e on 3.10.10 Signed-off-by: Samir Benmendil <samir.benmendil@gmail.com> Signed-off-by: Tejun Heo <tj@kernel.org> Reviewed-by: Levente Kurusa <levex@linux.com> Cc: stable@vger.kernel.org
2013-11-18 06:56:17 +08:00
{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
.driver_data = board_ahci_yes_fbs },
ata: ahci: Skip 200 ms debounce delay for Marvell 88SE9235 The 200 ms delay before debouncing the PHY in `sata_link_resume()` is not needed for the Marvell 88SE9235. $ lspci -nn -s 0021:0e:00.0 0021:0e:00.0 SATA controller [0106]: Marvell Technology Group Ltd. 88SE9235 PCIe 2.0 x2 4-port SATA 6 Gb/s Controller [1b4b:9235] (rev 11) So, remove it using the board_ahci_no_debounce_delay board definition. Tested on IBM S822LC with current Linux 5.17-rc1: Currently, without this patch (with 200 ms delay), device probe for ata1 takes 485 ms: [ 3.358158] ata1: SATA max UDMA/133 abar m2048@0x3fe881000000 port 0x3fe881000100 irq 39 [ 3.358175] ata2: SATA max UDMA/133 abar m2048@0x3fe881000000 port 0x3fe881000180 irq 39 [ 3.358191] ata3: SATA max UDMA/133 abar m2048@0x3fe881000000 port 0x3fe881000200 irq 39 [ 3.358207] ata4: SATA max UDMA/133 abar m2048@0x3fe881000000 port 0x3fe881000280 irq 39 […] [ 3.677542] ata3: SATA link down (SStatus 0 SControl 300) [ 3.677719] ata4: SATA link down (SStatus 0 SControl 300) [ 3.839242] ata2: SATA link up 6.0 Gbps (SStatus 133 SControl 300) [ 3.839828] ata2.00: ATA-10: ST1000NX0313 00LY266 00LY265IBM, BE33, max UDMA/133 [ 3.840029] ata2.00: 1953525168 sectors, multi 0: LBA48 NCQ (depth 32), AA [ 3.841796] ata2.00: configured for UDMA/133 [ 3.843231] ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300) [ 3.844083] ata1.00: ATA-10: ST1000NX0313 00LY266 00LY265IBM, BE33, max UDMA/133 [ 3.844313] ata1.00: 1953525168 sectors, multi 0: LBA48 NCQ (depth 32), AA [ 3.846043] ata1.00: configured for UDMA/133 With this patch (no delay) device probe for ata1 takes 273 ms: [ 3.624259] ata1: SATA max UDMA/133 abar m2048@0x3fe881000000 port 0x3f e881000100 irq 39 [ 3.624436] ata2: SATA max UDMA/133 abar m2048@0x3fe881000000 port 0x3f e881000180 irq 39 [ 3.624452] ata3: SATA max UDMA/133 abar m2048@0x3fe881000000 port 0x3f e881000200 irq 39 [ 3.624468] ata4: SATA max UDMA/133 abar m2048@0x3fe881000000 port 0x3f e881000280 irq 39 […] [ 3.731966] ata3: SATA link down (SStatus 0 SControl 300) [ 3.732069] ata4: SATA link down (SStatus 0 SControl 300) [ 3.897448] ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300) [ 3.897678] ata2: SATA link up 6.0 Gbps (SStatus 133 SControl 300) [ 3.898140] ata1.00: ATA-10: ST1000NX0313 00LY266 00LY265IBM, BE33, max UDMA/133 [ 3.898175] ata2.00: ATA-10: ST1000NX0313 00LY266 00LY265IBM, BE33, max UDMA/133 [ 3.898287] ata1.00: 1953525168 sectors, multi 0: LBA48 NCQ (depth 32), AA [ 3.898349] ata2.00: 1953525168 sectors, multi 0: LBA48 NCQ (depth 32), AA [ 3.900070] ata1.00: configured for UDMA/133 [ 3.900166] ata2.00: configured for UDMA/133 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
2022-02-01 15:12:23 +08:00
{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9235),
.driver_data = board_ahci_no_debounce_delay },
ahci: Add PCI-id for the Highpoint Rocketraid 644L card Like the Highpoint Rocketraid 642L and cards using a Marvel 88SE9235 controller in general, this RAID card also supports AHCI mode and short of a custom driver, this is the only way to make it work under Linux. Note that even though the card is called to 644L, it has a product-id of 0x0645. Cc: stable@vger.kernel.org BugLink: https://bugzilla.redhat.com/show_bug.cgi?id=1534106 Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Tejun Heo <tj@kernel.org> Acked-by: Bjorn Helgaas <bhelgaas@google.com>
2018-03-02 18:36:32 +08:00
{ PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642), /* highpoint rocketraid 642L */
.driver_data = board_ahci_yes_fbs },
{ PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0645), /* highpoint rocketraid 644L */
ahci: Add Device ID for HighPoint RocketRaid 642L This device normally comes with a proprietary driver, using a web GUI to configure RAID: http://www.highpoint-tech.com/USA_new/series_rr600-download.htm But thankfully it also works out of the box with the AHCI driver, being just a Marvell 88SE9235. Devices 640L, 644L, 644LS should also be supported but not tested here. Signed-off-by: Jérôme Carretero <cJ-ko@zougloub.eu> Signed-off-by: Tejun Heo <tj@kernel.org> Cc: stable@vger.kernel.org
2014-06-04 02:56:25 +08:00
.driver_data = board_ahci_yes_fbs },
[libata] AHCI: Add support for Marvell AHCI-like chips (initially 6145) Add support for the SATA portion of Marvell's AHCI-compatible chips. The PATA port capability, also available via AHCI, is disabled until support is completed. NCQ and PCI MSI are disabled by default. Marvell says "we use NCQ" in their drivers but "we do not use PCI MSI." Theoretically that implies we need to fix ahci.c to work with Marvell NCQ, but one wonders why Marvell NCQ is any different from other AHCI chips. Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-07-08 14:29:42 +08:00
ahci: Add support for Promise PDC42819 Add an appropriate entry for the Promise PDC42819 controller. It has an AHCI mode and so far works correctly with board_ahci. This chip is found on Promise's FastTrak TX2650 (2 port) and TX4650 (4 port) software-based RAID cards (for which there is a binary driver, t3sas) and can be found on some motherboards, for example the MSI K9A2 Platinum, which calls the chip a Promise T3 controller. Although this controller also supports SAS devices, its default bootup mode is AHCI and the binary driver has to do some magic to get the chip into the appropriate mode to drive SAS disks. Seeing as no documentation is provided by Promise, adding this entry to the ahci driver allows the controller to be useful to people as a SATA controller (with no ill effects on the system if a SAS disk is connected - probing of the port just times out with "link online but device misclassified"), without having to resort to using the binary driver. Users who require SAS or the proprietary software raid can get this functionality using the binary driver. Signed-off-by: Mark Nelson <mdnelson8@gmail.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2008-10-23 11:08:16 +08:00
/* Promise */
{ PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
ahci: add support for the Promise FastTrak TX8660 SATA HBA (ahci mode) Add support of the Promise FastTrak TX8660 SATA HBA in ahci mode by registering the board in the ahci_pci_tbl[]. Note: this HBA also provide a hardware RAID mode when activated in BIOS but specific drivers from the manufacturer are required in this case. Signed-off-by: Romain Degez <romain.degez@gmail.com> Tested-by: Romain Degez <romain.degez@gmail.com> Signed-off-by: Tejun Heo <tj@kernel.org> Cc: stable@vger.kernel.org
2014-07-12 00:08:13 +08:00
{ PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
ahci: Add support for Promise PDC42819 Add an appropriate entry for the Promise PDC42819 controller. It has an AHCI mode and so far works correctly with board_ahci. This chip is found on Promise's FastTrak TX2650 (2 port) and TX4650 (4 port) software-based RAID cards (for which there is a binary driver, t3sas) and can be found on some motherboards, for example the MSI K9A2 Platinum, which calls the chip a Promise T3 controller. Although this controller also supports SAS devices, its default bootup mode is AHCI and the binary driver has to do some magic to get the chip into the appropriate mode to drive SAS disks. Seeing as no documentation is provided by Promise, adding this entry to the ahci driver allows the controller to be useful to people as a SATA controller (with no ill effects on the system if a SAS disk is connected - probing of the port just times out with "link online but device misclassified"), without having to resort to using the binary driver. Users who require SAS or the proprietary software raid can get this functionality using the binary driver. Signed-off-by: Mark Nelson <mdnelson8@gmail.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2008-10-23 11:08:16 +08:00
ahci: add 43-bit DMA address quirk for ASMedia ASM1061 controllers With one of the on-board ASM1061 AHCI controllers (1b21:0612) on an ASUSTeK Pro WS WRX80E-SAGE SE WIFI mainboard, a controller hang was observed that was immediately preceded by the following kernel messages: ahci 0000:28:00.0: Using 64-bit DMA addresses ahci 0000:28:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0035 address=0x7fffff00000 flags=0x0000] ahci 0000:28:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0035 address=0x7fffff00300 flags=0x0000] ahci 0000:28:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0035 address=0x7fffff00380 flags=0x0000] ahci 0000:28:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0035 address=0x7fffff00400 flags=0x0000] ahci 0000:28:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0035 address=0x7fffff00680 flags=0x0000] ahci 0000:28:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0035 address=0x7fffff00700 flags=0x0000] The first message is produced by code in drivers/iommu/dma-iommu.c which is accompanied by the following comment that seems to apply: /* * Try to use all the 32-bit PCI addresses first. The original SAC vs. * DAC reasoning loses relevance with PCIe, but enough hardware and * firmware bugs are still lurking out there that it's safest not to * venture into the 64-bit space until necessary. * * If your device goes wrong after seeing the notice then likely either * its driver is not setting DMA masks accurately, the hardware has * some inherent bug in handling >32-bit addresses, or not all the * expected address bits are wired up between the device and the IOMMU. */ Asking the ASM1061 on a discrete PCIe card to DMA from I/O virtual address 0xffffffff00000000 produces the following I/O page faults: vfio-pci 0000:07:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0021 address=0x7ff00000000 flags=0x0010] vfio-pci 0000:07:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0021 address=0x7ff00000500 flags=0x0010] Note that the upper 21 bits of the logged DMA address are zero. (When asking a different PCIe device in the same PCIe slot to DMA to the same I/O virtual address, we do see all the upper 32 bits of the DMA address as 1, so this is not an issue with the chipset or IOMMU configuration on the test system.) Also, hacking libahci to always set the upper 21 bits of all DMA addresses to 1 produces no discernible effect on the behavior of the ASM1061, and mkfs/mount/scrub/etc work as without this hack. This all strongly suggests that the ASM1061 has a 43 bit DMA address limit, and this commit therefore adds a quirk to deal with this limit. This issue probably applies to (some of) the other supported ASMedia parts as well, but we limit it to the PCI IDs known to refer to ASM1061 parts, as that's the only part we know for sure to be affected by this issue at this point. Link: https://lore.kernel.org/linux-ide/ZaZ2PIpEId-rl6jv@wantstofly.org/ Signed-off-by: Lennert Buytenhek <kernel@wantstofly.org> [cassel: drop date from error messages in commit log] Signed-off-by: Niklas Cassel <cassel@kernel.org>
2024-01-25 23:04:01 +08:00
/* ASMedia */
ahci: Extend ASM1061 43-bit DMA address quirk to other ASM106x parts ASMedia have confirmed that all ASM106x parts currently listed in ahci_pci_tbl[] suffer from the 43-bit DMA address limitation that we ran into on the ASM1061, and therefore, we need to apply the quirk added by commit 20730e9b2778 ("ahci: add 43-bit DMA address quirk for ASMedia ASM1061 controllers") to the other supported ASM106x parts as well. Cc: stable@vger.kernel.org Link: https://lore.kernel.org/linux-ide/ZbopwKZJAKQRA4Xv@x1-carbon/ Signed-off-by: Lennert Buytenhek <kernel@wantstofly.org> [cassel: add link to ASMedia confirmation email] Signed-off-by: Niklas Cassel <cassel@kernel.org>
2024-01-30 21:21:51 +08:00
{ PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci_43bit_dma }, /* ASM1060 */
{ PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci_43bit_dma }, /* ASM1060 */
ahci: add 43-bit DMA address quirk for ASMedia ASM1061 controllers With one of the on-board ASM1061 AHCI controllers (1b21:0612) on an ASUSTeK Pro WS WRX80E-SAGE SE WIFI mainboard, a controller hang was observed that was immediately preceded by the following kernel messages: ahci 0000:28:00.0: Using 64-bit DMA addresses ahci 0000:28:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0035 address=0x7fffff00000 flags=0x0000] ahci 0000:28:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0035 address=0x7fffff00300 flags=0x0000] ahci 0000:28:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0035 address=0x7fffff00380 flags=0x0000] ahci 0000:28:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0035 address=0x7fffff00400 flags=0x0000] ahci 0000:28:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0035 address=0x7fffff00680 flags=0x0000] ahci 0000:28:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0035 address=0x7fffff00700 flags=0x0000] The first message is produced by code in drivers/iommu/dma-iommu.c which is accompanied by the following comment that seems to apply: /* * Try to use all the 32-bit PCI addresses first. The original SAC vs. * DAC reasoning loses relevance with PCIe, but enough hardware and * firmware bugs are still lurking out there that it's safest not to * venture into the 64-bit space until necessary. * * If your device goes wrong after seeing the notice then likely either * its driver is not setting DMA masks accurately, the hardware has * some inherent bug in handling >32-bit addresses, or not all the * expected address bits are wired up between the device and the IOMMU. */ Asking the ASM1061 on a discrete PCIe card to DMA from I/O virtual address 0xffffffff00000000 produces the following I/O page faults: vfio-pci 0000:07:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0021 address=0x7ff00000000 flags=0x0010] vfio-pci 0000:07:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0021 address=0x7ff00000500 flags=0x0010] Note that the upper 21 bits of the logged DMA address are zero. (When asking a different PCIe device in the same PCIe slot to DMA to the same I/O virtual address, we do see all the upper 32 bits of the DMA address as 1, so this is not an issue with the chipset or IOMMU configuration on the test system.) Also, hacking libahci to always set the upper 21 bits of all DMA addresses to 1 produces no discernible effect on the behavior of the ASM1061, and mkfs/mount/scrub/etc work as without this hack. This all strongly suggests that the ASM1061 has a 43 bit DMA address limit, and this commit therefore adds a quirk to deal with this limit. This issue probably applies to (some of) the other supported ASMedia parts as well, but we limit it to the PCI IDs known to refer to ASM1061 parts, as that's the only part we know for sure to be affected by this issue at this point. Link: https://lore.kernel.org/linux-ide/ZaZ2PIpEId-rl6jv@wantstofly.org/ Signed-off-by: Lennert Buytenhek <kernel@wantstofly.org> [cassel: drop date from error messages in commit log] Signed-off-by: Niklas Cassel <cassel@kernel.org>
2024-01-25 23:04:01 +08:00
{ PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci_43bit_dma }, /* ASM1061 */
{ PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci_43bit_dma }, /* ASM1061/1062 */
ahci: Extend ASM1061 43-bit DMA address quirk to other ASM106x parts ASMedia have confirmed that all ASM106x parts currently listed in ahci_pci_tbl[] suffer from the 43-bit DMA address limitation that we ran into on the ASM1061, and therefore, we need to apply the quirk added by commit 20730e9b2778 ("ahci: add 43-bit DMA address quirk for ASMedia ASM1061 controllers") to the other supported ASM106x parts as well. Cc: stable@vger.kernel.org Link: https://lore.kernel.org/linux-ide/ZbopwKZJAKQRA4Xv@x1-carbon/ Signed-off-by: Lennert Buytenhek <kernel@wantstofly.org> [cassel: add link to ASMedia confirmation email] Signed-off-by: Niklas Cassel <cassel@kernel.org>
2024-01-30 21:21:51 +08:00
{ PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci_43bit_dma }, /* ASM1061R */
{ PCI_VDEVICE(ASMEDIA, 0x0622), board_ahci_43bit_dma }, /* ASM1062R */
{ PCI_VDEVICE(ASMEDIA, 0x0624), board_ahci_43bit_dma }, /* ASM1062+JMB575 */
ata: ahci: add identifiers for ASM2116 series adapters Add support for PCIe SATA adapter cards based on Asmedia 2116 controllers. These cards can provide up to 10 SATA ports on PCIe card. Signed-off-by: Szuying Chen <Chloe_Chen@asmedia.com.tw> Signed-off-by: Damien Le Moal <dlemoal@kernel.org>
2023-09-21 17:33:51 +08:00
{ PCI_VDEVICE(ASMEDIA, 0x1062), board_ahci }, /* ASM1062A */
{ PCI_VDEVICE(ASMEDIA, 0x1064), board_ahci }, /* ASM1064 */
{ PCI_VDEVICE(ASMEDIA, 0x1164), board_ahci }, /* ASM1164 */
{ PCI_VDEVICE(ASMEDIA, 0x1165), board_ahci }, /* ASM1165 */
{ PCI_VDEVICE(ASMEDIA, 0x1166), board_ahci }, /* ASM1166 */
[libata] ahci: Add ASMedia ASM1061 support Signed-off-by: Keng-Yu Lin <kengyu@canonical.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2011-11-09 14:47:36 +08:00
ahci: disable NCQ on Samsung pci-e SSDs on macbooks Samsung's pci-e SSDs with device ID 0x1600 which are found on some macbooks time out on NCQ commands. Blacklist NCQ on the device so that the affected machines can at least boot. Original-patch-by: Levente Kurusa <levex@linux.com> Signed-off-by: Tejun Heo <tj@kernel.org> Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=60731 Cc: stable@vger.kernel.org
2014-02-18 23:22:17 +08:00
/*
ahci: disable MSI instead of NCQ on Samsung pci-e SSDs on macbooks Samsung pci-e SSDs on macbooks failed miserably on NCQ commands, so 67809f85d31e ("ahci: disable NCQ on Samsung pci-e SSDs on macbooks") disabled NCQ on them. It turns out that NCQ is fine as long as MSI is not used, so let's turn off MSI and leave NCQ on. Signed-off-by: Tejun Heo <tj@kernel.org> Link: https://bugzilla.kernel.org/show_bug.cgi?id=60731 Tested-by: <dorin@i51.org> Tested-by: Imre Kaloz <kaloz@openwrt.org> Cc: stable@vger.kernel.org Fixes: 67809f85d31e ("ahci: disable NCQ on Samsung pci-e SSDs on macbooks")
2014-10-27 22:22:56 +08:00
* Samsung SSDs found on some macbooks. NCQ times out if MSI is
* enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
ahci: disable NCQ on Samsung pci-e SSDs on macbooks Samsung's pci-e SSDs with device ID 0x1600 which are found on some macbooks time out on NCQ commands. Blacklist NCQ on the device so that the affected machines can at least boot. Original-patch-by: Levente Kurusa <levex@linux.com> Signed-off-by: Tejun Heo <tj@kernel.org> Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=60731 Cc: stable@vger.kernel.org
2014-02-18 23:22:17 +08:00
*/
ahci: disable MSI instead of NCQ on Samsung pci-e SSDs on macbooks Samsung pci-e SSDs on macbooks failed miserably on NCQ commands, so 67809f85d31e ("ahci: disable NCQ on Samsung pci-e SSDs on macbooks") disabled NCQ on them. It turns out that NCQ is fine as long as MSI is not used, so let's turn off MSI and leave NCQ on. Signed-off-by: Tejun Heo <tj@kernel.org> Link: https://bugzilla.kernel.org/show_bug.cgi?id=60731 Tested-by: <dorin@i51.org> Tested-by: Imre Kaloz <kaloz@openwrt.org> Cc: stable@vger.kernel.org Fixes: 67809f85d31e ("ahci: disable NCQ on Samsung pci-e SSDs on macbooks")
2014-10-27 22:22:56 +08:00
{ PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
ahci: disable MSI on SAMSUNG 0xa800 SSD Just like 0x1600 which got blacklisted by 66a7cbc303f4 ("ahci: disable MSI instead of NCQ on Samsung pci-e SSDs on macbooks"), 0xa800 chokes on NCQ commands if MSI is enabled. Disable MSI. Signed-off-by: Tejun Heo <tj@kernel.org> Reported-by: Dominik Mierzejewski <dominik@greysector.net> Link: https://bugzilla.kernel.org/show_bug.cgi?id=89171 Cc: stable@vger.kernel.org
2014-12-05 02:13:28 +08:00
{ PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
ahci: disable NCQ on Samsung pci-e SSDs on macbooks Samsung's pci-e SSDs with device ID 0x1600 which are found on some macbooks time out on NCQ commands. Blacklist NCQ on the device so that the affected machines can at least boot. Original-patch-by: Levente Kurusa <levex@linux.com> Signed-off-by: Tejun Heo <tj@kernel.org> Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=60731 Cc: stable@vger.kernel.org
2014-02-18 23:22:17 +08:00
[libata] ahci: Add support for Enmotus Bobcat device. Silicon does not support standard AHCI BAR assignment. Add vendor/device exception to force BAR 2. Signed-off-by: Hugh Daschbach <hugh.daschbach@enmotus.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2013-01-05 06:39:09 +08:00
/* Enmotus */
{ PCI_DEVICE(0x1c44, 0x8000), board_ahci },
AHCI: Add support for Loongson 7A1000 SATA controller Loongson 7A1000 SATA controller uses BAR0 as the base address register. Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn> Signed-off-by: Jens Axboe <axboe@kernel.dk>
2020-03-10 20:50:08 +08:00
/* Loongson */
{ PCI_VDEVICE(LOONGSON, 0x7a08), board_ahci },
[libata] ahci: Match PCI class code for AHCI Signed-off-by: Jeff Garzik <jeff@garzik.org>
2006-11-01 18:10:42 +08:00
/* Generic, PCI class code for AHCI */
{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
Add pci class code for SATA & AHCI, and replace some magic numbers. Signed-off-by: Conke Hu <conke.hu@amd.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-01-09 18:32:51 +08:00
PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
[libata] ahci: Match PCI class code for AHCI Signed-off-by: Jeff Garzik <jeff@garzik.org>
2006-11-01 18:10:42 +08:00
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 06:20:36 +08:00
{ } /* terminate list */
};
ahci: Convert driver to use modern PM hooks In order to add support for runtime PM to the ahci driver we first need to convert the driver to use modern non-legacy system suspend hooks. There should be no functional changes. tj: Updated .driver.pm init for older compilers as suggested by Andy and Chrsitoph. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Cc: Andy Shevchenko <andy.shevchenko@gmail.com> Cc: Christoph Hellwig <hch@infradead.org> Signed-off-by: Tejun Heo <tj@kernel.org>
2016-02-18 16:54:15 +08:00
static const struct dev_pm_ops ahci_pci_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume)
ahci: Add runtime PM support for the host controller This patch adds runtime PM support for the AHCI host controller driver so that the host controller is powered down when all SATA ports are runtime suspended. Powering down the AHCI host controller can reduce power consumption and possibly allow the CPU to enter lower power idle states (S0ix) during runtime. Runtime PM is blocked by default and needs to be unblocked from userspace as needed (via power/* sysfs nodes). Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2016-02-18 16:54:17 +08:00
SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend,
ahci_pci_device_runtime_resume, NULL)
ahci: Convert driver to use modern PM hooks In order to add support for runtime PM to the ahci driver we first need to convert the driver to use modern non-legacy system suspend hooks. There should be no functional changes. tj: Updated .driver.pm init for older compilers as suggested by Andy and Chrsitoph. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Cc: Andy Shevchenko <andy.shevchenko@gmail.com> Cc: Christoph Hellwig <hch@infradead.org> Signed-off-by: Tejun Heo <tj@kernel.org>
2016-02-18 16:54:15 +08:00
};
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 06:20:36 +08:00
static struct pci_driver ahci_pci_driver = {
.name = DRV_NAME,
.id_table = ahci_pci_tbl,
.probe = ahci_init_one,
ahci: Add runtime PM support for the host controller This patch adds runtime PM support for the AHCI host controller driver so that the host controller is powered down when all SATA ports are runtime suspended. Powering down the AHCI host controller can reduce power consumption and possibly allow the CPU to enter lower power idle states (S0ix) during runtime. Runtime PM is blocked by default and needs to be unblocked from userspace as needed (via power/* sysfs nodes). Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2016-02-18 16:54:17 +08:00
.remove = ahci_remove_one,
ata: ahci: Add shutdown to freeze hardware resources of ahci device_shutdown() called from reboot or power_shutdown expect all devices to be shutdown. Same is true for even ahci pci driver. As no ahci shutdown function is implemented, the ata subsystem always remains alive with DMA & interrupt support. File system related calls should not be honored after device_shutdown(). So defining ahci pci driver shutdown to freeze hardware (mask interrupt, stop DMA engine and free DMA resources). Signed-off-by: Prabhakar Kushwaha <pkushwaha@marvell.com> Signed-off-by: Jens Axboe <axboe@kernel.dk>
2020-01-25 11:37:29 +08:00
.shutdown = ahci_shutdown_one,
ahci: Convert driver to use modern PM hooks In order to add support for runtime PM to the ahci driver we first need to convert the driver to use modern non-legacy system suspend hooks. There should be no functional changes. tj: Updated .driver.pm init for older compilers as suggested by Andy and Chrsitoph. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Cc: Andy Shevchenko <andy.shevchenko@gmail.com> Cc: Christoph Hellwig <hch@infradead.org> Signed-off-by: Tejun Heo <tj@kernel.org>
2016-02-18 16:54:15 +08:00
.driver = {
.pm = &ahci_pci_pm_ops,
},
ahci: Move generic code into libahci This patch should contain no functional changes, just moves code around. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-03-28 12:22:14 +08:00
};
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 06:20:36 +08:00
ata: Use IS_ENABLED() instead of checking for built-in or module The IS_ENABLED() macro checks if a Kconfig symbol has been enabled either built-in or as a module, use that macro instead of open coding the same. Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2016-05-19 04:11:28 +08:00
#if IS_ENABLED(CONFIG_PATA_MARVELL)
ahci: Move generic code into libahci This patch should contain no functional changes, just moves code around. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-03-28 12:22:14 +08:00
static int marvell_enable;
#else
static int marvell_enable = 1;
#endif
module_param(marvell_enable, int, 0644);
MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
ahci: give another shot at clearing all bits in irq_stat Commit ea0c62f7cf70f13a67830471b613337bd0c9a62e tried to clear all bits in irq_stat but it didn't actually achieve that as irq_stat was anded with port_map right after read. This patch makes ahci driver always use the unmasked value to clear irq_status. While at it, add explanation on the peculiarities of ahci IRQ clearing. This was spotted by Linus Torvalds. Signed-off-by: Tejun Heo <tj@kernel.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2008-07-05 12:10:50 +08:00
ata: ahci: Enable DEVSLP by default on x86 with SLP_S0 One of the requirement for modern x86 system to enter lowest power mode (SLP_S0) is SATA IP block to be off. This is true even during when platform is suspended to idle and not only in opportunistic (runtime) suspend. Several of these system don't have traditional ACPI S3, so it is important that they enter SLP_S0 state, to avoid draining battery even during suspend. So it is important that out of the box Linux installation reach this state. SATA IP block doesn't get turned off till SATA is in DEVSLP mode. Here user has to either use scsi-host sysfs or tools like powertop to set the sata-host link_power_management_policy to min_power. This change sets by default link power management policy to min_power with partial (preferred) or slumber support on idle for some platforms. To avoid regressions, the following conditions are used: - User didn't override the policy from module parameter - The kernel config is already set to use med_power_with_dipm or deeper - System is a SLP_S0 capable using ACPI low power idle flag This combination will make sure that systems are fairly recent and since getting shipped with SLP_S0 support, the DEVSLP function is already validated. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2018-07-28 04:47:03 +08:00
static int mobile_lpm_policy = -1;
ahci: Allow setting a default LPM policy for mobile chipsets On many laptops setting a different LPM policy then unknown / max_performance can lead to power-savings of 1.0 - 1.5 Watts (when idle). Modern ultrabooks idle around 6W (at 50% screen brightness), 1.0 - 1.5W is a significant chunk of this. There are some performance / latency costs to enabling LPM by default, so it is desirable to make it possible to set a different LPM policy for mobile / laptop variants of chipsets / "South Bridges" vs their desktop / server counterparts. Also enabling LPM by default is not entirely without risk of regressions. At least min_power is known to cause issues with some disks, including some reports of data corruption. This commits adds a new ahci.mobile_lpm_policy kernel cmdline option, which defaults to a new SATA_MOBILE_LPM_POLICY Kconfig option so that Linux distributions can choose to set a LPM policy for mobile chipsets by default. The reason to have both a kernel cmdline option and a Kconfig default value for it, is to allow easy overriding of the default to allow trouble-shooting without needing to rebuild the kernel. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2017-12-12 00:52:16 +08:00
module_param(mobile_lpm_policy, int, 0644);
MODULE_PARM_DESC(mobile_lpm_policy, "Default LPM policy for mobile chipsets");
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 06:20:36 +08:00
ahci: Move generic code into libahci This patch should contain no functional changes, just moves code around. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-03-28 12:22:14 +08:00
static void ahci_pci_save_initial_config(struct pci_dev *pdev,
struct ahci_host_priv *hpriv)
{
ahci: asm1166: correct count of reported ports The ASM1166 SATA host controller always reports wrongly, that it has 32 ports. But in reality, it only has six ports. This seems to be a hardware issue, as all tested ASM1166 SATA host controllers reports such high count of ports. Example output: ahci 0000:09:00.0: AHCI 0001.0301 32 slots 32 ports 6 Gbps 0xffffff3f impl SATA mode. By adjusting the port_map, the count is limited to six ports. New output: ahci 0000:09:00.0: AHCI 0001.0301 32 slots 32 ports 6 Gbps 0x3f impl SATA mode. Closes: https://bugzilla.kernel.org/show_bug.cgi?id=211873 Closes: https://bugzilla.kernel.org/show_bug.cgi?id=218346 Signed-off-by: Conrad Kostecki <conikost@gentoo.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Niklas Cassel <cassel@kernel.org>
2024-01-24 02:30:02 +08:00
if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && pdev->device == 0x1166) {
dev_info(&pdev->dev, "ASM1166 has only six ports\n");
hpriv->saved_port_map = 0x3f;
}
ahci: Move generic code into libahci This patch should contain no functional changes, just moves code around. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-03-28 12:22:14 +08:00
if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
dev_info(&pdev->dev, "JMB361 has only one port\n");
ata: libahci: Discard redundant force_port_map parameter Currently there are four port-map-related fields declared in the ahci_host_priv structure and used to setup the HBA ports mapping. First the ports-mapping is read from the PI register and immediately stored in the saved_port_map field. If forced_port_map is initialized with non-zero value then its value will have greater priority over the value read from PI, thus it will override the saved_port_map field. That value will be then masked by a non-zero mask_port_map field and after some sanity checks it will be stored in the ahci_host_priv.port_map field as a final port mapping. As you can see the logic is a bit too complicated for such a simple task. We can freely get rid from at least one of the fields with no change to the implemented semantic. The force_port_map field can be replaced with taking non-zero saved_port_map value into account. So if saved_port_map is pre-initialized by the low level drivers (platform drivers) then it will have greater priority over the value read from PI register and will be used as actual HBA ports mapping later on. Thus the ports map forcing task will be just transferred from force_port_map to the saved_port_map field. This modification will perfectly fit into the feature of having OF-based initialization of the HW-init HBA CSR fields we are about to introduce in the next commit. Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Reviewed-by: Hannes Reinecke <hare@suse.de> Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
2022-09-10 03:36:11 +08:00
hpriv->saved_port_map = 1;
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 06:20:36 +08:00
}
ahci: Move generic code into libahci This patch should contain no functional changes, just moves code around. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-03-28 12:22:14 +08:00
/*
* Temporary Marvell 6145 hack: PATA port presence
* is asserted through the standard AHCI port
* presence register, as bit 4 (counting from 0)
ahci: give another shot at clearing all bits in irq_stat Commit ea0c62f7cf70f13a67830471b613337bd0c9a62e tried to clear all bits in irq_stat but it didn't actually achieve that as irq_stat was anded with port_map right after read. This patch makes ahci driver always use the unmasked value to clear irq_status. While at it, add explanation on the peculiarities of ahci IRQ clearing. This was spotted by Linus Torvalds. Signed-off-by: Tejun Heo <tj@kernel.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2008-07-05 12:10:50 +08:00
*/
ahci: Move generic code into libahci This patch should contain no functional changes, just moves code around. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-03-28 12:22:14 +08:00
if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
if (pdev->device == 0x6121)
ahci: fix AHCI parameters not taken into account Changes into the AHCI subsystem have introduced a bug by not taking into account the force_port_map and mask_port_map parameters when using the ahci_pci_save_initial_config function. This commit fixes it by setting the internal parameters of the ahci_port_priv structure. Fixes: 725c7b570fda Reported-and-tested-by: Zlatko Calusic <zcalusic@bitsync.net> Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
2014-11-03 16:56:11 +08:00
hpriv->mask_port_map = 0x3;
ahci: Move generic code into libahci This patch should contain no functional changes, just moves code around. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-03-28 12:22:14 +08:00
else
ahci: fix AHCI parameters not taken into account Changes into the AHCI subsystem have introduced a bug by not taking into account the force_port_map and mask_port_map parameters when using the ahci_pci_save_initial_config function. This commit fixes it by setting the internal parameters of the ahci_port_priv structure. Fixes: 725c7b570fda Reported-and-tested-by: Zlatko Calusic <zcalusic@bitsync.net> Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
2014-11-03 16:56:11 +08:00
hpriv->mask_port_map = 0xf;
ahci: Move generic code into libahci This patch should contain no functional changes, just moves code around. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-03-28 12:22:14 +08:00
dev_info(&pdev->dev,
"Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
}
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 06:20:36 +08:00
ata: libahci_platform: move port_map parameters into the AHCI structure This patch moves force_port_map and mask_port_map into the ahci_host_priv structure. This allows to modify them into the AHCI framework. This is needed by the new dt bindings representing ports as the port_map mask is computed automatically. Parameters modifying force_port_map, mask_port_map and flags have been removed from the ahci_platform_init_host() function, and inputs in the ahci_host_priv structure are now directly filed. Signed-off-by: Antoine Ténart <antoine.tenart@free-electrons.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2014-07-31 02:13:56 +08:00
ahci_save_initial_config(&pdev->dev, hpriv);
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 06:20:36 +08:00
}
ata: ahci: Fix PCS quirk application for suspend Since kernel 5.3.4 my laptop (ICH8M controller) does not see Kingston SV300S37A60G SSD disk connected into a SATA connector on wake from suspend. The problem was introduced in c312ef176399 ("libata/ahci: Drop PCS quirk for Denverton and beyond"): the quirk is not applied on wake from suspend as it originally was. It is worth to mention the commit contained another bug: the quirk is not applied at all to controllers which require it. The fix commit 09d6ac8dc51a ("libata/ahci: Fix PCS quirk application") landed in 5.3.8. So testing my patch anywhere between commits c312ef176399 and 09d6ac8dc51a is pointless. Not all disks trigger the problem. For example nothing bad happens with Western Digital WD5000LPCX HDD. Test hardware: - Acer 5920G with ICH8M SATA controller - sda: some SATA HDD connnected into the DVD drive IDE port with a SATA-IDE caddy. It is a boot disk - sdb: Kingston SV300S37A60G SSD connected into the only SATA port Sample "dmesg --notime | grep -E '^(sd |ata)'" output on wake: sd 0:0:0:0: [sda] Starting disk sd 2:0:0:0: [sdb] Starting disk ata4: SATA link down (SStatus 4 SControl 300) ata3: SATA link down (SStatus 4 SControl 300) ata1.00: ACPI cmd ef/03:0c:00:00:00:a0 (SET FEATURES) filtered out ata1.00: ACPI cmd ef/03:42:00:00:00:a0 (SET FEATURES) filtered out ata1: FORCE: cable set to 80c ata5: SATA link down (SStatus 0 SControl 300) ata3: SATA link down (SStatus 4 SControl 300) ata3: SATA link down (SStatus 4 SControl 300) ata3.00: disabled sd 2:0:0:0: rejecting I/O to offline device ata3.00: detaching (SCSI 2:0:0:0) sd 2:0:0:0: [sdb] Start/Stop Unit failed: Result: hostbyte=DID_NO_CONNECT driverbyte=DRIVER_OK sd 2:0:0:0: [sdb] Synchronizing SCSI cache sd 2:0:0:0: [sdb] Synchronize Cache(10) failed: Result: hostbyte=DID_BAD_TARGET driverbyte=DRIVER_OK sd 2:0:0:0: [sdb] Stopping disk sd 2:0:0:0: [sdb] Start/Stop Unit failed: Result: hostbyte=DID_BAD_TARGET driverbyte=DRIVER_OK Commit c312ef176399 dropped ahci_pci_reset_controller() which internally calls ahci_reset_controller() and applies the PCS quirk if needed after that. It was called each time a reset was required instead of just ahci_reset_controller(). This patch puts the function back in place. Fixes: c312ef176399 ("libata/ahci: Drop PCS quirk for Denverton and beyond") Signed-off-by: Adam Vodopjan <grozzly@protonmail.com> Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
2022-12-09 17:26:34 +08:00
static int ahci_pci_reset_controller(struct ata_host *host)
{
struct pci_dev *pdev = to_pci_dev(host->dev);
struct ahci_host_priv *hpriv = host->private_data;
int rc;
rc = ahci_reset_controller(host);
if (rc)
return rc;
/*
* If platform firmware failed to enable ports, try to enable
* them here.
*/
ahci_intel_pcs_quirk(pdev, hpriv);
return 0;
}
ahci: Move generic code into libahci This patch should contain no functional changes, just moves code around. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-03-28 12:22:14 +08:00
static void ahci_pci_init_controller(struct ata_host *host)
[PATCH] ahci: convert to new EH Convert AHCI to new EH. Unfortunately, ICH7 AHCI reacts badly if IRQ mask is diddled during operation. So, freezing is implemented by unconditionally clearing interrupt conditions while frozen. * Interrupts are categorized according to required action. e.g. Connection status or unknown FIS error requires freezing the port while TF or HBUS_DATA don't. * Only CONNECT (reflects SErr.X) interrupt is taken into account not PHYRDY (SErr.N), as CONNECT is better cue for starting EH. * AHCI may be invoked without any active command. e.g. CONNECT irq occuring while no qc in progress still triggers EH and will reset the port and revalidate attached device. Signed-off-by: Tejun Heo <htejun@gmail.com>
2006-05-15 19:58:29 +08:00
{
ahci: Move generic code into libahci This patch should contain no functional changes, just moves code around. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-03-28 12:22:14 +08:00
struct ahci_host_priv *hpriv = host->private_data;
struct pci_dev *pdev = to_pci_dev(host->dev);
void __iomem *port_mmio;
[PATCH] ahci: convert to new EH Convert AHCI to new EH. Unfortunately, ICH7 AHCI reacts badly if IRQ mask is diddled during operation. So, freezing is implemented by unconditionally clearing interrupt conditions while frozen. * Interrupts are categorized according to required action. e.g. Connection status or unknown FIS error requires freezing the port while TF or HBUS_DATA don't. * Only CONNECT (reflects SErr.X) interrupt is taken into account not PHYRDY (SErr.N), as CONNECT is better cue for starting EH. * AHCI may be invoked without any active command. e.g. CONNECT irq occuring while no qc in progress still triggers EH and will reset the port and revalidate attached device. Signed-off-by: Tejun Heo <htejun@gmail.com>
2006-05-15 19:58:29 +08:00
u32 tmp;
ahci: Move generic code into libahci This patch should contain no functional changes, just moves code around. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-03-28 12:22:14 +08:00
int mv;
[PATCH] ahci: convert to new EH Convert AHCI to new EH. Unfortunately, ICH7 AHCI reacts badly if IRQ mask is diddled during operation. So, freezing is implemented by unconditionally clearing interrupt conditions while frozen. * Interrupts are categorized according to required action. e.g. Connection status or unknown FIS error requires freezing the port while TF or HBUS_DATA don't. * Only CONNECT (reflects SErr.X) interrupt is taken into account not PHYRDY (SErr.N), as CONNECT is better cue for starting EH. * AHCI may be invoked without any active command. e.g. CONNECT irq occuring while no qc in progress still triggers EH and will reset the port and revalidate attached device. Signed-off-by: Tejun Heo <htejun@gmail.com>
2006-05-15 19:58:29 +08:00
ahci: Move generic code into libahci This patch should contain no functional changes, just moves code around. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-03-28 12:22:14 +08:00
if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
if (pdev->device == 0x6121)
mv = 2;
else
mv = 4;
ata: ahci: Convert __ahci_port_base to accepting hpriv as arguments The port base address may be required even before the ata_host instance is initialized and activated, for instance in the ahci_save_initial_config() method which we are about to update (consider this modification as a preparation for that one). Seeing the __ahci_port_base() function isn't used much it's the best candidate to provide the required functionality. So let's convert it to accepting the ahci_host_priv structure pointer. Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Reviewed-by: Hannes Reinecke <hare@suse.de> Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
2022-09-10 03:36:13 +08:00
port_mmio = __ahci_port_base(hpriv, mv);
[PATCH] ahci: convert to new EH Convert AHCI to new EH. Unfortunately, ICH7 AHCI reacts badly if IRQ mask is diddled during operation. So, freezing is implemented by unconditionally clearing interrupt conditions while frozen. * Interrupts are categorized according to required action. e.g. Connection status or unknown FIS error requires freezing the port while TF or HBUS_DATA don't. * Only CONNECT (reflects SErr.X) interrupt is taken into account not PHYRDY (SErr.N), as CONNECT is better cue for starting EH. * AHCI may be invoked without any active command. e.g. CONNECT irq occuring while no qc in progress still triggers EH and will reset the port and revalidate attached device. Signed-off-by: Tejun Heo <htejun@gmail.com>
2006-05-15 19:58:29 +08:00
ahci: Move generic code into libahci This patch should contain no functional changes, just moves code around. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-03-28 12:22:14 +08:00
writel(0, port_mmio + PORT_IRQ_MASK);
[PATCH] ahci: convert to new EH Convert AHCI to new EH. Unfortunately, ICH7 AHCI reacts badly if IRQ mask is diddled during operation. So, freezing is implemented by unconditionally clearing interrupt conditions while frozen. * Interrupts are categorized according to required action. e.g. Connection status or unknown FIS error requires freezing the port while TF or HBUS_DATA don't. * Only CONNECT (reflects SErr.X) interrupt is taken into account not PHYRDY (SErr.N), as CONNECT is better cue for starting EH. * AHCI may be invoked without any active command. e.g. CONNECT irq occuring while no qc in progress still triggers EH and will reset the port and revalidate attached device. Signed-off-by: Tejun Heo <htejun@gmail.com>
2006-05-15 19:58:29 +08:00
ahci: Move generic code into libahci This patch should contain no functional changes, just moves code around. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-03-28 12:22:14 +08:00
/* clear port IRQ */
tmp = readl(port_mmio + PORT_IRQ_STAT);
ata: ahci: Drop pointless VPRINTK() calls and convert the remaining ones Drop pointless VPRINTK() calls for entering and existing interrupt routines and convert the remaining calls to dev_dbg(). Signed-off-by: Hannes Reinecke <hare@suse.de> Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
2021-12-21 15:20:47 +08:00
dev_dbg(&pdev->dev, "PORT_IRQ_STAT 0x%x\n", tmp);
ahci: Move generic code into libahci This patch should contain no functional changes, just moves code around. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-03-28 12:22:14 +08:00
if (tmp)
writel(tmp, port_mmio + PORT_IRQ_STAT);
[PATCH] ahci: convert to new EH Convert AHCI to new EH. Unfortunately, ICH7 AHCI reacts badly if IRQ mask is diddled during operation. So, freezing is implemented by unconditionally clearing interrupt conditions while frozen. * Interrupts are categorized according to required action. e.g. Connection status or unknown FIS error requires freezing the port while TF or HBUS_DATA don't. * Only CONNECT (reflects SErr.X) interrupt is taken into account not PHYRDY (SErr.N), as CONNECT is better cue for starting EH. * AHCI may be invoked without any active command. e.g. CONNECT irq occuring while no qc in progress still triggers EH and will reset the port and revalidate attached device. Signed-off-by: Tejun Heo <htejun@gmail.com>
2006-05-15 19:58:29 +08:00
}
ahci: Move generic code into libahci This patch should contain no functional changes, just moves code around. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-03-28 12:22:14 +08:00
ahci_init_controller(host);
ahci: ahci: implement workaround for ASUS P5W-DH Deluxe ahci_broken_hardreset(), take #2 P5W-DH Deluxe has ICH9 which doesn't have PMP support but SIMG 4726 hardwired to the second port of AHCI controller at PCI device 1f.2. The 4726 doesn't work as PMP but as a storage processor which can do hardware RAID on downstream ports. When no device is attached to the downstream port of the 4726, pseudo ATA device for configuration appears. Unfortunately, ATA emulation on the device is very lousy and causes long hang during boot. This patch implements workaround for the board. If the mainboard is P5W-DH Deluxe (matched using DMI), only hardreset is used on the second port of AHCI controller @ 1f.2 and the hardreset doesn't depend on receiving the first FIS and just proceed to IDENTIFY. This workaround fixes bugzilla #8923. http://bugzilla.kernel.org/show_bug.cgi?id=8923 Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-10-25 13:59:16 +08:00
}
ahci: Move generic code into libahci This patch should contain no functional changes, just moves code around. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-03-28 12:22:14 +08:00
static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
unsigned long deadline)
ahci: Implement SATA AHCI FIS-based switching support Tested on AMD internal reference board. Signed-off-by: Shane Huang <shane.huang@amd.com> Acked-by: Tejun Heo <tj@kernel.org> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-12-09 17:23:04 +08:00
{
ahci: Move generic code into libahci This patch should contain no functional changes, just moves code around. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-03-28 12:22:14 +08:00
struct ata_port *ap = link->ap;
libahci: Allow drivers to override start_engine Allwinner A10 and A20 ARM SoCs have an AHCI sata controller which needs a special register to be poked before starting the DMA engine. This register gets reset on an ahci_stop_engine call, so there is no other place then ahci_start_engine where this poking can be done. This commit allows drivers to override ahci_start_engine behavior for use by the Allwinner AHCI driver (and potentially other drivers in the future). Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2014-02-22 23:53:30 +08:00
struct ahci_host_priv *hpriv = ap->host->private_data;
ahci: Move generic code into libahci This patch should contain no functional changes, just moves code around. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-03-28 12:22:14 +08:00
bool online;
ahci: Implement SATA AHCI FIS-based switching support Tested on AMD internal reference board. Signed-off-by: Shane Huang <shane.huang@amd.com> Acked-by: Tejun Heo <tj@kernel.org> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-12-09 17:23:04 +08:00
int rc;
libahci: Allow drivers to override stop_engine Marvell armada37xx, armada7k and armada8k share the same AHCI sata controller IP, and currently there is an issue (Errata Ref#226)that the SATA can not be detected via SATA Port-MultiPlayer(PMP). After debugging, the reason is found that the value of Port-x FIS-based Switching Control (PxFBS@0x40) became wrong. According to design, the bits[11:8, 0] of register PxFBS are cleared when Port Command and Status (0x18) bit[0] changes its value from 1 to 0, i.e. falling edge of Port Command and Status bit[0] sends PULSE that resets PxFBS bits[11:8; 0]. So it needs save the port PxFBS register before PxCMD ST write and restore the port PxFBS register afterwards in ahci_stop_engine(). This commit allows drivers to override ahci_stop_engine behavior for use by the Marvell AHCI driver(and potentially other drivers in the future). Signed-off-by: Evan Wang <xswang@marvell.com> Cc: Ofer Heifetz <oferh@marvell.com> Cc: Tejun Heo <tj@kernel.org> Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2018-04-13 12:32:30 +08:00
hpriv->stop_engine(ap);
ahci: Implement SATA AHCI FIS-based switching support Tested on AMD internal reference board. Signed-off-by: Shane Huang <shane.huang@amd.com> Acked-by: Tejun Heo <tj@kernel.org> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-12-09 17:23:04 +08:00
ahci: Move generic code into libahci This patch should contain no functional changes, just moves code around. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-03-28 12:22:14 +08:00
rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
deadline, &online, NULL);
ahci: Implement SATA AHCI FIS-based switching support Tested on AMD internal reference board. Signed-off-by: Shane Huang <shane.huang@amd.com> Acked-by: Tejun Heo <tj@kernel.org> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-12-09 17:23:04 +08:00
libahci: Allow drivers to override start_engine Allwinner A10 and A20 ARM SoCs have an AHCI sata controller which needs a special register to be poked before starting the DMA engine. This register gets reset on an ahci_stop_engine call, so there is no other place then ahci_start_engine where this poking can be done. This commit allows drivers to override ahci_start_engine behavior for use by the Allwinner AHCI driver (and potentially other drivers in the future). Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2014-02-22 23:53:30 +08:00
hpriv->start_engine(ap);
ahci: Implement SATA AHCI FIS-based switching support Tested on AMD internal reference board. Signed-off-by: Shane Huang <shane.huang@amd.com> Acked-by: Tejun Heo <tj@kernel.org> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-12-09 17:23:04 +08:00
ahci: Move generic code into libahci This patch should contain no functional changes, just moves code around. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-03-28 12:22:14 +08:00
/* vt8251 doesn't clear BSY on signature FIS reception,
* request follow-up softreset.
*/
return online ? -EAGAIN : rc;
ahci: implement PMP support Implement AHCI PMP support. ahci only supports command based switching. Also, for some reason, NCQ over PMP doesn't work now. Other than that, everything works. Tested on ICH9R, JMB360/363 + SIMG3726, 4726 and 5744. Signed-off-by: Tejun Heo <htejun@gmail.com> Cc: Forrest Zhao <forrest.zhao@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-09-23 12:19:54 +08:00
}
ahci: Move generic code into libahci This patch should contain no functional changes, just moves code around. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-03-28 12:22:14 +08:00
static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
unsigned long deadline)
ahci: implement PMP support Implement AHCI PMP support. ahci only supports command based switching. Also, for some reason, NCQ over PMP doesn't work now. Other than that, everything works. Tested on ICH9R, JMB360/363 + SIMG3726, 4726 and 5744. Signed-off-by: Tejun Heo <htejun@gmail.com> Cc: Forrest Zhao <forrest.zhao@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-09-23 12:19:54 +08:00
{
ahci: Move generic code into libahci This patch should contain no functional changes, just moves code around. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-03-28 12:22:14 +08:00
struct ata_port *ap = link->ap;
ahci: clean up PORT_IRQ_BAD_PMP enabling Now that we have pp->intr_mask, move PORT_IRQ_BAD_PMP enabling to ahci_pmp_attach/detach() where it belongs. Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-10-09 14:01:37 +08:00
struct ahci_port_priv *pp = ap->private_data;
libahci: Allow drivers to override start_engine Allwinner A10 and A20 ARM SoCs have an AHCI sata controller which needs a special register to be poked before starting the DMA engine. This register gets reset on an ahci_stop_engine call, so there is no other place then ahci_start_engine where this poking can be done. This commit allows drivers to override ahci_start_engine behavior for use by the Allwinner AHCI driver (and potentially other drivers in the future). Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2014-02-22 23:53:30 +08:00
struct ahci_host_priv *hpriv = ap->host->private_data;
ahci: Move generic code into libahci This patch should contain no functional changes, just moves code around. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-03-28 12:22:14 +08:00
u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
struct ata_taskfile tf;
bool online;
int rc;
ahci: implement PMP support Implement AHCI PMP support. ahci only supports command based switching. Also, for some reason, NCQ over PMP doesn't work now. Other than that, everything works. Tested on ICH9R, JMB360/363 + SIMG3726, 4726 and 5744. Signed-off-by: Tejun Heo <htejun@gmail.com> Cc: Forrest Zhao <forrest.zhao@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-09-23 12:19:54 +08:00
libahci: Allow drivers to override stop_engine Marvell armada37xx, armada7k and armada8k share the same AHCI sata controller IP, and currently there is an issue (Errata Ref#226)that the SATA can not be detected via SATA Port-MultiPlayer(PMP). After debugging, the reason is found that the value of Port-x FIS-based Switching Control (PxFBS@0x40) became wrong. According to design, the bits[11:8, 0] of register PxFBS are cleared when Port Command and Status (0x18) bit[0] changes its value from 1 to 0, i.e. falling edge of Port Command and Status bit[0] sends PULSE that resets PxFBS bits[11:8; 0]. So it needs save the port PxFBS register before PxCMD ST write and restore the port PxFBS register afterwards in ahci_stop_engine(). This commit allows drivers to override ahci_stop_engine behavior for use by the Marvell AHCI driver(and potentially other drivers in the future). Signed-off-by: Evan Wang <xswang@marvell.com> Cc: Ofer Heifetz <oferh@marvell.com> Cc: Tejun Heo <tj@kernel.org> Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2018-04-13 12:32:30 +08:00
hpriv->stop_engine(ap);
ahci.c: fix CONFIG_PM=n compilation Commit df69c9c5438b4e396a64d42608b2a6c48a3e7475 moved only prototype of out of CONFIG_PM. Move function out as well. Box seems to boot fine. Signed-off-by: Alexey Dobriyan <adobriyan@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-07-18 03:48:48 +08:00
ahci: Move generic code into libahci This patch should contain no functional changes, just moves code around. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-03-28 12:22:14 +08:00
/* clear D2H reception area to properly wait for D2H FIS */
ata_tf_init(link->device, &tf);
ata: add/use ata_taskfile::{error|status} fields Add the explicit error and status register fields to 'struct ata_taskfile' using the anonymous *union*s ('struct ide_taskfile' had that for ages!) and update the libata taskfile code accordingly. There should be no object code changes resulting from that... Signed-off-by: Sergey Shtylyov <s.shtylyov@omp.ru> Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
2022-02-16 02:49:26 +08:00
tf.status = ATA_BUSY;
ahci: Move generic code into libahci This patch should contain no functional changes, just moves code around. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-03-28 12:22:14 +08:00
ata_tf_to_fis(&tf, 0, 0, d2h_fis);
ahci: implement PMP support Implement AHCI PMP support. ahci only supports command based switching. Also, for some reason, NCQ over PMP doesn't work now. Other than that, everything works. Tested on ICH9R, JMB360/363 + SIMG3726, 4726 and 5744. Signed-off-by: Tejun Heo <htejun@gmail.com> Cc: Forrest Zhao <forrest.zhao@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-09-23 12:19:54 +08:00
ahci: Move generic code into libahci This patch should contain no functional changes, just moves code around. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-03-28 12:22:14 +08:00
rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
deadline, &online, NULL);
ahci.c: fix CONFIG_PM=n compilation Commit df69c9c5438b4e396a64d42608b2a6c48a3e7475 moved only prototype of out of CONFIG_PM. Move function out as well. Box seems to boot fine. Signed-off-by: Alexey Dobriyan <adobriyan@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-07-18 03:48:48 +08:00
libahci: Allow drivers to override start_engine Allwinner A10 and A20 ARM SoCs have an AHCI sata controller which needs a special register to be poked before starting the DMA engine. This register gets reset on an ahci_stop_engine call, so there is no other place then ahci_start_engine where this poking can be done. This commit allows drivers to override ahci_start_engine behavior for use by the Allwinner AHCI driver (and potentially other drivers in the future). Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2014-02-22 23:53:30 +08:00
hpriv->start_engine(ap);
[PATCH] ahci: implement Power Management support Implement power management support. Original implementation is from Zhao, Forrest <forrest.zhao@intel.com> Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Zhao, Forrest <forrest.zhao@intel.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2006-07-26 14:59:26 +08:00
ahci: Move generic code into libahci This patch should contain no functional changes, just moves code around. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-03-28 12:22:14 +08:00
/* The pseudo configuration device on SIMG4726 attached to
* ASUS P5W-DH Deluxe doesn't send signature FIS after
* hardreset if no device is attached to the first downstream
* port && the pseudo device locks up on SRST w/ PMP==0. To
* work around this, wait for !BSY only briefly. If BSY isn't
* cleared, perform CLO and proceed to IDENTIFY (achieved by
* ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
*
* Wait for two seconds. Devices attached to downstream port
* which can't process the following IDENTIFY after this will
* have to be reset again. For most cases, this should
* suffice while making probing snappish enough.
*/
if (online) {
rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
ahci_check_ready);
if (rc)
ahci_kick_engine(ap);
[PATCH] ahci: implement Power Management support Implement power management support. Original implementation is from Zhao, Forrest <forrest.zhao@intel.com> Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Zhao, Forrest <forrest.zhao@intel.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2006-07-26 14:59:26 +08:00
}
return rc;
}
ahci: avoton port-disable reset-quirk Avoton AHCI occasionally sees drive probe timeouts at driver load time. When this happens SCR_STATUS indicates device detected, but no D2H FIS reception. Reset the internal link state machines by bouncing port-enable in the PCS register when this occurs. Cc: <stable@vger.kernel.org> Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2015-05-09 03:23:55 +08:00
/*
* ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports.
*
* It has been observed with some SSDs that the timing of events in the
* link synchronization phase can leave the port in a state that can not
* be recovered by a SATA-hard-reset alone. The failing signature is
* SStatus.DET stuck at 1 ("Device presence detected but Phy
* communication not established"). It was found that unloading and
* reloading the driver when this problem occurs allows the drive
* connection to be recovered (DET advanced to 0x3). The critical
* component of reloading the driver is that the port state machines are
* reset by bouncing "port enable" in the AHCI PCS configuration
* register. So, reproduce that effect by bouncing a port whenever we
* see DET==1 after a reset.
*/
static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
unsigned long deadline)
{
ata: fix debounce timings type sata_deb_timing_{hotplug|long|normal}[] store 'unsigned long' debounce timeouts in ms, while sata_link_debounce() eventually uses those timeouts by calling ata_{deadline|msleep}( which take just 'unsigned int'. Change the debounce timeout table element's type to 'unsigned int' -- all these timeouts happily fit into 'unsigned int'... Signed-off-by: Sergey Shtylyov <s.shtylyov@omp.ru> Signed-off-by: Damien Le Moal <dlemoal@kernel.org>
2023-07-30 04:17:49 +08:00
const unsigned int *timing = sata_ehc_deb_timing(&link->eh_context);
ahci: avoton port-disable reset-quirk Avoton AHCI occasionally sees drive probe timeouts at driver load time. When this happens SCR_STATUS indicates device detected, but no D2H FIS reception. Reset the internal link state machines by bouncing port-enable in the PCS register when this occurs. Cc: <stable@vger.kernel.org> Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2015-05-09 03:23:55 +08:00
struct ata_port *ap = link->ap;
struct ahci_port_priv *pp = ap->private_data;
struct ahci_host_priv *hpriv = ap->host->private_data;
u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
unsigned long tmo = deadline - jiffies;
struct ata_taskfile tf;
bool online;
int rc, i;
libahci: Allow drivers to override stop_engine Marvell armada37xx, armada7k and armada8k share the same AHCI sata controller IP, and currently there is an issue (Errata Ref#226)that the SATA can not be detected via SATA Port-MultiPlayer(PMP). After debugging, the reason is found that the value of Port-x FIS-based Switching Control (PxFBS@0x40) became wrong. According to design, the bits[11:8, 0] of register PxFBS are cleared when Port Command and Status (0x18) bit[0] changes its value from 1 to 0, i.e. falling edge of Port Command and Status bit[0] sends PULSE that resets PxFBS bits[11:8; 0]. So it needs save the port PxFBS register before PxCMD ST write and restore the port PxFBS register afterwards in ahci_stop_engine(). This commit allows drivers to override ahci_stop_engine behavior for use by the Marvell AHCI driver(and potentially other drivers in the future). Signed-off-by: Evan Wang <xswang@marvell.com> Cc: Ofer Heifetz <oferh@marvell.com> Cc: Tejun Heo <tj@kernel.org> Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2018-04-13 12:32:30 +08:00
hpriv->stop_engine(ap);
ahci: avoton port-disable reset-quirk Avoton AHCI occasionally sees drive probe timeouts at driver load time. When this happens SCR_STATUS indicates device detected, but no D2H FIS reception. Reset the internal link state machines by bouncing port-enable in the PCS register when this occurs. Cc: <stable@vger.kernel.org> Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2015-05-09 03:23:55 +08:00
for (i = 0; i < 2; i++) {
u16 val;
u32 sstatus;
int port = ap->port_no;
struct ata_host *host = ap->host;
struct pci_dev *pdev = to_pci_dev(host->dev);
/* clear D2H reception area to properly wait for D2H FIS */
ata_tf_init(link->device, &tf);
ata: add/use ata_taskfile::{error|status} fields Add the explicit error and status register fields to 'struct ata_taskfile' using the anonymous *union*s ('struct ide_taskfile' had that for ages!) and update the libata taskfile code accordingly. There should be no object code changes resulting from that... Signed-off-by: Sergey Shtylyov <s.shtylyov@omp.ru> Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
2022-02-16 02:49:26 +08:00
tf.status = ATA_BUSY;
ahci: avoton port-disable reset-quirk Avoton AHCI occasionally sees drive probe timeouts at driver load time. When this happens SCR_STATUS indicates device detected, but no D2H FIS reception. Reset the internal link state machines by bouncing port-enable in the PCS register when this occurs. Cc: <stable@vger.kernel.org> Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2015-05-09 03:23:55 +08:00
ata_tf_to_fis(&tf, 0, 0, d2h_fis);
rc = sata_link_hardreset(link, timing, deadline, &online,
ahci_check_ready);
if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 ||
(sstatus & 0xf) != 1)
break;
ata: ahci: use ata_link_info() instead of ata_link_printk() Using ata_link_info() instead of ata_link_printk(). Signed-off-by: Xu Wang <vulab@iscas.ac.cn> Signed-off-by: Jens Axboe <axboe@kernel.dk>
2020-08-17 11:29:13 +08:00
ata_link_info(link, "avn bounce port%d\n", port);
ahci: avoton port-disable reset-quirk Avoton AHCI occasionally sees drive probe timeouts at driver load time. When this happens SCR_STATUS indicates device detected, but no D2H FIS reception. Reset the internal link state machines by bouncing port-enable in the PCS register when this occurs. Cc: <stable@vger.kernel.org> Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2015-05-09 03:23:55 +08:00
pci_read_config_word(pdev, 0x92, &val);
val &= ~(1 << port);
pci_write_config_word(pdev, 0x92, val);
ata_msleep(ap, 1000);
val |= 1 << port;
pci_write_config_word(pdev, 0x92, val);
deadline += tmo;
}
hpriv->start_engine(ap);
if (online)
*class = ahci_dev_classify(ap);
return rc;
}
ahci: Add runtime PM support for the host controller This patch adds runtime PM support for the AHCI host controller driver so that the host controller is powered down when all SATA ports are runtime suspended. Powering down the AHCI host controller can reduce power consumption and possibly allow the CPU to enter lower power idle states (S0ix) during runtime. Runtime PM is blocked by default and needs to be unblocked from userspace as needed (via power/* sysfs nodes). Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2016-02-18 16:54:17 +08:00
#ifdef CONFIG_PM
static void ahci_pci_disable_interrupts(struct ata_host *host)
[PATCH] ahci: implement Power Management support Implement power management support. Original implementation is from Zhao, Forrest <forrest.zhao@intel.com> Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Zhao, Forrest <forrest.zhao@intel.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2006-07-26 14:59:26 +08:00
{
ahci: add warning messages for hp laptops with broken suspend Harddisks on HP dv[4-6] and HDX18 fail to come online after resume on earlier BIOSen. Fortunately, HP recently released BIOS updates for all machines to fix the issue. Detect old BIOSen, warn the user to update BIOS on boot and suspend attempts and fail suspend. Kudos to all the bug reporters. Signed-off-by: Tejun Heo <tj@kernel.org> Cc: kernel.org@epperson.homelinux.net Cc: emisca@gmail.com Cc: Gadi Cohen <dragon@wastelands.net> Cc: Paul Swanson <paul@procursa.com> Cc: s@ourada.org Cc: Trevor Davenport <trevor.davenport@gmail.com> Cc: corruptor1972 <steven_tierney@yahoo.co.uk> Cc: Victoria Wilson <mail@vwilson.co.uk> Cc: khiraly <khiraly.list@gmail.com> Cc: Sean <wollombi@gmail.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-05-30 19:50:12 +08:00
struct ahci_host_priv *hpriv = host->private_data;
ahci: Get rid of host->iomap usage Currently the driver uses host->iomap to store all the iomapped BARs of a PCI device (while AHCI devices actually use just a single memory window). We're going to teach AHCI to work with non-PCI buses, so there are two options to make this work: 1. "fake" host->iomap array for non-PCI devices, and place the needed address at iomap[AHCI_PCI_BAR]; 2. Get rid of host->iomap usage, instead introduce a private mmio field. This patch implements the second option. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-03-04 01:17:34 +08:00
void __iomem *mmio = hpriv->mmio;
[PATCH] ahci: implement Power Management support Implement power management support. Original implementation is from Zhao, Forrest <forrest.zhao@intel.com> Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Zhao, Forrest <forrest.zhao@intel.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2006-07-26 14:59:26 +08:00
u32 ctl;
ahci: Convert driver to use modern PM hooks In order to add support for runtime PM to the ahci driver we first need to convert the driver to use modern non-legacy system suspend hooks. There should be no functional changes. tj: Updated .driver.pm init for older compilers as suggested by Andy and Chrsitoph. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Cc: Andy Shevchenko <andy.shevchenko@gmail.com> Cc: Christoph Hellwig <hch@infradead.org> Signed-off-by: Tejun Heo <tj@kernel.org>
2016-02-18 16:54:15 +08:00
/* AHCI spec rev1.1 section 8.3.3:
* Software must disable interrupts prior to requesting a
* transition of the HBA to D3 state.
*/
ctl = readl(mmio + HOST_CTL);
ctl &= ~HOST_IRQ_EN;
writel(ctl, mmio + HOST_CTL);
readl(mmio + HOST_CTL); /* flush */
ahci: Add runtime PM support for the host controller This patch adds runtime PM support for the AHCI host controller driver so that the host controller is powered down when all SATA ports are runtime suspended. Powering down the AHCI host controller can reduce power consumption and possibly allow the CPU to enter lower power idle states (S0ix) during runtime. Runtime PM is blocked by default and needs to be unblocked from userspace as needed (via power/* sysfs nodes). Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2016-02-18 16:54:17 +08:00
}
static int ahci_pci_device_runtime_suspend(struct device *dev)
{
struct pci_dev *pdev = to_pci_dev(dev);
struct ata_host *host = pci_get_drvdata(pdev);
[PATCH] ahci: implement Power Management support Implement power management support. Original implementation is from Zhao, Forrest <forrest.zhao@intel.com> Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Zhao, Forrest <forrest.zhao@intel.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2006-07-26 14:59:26 +08:00
ahci: Add runtime PM support for the host controller This patch adds runtime PM support for the AHCI host controller driver so that the host controller is powered down when all SATA ports are runtime suspended. Powering down the AHCI host controller can reduce power consumption and possibly allow the CPU to enter lower power idle states (S0ix) during runtime. Runtime PM is blocked by default and needs to be unblocked from userspace as needed (via power/* sysfs nodes). Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2016-02-18 16:54:17 +08:00
ahci_pci_disable_interrupts(host);
return 0;
}
static int ahci_pci_device_runtime_resume(struct device *dev)
{
struct pci_dev *pdev = to_pci_dev(dev);
struct ata_host *host = pci_get_drvdata(pdev);
int rc;
ata: ahci: Fix PCS quirk application for suspend Since kernel 5.3.4 my laptop (ICH8M controller) does not see Kingston SV300S37A60G SSD disk connected into a SATA connector on wake from suspend. The problem was introduced in c312ef176399 ("libata/ahci: Drop PCS quirk for Denverton and beyond"): the quirk is not applied on wake from suspend as it originally was. It is worth to mention the commit contained another bug: the quirk is not applied at all to controllers which require it. The fix commit 09d6ac8dc51a ("libata/ahci: Fix PCS quirk application") landed in 5.3.8. So testing my patch anywhere between commits c312ef176399 and 09d6ac8dc51a is pointless. Not all disks trigger the problem. For example nothing bad happens with Western Digital WD5000LPCX HDD. Test hardware: - Acer 5920G with ICH8M SATA controller - sda: some SATA HDD connnected into the DVD drive IDE port with a SATA-IDE caddy. It is a boot disk - sdb: Kingston SV300S37A60G SSD connected into the only SATA port Sample "dmesg --notime | grep -E '^(sd |ata)'" output on wake: sd 0:0:0:0: [sda] Starting disk sd 2:0:0:0: [sdb] Starting disk ata4: SATA link down (SStatus 4 SControl 300) ata3: SATA link down (SStatus 4 SControl 300) ata1.00: ACPI cmd ef/03:0c:00:00:00:a0 (SET FEATURES) filtered out ata1.00: ACPI cmd ef/03:42:00:00:00:a0 (SET FEATURES) filtered out ata1: FORCE: cable set to 80c ata5: SATA link down (SStatus 0 SControl 300) ata3: SATA link down (SStatus 4 SControl 300) ata3: SATA link down (SStatus 4 SControl 300) ata3.00: disabled sd 2:0:0:0: rejecting I/O to offline device ata3.00: detaching (SCSI 2:0:0:0) sd 2:0:0:0: [sdb] Start/Stop Unit failed: Result: hostbyte=DID_NO_CONNECT driverbyte=DRIVER_OK sd 2:0:0:0: [sdb] Synchronizing SCSI cache sd 2:0:0:0: [sdb] Synchronize Cache(10) failed: Result: hostbyte=DID_BAD_TARGET driverbyte=DRIVER_OK sd 2:0:0:0: [sdb] Stopping disk sd 2:0:0:0: [sdb] Start/Stop Unit failed: Result: hostbyte=DID_BAD_TARGET driverbyte=DRIVER_OK Commit c312ef176399 dropped ahci_pci_reset_controller() which internally calls ahci_reset_controller() and applies the PCS quirk if needed after that. It was called each time a reset was required instead of just ahci_reset_controller(). This patch puts the function back in place. Fixes: c312ef176399 ("libata/ahci: Drop PCS quirk for Denverton and beyond") Signed-off-by: Adam Vodopjan <grozzly@protonmail.com> Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
2022-12-09 17:26:34 +08:00
rc = ahci_pci_reset_controller(host);
ahci: Add runtime PM support for the host controller This patch adds runtime PM support for the AHCI host controller driver so that the host controller is powered down when all SATA ports are runtime suspended. Powering down the AHCI host controller can reduce power consumption and possibly allow the CPU to enter lower power idle states (S0ix) during runtime. Runtime PM is blocked by default and needs to be unblocked from userspace as needed (via power/* sysfs nodes). Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2016-02-18 16:54:17 +08:00
if (rc)
return rc;
ahci_pci_init_controller(host);
return 0;
}
#ifdef CONFIG_PM_SLEEP
static int ahci_pci_device_suspend(struct device *dev)
{
struct pci_dev *pdev = to_pci_dev(dev);
struct ata_host *host = pci_get_drvdata(pdev);
struct ahci_host_priv *hpriv = host->private_data;
if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
dev_err(&pdev->dev,
"BIOS update required for suspend/resume\n");
return -EIO;
}
ahci_pci_disable_interrupts(host);
ata: libata: make ata_host_suspend() *void* ata_host_suspend() always returns 0, so the result checks in many drivers look pointless. Let's make this function return *void* instead of *int*. Found by Linux Verification Center (linuxtesting.org) with the SVACE static analysis tool. Signed-off-by: Sergey Shtylyov <s.shtylyov@omp.ru> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Reviewed-by: Hannes Reinecke <hare@suse.de> Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
2022-02-03 04:58:21 +08:00
ata_host_suspend(host, PMSG_SUSPEND);
return 0;
[PATCH] ahci: implement Power Management support Implement power management support. Original implementation is from Zhao, Forrest <forrest.zhao@intel.com> Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Zhao, Forrest <forrest.zhao@intel.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2006-07-26 14:59:26 +08:00
}
ahci: Convert driver to use modern PM hooks In order to add support for runtime PM to the ahci driver we first need to convert the driver to use modern non-legacy system suspend hooks. There should be no functional changes. tj: Updated .driver.pm init for older compilers as suggested by Andy and Chrsitoph. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Cc: Andy Shevchenko <andy.shevchenko@gmail.com> Cc: Christoph Hellwig <hch@infradead.org> Signed-off-by: Tejun Heo <tj@kernel.org>
2016-02-18 16:54:15 +08:00
static int ahci_pci_device_resume(struct device *dev)
[PATCH] ahci: implement Power Management support Implement power management support. Original implementation is from Zhao, Forrest <forrest.zhao@intel.com> Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Zhao, Forrest <forrest.zhao@intel.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2006-07-26 14:59:26 +08:00
{
ahci: Convert driver to use modern PM hooks In order to add support for runtime PM to the ahci driver we first need to convert the driver to use modern non-legacy system suspend hooks. There should be no functional changes. tj: Updated .driver.pm init for older compilers as suggested by Andy and Chrsitoph. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Cc: Andy Shevchenko <andy.shevchenko@gmail.com> Cc: Christoph Hellwig <hch@infradead.org> Signed-off-by: Tejun Heo <tj@kernel.org>
2016-02-18 16:54:15 +08:00
struct pci_dev *pdev = to_pci_dev(dev);
ata: use pci_get_drvdata() Use the wrapper function for getting the driver data using pci_dev instead of using dev_get_drvdata() with &pdev->dev, so we can directly pass a struct pci_dev. This is a purely cosmetic change. Signed-off-by: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2013-06-03 13:05:36 +08:00
struct ata_host *host = pci_get_drvdata(pdev);
[PATCH] ahci: implement Power Management support Implement power management support. Original implementation is from Zhao, Forrest <forrest.zhao@intel.com> Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Zhao, Forrest <forrest.zhao@intel.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2006-07-26 14:59:26 +08:00
int rc;
ahci: mcp89: enter AHCI mode under Apple BIOS emulation Apple's BIOS emulation forcibly disables MCP89 AHCI, eg. on Macbook7,1. We can re-enable it, replacing the previous workaround of using ata_generic. tj: whitespace adjustments, dropped inline from is_mcp89_apple() Signed-off-by: James Laird <jhl@mafipulation.org> Signed-off-by: Tejun Heo <tj@kernel.org>
2013-11-19 08:06:38 +08:00
/* Apple BIOS helpfully mangles the registers on resume */
if (is_mcp89_apple(pdev))
ahci_mcp89_apple_enable(pdev);
[PATCH] ahci: implement Power Management support Implement power management support. Original implementation is from Zhao, Forrest <forrest.zhao@intel.com> Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Zhao, Forrest <forrest.zhao@intel.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2006-07-26 14:59:26 +08:00
if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
ata: ahci: Fix PCS quirk application for suspend Since kernel 5.3.4 my laptop (ICH8M controller) does not see Kingston SV300S37A60G SSD disk connected into a SATA connector on wake from suspend. The problem was introduced in c312ef176399 ("libata/ahci: Drop PCS quirk for Denverton and beyond"): the quirk is not applied on wake from suspend as it originally was. It is worth to mention the commit contained another bug: the quirk is not applied at all to controllers which require it. The fix commit 09d6ac8dc51a ("libata/ahci: Fix PCS quirk application") landed in 5.3.8. So testing my patch anywhere between commits c312ef176399 and 09d6ac8dc51a is pointless. Not all disks trigger the problem. For example nothing bad happens with Western Digital WD5000LPCX HDD. Test hardware: - Acer 5920G with ICH8M SATA controller - sda: some SATA HDD connnected into the DVD drive IDE port with a SATA-IDE caddy. It is a boot disk - sdb: Kingston SV300S37A60G SSD connected into the only SATA port Sample "dmesg --notime | grep -E '^(sd |ata)'" output on wake: sd 0:0:0:0: [sda] Starting disk sd 2:0:0:0: [sdb] Starting disk ata4: SATA link down (SStatus 4 SControl 300) ata3: SATA link down (SStatus 4 SControl 300) ata1.00: ACPI cmd ef/03:0c:00:00:00:a0 (SET FEATURES) filtered out ata1.00: ACPI cmd ef/03:42:00:00:00:a0 (SET FEATURES) filtered out ata1: FORCE: cable set to 80c ata5: SATA link down (SStatus 0 SControl 300) ata3: SATA link down (SStatus 4 SControl 300) ata3: SATA link down (SStatus 4 SControl 300) ata3.00: disabled sd 2:0:0:0: rejecting I/O to offline device ata3.00: detaching (SCSI 2:0:0:0) sd 2:0:0:0: [sdb] Start/Stop Unit failed: Result: hostbyte=DID_NO_CONNECT driverbyte=DRIVER_OK sd 2:0:0:0: [sdb] Synchronizing SCSI cache sd 2:0:0:0: [sdb] Synchronize Cache(10) failed: Result: hostbyte=DID_BAD_TARGET driverbyte=DRIVER_OK sd 2:0:0:0: [sdb] Stopping disk sd 2:0:0:0: [sdb] Start/Stop Unit failed: Result: hostbyte=DID_BAD_TARGET driverbyte=DRIVER_OK Commit c312ef176399 dropped ahci_pci_reset_controller() which internally calls ahci_reset_controller() and applies the PCS quirk if needed after that. It was called each time a reset was required instead of just ahci_reset_controller(). This patch puts the function back in place. Fixes: c312ef176399 ("libata/ahci: Drop PCS quirk for Denverton and beyond") Signed-off-by: Adam Vodopjan <grozzly@protonmail.com> Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
2022-12-09 17:26:34 +08:00
rc = ahci_pci_reset_controller(host);
[PATCH] ahci: implement Power Management support Implement power management support. Original implementation is from Zhao, Forrest <forrest.zhao@intel.com> Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Zhao, Forrest <forrest.zhao@intel.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2006-07-26 14:59:26 +08:00
if (rc)
return rc;
ahci: Factor out PCI specifics from ahci_init_controller() Move PCI stuff into ahci_pci_init_controller(). Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-03-04 01:17:42 +08:00
ahci_pci_init_controller(host);
[PATCH] ahci: implement Power Management support Implement power management support. Original implementation is from Zhao, Forrest <forrest.zhao@intel.com> Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Zhao, Forrest <forrest.zhao@intel.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2006-07-26 14:59:26 +08:00
}
libata: Grand renaming. The biggest change is that ata_host_set is renamed to ata_host. * ata_host_set => ata_host * ata_probe_ent->host_flags => ata_probe_ent->port_flags * ata_probe_ent->host_set_flags => ata_probe_ent->_host_flags * ata_host_stats => ata_port_stats * ata_port->host => ata_port->scsi_host * ata_port->host_set => ata_port->host * ata_port_info->host_flags => ata_port_info->flags * ata_(.*)host_set(.*)\(\) => ata_\1host\2() The leading underscore in ata_probe_ent->_host_flags is to avoid reusing ->host_flags for different purpose. Currently, the only user of the field is libata-bmdma.c and probe_ent itself is scheduled to be removed. ata_port->host is reused for different purpose but this field is used inside libata core proper and of different type. Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2006-08-24 15:19:22 +08:00
ata_host_resume(host);
[PATCH] ahci: implement Power Management support Implement power management support. Original implementation is from Zhao, Forrest <forrest.zhao@intel.com> Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Zhao, Forrest <forrest.zhao@intel.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2006-07-26 14:59:26 +08:00
return 0;
}
libata: add missing CONFIG_PM in LLDs Add missing #ifdef CONFIG_PM conditionals around all PM related parts in libata LLDs. Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-03-02 16:31:26 +08:00
#endif
[PATCH] ahci: implement Power Management support Implement power management support. Original implementation is from Zhao, Forrest <forrest.zhao@intel.com> Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Zhao, Forrest <forrest.zhao@intel.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2006-07-26 14:59:26 +08:00
ahci: Add runtime PM support for the host controller This patch adds runtime PM support for the AHCI host controller driver so that the host controller is powered down when all SATA ports are runtime suspended. Powering down the AHCI host controller can reduce power consumption and possibly allow the CPU to enter lower power idle states (S0ix) during runtime. Runtime PM is blocked by default and needs to be unblocked from userspace as needed (via power/* sysfs nodes). Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2016-02-18 16:54:17 +08:00
#endif /* CONFIG_PM */
ahci: add 43-bit DMA address quirk for ASMedia ASM1061 controllers With one of the on-board ASM1061 AHCI controllers (1b21:0612) on an ASUSTeK Pro WS WRX80E-SAGE SE WIFI mainboard, a controller hang was observed that was immediately preceded by the following kernel messages: ahci 0000:28:00.0: Using 64-bit DMA addresses ahci 0000:28:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0035 address=0x7fffff00000 flags=0x0000] ahci 0000:28:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0035 address=0x7fffff00300 flags=0x0000] ahci 0000:28:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0035 address=0x7fffff00380 flags=0x0000] ahci 0000:28:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0035 address=0x7fffff00400 flags=0x0000] ahci 0000:28:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0035 address=0x7fffff00680 flags=0x0000] ahci 0000:28:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0035 address=0x7fffff00700 flags=0x0000] The first message is produced by code in drivers/iommu/dma-iommu.c which is accompanied by the following comment that seems to apply: /* * Try to use all the 32-bit PCI addresses first. The original SAC vs. * DAC reasoning loses relevance with PCIe, but enough hardware and * firmware bugs are still lurking out there that it's safest not to * venture into the 64-bit space until necessary. * * If your device goes wrong after seeing the notice then likely either * its driver is not setting DMA masks accurately, the hardware has * some inherent bug in handling >32-bit addresses, or not all the * expected address bits are wired up between the device and the IOMMU. */ Asking the ASM1061 on a discrete PCIe card to DMA from I/O virtual address 0xffffffff00000000 produces the following I/O page faults: vfio-pci 0000:07:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0021 address=0x7ff00000000 flags=0x0010] vfio-pci 0000:07:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0021 address=0x7ff00000500 flags=0x0010] Note that the upper 21 bits of the logged DMA address are zero. (When asking a different PCIe device in the same PCIe slot to DMA to the same I/O virtual address, we do see all the upper 32 bits of the DMA address as 1, so this is not an issue with the chipset or IOMMU configuration on the test system.) Also, hacking libahci to always set the upper 21 bits of all DMA addresses to 1 produces no discernible effect on the behavior of the ASM1061, and mkfs/mount/scrub/etc work as without this hack. This all strongly suggests that the ASM1061 has a 43 bit DMA address limit, and this commit therefore adds a quirk to deal with this limit. This issue probably applies to (some of) the other supported ASMedia parts as well, but we limit it to the PCI IDs known to refer to ASM1061 parts, as that's the only part we know for sure to be affected by this issue at this point. Link: https://lore.kernel.org/linux-ide/ZaZ2PIpEId-rl6jv@wantstofly.org/ Signed-off-by: Lennert Buytenhek <kernel@wantstofly.org> [cassel: drop date from error messages in commit log] Signed-off-by: Niklas Cassel <cassel@kernel.org>
2024-01-25 23:04:01 +08:00
static int ahci_configure_dma_masks(struct pci_dev *pdev,
struct ahci_host_priv *hpriv)
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 06:20:36 +08:00
{
ahci: add 43-bit DMA address quirk for ASMedia ASM1061 controllers With one of the on-board ASM1061 AHCI controllers (1b21:0612) on an ASUSTeK Pro WS WRX80E-SAGE SE WIFI mainboard, a controller hang was observed that was immediately preceded by the following kernel messages: ahci 0000:28:00.0: Using 64-bit DMA addresses ahci 0000:28:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0035 address=0x7fffff00000 flags=0x0000] ahci 0000:28:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0035 address=0x7fffff00300 flags=0x0000] ahci 0000:28:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0035 address=0x7fffff00380 flags=0x0000] ahci 0000:28:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0035 address=0x7fffff00400 flags=0x0000] ahci 0000:28:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0035 address=0x7fffff00680 flags=0x0000] ahci 0000:28:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0035 address=0x7fffff00700 flags=0x0000] The first message is produced by code in drivers/iommu/dma-iommu.c which is accompanied by the following comment that seems to apply: /* * Try to use all the 32-bit PCI addresses first. The original SAC vs. * DAC reasoning loses relevance with PCIe, but enough hardware and * firmware bugs are still lurking out there that it's safest not to * venture into the 64-bit space until necessary. * * If your device goes wrong after seeing the notice then likely either * its driver is not setting DMA masks accurately, the hardware has * some inherent bug in handling >32-bit addresses, or not all the * expected address bits are wired up between the device and the IOMMU. */ Asking the ASM1061 on a discrete PCIe card to DMA from I/O virtual address 0xffffffff00000000 produces the following I/O page faults: vfio-pci 0000:07:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0021 address=0x7ff00000000 flags=0x0010] vfio-pci 0000:07:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0021 address=0x7ff00000500 flags=0x0010] Note that the upper 21 bits of the logged DMA address are zero. (When asking a different PCIe device in the same PCIe slot to DMA to the same I/O virtual address, we do see all the upper 32 bits of the DMA address as 1, so this is not an issue with the chipset or IOMMU configuration on the test system.) Also, hacking libahci to always set the upper 21 bits of all DMA addresses to 1 produces no discernible effect on the behavior of the ASM1061, and mkfs/mount/scrub/etc work as without this hack. This all strongly suggests that the ASM1061 has a 43 bit DMA address limit, and this commit therefore adds a quirk to deal with this limit. This issue probably applies to (some of) the other supported ASMedia parts as well, but we limit it to the PCI IDs known to refer to ASM1061 parts, as that's the only part we know for sure to be affected by this issue at this point. Link: https://lore.kernel.org/linux-ide/ZaZ2PIpEId-rl6jv@wantstofly.org/ Signed-off-by: Lennert Buytenhek <kernel@wantstofly.org> [cassel: drop date from error messages in commit log] Signed-off-by: Niklas Cassel <cassel@kernel.org>
2024-01-25 23:04:01 +08:00
int dma_bits;
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 06:20:36 +08:00
int rc;
ahci: add 43-bit DMA address quirk for ASMedia ASM1061 controllers With one of the on-board ASM1061 AHCI controllers (1b21:0612) on an ASUSTeK Pro WS WRX80E-SAGE SE WIFI mainboard, a controller hang was observed that was immediately preceded by the following kernel messages: ahci 0000:28:00.0: Using 64-bit DMA addresses ahci 0000:28:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0035 address=0x7fffff00000 flags=0x0000] ahci 0000:28:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0035 address=0x7fffff00300 flags=0x0000] ahci 0000:28:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0035 address=0x7fffff00380 flags=0x0000] ahci 0000:28:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0035 address=0x7fffff00400 flags=0x0000] ahci 0000:28:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0035 address=0x7fffff00680 flags=0x0000] ahci 0000:28:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0035 address=0x7fffff00700 flags=0x0000] The first message is produced by code in drivers/iommu/dma-iommu.c which is accompanied by the following comment that seems to apply: /* * Try to use all the 32-bit PCI addresses first. The original SAC vs. * DAC reasoning loses relevance with PCIe, but enough hardware and * firmware bugs are still lurking out there that it's safest not to * venture into the 64-bit space until necessary. * * If your device goes wrong after seeing the notice then likely either * its driver is not setting DMA masks accurately, the hardware has * some inherent bug in handling >32-bit addresses, or not all the * expected address bits are wired up between the device and the IOMMU. */ Asking the ASM1061 on a discrete PCIe card to DMA from I/O virtual address 0xffffffff00000000 produces the following I/O page faults: vfio-pci 0000:07:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0021 address=0x7ff00000000 flags=0x0010] vfio-pci 0000:07:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0021 address=0x7ff00000500 flags=0x0010] Note that the upper 21 bits of the logged DMA address are zero. (When asking a different PCIe device in the same PCIe slot to DMA to the same I/O virtual address, we do see all the upper 32 bits of the DMA address as 1, so this is not an issue with the chipset or IOMMU configuration on the test system.) Also, hacking libahci to always set the upper 21 bits of all DMA addresses to 1 produces no discernible effect on the behavior of the ASM1061, and mkfs/mount/scrub/etc work as without this hack. This all strongly suggests that the ASM1061 has a 43 bit DMA address limit, and this commit therefore adds a quirk to deal with this limit. This issue probably applies to (some of) the other supported ASMedia parts as well, but we limit it to the PCI IDs known to refer to ASM1061 parts, as that's the only part we know for sure to be affected by this issue at this point. Link: https://lore.kernel.org/linux-ide/ZaZ2PIpEId-rl6jv@wantstofly.org/ Signed-off-by: Lennert Buytenhek <kernel@wantstofly.org> [cassel: drop date from error messages in commit log] Signed-off-by: Niklas Cassel <cassel@kernel.org>
2024-01-25 23:04:01 +08:00
if (hpriv->cap & HOST_CAP_64) {
dma_bits = 64;
if (hpriv->flags & AHCI_HFLAG_43BIT_ONLY)
dma_bits = 43;
} else {
dma_bits = 32;
}
ahci: support the STA2X11 I/O Hub The AHCI controller found in the STA2X11 chip uses BAR number 0 instead of 5. Also, the chip's fixup code sets a special DMA mask for all of its PCI functions, and the mask must be preserved here. Signed-off-by: Alessandro Rubini <rubini@gnudd.com> Acked-by: Giancarlo Asnaghi <giancarlo.asnaghi@st.com> Cc: Alan Cox <alan@linux.intel.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2012-01-06 20:33:39 +08:00
/*
* If the device fixup already set the dma_mask to some non-standard
* value, don't extend it here. This happens on STA2X11, for example.
ahci: use dma_set_mask_and_coherent Use the dma_set_mask_and_coherent helper to set the DMA mask. Rely on the relatively recent change that setting a larger than required mask will never fail to avoid the need for the boilerplate 32-bit fallback code. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Jens Axboe <axboe@kernel.dk>
2019-08-26 18:57:19 +08:00
*
* XXX: manipulating the DMA mask from platform code is completely
dma-mapping: treat dev->bus_dma_mask as a DMA limit Using a mask to represent bus DMA constraints has a set of limitations. The biggest one being it can only hold a power of two (minus one). The DMA mapping code is already aware of this and treats dev->bus_dma_mask as a limit. This quirk is already used by some architectures although still rare. With the introduction of the Raspberry Pi 4 we've found a new contender for the use of bus DMA limits, as its PCIe bus can only address the lower 3GB of memory (of a total of 4GB). This is impossible to represent with a mask. To make things worse the device-tree code rounds non power of two bus DMA limits to the next power of two, which is unacceptable in this case. In the light of this, rename dev->bus_dma_mask to dev->bus_dma_limit all over the tree and treat it as such. Note that dev->bus_dma_limit should contain the higher accessible DMA address. Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Reviewed-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Christoph Hellwig <hch@lst.de>
2019-11-21 17:26:44 +08:00
* bogus, platform code should use dev->bus_dma_limit instead..
ahci: support the STA2X11 I/O Hub The AHCI controller found in the STA2X11 chip uses BAR number 0 instead of 5. Also, the chip's fixup code sets a special DMA mask for all of its PCI functions, and the mask must be preserved here. Signed-off-by: Alessandro Rubini <rubini@gnudd.com> Acked-by: Giancarlo Asnaghi <giancarlo.asnaghi@st.com> Cc: Alan Cox <alan@linux.intel.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2012-01-06 20:33:39 +08:00
*/
if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
return 0;
ahci: use dma_set_mask_and_coherent Use the dma_set_mask_and_coherent helper to set the DMA mask. Rely on the relatively recent change that setting a larger than required mask will never fail to avoid the need for the boilerplate 32-bit fallback code. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Jens Axboe <axboe@kernel.dk>
2019-08-26 18:57:19 +08:00
rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(dma_bits));
if (rc)
dev_err(&pdev->dev, "DMA enable failed\n");
return rc;
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 06:20:36 +08:00
}
ahci: Factor out PCI specifics from ahci_print_info() Introduce ahci_pci_print_info() that now handles PCI stuff. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-03-04 01:17:43 +08:00
static void ahci_pci_print_info(struct ata_host *host)
{
struct pci_dev *pdev = to_pci_dev(host->dev);
u16 cc;
const char *scc_s;
pci_read_config_word(pdev, 0x0a, &cc);
if (cc == PCI_CLASS_STORAGE_IDE)
scc_s = "IDE";
else if (cc == PCI_CLASS_STORAGE_SATA)
scc_s = "SATA";
else if (cc == PCI_CLASS_STORAGE_RAID)
scc_s = "RAID";
else
scc_s = "unknown";
ahci_print_info(host, scc_s);
}
ahci: ahci: implement workaround for ASUS P5W-DH Deluxe ahci_broken_hardreset(), take #2 P5W-DH Deluxe has ICH9 which doesn't have PMP support but SIMG 4726 hardwired to the second port of AHCI controller at PCI device 1f.2. The 4726 doesn't work as PMP but as a storage processor which can do hardware RAID on downstream ports. When no device is attached to the downstream port of the 4726, pseudo ATA device for configuration appears. Unfortunately, ATA emulation on the device is very lousy and causes long hang during boot. This patch implements workaround for the board. If the mainboard is P5W-DH Deluxe (matched using DMI), only hardreset is used on the second port of AHCI controller @ 1f.2 and the hardreset doesn't depend on receiving the first FIS and just proceed to IDENTIFY. This workaround fixes bugzilla #8923. http://bugzilla.kernel.org/show_bug.cgi?id=8923 Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-10-25 13:59:16 +08:00
/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
* hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
* support PMP and the 4726 either directly exports the device
* attached to the first downstream port or acts as a hardware storage
* controller and emulate a single ATA device (can be RAID 0/1 or some
* other configuration).
*
* When there's no device attached to the first downstream port of the
* 4726, "Config Disk" appears, which is a pseudo ATA device to
* configure the 4726. However, ATA emulation of the device is very
* lame. It doesn't send signature D2H Reg FIS after the initial
* hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
*
* The following function works around the problem by always using
* hardreset on the port and not depending on receiving signature FIS
* afterward. If signature FIS isn't received soon, ATA class is
* assumed without follow-up softreset.
*/
static void ahci_p5wdh_workaround(struct ata_host *host)
{
ahci: ahci_p5wdh_workaround - constify DMI table The DMI table does not need to be written to, make it r/o. Signed-off-by: Mathias Krause <minipli@googlemail.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2014-08-31 16:57:09 +08:00
static const struct dmi_system_id sysids[] = {
ahci: ahci: implement workaround for ASUS P5W-DH Deluxe ahci_broken_hardreset(), take #2 P5W-DH Deluxe has ICH9 which doesn't have PMP support but SIMG 4726 hardwired to the second port of AHCI controller at PCI device 1f.2. The 4726 doesn't work as PMP but as a storage processor which can do hardware RAID on downstream ports. When no device is attached to the downstream port of the 4726, pseudo ATA device for configuration appears. Unfortunately, ATA emulation on the device is very lousy and causes long hang during boot. This patch implements workaround for the board. If the mainboard is P5W-DH Deluxe (matched using DMI), only hardreset is used on the second port of AHCI controller @ 1f.2 and the hardreset doesn't depend on receiving the first FIS and just proceed to IDENTIFY. This workaround fixes bugzilla #8923. http://bugzilla.kernel.org/show_bug.cgi?id=8923 Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-10-25 13:59:16 +08:00
{
.ident = "P5W DH Deluxe",
.matches = {
DMI_MATCH(DMI_SYS_VENDOR,
"ASUSTEK COMPUTER INC"),
DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
},
},
{ }
};
struct pci_dev *pdev = to_pci_dev(host->dev);
if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
dmi_check_system(sysids)) {
struct ata_port *ap = host->ports[1];
ata: Convert dev_printk(KERN_<LEVEL> to dev_<level>( Saves a bit of text as the call takes fewer args. Coalesce a few formats. Convert a few bare printks to pr_cont. $ size drivers/ata/built-in.o* text data bss dec hex filename 558429 73893 117864 750186 b726a drivers/ata/built-in.o.allyesconfig.new 559574 73893 117888 751355 b76fb drivers/ata/built-in.o.allyesconfig.old 149567 14689 4220 168476 2921c drivers/ata/built-in.o.defconfig.new 149851 14689 4220 168760 29338 drivers/ata/built-in.o.defconfig.old Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
2011-04-16 06:51:58 +08:00
dev_info(&pdev->dev,
"enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
ahci: ahci: implement workaround for ASUS P5W-DH Deluxe ahci_broken_hardreset(), take #2 P5W-DH Deluxe has ICH9 which doesn't have PMP support but SIMG 4726 hardwired to the second port of AHCI controller at PCI device 1f.2. The 4726 doesn't work as PMP but as a storage processor which can do hardware RAID on downstream ports. When no device is attached to the downstream port of the 4726, pseudo ATA device for configuration appears. Unfortunately, ATA emulation on the device is very lousy and causes long hang during boot. This patch implements workaround for the board. If the mainboard is P5W-DH Deluxe (matched using DMI), only hardreset is used on the second port of AHCI controller @ 1f.2 and the hardreset doesn't depend on receiving the first FIS and just proceed to IDENTIFY. This workaround fixes bugzilla #8923. http://bugzilla.kernel.org/show_bug.cgi?id=8923 Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-10-25 13:59:16 +08:00
ap->ops = &ahci_p5wdh_ops;
ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
}
}
ahci: mcp89: enter AHCI mode under Apple BIOS emulation Apple's BIOS emulation forcibly disables MCP89 AHCI, eg. on Macbook7,1. We can re-enable it, replacing the previous workaround of using ata_generic. tj: whitespace adjustments, dropped inline from is_mcp89_apple() Signed-off-by: James Laird <jhl@mafipulation.org> Signed-off-by: Tejun Heo <tj@kernel.org>
2013-11-19 08:06:38 +08:00
/*
* Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
* booting in BIOS compatibility mode. We restore the registers but not ID.
*/
static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
{
u32 val;
printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
pci_read_config_dword(pdev, 0xf8, &val);
val |= 1 << 0x1b;
/* the following changes the device ID, but appears not to affect function */
/* val = (val & ~0xf0000000) | 0x80000000; */
pci_write_config_dword(pdev, 0xf8, val);
pci_read_config_dword(pdev, 0x54c, &val);
val |= 1 << 0xc;
pci_write_config_dword(pdev, 0x54c, val);
pci_read_config_dword(pdev, 0x4a4, &val);
val &= 0xff;
val |= 0x01060100;
pci_write_config_dword(pdev, 0x4a4, val);
pci_read_config_dword(pdev, 0x54c, &val);
val &= ~(1 << 0xc);
pci_write_config_dword(pdev, 0x54c, val);
pci_read_config_dword(pdev, 0xf8, &val);
val &= ~(1 << 0x1b);
pci_write_config_dword(pdev, 0xf8, val);
}
static bool is_mcp89_apple(struct pci_dev *pdev)
{
return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
pdev->subsystem_device == 0xcb89;
}
ahci: disable 64bit DMA by default on SB600s Till now only one board, ASUS M2A-VM, can do 64bit dma with recent BIOSen. Enabling 64bit DMA by default already broke three boards. Enabling 64bit DMA isn't worth these regressions. Disable 64bit DMA by default and enable it only on boards which are known to work. Signed-off-by: Tejun Heo <tj@kernel.org> Reported-by: Gabriele Balducci <balducci@units.it> Reported-by: maierp@informatik.tu-muenchen.de Cc: Shane Huang <shane.huang@amd.com> Cc: stable@kernel.org Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-10-03 17:27:29 +08:00
/* only some SB600 ahci controllers can do 64bit DMA */
static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
[libata] ahci: Restore SB600 SATA controller 64 bit DMA Community reported one SB600 SATA issue(BZ #9412), which led to 64 bit DMA disablement for all SB600 revisions by driver maintainers with commits c7a42156d99bcea7f8173ba7a6034bbaa2ecb77c and 4cde32fc4b32e96a99063af3183acdfd54c563f0. But the root cause is ASUS M2A-VM system BIOS bug in old revisions like 0901, while forcing into 32bit DMA happens to work as workaround. Now it's time to withdraw 4cde32fc4b32e96a99063af3183acdfd54c563f0 so as to restore the SB600 SATA 64bit DMA capability. This patch is also adding the workaround for M2A-VM old BIOS revisions, but users are suggested to upgrade their system BIOS to the latest one if they meet this issue. Signed-off-by: Shane Huang <shane.huang@amd.com> Cc: Tejun Heo <tj@kernel.org> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-05-27 15:04:43 +08:00
{
static const struct dmi_system_id sysids[] = {
ahci: make ahci_asus_m2a_vm_32bit_only() quirk more generic It turns out ASUS M2A-VM isn't the only one with the 32bit DMA problem. Make ahci_asus_m2a_vm_32bit_only() more generic using the new dmi_get_date() and rename it to ahci_sb600_32bit_only(). Cut off date is now pointed to by dmi_system_id->driver_data in "yyyymmdd" format and it's now also allowed to be omitted. Signed-off-by: Tejun Heo <tj@kernel.org> Cc: Sandor Bodo-Merle <sbodomerle@gmail.com> Cc: Shane Huang <shane.huang@amd.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-08-16 20:04:02 +08:00
/*
* The oldest version known to be broken is 0901 and
* working is 1501 which was released on 2007-10-26.
ahci: disable 64bit DMA by default on SB600s Till now only one board, ASUS M2A-VM, can do 64bit dma with recent BIOSen. Enabling 64bit DMA by default already broke three boards. Enabling 64bit DMA isn't worth these regressions. Disable 64bit DMA by default and enable it only on boards which are known to work. Signed-off-by: Tejun Heo <tj@kernel.org> Reported-by: Gabriele Balducci <balducci@units.it> Reported-by: maierp@informatik.tu-muenchen.de Cc: Shane Huang <shane.huang@amd.com> Cc: stable@kernel.org Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-10-03 17:27:29 +08:00
* Enable 64bit DMA on 1501 and anything newer.
*
ahci: make ahci_asus_m2a_vm_32bit_only() quirk more generic It turns out ASUS M2A-VM isn't the only one with the 32bit DMA problem. Make ahci_asus_m2a_vm_32bit_only() more generic using the new dmi_get_date() and rename it to ahci_sb600_32bit_only(). Cut off date is now pointed to by dmi_system_id->driver_data in "yyyymmdd" format and it's now also allowed to be omitted. Signed-off-by: Tejun Heo <tj@kernel.org> Cc: Sandor Bodo-Merle <sbodomerle@gmail.com> Cc: Shane Huang <shane.huang@amd.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-08-16 20:04:02 +08:00
* Please read bko#9412 for more info.
*/
[libata] ahci: Restore SB600 SATA controller 64 bit DMA Community reported one SB600 SATA issue(BZ #9412), which led to 64 bit DMA disablement for all SB600 revisions by driver maintainers with commits c7a42156d99bcea7f8173ba7a6034bbaa2ecb77c and 4cde32fc4b32e96a99063af3183acdfd54c563f0. But the root cause is ASUS M2A-VM system BIOS bug in old revisions like 0901, while forcing into 32bit DMA happens to work as workaround. Now it's time to withdraw 4cde32fc4b32e96a99063af3183acdfd54c563f0 so as to restore the SB600 SATA 64bit DMA capability. This patch is also adding the workaround for M2A-VM old BIOS revisions, but users are suggested to upgrade their system BIOS to the latest one if they meet this issue. Signed-off-by: Shane Huang <shane.huang@amd.com> Cc: Tejun Heo <tj@kernel.org> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-05-27 15:04:43 +08:00
{
.ident = "ASUS M2A-VM",
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR,
"ASUSTeK Computer INC."),
DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
},
ahci: make ahci_asus_m2a_vm_32bit_only() quirk more generic It turns out ASUS M2A-VM isn't the only one with the 32bit DMA problem. Make ahci_asus_m2a_vm_32bit_only() more generic using the new dmi_get_date() and rename it to ahci_sb600_32bit_only(). Cut off date is now pointed to by dmi_system_id->driver_data in "yyyymmdd" format and it's now also allowed to be omitted. Signed-off-by: Tejun Heo <tj@kernel.org> Cc: Sandor Bodo-Merle <sbodomerle@gmail.com> Cc: Shane Huang <shane.huang@amd.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-08-16 20:04:02 +08:00
.driver_data = "20071026", /* yyyymmdd */
[libata] ahci: Restore SB600 SATA controller 64 bit DMA Community reported one SB600 SATA issue(BZ #9412), which led to 64 bit DMA disablement for all SB600 revisions by driver maintainers with commits c7a42156d99bcea7f8173ba7a6034bbaa2ecb77c and 4cde32fc4b32e96a99063af3183acdfd54c563f0. But the root cause is ASUS M2A-VM system BIOS bug in old revisions like 0901, while forcing into 32bit DMA happens to work as workaround. Now it's time to withdraw 4cde32fc4b32e96a99063af3183acdfd54c563f0 so as to restore the SB600 SATA 64bit DMA capability. This patch is also adding the workaround for M2A-VM old BIOS revisions, but users are suggested to upgrade their system BIOS to the latest one if they meet this issue. Signed-off-by: Shane Huang <shane.huang@amd.com> Cc: Tejun Heo <tj@kernel.org> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-05-27 15:04:43 +08:00
},
ahci: Enable SB600 64bit DMA on MSI K9A2 Platinum v2 Like the Asus M2A-VM, MSI's K9A2 Platinum (MS-7376) can also support 64bit DMA. It is a new enough board that all the BIOS releases work correctly with 64bit DMA enabled. Signed-off-by: Mark Nelson <mdnelson8@gmail.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-11-03 17:06:48 +08:00
/*
* All BIOS versions for the MSI K9A2 Platinum (MS-7376)
* support 64bit DMA.
*
* BIOS versions earlier than 1.5 had the Manufacturer DMI
* fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
* This spelling mistake was fixed in BIOS version 1.5, so
* 1.5 and later have the Manufacturer as
* "MICRO-STAR INTERNATIONAL CO.,LTD".
* So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
*
* BIOS versions earlier than 1.9 had a Board Product Name
* DMI field of "MS-7376". This was changed to be
* "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
* match on DMI_BOARD_NAME of "MS-7376".
*/
{
.ident = "MSI K9A2 Platinum",
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR,
"MICRO-STAR INTER"),
DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
},
},
ahci: Enable SB600 64bit DMA on MSI K9AGM2 (MS-7327) v2 Like e65cc194f7628ecaa02462f22f42fb09b50dcd49 (ahci: Enable SB600 64bit DMA on MSI K9A2 Platinum) and 3c4aa91f21f65b7b40bdfb015eacbcb8453ccae2 (ahci: Enable SB600 64bit DMA on Asus M3A), this patch enables 64bit DMA for the AHCI SATA controller of another board that has the SB600 southbridge. In this case though we're enabling 64bit DMA for another MSI motherboard, the K9AGM2 or MS-7327. It is new enough that all of the BIOS releases since the initial release (1.0 from 2007-02-09) work correctly with 64bit DMA enabled. Signed-off-by: Mark Nelson <mdnelson8@gmail.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2012-06-28 10:32:14 +08:00
/*
* All BIOS versions for the MSI K9AGM2 (MS-7327) support
* 64bit DMA.
*
* This board also had the typo mentioned above in the
* Manufacturer DMI field (fixed in BIOS version 1.5), so
* match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
*/
{
.ident = "MSI K9AGM2",
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR,
"MICRO-STAR INTER"),
DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
},
},
ahci: Enable SB600 64bit DMA on Asus M3A Like e65cc194f7628ecaa02462f22f42fb09b50dcd49 this patch enables 64bit DMA for the AHCI SATA controller of a board that has the SB600 southbridge. In this case though we're enabling 64bit DMA for the Asus M3A motherboard. It is a new enough board that all of the BIOS releases since the initial release (0301 from 2007-10-22) work correctly with 64bit DMA enabled. Signed-off-by: Mark Nelson <mdnelson8@gmail.com> Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
2011-06-27 14:33:44 +08:00
/*
* All BIOS versions for the Asus M3A support 64bit DMA.
* (all release versions from 0301 to 1206 were tested)
*/
{
.ident = "ASUS M3A",
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR,
"ASUSTeK Computer INC."),
DMI_MATCH(DMI_BOARD_NAME, "M3A"),
},
},
[libata] ahci: Restore SB600 SATA controller 64 bit DMA Community reported one SB600 SATA issue(BZ #9412), which led to 64 bit DMA disablement for all SB600 revisions by driver maintainers with commits c7a42156d99bcea7f8173ba7a6034bbaa2ecb77c and 4cde32fc4b32e96a99063af3183acdfd54c563f0. But the root cause is ASUS M2A-VM system BIOS bug in old revisions like 0901, while forcing into 32bit DMA happens to work as workaround. Now it's time to withdraw 4cde32fc4b32e96a99063af3183acdfd54c563f0 so as to restore the SB600 SATA 64bit DMA capability. This patch is also adding the workaround for M2A-VM old BIOS revisions, but users are suggested to upgrade their system BIOS to the latest one if they meet this issue. Signed-off-by: Shane Huang <shane.huang@amd.com> Cc: Tejun Heo <tj@kernel.org> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-05-27 15:04:43 +08:00
{ }
};
ahci: make ahci_asus_m2a_vm_32bit_only() quirk more generic It turns out ASUS M2A-VM isn't the only one with the 32bit DMA problem. Make ahci_asus_m2a_vm_32bit_only() more generic using the new dmi_get_date() and rename it to ahci_sb600_32bit_only(). Cut off date is now pointed to by dmi_system_id->driver_data in "yyyymmdd" format and it's now also allowed to be omitted. Signed-off-by: Tejun Heo <tj@kernel.org> Cc: Sandor Bodo-Merle <sbodomerle@gmail.com> Cc: Shane Huang <shane.huang@amd.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-08-16 20:04:02 +08:00
const struct dmi_system_id *match;
ahci: disable 64bit DMA by default on SB600s Till now only one board, ASUS M2A-VM, can do 64bit dma with recent BIOSen. Enabling 64bit DMA by default already broke three boards. Enabling 64bit DMA isn't worth these regressions. Disable 64bit DMA by default and enable it only on boards which are known to work. Signed-off-by: Tejun Heo <tj@kernel.org> Reported-by: Gabriele Balducci <balducci@units.it> Reported-by: maierp@informatik.tu-muenchen.de Cc: Shane Huang <shane.huang@amd.com> Cc: stable@kernel.org Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-10-03 17:27:29 +08:00
int year, month, date;
char buf[9];
[libata] ahci: Restore SB600 SATA controller 64 bit DMA Community reported one SB600 SATA issue(BZ #9412), which led to 64 bit DMA disablement for all SB600 revisions by driver maintainers with commits c7a42156d99bcea7f8173ba7a6034bbaa2ecb77c and 4cde32fc4b32e96a99063af3183acdfd54c563f0. But the root cause is ASUS M2A-VM system BIOS bug in old revisions like 0901, while forcing into 32bit DMA happens to work as workaround. Now it's time to withdraw 4cde32fc4b32e96a99063af3183acdfd54c563f0 so as to restore the SB600 SATA 64bit DMA capability. This patch is also adding the workaround for M2A-VM old BIOS revisions, but users are suggested to upgrade their system BIOS to the latest one if they meet this issue. Signed-off-by: Shane Huang <shane.huang@amd.com> Cc: Tejun Heo <tj@kernel.org> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-05-27 15:04:43 +08:00
ahci: make ahci_asus_m2a_vm_32bit_only() quirk more generic It turns out ASUS M2A-VM isn't the only one with the 32bit DMA problem. Make ahci_asus_m2a_vm_32bit_only() more generic using the new dmi_get_date() and rename it to ahci_sb600_32bit_only(). Cut off date is now pointed to by dmi_system_id->driver_data in "yyyymmdd" format and it's now also allowed to be omitted. Signed-off-by: Tejun Heo <tj@kernel.org> Cc: Sandor Bodo-Merle <sbodomerle@gmail.com> Cc: Shane Huang <shane.huang@amd.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-08-16 20:04:02 +08:00
match = dmi_first_match(sysids);
[libata] ahci: Restore SB600 SATA controller 64 bit DMA Community reported one SB600 SATA issue(BZ #9412), which led to 64 bit DMA disablement for all SB600 revisions by driver maintainers with commits c7a42156d99bcea7f8173ba7a6034bbaa2ecb77c and 4cde32fc4b32e96a99063af3183acdfd54c563f0. But the root cause is ASUS M2A-VM system BIOS bug in old revisions like 0901, while forcing into 32bit DMA happens to work as workaround. Now it's time to withdraw 4cde32fc4b32e96a99063af3183acdfd54c563f0 so as to restore the SB600 SATA 64bit DMA capability. This patch is also adding the workaround for M2A-VM old BIOS revisions, but users are suggested to upgrade their system BIOS to the latest one if they meet this issue. Signed-off-by: Shane Huang <shane.huang@amd.com> Cc: Tejun Heo <tj@kernel.org> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-05-27 15:04:43 +08:00
if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
ahci: make ahci_asus_m2a_vm_32bit_only() quirk more generic It turns out ASUS M2A-VM isn't the only one with the 32bit DMA problem. Make ahci_asus_m2a_vm_32bit_only() more generic using the new dmi_get_date() and rename it to ahci_sb600_32bit_only(). Cut off date is now pointed to by dmi_system_id->driver_data in "yyyymmdd" format and it's now also allowed to be omitted. Signed-off-by: Tejun Heo <tj@kernel.org> Cc: Sandor Bodo-Merle <sbodomerle@gmail.com> Cc: Shane Huang <shane.huang@amd.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-08-16 20:04:02 +08:00
!match)
[libata] ahci: Restore SB600 SATA controller 64 bit DMA Community reported one SB600 SATA issue(BZ #9412), which led to 64 bit DMA disablement for all SB600 revisions by driver maintainers with commits c7a42156d99bcea7f8173ba7a6034bbaa2ecb77c and 4cde32fc4b32e96a99063af3183acdfd54c563f0. But the root cause is ASUS M2A-VM system BIOS bug in old revisions like 0901, while forcing into 32bit DMA happens to work as workaround. Now it's time to withdraw 4cde32fc4b32e96a99063af3183acdfd54c563f0 so as to restore the SB600 SATA 64bit DMA capability. This patch is also adding the workaround for M2A-VM old BIOS revisions, but users are suggested to upgrade their system BIOS to the latest one if they meet this issue. Signed-off-by: Shane Huang <shane.huang@amd.com> Cc: Tejun Heo <tj@kernel.org> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-05-27 15:04:43 +08:00
return false;
ahci: Enable SB600 64bit DMA on MSI K9A2 Platinum v2 Like the Asus M2A-VM, MSI's K9A2 Platinum (MS-7376) can also support 64bit DMA. It is a new enough board that all the BIOS releases work correctly with 64bit DMA enabled. Signed-off-by: Mark Nelson <mdnelson8@gmail.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-11-03 17:06:48 +08:00
if (!match->driver_data)
goto enable_64bit;
ahci: disable 64bit DMA by default on SB600s Till now only one board, ASUS M2A-VM, can do 64bit dma with recent BIOSen. Enabling 64bit DMA by default already broke three boards. Enabling 64bit DMA isn't worth these regressions. Disable 64bit DMA by default and enable it only on boards which are known to work. Signed-off-by: Tejun Heo <tj@kernel.org> Reported-by: Gabriele Balducci <balducci@units.it> Reported-by: maierp@informatik.tu-muenchen.de Cc: Shane Huang <shane.huang@amd.com> Cc: stable@kernel.org Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-10-03 17:27:29 +08:00
dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
ahci: make ahci_asus_m2a_vm_32bit_only() quirk more generic It turns out ASUS M2A-VM isn't the only one with the 32bit DMA problem. Make ahci_asus_m2a_vm_32bit_only() more generic using the new dmi_get_date() and rename it to ahci_sb600_32bit_only(). Cut off date is now pointed to by dmi_system_id->driver_data in "yyyymmdd" format and it's now also allowed to be omitted. Signed-off-by: Tejun Heo <tj@kernel.org> Cc: Sandor Bodo-Merle <sbodomerle@gmail.com> Cc: Shane Huang <shane.huang@amd.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-08-16 20:04:02 +08:00
ahci: Enable SB600 64bit DMA on MSI K9A2 Platinum v2 Like the Asus M2A-VM, MSI's K9A2 Platinum (MS-7376) can also support 64bit DMA. It is a new enough board that all the BIOS releases work correctly with 64bit DMA enabled. Signed-off-by: Mark Nelson <mdnelson8@gmail.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-11-03 17:06:48 +08:00
if (strcmp(buf, match->driver_data) >= 0)
goto enable_64bit;
else {
ata: Convert dev_printk(KERN_<LEVEL> to dev_<level>( Saves a bit of text as the call takes fewer args. Coalesce a few formats. Convert a few bare printks to pr_cont. $ size drivers/ata/built-in.o* text data bss dec hex filename 558429 73893 117864 750186 b726a drivers/ata/built-in.o.allyesconfig.new 559574 73893 117888 751355 b76fb drivers/ata/built-in.o.allyesconfig.old 149567 14689 4220 168476 2921c drivers/ata/built-in.o.defconfig.new 149851 14689 4220 168760 29338 drivers/ata/built-in.o.defconfig.old Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
2011-04-16 06:51:58 +08:00
dev_warn(&pdev->dev,
"%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
match->ident);
ahci: disable 64bit DMA by default on SB600s Till now only one board, ASUS M2A-VM, can do 64bit dma with recent BIOSen. Enabling 64bit DMA by default already broke three boards. Enabling 64bit DMA isn't worth these regressions. Disable 64bit DMA by default and enable it only on boards which are known to work. Signed-off-by: Tejun Heo <tj@kernel.org> Reported-by: Gabriele Balducci <balducci@units.it> Reported-by: maierp@informatik.tu-muenchen.de Cc: Shane Huang <shane.huang@amd.com> Cc: stable@kernel.org Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-10-03 17:27:29 +08:00
return false;
}
ahci: Enable SB600 64bit DMA on MSI K9A2 Platinum v2 Like the Asus M2A-VM, MSI's K9A2 Platinum (MS-7376) can also support 64bit DMA. It is a new enough board that all the BIOS releases work correctly with 64bit DMA enabled. Signed-off-by: Mark Nelson <mdnelson8@gmail.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-11-03 17:06:48 +08:00
enable_64bit:
ata: Convert dev_printk(KERN_<LEVEL> to dev_<level>( Saves a bit of text as the call takes fewer args. Coalesce a few formats. Convert a few bare printks to pr_cont. $ size drivers/ata/built-in.o* text data bss dec hex filename 558429 73893 117864 750186 b726a drivers/ata/built-in.o.allyesconfig.new 559574 73893 117888 751355 b76fb drivers/ata/built-in.o.allyesconfig.old 149567 14689 4220 168476 2921c drivers/ata/built-in.o.defconfig.new 149851 14689 4220 168760 29338 drivers/ata/built-in.o.defconfig.old Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
2011-04-16 06:51:58 +08:00
dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
ahci: Enable SB600 64bit DMA on MSI K9A2 Platinum v2 Like the Asus M2A-VM, MSI's K9A2 Platinum (MS-7376) can also support 64bit DMA. It is a new enough board that all the BIOS releases work correctly with 64bit DMA enabled. Signed-off-by: Mark Nelson <mdnelson8@gmail.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-11-03 17:06:48 +08:00
return true;
[libata] ahci: Restore SB600 SATA controller 64 bit DMA Community reported one SB600 SATA issue(BZ #9412), which led to 64 bit DMA disablement for all SB600 revisions by driver maintainers with commits c7a42156d99bcea7f8173ba7a6034bbaa2ecb77c and 4cde32fc4b32e96a99063af3183acdfd54c563f0. But the root cause is ASUS M2A-VM system BIOS bug in old revisions like 0901, while forcing into 32bit DMA happens to work as workaround. Now it's time to withdraw 4cde32fc4b32e96a99063af3183acdfd54c563f0 so as to restore the SB600 SATA 64bit DMA capability. This patch is also adding the workaround for M2A-VM old BIOS revisions, but users are suggested to upgrade their system BIOS to the latest one if they meet this issue. Signed-off-by: Shane Huang <shane.huang@amd.com> Cc: Tejun Heo <tj@kernel.org> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-05-27 15:04:43 +08:00
}
SATA AHCI: Blacklist system that spins off disks during ACPI power off Some notebooks from HP have the problem that their BIOSes attempt to spin down hard drives before entering ACPI system states S4 and S5. This leads to a yo-yo effect during system power-off shutdown and the last phase of hibernation when the disk is first spun down by the kernel and then almost immediately turned on and off by the BIOS. This, in turn, may result in shortening the disk's life times. To prevent this from happening we can blacklist the affected systems using DMI information. Blacklist HP nx6310 that uses the AHCI driver. Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-01-20 03:57:36 +08:00
static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
{
static const struct dmi_system_id broken_systems[] = {
{
.ident = "HP Compaq nx6310",
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
},
/* PCI slot number of the controller */
.driver_data = (void *)0x1FUL,
},
ahci: Blacklist HP Compaq 6720s that spins off disks during ACPI power off Blacklist HP Compaq 6720s so that it doesn't play a "spin down, spin up, spin down" ping-pong with the hard disk during system power off. Signed-off-by: Maciej Rutecki <maciej.rutecki@gmail.com> Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-03-20 07:06:46 +08:00
{
.ident = "HP Compaq 6720s",
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
},
/* PCI slot number of the controller */
.driver_data = (void *)0x1FUL,
},
SATA AHCI: Blacklist system that spins off disks during ACPI power off Some notebooks from HP have the problem that their BIOSes attempt to spin down hard drives before entering ACPI system states S4 and S5. This leads to a yo-yo effect during system power-off shutdown and the last phase of hibernation when the disk is first spun down by the kernel and then almost immediately turned on and off by the BIOS. This, in turn, may result in shortening the disk's life times. To prevent this from happening we can blacklist the affected systems using DMI information. Blacklist HP nx6310 that uses the AHCI driver. Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-01-20 03:57:36 +08:00
{ } /* terminate list */
};
const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
if (dmi) {
unsigned long slot = (unsigned long)dmi->driver_data;
/* apply the quirk only to on-board controllers */
return slot == PCI_SLOT(pdev->devfn);
}
return false;
}
ahci: add warning messages for hp laptops with broken suspend Harddisks on HP dv[4-6] and HDX18 fail to come online after resume on earlier BIOSen. Fortunately, HP recently released BIOS updates for all machines to fix the issue. Detect old BIOSen, warn the user to update BIOS on boot and suspend attempts and fail suspend. Kudos to all the bug reporters. Signed-off-by: Tejun Heo <tj@kernel.org> Cc: kernel.org@epperson.homelinux.net Cc: emisca@gmail.com Cc: Gadi Cohen <dragon@wastelands.net> Cc: Paul Swanson <paul@procursa.com> Cc: s@ourada.org Cc: Trevor Davenport <trevor.davenport@gmail.com> Cc: corruptor1972 <steven_tierney@yahoo.co.uk> Cc: Victoria Wilson <mail@vwilson.co.uk> Cc: khiraly <khiraly.list@gmail.com> Cc: Sean <wollombi@gmail.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-05-30 19:50:12 +08:00
static bool ahci_broken_suspend(struct pci_dev *pdev)
{
static const struct dmi_system_id sysids[] = {
/*
* On HP dv[4-6] and HDX18 with earlier BIOSen, link
* to the harddisk doesn't become online after
* resuming from STR. Warn and fail suspend.
ahci: use BIOS date in broken_suspend list HP is recycling both DMI_PRODUCT_NAME and DMI_BIOS_VERSION making ahci_broken_suspend() trigger for later products which are not affected by the original problems. Match BIOS date instead of version and add references to bko's so that full information can be found easier later. This fixes http://bugzilla.kernel.org/show_bug.cgi?id=15462 Signed-off-by: Tejun Heo <tj@kernel.org> Reported-by: tigerfishdaisy@gmail.com Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-03-16 08:50:26 +08:00
*
* http://bugzilla.kernel.org/show_bug.cgi?id=12276
*
* Use dates instead of versions to match as HP is
* apparently recycling both product and version
* strings.
*
* http://bugzilla.kernel.org/show_bug.cgi?id=15462
ahci: add warning messages for hp laptops with broken suspend Harddisks on HP dv[4-6] and HDX18 fail to come online after resume on earlier BIOSen. Fortunately, HP recently released BIOS updates for all machines to fix the issue. Detect old BIOSen, warn the user to update BIOS on boot and suspend attempts and fail suspend. Kudos to all the bug reporters. Signed-off-by: Tejun Heo <tj@kernel.org> Cc: kernel.org@epperson.homelinux.net Cc: emisca@gmail.com Cc: Gadi Cohen <dragon@wastelands.net> Cc: Paul Swanson <paul@procursa.com> Cc: s@ourada.org Cc: Trevor Davenport <trevor.davenport@gmail.com> Cc: corruptor1972 <steven_tierney@yahoo.co.uk> Cc: Victoria Wilson <mail@vwilson.co.uk> Cc: khiraly <khiraly.list@gmail.com> Cc: Sean <wollombi@gmail.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-05-30 19:50:12 +08:00
*/
{
.ident = "dv4",
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
DMI_MATCH(DMI_PRODUCT_NAME,
"HP Pavilion dv4 Notebook PC"),
},
ahci: use BIOS date in broken_suspend list HP is recycling both DMI_PRODUCT_NAME and DMI_BIOS_VERSION making ahci_broken_suspend() trigger for later products which are not affected by the original problems. Match BIOS date instead of version and add references to bko's so that full information can be found easier later. This fixes http://bugzilla.kernel.org/show_bug.cgi?id=15462 Signed-off-by: Tejun Heo <tj@kernel.org> Reported-by: tigerfishdaisy@gmail.com Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-03-16 08:50:26 +08:00
.driver_data = "20090105", /* F.30 */
ahci: add warning messages for hp laptops with broken suspend Harddisks on HP dv[4-6] and HDX18 fail to come online after resume on earlier BIOSen. Fortunately, HP recently released BIOS updates for all machines to fix the issue. Detect old BIOSen, warn the user to update BIOS on boot and suspend attempts and fail suspend. Kudos to all the bug reporters. Signed-off-by: Tejun Heo <tj@kernel.org> Cc: kernel.org@epperson.homelinux.net Cc: emisca@gmail.com Cc: Gadi Cohen <dragon@wastelands.net> Cc: Paul Swanson <paul@procursa.com> Cc: s@ourada.org Cc: Trevor Davenport <trevor.davenport@gmail.com> Cc: corruptor1972 <steven_tierney@yahoo.co.uk> Cc: Victoria Wilson <mail@vwilson.co.uk> Cc: khiraly <khiraly.list@gmail.com> Cc: Sean <wollombi@gmail.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-05-30 19:50:12 +08:00
},
{
.ident = "dv5",
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
DMI_MATCH(DMI_PRODUCT_NAME,
"HP Pavilion dv5 Notebook PC"),
},
ahci: use BIOS date in broken_suspend list HP is recycling both DMI_PRODUCT_NAME and DMI_BIOS_VERSION making ahci_broken_suspend() trigger for later products which are not affected by the original problems. Match BIOS date instead of version and add references to bko's so that full information can be found easier later. This fixes http://bugzilla.kernel.org/show_bug.cgi?id=15462 Signed-off-by: Tejun Heo <tj@kernel.org> Reported-by: tigerfishdaisy@gmail.com Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-03-16 08:50:26 +08:00
.driver_data = "20090506", /* F.16 */
ahci: add warning messages for hp laptops with broken suspend Harddisks on HP dv[4-6] and HDX18 fail to come online after resume on earlier BIOSen. Fortunately, HP recently released BIOS updates for all machines to fix the issue. Detect old BIOSen, warn the user to update BIOS on boot and suspend attempts and fail suspend. Kudos to all the bug reporters. Signed-off-by: Tejun Heo <tj@kernel.org> Cc: kernel.org@epperson.homelinux.net Cc: emisca@gmail.com Cc: Gadi Cohen <dragon@wastelands.net> Cc: Paul Swanson <paul@procursa.com> Cc: s@ourada.org Cc: Trevor Davenport <trevor.davenport@gmail.com> Cc: corruptor1972 <steven_tierney@yahoo.co.uk> Cc: Victoria Wilson <mail@vwilson.co.uk> Cc: khiraly <khiraly.list@gmail.com> Cc: Sean <wollombi@gmail.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-05-30 19:50:12 +08:00
},
{
.ident = "dv6",
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
DMI_MATCH(DMI_PRODUCT_NAME,
"HP Pavilion dv6 Notebook PC"),
},
ahci: use BIOS date in broken_suspend list HP is recycling both DMI_PRODUCT_NAME and DMI_BIOS_VERSION making ahci_broken_suspend() trigger for later products which are not affected by the original problems. Match BIOS date instead of version and add references to bko's so that full information can be found easier later. This fixes http://bugzilla.kernel.org/show_bug.cgi?id=15462 Signed-off-by: Tejun Heo <tj@kernel.org> Reported-by: tigerfishdaisy@gmail.com Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-03-16 08:50:26 +08:00
.driver_data = "20090423", /* F.21 */
ahci: add warning messages for hp laptops with broken suspend Harddisks on HP dv[4-6] and HDX18 fail to come online after resume on earlier BIOSen. Fortunately, HP recently released BIOS updates for all machines to fix the issue. Detect old BIOSen, warn the user to update BIOS on boot and suspend attempts and fail suspend. Kudos to all the bug reporters. Signed-off-by: Tejun Heo <tj@kernel.org> Cc: kernel.org@epperson.homelinux.net Cc: emisca@gmail.com Cc: Gadi Cohen <dragon@wastelands.net> Cc: Paul Swanson <paul@procursa.com> Cc: s@ourada.org Cc: Trevor Davenport <trevor.davenport@gmail.com> Cc: corruptor1972 <steven_tierney@yahoo.co.uk> Cc: Victoria Wilson <mail@vwilson.co.uk> Cc: khiraly <khiraly.list@gmail.com> Cc: Sean <wollombi@gmail.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-05-30 19:50:12 +08:00
},
{
.ident = "HDX18",
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
DMI_MATCH(DMI_PRODUCT_NAME,
"HP HDX18 Notebook PC"),
},
ahci: use BIOS date in broken_suspend list HP is recycling both DMI_PRODUCT_NAME and DMI_BIOS_VERSION making ahci_broken_suspend() trigger for later products which are not affected by the original problems. Match BIOS date instead of version and add references to bko's so that full information can be found easier later. This fixes http://bugzilla.kernel.org/show_bug.cgi?id=15462 Signed-off-by: Tejun Heo <tj@kernel.org> Reported-by: tigerfishdaisy@gmail.com Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-03-16 08:50:26 +08:00
.driver_data = "20090430", /* F.23 */
ahci: add warning messages for hp laptops with broken suspend Harddisks on HP dv[4-6] and HDX18 fail to come online after resume on earlier BIOSen. Fortunately, HP recently released BIOS updates for all machines to fix the issue. Detect old BIOSen, warn the user to update BIOS on boot and suspend attempts and fail suspend. Kudos to all the bug reporters. Signed-off-by: Tejun Heo <tj@kernel.org> Cc: kernel.org@epperson.homelinux.net Cc: emisca@gmail.com Cc: Gadi Cohen <dragon@wastelands.net> Cc: Paul Swanson <paul@procursa.com> Cc: s@ourada.org Cc: Trevor Davenport <trevor.davenport@gmail.com> Cc: corruptor1972 <steven_tierney@yahoo.co.uk> Cc: Victoria Wilson <mail@vwilson.co.uk> Cc: khiraly <khiraly.list@gmail.com> Cc: Sean <wollombi@gmail.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-05-30 19:50:12 +08:00
},
ahci: add Acer G725 to broken suspend list Acer G725 shares the same suspend problem with the HP laptops which lose ATA devices on resume. New firmware which fixes the problem is already available. Add G725 with old firmwares to the broken suspend list. This problem has been reported in bko#15104. http://bugzilla.kernel.org/show_bug.cgi?id=15104 Signed-off-by: Tejun Heo <tj@kernel.org> Reported-by: Jani-Matti Hätinen <jani-matti.hatinen@iki.fi> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-01-28 15:04:15 +08:00
/*
* Acer eMachines G725 has the same problem. BIOS
* V1.03 is known to be broken. V3.04 is known to
Fix common misspellings Fixes generated by 'codespell' and manually reviewed. Signed-off-by: Lucas De Marchi <lucas.demarchi@profusion.mobi>
2011-03-31 09:57:33 +08:00
* work. Between, there are V1.06, V2.06 and V3.03
ahci: add Acer G725 to broken suspend list Acer G725 shares the same suspend problem with the HP laptops which lose ATA devices on resume. New firmware which fixes the problem is already available. Add G725 with old firmwares to the broken suspend list. This problem has been reported in bko#15104. http://bugzilla.kernel.org/show_bug.cgi?id=15104 Signed-off-by: Tejun Heo <tj@kernel.org> Reported-by: Jani-Matti Hätinen <jani-matti.hatinen@iki.fi> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-01-28 15:04:15 +08:00
* that we don't have much idea about. For now,
* blacklist anything older than V3.04.
ahci: use BIOS date in broken_suspend list HP is recycling both DMI_PRODUCT_NAME and DMI_BIOS_VERSION making ahci_broken_suspend() trigger for later products which are not affected by the original problems. Match BIOS date instead of version and add references to bko's so that full information can be found easier later. This fixes http://bugzilla.kernel.org/show_bug.cgi?id=15462 Signed-off-by: Tejun Heo <tj@kernel.org> Reported-by: tigerfishdaisy@gmail.com Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-03-16 08:50:26 +08:00
*
* http://bugzilla.kernel.org/show_bug.cgi?id=15104
ahci: add Acer G725 to broken suspend list Acer G725 shares the same suspend problem with the HP laptops which lose ATA devices on resume. New firmware which fixes the problem is already available. Add G725 with old firmwares to the broken suspend list. This problem has been reported in bko#15104. http://bugzilla.kernel.org/show_bug.cgi?id=15104 Signed-off-by: Tejun Heo <tj@kernel.org> Reported-by: Jani-Matti Hätinen <jani-matti.hatinen@iki.fi> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-01-28 15:04:15 +08:00
*/
{
.ident = "G725",
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
},
ahci: use BIOS date in broken_suspend list HP is recycling both DMI_PRODUCT_NAME and DMI_BIOS_VERSION making ahci_broken_suspend() trigger for later products which are not affected by the original problems. Match BIOS date instead of version and add references to bko's so that full information can be found easier later. This fixes http://bugzilla.kernel.org/show_bug.cgi?id=15462 Signed-off-by: Tejun Heo <tj@kernel.org> Reported-by: tigerfishdaisy@gmail.com Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-03-16 08:50:26 +08:00
.driver_data = "20091216", /* V3.04 */
ahci: add Acer G725 to broken suspend list Acer G725 shares the same suspend problem with the HP laptops which lose ATA devices on resume. New firmware which fixes the problem is already available. Add G725 with old firmwares to the broken suspend list. This problem has been reported in bko#15104. http://bugzilla.kernel.org/show_bug.cgi?id=15104 Signed-off-by: Tejun Heo <tj@kernel.org> Reported-by: Jani-Matti Hätinen <jani-matti.hatinen@iki.fi> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-01-28 15:04:15 +08:00
},
ahci: add warning messages for hp laptops with broken suspend Harddisks on HP dv[4-6] and HDX18 fail to come online after resume on earlier BIOSen. Fortunately, HP recently released BIOS updates for all machines to fix the issue. Detect old BIOSen, warn the user to update BIOS on boot and suspend attempts and fail suspend. Kudos to all the bug reporters. Signed-off-by: Tejun Heo <tj@kernel.org> Cc: kernel.org@epperson.homelinux.net Cc: emisca@gmail.com Cc: Gadi Cohen <dragon@wastelands.net> Cc: Paul Swanson <paul@procursa.com> Cc: s@ourada.org Cc: Trevor Davenport <trevor.davenport@gmail.com> Cc: corruptor1972 <steven_tierney@yahoo.co.uk> Cc: Victoria Wilson <mail@vwilson.co.uk> Cc: khiraly <khiraly.list@gmail.com> Cc: Sean <wollombi@gmail.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-05-30 19:50:12 +08:00
{ } /* terminate list */
};
const struct dmi_system_id *dmi = dmi_first_match(sysids);
ahci: use BIOS date in broken_suspend list HP is recycling both DMI_PRODUCT_NAME and DMI_BIOS_VERSION making ahci_broken_suspend() trigger for later products which are not affected by the original problems. Match BIOS date instead of version and add references to bko's so that full information can be found easier later. This fixes http://bugzilla.kernel.org/show_bug.cgi?id=15462 Signed-off-by: Tejun Heo <tj@kernel.org> Reported-by: tigerfishdaisy@gmail.com Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-03-16 08:50:26 +08:00
int year, month, date;
char buf[9];
ahci: add warning messages for hp laptops with broken suspend Harddisks on HP dv[4-6] and HDX18 fail to come online after resume on earlier BIOSen. Fortunately, HP recently released BIOS updates for all machines to fix the issue. Detect old BIOSen, warn the user to update BIOS on boot and suspend attempts and fail suspend. Kudos to all the bug reporters. Signed-off-by: Tejun Heo <tj@kernel.org> Cc: kernel.org@epperson.homelinux.net Cc: emisca@gmail.com Cc: Gadi Cohen <dragon@wastelands.net> Cc: Paul Swanson <paul@procursa.com> Cc: s@ourada.org Cc: Trevor Davenport <trevor.davenport@gmail.com> Cc: corruptor1972 <steven_tierney@yahoo.co.uk> Cc: Victoria Wilson <mail@vwilson.co.uk> Cc: khiraly <khiraly.list@gmail.com> Cc: Sean <wollombi@gmail.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-05-30 19:50:12 +08:00
if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
return false;
ahci: use BIOS date in broken_suspend list HP is recycling both DMI_PRODUCT_NAME and DMI_BIOS_VERSION making ahci_broken_suspend() trigger for later products which are not affected by the original problems. Match BIOS date instead of version and add references to bko's so that full information can be found easier later. This fixes http://bugzilla.kernel.org/show_bug.cgi?id=15462 Signed-off-by: Tejun Heo <tj@kernel.org> Reported-by: tigerfishdaisy@gmail.com Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-03-16 08:50:26 +08:00
dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
ahci: add warning messages for hp laptops with broken suspend Harddisks on HP dv[4-6] and HDX18 fail to come online after resume on earlier BIOSen. Fortunately, HP recently released BIOS updates for all machines to fix the issue. Detect old BIOSen, warn the user to update BIOS on boot and suspend attempts and fail suspend. Kudos to all the bug reporters. Signed-off-by: Tejun Heo <tj@kernel.org> Cc: kernel.org@epperson.homelinux.net Cc: emisca@gmail.com Cc: Gadi Cohen <dragon@wastelands.net> Cc: Paul Swanson <paul@procursa.com> Cc: s@ourada.org Cc: Trevor Davenport <trevor.davenport@gmail.com> Cc: corruptor1972 <steven_tierney@yahoo.co.uk> Cc: Victoria Wilson <mail@vwilson.co.uk> Cc: khiraly <khiraly.list@gmail.com> Cc: Sean <wollombi@gmail.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-05-30 19:50:12 +08:00
ahci: use BIOS date in broken_suspend list HP is recycling both DMI_PRODUCT_NAME and DMI_BIOS_VERSION making ahci_broken_suspend() trigger for later products which are not affected by the original problems. Match BIOS date instead of version and add references to bko's so that full information can be found easier later. This fixes http://bugzilla.kernel.org/show_bug.cgi?id=15462 Signed-off-by: Tejun Heo <tj@kernel.org> Reported-by: tigerfishdaisy@gmail.com Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-03-16 08:50:26 +08:00
return strcmp(buf, dmi->driver_data) < 0;
ahci: add warning messages for hp laptops with broken suspend Harddisks on HP dv[4-6] and HDX18 fail to come online after resume on earlier BIOSen. Fortunately, HP recently released BIOS updates for all machines to fix the issue. Detect old BIOSen, warn the user to update BIOS on boot and suspend attempts and fail suspend. Kudos to all the bug reporters. Signed-off-by: Tejun Heo <tj@kernel.org> Cc: kernel.org@epperson.homelinux.net Cc: emisca@gmail.com Cc: Gadi Cohen <dragon@wastelands.net> Cc: Paul Swanson <paul@procursa.com> Cc: s@ourada.org Cc: Trevor Davenport <trevor.davenport@gmail.com> Cc: corruptor1972 <steven_tierney@yahoo.co.uk> Cc: Victoria Wilson <mail@vwilson.co.uk> Cc: khiraly <khiraly.list@gmail.com> Cc: Sean <wollombi@gmail.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-05-30 19:50:12 +08:00
}
ahci: Disable LPM on Lenovo 50 series laptops with a too old BIOS There have been several reports of LPM related hard freezes about once a day on multiple Lenovo 50 series models. Strange enough these reports where not disk model specific as LPM issues usually are and some users with the exact same disk + laptop where seeing them while other users where not seeing these issues. It turns out that enabling LPM triggers a firmware bug somewhere, which has been fixed in later BIOS versions. This commit adds a new ahci_broken_lpm() function and a new ATA_FLAG_NO_LPM for dealing with this. The ahci_broken_lpm() function contains DMI match info for the 4 models which are known to be affected by this and the DMI BIOS date field for known good BIOS versions. If the BIOS date is older then the one in the table LPM will be disabled and a warning will be printed. Note the BIOS dates are for known good versions, some older versions may work too, but we don't know for sure, the table is using dates from BIOS versions for which users have confirmed that upgrading to that version makes the problem go away. Unfortunately I've been unable to get hold of the reporter who reported that BIOS version 2.35 fixed the problems on the W541 for him. I've been able to verify the DMI_SYS_VENDOR and DMI_PRODUCT_VERSION from an older dmidecode, but I don't know the exact BIOS date as reported in the DMI. Lenovo keeps a changelog with dates in their release notes, but the dates there are the release dates not the build dates which are in DMI. So I've chosen to set the date to which we compare to one day past the release date of the 2.34 BIOS. I plan to fix this with a follow up commit once I've the necessary info. Cc: stable@vger.kernel.org Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2018-07-01 18:15:46 +08:00
static bool ahci_broken_lpm(struct pci_dev *pdev)
{
static const struct dmi_system_id sysids[] = {
/* Various Lenovo 50 series have LPM issues with older BIOSen */
{
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X250"),
},
.driver_data = "20180406", /* 1.31 */
},
{
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad L450"),
},
.driver_data = "20180420", /* 1.28 */
},
{
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad T450s"),
},
.driver_data = "20180315", /* 1.33 */
},
{
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad W541"),
},
/*
* Note date based on release notes, 2.35 has been
* reported to be good, but I've been unable to get
* a hold of the reporter to get the DMI BIOS date.
* TODO: fix this.
*/
.driver_data = "20180310", /* 2.35 */
},
{ } /* terminate list */
};
const struct dmi_system_id *dmi = dmi_first_match(sysids);
int year, month, date;
char buf[9];
if (!dmi)
return false;
dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
return strcmp(buf, dmi->driver_data) < 0;
}
ahci: add workaround for on-board 5723s on some gigabyte boards Some gigabytes have on-board SIMG5723s connected to JMB ahcis. These are used to implement hardware raid. Unfortunately some firmware revisions on these 5723s don't bring the link down when all the downstream ports are unoccupied while not responding to reset protocol which makes libata think that there's device attached to the port but is not responding and retry. This results in painfully wrong boot detection time for these ports when they're empty. This patch quirks those boards such that ahci gives up after the initial timeout. Combined with parallel probing, this gives quick enough probing and also is safe because SIMG5723 will respond to the first try if any of the downstream ports is occupied. Signed-off-by: Tejun Heo <tj@kernel.org> Reported-by: Marc Bowes <marcbowes@gmail.com> Reported-by: Nicolas Mailhot <Nicolas.Mailhot@LaPoste.net> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-08-04 13:30:08 +08:00
static bool ahci_broken_online(struct pci_dev *pdev)
{
#define ENCODE_BUSDEVFN(bus, slot, func) \
(void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
static const struct dmi_system_id sysids[] = {
/*
* There are several gigabyte boards which use
* SIMG5723s configured as hardware RAID. Certain
* 5723 firmware revisions shipped there keep the link
* online but fail to answer properly to SRST or
* IDENTIFY when no device is attached downstream
* causing libata to retry quite a few times leading
* to excessive detection delay.
*
* As these firmwares respond to the second reset try
* with invalid device signature, considering unknown
* sig as offline works around the problem acceptably.
*/
{
.ident = "EP45-DQ6",
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR,
"Gigabyte Technology Co., Ltd."),
DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
},
.driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
},
{
.ident = "EP45-DS5",
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR,
"Gigabyte Technology Co., Ltd."),
DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
},
.driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
},
{ } /* terminate list */
};
#undef ENCODE_BUSDEVFN
const struct dmi_system_id *dmi = dmi_first_match(sysids);
unsigned int val;
if (!dmi)
return false;
val = (unsigned long)dmi->driver_data;
return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
}
ahci: disable DEVSLP for Intel Valleyview On Intel Valleyview SoC, SATA device sleep is not reliable. When DEVSLP is attempted on certain SSDs, port_devslp write would fail and result in malfunction of AHCI controller. AHCI controller may be not shown in PCI enumeration after reset. Complete power source removal may be required to recover from this failure. So we blacklist this device and override host device reported capabilities such that device LPM will only attempt slumber but not DEVSLP. Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com> Acked-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2014-04-16 13:27:11 +08:00
static bool ahci_broken_devslp(struct pci_dev *pdev)
{
/* device with broken DEVSLP but still showing SDS capability */
static const struct pci_device_id ids[] = {
{ PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */
{}
};
return pci_match_id(ids, pdev);
}
ahci: Add ifdef wrapper to ahci_gtf_filter_workaround Commit f80ae7e45a0e03da188494c6e947a5c8b0cdfb4a ahci: filter FPDMA non-zero offset enable for Aspire 3810T breaks the current git build for configurations that don't define CONFIG_ATA_ACPI. This adds an ifdef wrapper to ahci_gtf_filter_workaround. Signed-off-by: Markus Trippelsdorf <markus@trippelsdorf.de> Acked-by: Tejun Heo <tj@kernel.org> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-10-09 11:41:47 +08:00
#ifdef CONFIG_ATA_ACPI
ahci: filter FPDMA non-zero offset enable for Aspire 3810T Curiously, Aspire 3810T issues many SATA feature enable commands via _GTF, of which one is invalid and another is not supported by the drive. In the process, it also enables FPDMA non-zero offset. However, the feature also needs to be supported and enabled from the controller and it's wrong to enable it from _GTF unless the controller can do it by default. Currently, this ends up enabling FPDMA non-zero offset only on the drive side leading to NCQ command failures and eventual disabling of NCQ. This patch makes libata filter out FPDMA non-zero offset enable for the machine. This was reported by Marcus Meissner in bnc#522790. https://bugzilla.novell.com/show_bug.cgi?id=522790 Reported-by: Marcus Meissner <meissner@novell.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-09-16 03:18:03 +08:00
static void ahci_gtf_filter_workaround(struct ata_host *host)
{
static const struct dmi_system_id sysids[] = {
/*
* Aspire 3810T issues a bunch of SATA enable commands
* via _GTF including an invalid one and one which is
* rejected by the device. Among the successful ones
* is FPDMA non-zero offset enable which when enabled
* only on the drive side leads to NCQ command
* failures. Filter it out.
*/
{
.ident = "Aspire 3810T",
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
},
.driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
},
{ }
};
const struct dmi_system_id *dmi = dmi_first_match(sysids);
unsigned int filter;
int i;
if (!dmi)
return;
filter = (unsigned long)dmi->driver_data;
ata: Convert dev_printk(KERN_<LEVEL> to dev_<level>( Saves a bit of text as the call takes fewer args. Coalesce a few formats. Convert a few bare printks to pr_cont. $ size drivers/ata/built-in.o* text data bss dec hex filename 558429 73893 117864 750186 b726a drivers/ata/built-in.o.allyesconfig.new 559574 73893 117888 751355 b76fb drivers/ata/built-in.o.allyesconfig.old 149567 14689 4220 168476 2921c drivers/ata/built-in.o.defconfig.new 149851 14689 4220 168760 29338 drivers/ata/built-in.o.defconfig.old Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
2011-04-16 06:51:58 +08:00
dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
filter, dmi->ident);
ahci: filter FPDMA non-zero offset enable for Aspire 3810T Curiously, Aspire 3810T issues many SATA feature enable commands via _GTF, of which one is invalid and another is not supported by the drive. In the process, it also enables FPDMA non-zero offset. However, the feature also needs to be supported and enabled from the controller and it's wrong to enable it from _GTF unless the controller can do it by default. Currently, this ends up enabling FPDMA non-zero offset only on the drive side leading to NCQ command failures and eventual disabling of NCQ. This patch makes libata filter out FPDMA non-zero offset enable for the machine. This was reported by Marcus Meissner in bnc#522790. https://bugzilla.novell.com/show_bug.cgi?id=522790 Reported-by: Marcus Meissner <meissner@novell.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-09-16 03:18:03 +08:00
for (i = 0; i < host->n_ports; i++) {
struct ata_port *ap = host->ports[i];
struct ata_link *link;
struct ata_device *dev;
ata_for_each_link(link, ap, EDGE)
ata_for_each_dev(dev, link, ALL)
dev->gtf_filter |= filter;
}
}
ahci: Add ifdef wrapper to ahci_gtf_filter_workaround Commit f80ae7e45a0e03da188494c6e947a5c8b0cdfb4a ahci: filter FPDMA non-zero offset enable for Aspire 3810T breaks the current git build for configurations that don't define CONFIG_ATA_ACPI. This adds an ifdef wrapper to ahci_gtf_filter_workaround. Signed-off-by: Markus Trippelsdorf <markus@trippelsdorf.de> Acked-by: Tejun Heo <tj@kernel.org> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-10-09 11:41:47 +08:00
#else
static inline void ahci_gtf_filter_workaround(struct ata_host *host)
{}
#endif
ahci: filter FPDMA non-zero offset enable for Aspire 3810T Curiously, Aspire 3810T issues many SATA feature enable commands via _GTF, of which one is invalid and another is not supported by the drive. In the process, it also enables FPDMA non-zero offset. However, the feature also needs to be supported and enabled from the controller and it's wrong to enable it from _GTF unless the controller can do it by default. Currently, this ends up enabling FPDMA non-zero offset only on the drive side leading to NCQ command failures and eventual disabling of NCQ. This patch makes libata filter out FPDMA non-zero offset enable for the machine. This was reported by Marcus Meissner in bnc#522790. https://bugzilla.novell.com/show_bug.cgi?id=522790 Reported-by: Marcus Meissner <meissner@novell.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-09-16 03:18:03 +08:00
ahci: Acer SA5-271 SSD Not Detected Fix (Correction in this resend: fixed function name acer_sa5_271_workaround; fixed the always-true condition in the function; fixed description.) On the Acer Switch Alpha 12 (model number: SA5-271), the internal SSD may not get detected because the port_map and CAP.nr_ports combination causes the driver to skip the port that is actually connected to the SSD. More specifically, either all SATA ports are identified as DUMMY, or all ports get ``link down'' and never get up again. This problem occurs occasionally. When this problem occurs, CAP may hold a value of 0xC734FF00 or 0xC734FF01 and port_map may hold a value of 0x00 or 0x01. When this problem does not occur, CAP holds a value of 0xC734FF02 and port_map may hold a value of 0x07. Overriding the CAP value to 0xC734FF02 and port_map to 0x7 significantly reduces the occurrence of this problem. Link: https://bugzilla.kernel.org/attachment.cgi?id=253091 Signed-off-by: Sui Chen <suichen6@gmail.com> Tested-by: Damian Ivanov <damianatorrpm@gmail.com> Cc: stable@vger.kernel.org Signed-off-by: Tejun Heo <tj@kernel.org>
2017-05-09 20:47:22 +08:00
/*
* On the Acer Aspire Switch Alpha 12, sometimes all SATA ports are detected
* as DUMMY, or detected but eventually get a "link down" and never get up
* again. When this happens, CAP.NP may hold a value of 0x00 or 0x01, and the
* port_map may hold a value of 0x00.
*
* Overriding CAP.NP to 0x02 and the port_map to 0x7 will reveal all 3 ports
* and can significantly reduce the occurrence of the problem.
*
* https://bugzilla.kernel.org/show_bug.cgi?id=189471
*/
static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv,
struct pci_dev *pdev)
{
static const struct dmi_system_id sysids[] = {
{
.ident = "Acer Switch Alpha 12",
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271")
},
},
{ }
};
if (dmi_check_system(sysids)) {
dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n");
if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) {
hpriv->port_map = 0x7;
hpriv->cap = 0xC734FF02;
}
}
}
ahci: Workaround for ThunderX Errata#22536 Due to Errata in ThunderX, HOST_IRQ_STAT should be cleared before leaving the interrupt handler. The patch attempts to satisfy the need. Changes from V2: - removed newfile - code is now under CONFIG_ARM64 Changes from V1: - Rebased on top of libata/for-4.6 - Moved ThunderX intr handler to new file tj: Minor adjustments to comments. Signed-off-by: Tirumalesh Chalamarla <tchalamarla@caviumnetworks.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2016-02-17 04:08:49 +08:00
#ifdef CONFIG_ARM64
/*
* Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently.
* Workaround is to make sure all pending IRQs are served before leaving
* handler.
*/
static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance)
{
struct ata_host *host = dev_instance;
struct ahci_host_priv *hpriv;
unsigned int rc = 0;
void __iomem *mmio;
u32 irq_stat, irq_masked;
unsigned int handled = 1;
hpriv = host->private_data;
mmio = hpriv->mmio;
irq_stat = readl(mmio + HOST_IRQ_STAT);
if (!irq_stat)
return IRQ_NONE;
do {
irq_masked = irq_stat & hpriv->port_map;
spin_lock(&host->lock);
rc = ahci_handle_port_intr(host, irq_masked);
if (!rc)
handled = 0;
writel(irq_stat, mmio + HOST_IRQ_STAT);
irq_stat = readl(mmio + HOST_IRQ_STAT);
spin_unlock(&host->lock);
} while (irq_stat);
return IRQ_RETVAL(handled);
}
#endif
ahci: warn about remapped NVMe devices Some Intel ahci implementations have a completely broken remapping mode where they hide one or more NVMe devices behind the bar of an AHCI device. Intel refuses to let the OS reprogram the BIOS to switch out of this mode at runtime, and so far we're not come up with another good way to undo the mess that the Chipset people created. So for now the only thing we can do is to alert users about this situation and switch to the faster and much saner so called "AHCI" mode insted of the RAID mode in the BIOS so that the BIOS does not hide the NVMe devices from us. The sitation is even worse as at least one vendor (thanks a lot Lenovo..) has started hardcoding their BIOS into the "RAID" mode even for laptops that don't use AHCI _at all_ and just have a single NVMe device. For now there is an unspported Linux-only BIOS that undoes this braindamage, but we'll have to see if things are getting better or worse from here. Based on an earlier patch from Dan Williams <dan.j.williams@intel.com>. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Tejun Heo <tj@kernel.org>
2016-12-03 02:31:03 +08:00
static void ahci_remap_check(struct pci_dev *pdev, int bar,
struct ahci_host_priv *hpriv)
{
ata: ahci: Add sysfs attribute to show remapped NVMe device count Add a new sysfs attribute to show how many NVMe devices are remapped. Userspace like distro installer can use this info to ask user to change the BIOS setting. Signed-off-by: Kai-Heng Feng <kai.heng.feng@canonical.com> Signed-off-by: Jens Axboe <axboe@kernel.dk>
2020-02-07 18:00:16 +08:00
int i;
ahci: warn about remapped NVMe devices Some Intel ahci implementations have a completely broken remapping mode where they hide one or more NVMe devices behind the bar of an AHCI device. Intel refuses to let the OS reprogram the BIOS to switch out of this mode at runtime, and so far we're not come up with another good way to undo the mess that the Chipset people created. So for now the only thing we can do is to alert users about this situation and switch to the faster and much saner so called "AHCI" mode insted of the RAID mode in the BIOS so that the BIOS does not hide the NVMe devices from us. The sitation is even worse as at least one vendor (thanks a lot Lenovo..) has started hardcoding their BIOS into the "RAID" mode even for laptops that don't use AHCI _at all_ and just have a single NVMe device. For now there is an unspported Linux-only BIOS that undoes this braindamage, but we'll have to see if things are getting better or worse from here. Based on an earlier patch from Dan Williams <dan.j.williams@intel.com>. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Tejun Heo <tj@kernel.org>
2016-12-03 02:31:03 +08:00
u32 cap;
/*
* Check if this device might have remapped nvme devices.
*/
if (pdev->vendor != PCI_VENDOR_ID_INTEL ||
pci_resource_len(pdev, bar) < SZ_512K ||
bar != AHCI_PCI_BAR_STANDARD ||
!(readl(hpriv->mmio + AHCI_VSCAP) & 1))
return;
cap = readq(hpriv->mmio + AHCI_REMAP_CAP);
for (i = 0; i < AHCI_MAX_REMAP; i++) {
if ((cap & (1 << i)) == 0)
continue;
if (readl(hpriv->mmio + ahci_remap_dcc(i))
!= PCI_CLASS_STORAGE_EXPRESS)
continue;
/* We've found a remapped device */
ata: ahci: Add sysfs attribute to show remapped NVMe device count Add a new sysfs attribute to show how many NVMe devices are remapped. Userspace like distro installer can use this info to ask user to change the BIOS setting. Signed-off-by: Kai-Heng Feng <kai.heng.feng@canonical.com> Signed-off-by: Jens Axboe <axboe@kernel.dk>
2020-02-07 18:00:16 +08:00
hpriv->remapped_nvme++;
ahci: warn about remapped NVMe devices Some Intel ahci implementations have a completely broken remapping mode where they hide one or more NVMe devices behind the bar of an AHCI device. Intel refuses to let the OS reprogram the BIOS to switch out of this mode at runtime, and so far we're not come up with another good way to undo the mess that the Chipset people created. So for now the only thing we can do is to alert users about this situation and switch to the faster and much saner so called "AHCI" mode insted of the RAID mode in the BIOS so that the BIOS does not hide the NVMe devices from us. The sitation is even worse as at least one vendor (thanks a lot Lenovo..) has started hardcoding their BIOS into the "RAID" mode even for laptops that don't use AHCI _at all_ and just have a single NVMe device. For now there is an unspported Linux-only BIOS that undoes this braindamage, but we'll have to see if things are getting better or worse from here. Based on an earlier patch from Dan Williams <dan.j.williams@intel.com>. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Tejun Heo <tj@kernel.org>
2016-12-03 02:31:03 +08:00
}
ata: ahci: Add sysfs attribute to show remapped NVMe device count Add a new sysfs attribute to show how many NVMe devices are remapped. Userspace like distro installer can use this info to ask user to change the BIOS setting. Signed-off-by: Kai-Heng Feng <kai.heng.feng@canonical.com> Signed-off-by: Jens Axboe <axboe@kernel.dk>
2020-02-07 18:00:16 +08:00
if (!hpriv->remapped_nvme)
ahci: warn about remapped NVMe devices Some Intel ahci implementations have a completely broken remapping mode where they hide one or more NVMe devices behind the bar of an AHCI device. Intel refuses to let the OS reprogram the BIOS to switch out of this mode at runtime, and so far we're not come up with another good way to undo the mess that the Chipset people created. So for now the only thing we can do is to alert users about this situation and switch to the faster and much saner so called "AHCI" mode insted of the RAID mode in the BIOS so that the BIOS does not hide the NVMe devices from us. The sitation is even worse as at least one vendor (thanks a lot Lenovo..) has started hardcoding their BIOS into the "RAID" mode even for laptops that don't use AHCI _at all_ and just have a single NVMe device. For now there is an unspported Linux-only BIOS that undoes this braindamage, but we'll have to see if things are getting better or worse from here. Based on an earlier patch from Dan Williams <dan.j.williams@intel.com>. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Tejun Heo <tj@kernel.org>
2016-12-03 02:31:03 +08:00
return;
ata: ahci: Add sysfs attribute to show remapped NVMe device count Add a new sysfs attribute to show how many NVMe devices are remapped. Userspace like distro installer can use this info to ask user to change the BIOS setting. Signed-off-by: Kai-Heng Feng <kai.heng.feng@canonical.com> Signed-off-by: Jens Axboe <axboe@kernel.dk>
2020-02-07 18:00:16 +08:00
dev_warn(&pdev->dev, "Found %u remapped NVMe devices.\n",
hpriv->remapped_nvme);
ahci: don't use MSI for devices with the silly Intel NVMe remapping scheme Intel AHCI controllers that also hide NVMe devices in their bar can't use MSI interrupts, so disable them. Reported-by: John Loy <john.robert.loy@gmail.com> Tested-by: John Loy <john.robert.loy@gmail.com> Signed-off-by: Christoph Hellwig <hch@lst.de> Fixes: d684a90d38e2 ("ahci: per-port msix support") Cc: stable@vger.kernel.org # v4.5+ Signed-off-by: Tejun Heo <tj@kernel.org>
2017-09-06 00:46:47 +08:00
dev_warn(&pdev->dev,
"Switch your BIOS from RAID to AHCI mode to use them.\n");
/*
* Don't rely on the msi-x capability in the remap case,
* share the legacy interrupt across ahci and remapped devices.
*/
hpriv->flags |= AHCI_HFLAG_NO_MSI;
ahci: warn about remapped NVMe devices Some Intel ahci implementations have a completely broken remapping mode where they hide one or more NVMe devices behind the bar of an AHCI device. Intel refuses to let the OS reprogram the BIOS to switch out of this mode at runtime, and so far we're not come up with another good way to undo the mess that the Chipset people created. So for now the only thing we can do is to alert users about this situation and switch to the faster and much saner so called "AHCI" mode insted of the RAID mode in the BIOS so that the BIOS does not hide the NVMe devices from us. The sitation is even worse as at least one vendor (thanks a lot Lenovo..) has started hardcoding their BIOS into the "RAID" mode even for laptops that don't use AHCI _at all_ and just have a single NVMe device. For now there is an unspported Linux-only BIOS that undoes this braindamage, but we'll have to see if things are getting better or worse from here. Based on an earlier patch from Dan Williams <dan.j.williams@intel.com>. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Tejun Heo <tj@kernel.org>
2016-12-03 02:31:03 +08:00
}
ahci: use pci_alloc_irq_vectors Use the new pci_alloc_irq_vectors API to allocate MSI-X and MSI vectors. The big advantage over the old code is that we can use the same API for MSI and MSI-X, and that we don't need to store the MSI-X vector mapping in driver-private data structures. This first conversion keeps the probe order as-is: MSI-X multi vector, MSI multi vector, MSI single vector, MSI-X single vector and last a single least legacy interrupt line. There is one small change of behavior: we now check the "MSI Revert to Single Message" flag for MSI-X in addition to MSI. Because the API to find the Linux IRQ number for a MSI/MSI-X vector is PCI specific, but libahaci is bus-agnostic I had to a get_irq_vector function pointer to struct ahci_host_priv. The alternative would be to move the multi-vector case of ahci_host_activate to ahci.c and just call ata_host_activate directly from the others users of ahci_host_activate. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Tejun Heo <tj@kernel.org>
2016-09-05 23:21:45 +08:00
static int ahci_get_irq_vector(struct ata_host *host, int port)
AHCI: Support multiple MSIs Take advantage of multiple MSIs implementation on x86 - on systems with IRQ remapping AHCI ports not only get assigned separate MSI vectors - but also separate IRQs. As result, interrupts generated by different ports could be serviced on different CPUs rather than on a single one. In cases when number of allocated MSIs is less than requested the Sharing Last MSI mode does not get used, no matter implemented in hardware or not. Instead, the driver assumes the advantage of multiple MSIs is negated and falls back to the single MSI mode as if MRSM bit was set (some Intel chips implement this strategy anyway - MRSM bit gets set even if the number of allocated MSIs exceeds the number of implemented ports). Signed-off-by: Alexander Gordeev <agordeev@redhat.com> Acked-by: Jeff Garzik <jgarzik@redhat.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Suresh Siddha <suresh.b.siddha@intel.com> Cc: Yinghai Lu <yinghai@kernel.org> Cc: Matthew Wilcox <willy@linux.intel.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Thomas Gleixner <tglx@linutronix.de> Link: http://lkml.kernel.org/r/15bf7ee314dd55f21ec7d2a01c47613cd8190a7c.1353324359.git.agordeev@redhat.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
2012-11-19 23:02:48 +08:00
{
ahci: use pci_alloc_irq_vectors Use the new pci_alloc_irq_vectors API to allocate MSI-X and MSI vectors. The big advantage over the old code is that we can use the same API for MSI and MSI-X, and that we don't need to store the MSI-X vector mapping in driver-private data structures. This first conversion keeps the probe order as-is: MSI-X multi vector, MSI multi vector, MSI single vector, MSI-X single vector and last a single least legacy interrupt line. There is one small change of behavior: we now check the "MSI Revert to Single Message" flag for MSI-X in addition to MSI. Because the API to find the Linux IRQ number for a MSI/MSI-X vector is PCI specific, but libahaci is bus-agnostic I had to a get_irq_vector function pointer to struct ahci_host_priv. The alternative would be to move the multi-vector case of ahci_host_activate to ahci.c and just call ata_host_activate directly from the others users of ahci_host_activate. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Tejun Heo <tj@kernel.org>
2016-09-05 23:21:45 +08:00
return pci_irq_vector(to_pci_dev(host->dev), port);
ahci: Add generic MSI-X support for single interrupts to SATA PCI driver This patch adds generic MSI-X support for single interrupts to the SATA PCI driver. MSI-X support is needed for host controller that only have MSI-X support implemented, but no MSI or intx. This patch only adds support for single interrupts, multiple per-port MSI-X interrupts are not yet implemented. The new implementation still initializes MSIs first. Only if that fails, the code tries to enable MSI-X. If that fails too, setup is continued with intx interrupts. To not break other chips by this generic code change, there are the following precautions: * Interrupt ranges are not enabled at all. * Only single interrupt mode is enabled for msix cap devices. Thus, only one interrupt will be setup. * During the discussion with Tejun we agreed to change the init sequence from msix-msi-intx to msi-msix-intx. Thus, if a device offers msi and init does not fail, the msix init code will not be executed. This is equivalent to current code. With this, the code only setups single mode msix as a last resort if msi fails. No interrupt range is enabled at all. Only one interrupt will be enabled. tj: comment edits. Changes of the patch series: v5: * updated patch subject that the patch only implements single IRQ * moved Cavium specific code to a separate patch * detect Cavium ThunderX device with PCI_CLASS_STORAGE_SATA_AHCI instead of vendor/dev id * added more comments to the code * enable single msix support for all kind of devices (removing strict check) * rebased onto update libata/for-4.2 with patch 1, 2 applied v4: * removed implementation of ahci_init_intx() * improved patch descriptions * rebased onto libata/for-4.2 v3: * store irq number in struct ahci_host_priv * change initialization order from msix-msi-intx to msi-msix-intx * improve comments in ahci_init_msix() * improve error message in ahci_init_msix() * do not enable MSI-X if MSI is actively disabled for the device v2: * determine irq vector from pci_dev->msi_list Based on a patch from Sunil Goutham <sgoutham@cavium.com>. Signed-off-by: Robert Richter <rrichter@cavium.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2015-06-06 01:49:25 +08:00
}
ahci: Move interrupt enablement code to a separate function This patch refactors ahci_init_interrupts() and moves msi code to a separate function. Need the split since we add msix initialization in a later patch. The initialization for msix will be done after msi but before intx. Signed-off-by: Robert Richter <rrichter@cavium.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2015-05-31 19:55:17 +08:00
static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports,
struct ahci_host_priv *hpriv)
AHCI: Support multiple MSIs Take advantage of multiple MSIs implementation on x86 - on systems with IRQ remapping AHCI ports not only get assigned separate MSI vectors - but also separate IRQs. As result, interrupts generated by different ports could be serviced on different CPUs rather than on a single one. In cases when number of allocated MSIs is less than requested the Sharing Last MSI mode does not get used, no matter implemented in hardware or not. Instead, the driver assumes the advantage of multiple MSIs is negated and falls back to the single MSI mode as if MRSM bit was set (some Intel chips implement this strategy anyway - MRSM bit gets set even if the number of allocated MSIs exceeds the number of implemented ports). Signed-off-by: Alexander Gordeev <agordeev@redhat.com> Acked-by: Jeff Garzik <jgarzik@redhat.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Suresh Siddha <suresh.b.siddha@intel.com> Cc: Yinghai Lu <yinghai@kernel.org> Cc: Matthew Wilcox <willy@linux.intel.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Thomas Gleixner <tglx@linutronix.de> Link: http://lkml.kernel.org/r/15bf7ee314dd55f21ec7d2a01c47613cd8190a7c.1353324359.git.agordeev@redhat.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
2012-11-19 23:02:48 +08:00
{
ahci: use pci_alloc_irq_vectors Use the new pci_alloc_irq_vectors API to allocate MSI-X and MSI vectors. The big advantage over the old code is that we can use the same API for MSI and MSI-X, and that we don't need to store the MSI-X vector mapping in driver-private data structures. This first conversion keeps the probe order as-is: MSI-X multi vector, MSI multi vector, MSI single vector, MSI-X single vector and last a single least legacy interrupt line. There is one small change of behavior: we now check the "MSI Revert to Single Message" flag for MSI-X in addition to MSI. Because the API to find the Linux IRQ number for a MSI/MSI-X vector is PCI specific, but libahaci is bus-agnostic I had to a get_irq_vector function pointer to struct ahci_host_priv. The alternative would be to move the multi-vector case of ahci_host_activate to ahci.c and just call ata_host_activate directly from the others users of ahci_host_activate. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Tejun Heo <tj@kernel.org>
2016-09-05 23:21:45 +08:00
int nvec;
AHCI: Support multiple MSIs Take advantage of multiple MSIs implementation on x86 - on systems with IRQ remapping AHCI ports not only get assigned separate MSI vectors - but also separate IRQs. As result, interrupts generated by different ports could be serviced on different CPUs rather than on a single one. In cases when number of allocated MSIs is less than requested the Sharing Last MSI mode does not get used, no matter implemented in hardware or not. Instead, the driver assumes the advantage of multiple MSIs is negated and falls back to the single MSI mode as if MRSM bit was set (some Intel chips implement this strategy anyway - MRSM bit gets set even if the number of allocated MSIs exceeds the number of implemented ports). Signed-off-by: Alexander Gordeev <agordeev@redhat.com> Acked-by: Jeff Garzik <jgarzik@redhat.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Suresh Siddha <suresh.b.siddha@intel.com> Cc: Yinghai Lu <yinghai@kernel.org> Cc: Matthew Wilcox <willy@linux.intel.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Thomas Gleixner <tglx@linutronix.de> Link: http://lkml.kernel.org/r/15bf7ee314dd55f21ec7d2a01c47613cd8190a7c.1353324359.git.agordeev@redhat.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
2012-11-19 23:02:48 +08:00
PCI/MSI: Remove pci_enable_msi_block_auto() The new pci_msi_vec_count() interface makes pci_enable_msi_block_auto() superfluous. Drivers can use pci_msi_vec_count() to learn the maximum number of MSIs supported by the device, and then call pci_enable_msi_block(). pci_enable_msi_block_auto() was introduced recently, and its only user is the AHCI driver, which is also updated by this change. Signed-off-by: Alexander Gordeev <agordeev@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Tejun Heo <tj@kernel.org>
2013-12-30 15:28:14 +08:00
if (hpriv->flags & AHCI_HFLAG_NO_MSI)
ahci: Move interrupt enablement code to a separate function This patch refactors ahci_init_interrupts() and moves msi code to a separate function. Need the split since we add msix initialization in a later patch. The initialization for msix will be done after msi but before intx. Signed-off-by: Robert Richter <rrichter@cavium.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2015-05-31 19:55:17 +08:00
return -ENODEV;
PCI/MSI: Remove pci_enable_msi_block_auto() The new pci_msi_vec_count() interface makes pci_enable_msi_block_auto() superfluous. Drivers can use pci_msi_vec_count() to learn the maximum number of MSIs supported by the device, and then call pci_enable_msi_block(). pci_enable_msi_block_auto() was introduced recently, and its only user is the AHCI driver, which is also updated by this change. Signed-off-by: Alexander Gordeev <agordeev@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Tejun Heo <tj@kernel.org>
2013-12-30 15:28:14 +08:00
/*
* If number of MSIs is less than number of ports then Sharing Last
* Message mode could be enforced. In this case assume that advantage
* of multipe MSIs is negated and use single MSI mode instead.
*/
ahci: only try to use multi-MSI mode if there is more than 1 port We should only try to allocate multiple MSI or MSI-X vectors if the device actually has multiple ports. Otherwise pci_alloc_irq_vectors will return a single vector due to n_ports = 1, in which case we shouldn't set the AHCI_HFLAG_MULTI_MSI flag. Signed-off-by: Christoph Hellwig <hch@lst.de> Fixes: 0b9e2988 ("ahci: use pci_alloc_irq_vectors") Reported-by: Emmanuel Benisty <benisty.e@gmail.com> Tested-by: Emmanuel Benisty <benisty.e@gmail.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2016-10-18 15:00:52 +08:00
if (n_ports > 1) {
nvec = pci_alloc_irq_vectors(pdev, n_ports, INT_MAX,
PCI_IRQ_MSIX | PCI_IRQ_MSI);
if (nvec > 0) {
if (!(readl(hpriv->mmio + HOST_CTL) & HOST_MRSM)) {
hpriv->get_irq_vector = ahci_get_irq_vector;
hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
return nvec;
}
AHCI: Support multiple MSIs Take advantage of multiple MSIs implementation on x86 - on systems with IRQ remapping AHCI ports not only get assigned separate MSI vectors - but also separate IRQs. As result, interrupts generated by different ports could be serviced on different CPUs rather than on a single one. In cases when number of allocated MSIs is less than requested the Sharing Last MSI mode does not get used, no matter implemented in hardware or not. Instead, the driver assumes the advantage of multiple MSIs is negated and falls back to the single MSI mode as if MRSM bit was set (some Intel chips implement this strategy anyway - MRSM bit gets set even if the number of allocated MSIs exceeds the number of implemented ports). Signed-off-by: Alexander Gordeev <agordeev@redhat.com> Acked-by: Jeff Garzik <jgarzik@redhat.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Suresh Siddha <suresh.b.siddha@intel.com> Cc: Yinghai Lu <yinghai@kernel.org> Cc: Matthew Wilcox <willy@linux.intel.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Thomas Gleixner <tglx@linutronix.de> Link: http://lkml.kernel.org/r/15bf7ee314dd55f21ec7d2a01c47613cd8190a7c.1353324359.git.agordeev@redhat.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
2012-11-19 23:02:48 +08:00
ahci: only try to use multi-MSI mode if there is more than 1 port We should only try to allocate multiple MSI or MSI-X vectors if the device actually has multiple ports. Otherwise pci_alloc_irq_vectors will return a single vector due to n_ports = 1, in which case we shouldn't set the AHCI_HFLAG_MULTI_MSI flag. Signed-off-by: Christoph Hellwig <hch@lst.de> Fixes: 0b9e2988 ("ahci: use pci_alloc_irq_vectors") Reported-by: Emmanuel Benisty <benisty.e@gmail.com> Tested-by: Emmanuel Benisty <benisty.e@gmail.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2016-10-18 15:00:52 +08:00
/*
* Fallback to single MSI mode if the controller
* enforced MRSM mode.
*/
printk(KERN_INFO
"ahci: MRSM is on, fallback to single MSI\n");
pci_free_irq_vectors(pdev);
}
ahci: fix nvec check commit 17a51f12 ("ahci: only try to use multi-MSI mode if there is more than 1 port") lead to a case where nvec isn't initialized before it's used. Fix this by moving the check into the n_ports conditional. Reported-and-reviewed-by Colin Ian King <colin.king@canonical.com> Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Tejun Heo <tj@kernel.org>
2016-10-20 23:15:41 +08:00
}
ahci: per-port msix support Some AHCI controllers support per-port MSI-X vectors. At the same time the Linux AHCI driver needs to support one-off architectures that implement a single MSI-X vector for all ports. The heuristic for enabling AHCI ports becomes, in order of preference: 1/ per-port multi-MSI-X 2/ per-port multi-MSI 3/ single MSI 4/ single MSI-X 5/ legacy INTX This all depends on AHCI implementations with potentially broken MSI-X requesting less vectors than the number of ports. If this assumption is violated we will need to start explicitly white-listing AHCI-MSIX implementations. Reported-by: Ricardo Neri <ricardo.neri@intel.com> [ricardo: fix struct msix_entry handling] Reported-by: kernel test robot <ying.huang@linux.intel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2015-11-12 08:27:33 +08:00
ahci: use pci_alloc_irq_vectors Use the new pci_alloc_irq_vectors API to allocate MSI-X and MSI vectors. The big advantage over the old code is that we can use the same API for MSI and MSI-X, and that we don't need to store the MSI-X vector mapping in driver-private data structures. This first conversion keeps the probe order as-is: MSI-X multi vector, MSI multi vector, MSI single vector, MSI-X single vector and last a single least legacy interrupt line. There is one small change of behavior: we now check the "MSI Revert to Single Message" flag for MSI-X in addition to MSI. Because the API to find the Linux IRQ number for a MSI/MSI-X vector is PCI specific, but libahaci is bus-agnostic I had to a get_irq_vector function pointer to struct ahci_host_priv. The alternative would be to move the multi-vector case of ahci_host_activate to ahci.c and just call ata_host_activate directly from the others users of ahci_host_activate. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Tejun Heo <tj@kernel.org>
2016-09-05 23:21:45 +08:00
/*
* If the host is not capable of supporting per-port vectors, fall
* back to single MSI before finally attempting single MSI-X.
*/
nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
if (nvec == 1)
ahci: Add generic MSI-X support for single interrupts to SATA PCI driver This patch adds generic MSI-X support for single interrupts to the SATA PCI driver. MSI-X support is needed for host controller that only have MSI-X support implemented, but no MSI or intx. This patch only adds support for single interrupts, multiple per-port MSI-X interrupts are not yet implemented. The new implementation still initializes MSIs first. Only if that fails, the code tries to enable MSI-X. If that fails too, setup is continued with intx interrupts. To not break other chips by this generic code change, there are the following precautions: * Interrupt ranges are not enabled at all. * Only single interrupt mode is enabled for msix cap devices. Thus, only one interrupt will be setup. * During the discussion with Tejun we agreed to change the init sequence from msix-msi-intx to msi-msix-intx. Thus, if a device offers msi and init does not fail, the msix init code will not be executed. This is equivalent to current code. With this, the code only setups single mode msix as a last resort if msi fails. No interrupt range is enabled at all. Only one interrupt will be enabled. tj: comment edits. Changes of the patch series: v5: * updated patch subject that the patch only implements single IRQ * moved Cavium specific code to a separate patch * detect Cavium ThunderX device with PCI_CLASS_STORAGE_SATA_AHCI instead of vendor/dev id * added more comments to the code * enable single msix support for all kind of devices (removing strict check) * rebased onto update libata/for-4.2 with patch 1, 2 applied v4: * removed implementation of ahci_init_intx() * improved patch descriptions * rebased onto libata/for-4.2 v3: * store irq number in struct ahci_host_priv * change initialization order from msix-msi-intx to msi-msix-intx * improve comments in ahci_init_msix() * improve error message in ahci_init_msix() * do not enable MSI-X if MSI is actively disabled for the device v2: * determine irq vector from pci_dev->msi_list Based on a patch from Sunil Goutham <sgoutham@cavium.com>. Signed-off-by: Robert Richter <rrichter@cavium.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2015-06-06 01:49:25 +08:00
return nvec;
ahci: use pci_alloc_irq_vectors Use the new pci_alloc_irq_vectors API to allocate MSI-X and MSI vectors. The big advantage over the old code is that we can use the same API for MSI and MSI-X, and that we don't need to store the MSI-X vector mapping in driver-private data structures. This first conversion keeps the probe order as-is: MSI-X multi vector, MSI multi vector, MSI single vector, MSI-X single vector and last a single least legacy interrupt line. There is one small change of behavior: we now check the "MSI Revert to Single Message" flag for MSI-X in addition to MSI. Because the API to find the Linux IRQ number for a MSI/MSI-X vector is PCI specific, but libahaci is bus-agnostic I had to a get_irq_vector function pointer to struct ahci_host_priv. The alternative would be to move the multi-vector case of ahci_host_activate to ahci.c and just call ata_host_activate directly from the others users of ahci_host_activate. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Tejun Heo <tj@kernel.org>
2016-09-05 23:21:45 +08:00
return pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX);
AHCI: Support multiple MSIs Take advantage of multiple MSIs implementation on x86 - on systems with IRQ remapping AHCI ports not only get assigned separate MSI vectors - but also separate IRQs. As result, interrupts generated by different ports could be serviced on different CPUs rather than on a single one. In cases when number of allocated MSIs is less than requested the Sharing Last MSI mode does not get used, no matter implemented in hardware or not. Instead, the driver assumes the advantage of multiple MSIs is negated and falls back to the single MSI mode as if MRSM bit was set (some Intel chips implement this strategy anyway - MRSM bit gets set even if the number of allocated MSIs exceeds the number of implemented ports). Signed-off-by: Alexander Gordeev <agordeev@redhat.com> Acked-by: Jeff Garzik <jgarzik@redhat.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Suresh Siddha <suresh.b.siddha@intel.com> Cc: Yinghai Lu <yinghai@kernel.org> Cc: Matthew Wilcox <willy@linux.intel.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Thomas Gleixner <tglx@linutronix.de> Link: http://lkml.kernel.org/r/15bf7ee314dd55f21ec7d2a01c47613cd8190a7c.1353324359.git.agordeev@redhat.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
2012-11-19 23:02:48 +08:00
}
ata: ahci: move marking of external port earlier Move the marking of an external port earlier in the call chain. This is needed for further cleanups. No functional change intended. Tested-by: Damien Le Moal <dlemoal@kernel.org> Tested-by: Jian-Hong Pan <jhp@endlessos.org> Reviewed-by: Damien Le Moal <dlemoal@kernel.org> Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Niklas Cassel <cassel@kernel.org>
2024-02-07 05:13:42 +08:00
static void ahci_mark_external_port(struct ata_port *ap)
{
struct ahci_host_priv *hpriv = ap->host->private_data;
void __iomem *port_mmio = ahci_port_base(ap);
u32 tmp;
ata: ahci: a hotplug capable port is an external port A hotplug capable port is an external port, so mark it as such. We even say this ourselves in libata-scsi.c: /* set scsi removable (RMB) bit per ata bit, or if the * AHCI port says it's external (Hotplug-capable, eSATA). */ This also matches the terminology used in AHCI 1.3.1 (the keyword to search for is "externally accessible"). Tested-by: Damien Le Moal <dlemoal@kernel.org> Tested-by: Jian-Hong Pan <jhp@endlessos.org> Reviewed-by: Damien Le Moal <dlemoal@kernel.org> Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Niklas Cassel <cassel@kernel.org>
2024-02-07 05:13:43 +08:00
/* mark external ports (hotplug-capable, eSATA) */
ata: ahci: move marking of external port earlier Move the marking of an external port earlier in the call chain. This is needed for further cleanups. No functional change intended. Tested-by: Damien Le Moal <dlemoal@kernel.org> Tested-by: Jian-Hong Pan <jhp@endlessos.org> Reviewed-by: Damien Le Moal <dlemoal@kernel.org> Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Niklas Cassel <cassel@kernel.org>
2024-02-07 05:13:42 +08:00
tmp = readl(port_mmio + PORT_CMD);
ata: ahci: a hotplug capable port is an external port A hotplug capable port is an external port, so mark it as such. We even say this ourselves in libata-scsi.c: /* set scsi removable (RMB) bit per ata bit, or if the * AHCI port says it's external (Hotplug-capable, eSATA). */ This also matches the terminology used in AHCI 1.3.1 (the keyword to search for is "externally accessible"). Tested-by: Damien Le Moal <dlemoal@kernel.org> Tested-by: Jian-Hong Pan <jhp@endlessos.org> Reviewed-by: Damien Le Moal <dlemoal@kernel.org> Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Niklas Cassel <cassel@kernel.org>
2024-02-07 05:13:43 +08:00
if (((tmp & PORT_CMD_ESP) && (hpriv->cap & HOST_CAP_SXS)) ||
(tmp & PORT_CMD_HPCP))
ata: ahci: move marking of external port earlier Move the marking of an external port earlier in the call chain. This is needed for further cleanups. No functional change intended. Tested-by: Damien Le Moal <dlemoal@kernel.org> Tested-by: Jian-Hong Pan <jhp@endlessos.org> Reviewed-by: Damien Le Moal <dlemoal@kernel.org> Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Niklas Cassel <cassel@kernel.org>
2024-02-07 05:13:42 +08:00
ap->pflags |= ATA_PFLAG_EXTERNAL;
}
ata: ahci: drop hpriv param from ahci_update_initial_lpm_policy() There is no need for ahci_update_initial_lpm_policy() to take hpriv as a parameter, it can easily be derived from the ata_port. Tested-by: Damien Le Moal <dlemoal@kernel.org> Tested-by: Jian-Hong Pan <jhp@endlessos.org> Acked-by: Jian-Hong Pan <jhp@endlessos.org> Reviewed-by: Damien Le Moal <dlemoal@kernel.org> Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Niklas Cassel <cassel@kernel.org>
2024-02-07 05:13:44 +08:00
static void ahci_update_initial_lpm_policy(struct ata_port *ap)
ata: ahci: Enable DEVSLP by default on x86 with SLP_S0 One of the requirement for modern x86 system to enter lowest power mode (SLP_S0) is SATA IP block to be off. This is true even during when platform is suspended to idle and not only in opportunistic (runtime) suspend. Several of these system don't have traditional ACPI S3, so it is important that they enter SLP_S0 state, to avoid draining battery even during suspend. So it is important that out of the box Linux installation reach this state. SATA IP block doesn't get turned off till SATA is in DEVSLP mode. Here user has to either use scsi-host sysfs or tools like powertop to set the sata-host link_power_management_policy to min_power. This change sets by default link power management policy to min_power with partial (preferred) or slumber support on idle for some platforms. To avoid regressions, the following conditions are used: - User didn't override the policy from module parameter - The kernel config is already set to use med_power_with_dipm or deeper - System is a SLP_S0 capable using ACPI low power idle flag This combination will make sure that systems are fairly recent and since getting shipped with SLP_S0 support, the DEVSLP function is already validated. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2018-07-28 04:47:03 +08:00
{
ata: ahci: drop hpriv param from ahci_update_initial_lpm_policy() There is no need for ahci_update_initial_lpm_policy() to take hpriv as a parameter, it can easily be derived from the ata_port. Tested-by: Damien Le Moal <dlemoal@kernel.org> Tested-by: Jian-Hong Pan <jhp@endlessos.org> Acked-by: Jian-Hong Pan <jhp@endlessos.org> Reviewed-by: Damien Le Moal <dlemoal@kernel.org> Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Niklas Cassel <cassel@kernel.org>
2024-02-07 05:13:44 +08:00
struct ahci_host_priv *hpriv = ap->host->private_data;
ata: ahci: Rename CONFIG_SATA_LPM_POLICY configuration item back CONFIG_SATA_LPM_MOBILE_POLICY was renamed to CONFIG_SATA_LPM_POLICY in commit 4dd4d3deb502 ("ata: ahci: Rename CONFIG_SATA_LPM_MOBILE_POLICY configuration item"). This can potentially cause problems as users would invisibly lose configuration policy defaults when they built the new kernel. To avoid such problems, switch back to the old name (even if it's wrong). Suggested-by: Christoph Hellwig <hch@infradead.org> Suggested-by: Damien Le Moal <damien.lemoal@opensource.wdc.com> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
2022-04-06 09:57:51 +08:00
int policy = CONFIG_SATA_MOBILE_LPM_POLICY;
ata: ahci: Enable DEVSLP by default on x86 with SLP_S0 One of the requirement for modern x86 system to enter lowest power mode (SLP_S0) is SATA IP block to be off. This is true even during when platform is suspended to idle and not only in opportunistic (runtime) suspend. Several of these system don't have traditional ACPI S3, so it is important that they enter SLP_S0 state, to avoid draining battery even during suspend. So it is important that out of the box Linux installation reach this state. SATA IP block doesn't get turned off till SATA is in DEVSLP mode. Here user has to either use scsi-host sysfs or tools like powertop to set the sata-host link_power_management_policy to min_power. This change sets by default link power management policy to min_power with partial (preferred) or slumber support on idle for some platforms. To avoid regressions, the following conditions are used: - User didn't override the policy from module parameter - The kernel config is already set to use med_power_with_dipm or deeper - System is a SLP_S0 capable using ACPI low power idle flag This combination will make sure that systems are fairly recent and since getting shipped with SLP_S0 support, the DEVSLP function is already validated. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2018-07-28 04:47:03 +08:00
ata: ahci: Rename `AHCI_HFLAG_IS_MOBILE` `AHCI_HFLAG_IS_MOBILE` designates that a chipset should be using the default link power management policy from a kernel configuration item. As desktop chipsets may also be interested in this default policy configuration, rename the flag to `AHCI_HFLAG_USE_LPM_POLICY` to more accurately reflect that a chipset doesn't have to be mobile to adopt it. Reviewed-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Paul Menzel <pmenzel@molgen.mpg.de> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
2022-02-26 01:23:18 +08:00
/* Ignore processing for chipsets that don't use policy */
if (!(hpriv->flags & AHCI_HFLAG_USE_LPM_POLICY))
ata: ahci: Enable DEVSLP by default on x86 with SLP_S0 One of the requirement for modern x86 system to enter lowest power mode (SLP_S0) is SATA IP block to be off. This is true even during when platform is suspended to idle and not only in opportunistic (runtime) suspend. Several of these system don't have traditional ACPI S3, so it is important that they enter SLP_S0 state, to avoid draining battery even during suspend. So it is important that out of the box Linux installation reach this state. SATA IP block doesn't get turned off till SATA is in DEVSLP mode. Here user has to either use scsi-host sysfs or tools like powertop to set the sata-host link_power_management_policy to min_power. This change sets by default link power management policy to min_power with partial (preferred) or slumber support on idle for some platforms. To avoid regressions, the following conditions are used: - User didn't override the policy from module parameter - The kernel config is already set to use med_power_with_dipm or deeper - System is a SLP_S0 capable using ACPI low power idle flag This combination will make sure that systems are fairly recent and since getting shipped with SLP_S0 support, the DEVSLP function is already validated. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2018-07-28 04:47:03 +08:00
return;
/* user modified policy via module param */
if (mobile_lpm_policy != -1) {
policy = mobile_lpm_policy;
goto update_policy;
}
ata: ahci: Do not check ACPI_FADT_LOW_POWER_S0 The ACPI_FADT_LOW_POWER_S0 flag merely means that it is better to use low-power S0 idle on the given platform than S3 (provided that the latter is supported) and it doesn't preclude using either of them (which of them will be used depends on the choices made by user space). For this reason, there is no benefit from checking that flag in ahci_update_initial_lpm_policy(). First off, it cannot be a bug to do S3 with policy set to either ATA_LPM_MIN_POWER_WITH_PARTIAL or ATA_LPM_MIN_POWER, because S3 can be used on systems with ACPI_FADT_LOW_POWER_S0 set and it must work if really supported, so the ACPI_FADT_LOW_POWER_S0 check is not needed to protect the S3-capable systems from failing. Second, suspend-to-idle can be carried out on a system with ACPI_FADT_LOW_POWER_S0 unset and it is expected to work, so if setting policy to either ATA_LPM_MIN_POWER_WITH_PARTIAL or ATA_LPM_MIN_POWER is needed to handle that case correctly, it should be done regardless of the ACPI_FADT_LOW_POWER_S0 value. Accordingly, replace the ACPI_FADT_LOW_POWER_S0 check in ahci_update_initial_lpm_policy() with pm_suspend_default_s2idle() which is more general and also takes the user's preference into account and drop the CONFIG_ACPI #ifdef around it that is not necessary any more. Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
2022-08-26 02:47:28 +08:00
if (policy > ATA_LPM_MED_POWER && pm_suspend_default_s2idle()) {
ata: ahci: Enable DEVSLP by default on x86 with SLP_S0 One of the requirement for modern x86 system to enter lowest power mode (SLP_S0) is SATA IP block to be off. This is true even during when platform is suspended to idle and not only in opportunistic (runtime) suspend. Several of these system don't have traditional ACPI S3, so it is important that they enter SLP_S0 state, to avoid draining battery even during suspend. So it is important that out of the box Linux installation reach this state. SATA IP block doesn't get turned off till SATA is in DEVSLP mode. Here user has to either use scsi-host sysfs or tools like powertop to set the sata-host link_power_management_policy to min_power. This change sets by default link power management policy to min_power with partial (preferred) or slumber support on idle for some platforms. To avoid regressions, the following conditions are used: - User didn't override the policy from module parameter - The kernel config is already set to use med_power_with_dipm or deeper - System is a SLP_S0 capable using ACPI low power idle flag This combination will make sure that systems are fairly recent and since getting shipped with SLP_S0 support, the DEVSLP function is already validated. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2018-07-28 04:47:03 +08:00
if (hpriv->cap & HOST_CAP_PART)
policy = ATA_LPM_MIN_POWER_WITH_PARTIAL;
else if (hpriv->cap & HOST_CAP_SSC)
policy = ATA_LPM_MIN_POWER;
}
update_policy:
if (policy >= ATA_LPM_UNKNOWN && policy <= ATA_LPM_MIN_POWER)
ap->target_lpm_policy = policy;
}
libata/ahci: Drop PCS quirk for Denverton and beyond The Linux ahci driver has historically implemented a configuration fixup for platforms / platform-firmware that fails to enable the ports prior to OS hand-off at boot. The fixup was originally implemented way back before ahci moved from drivers/scsi/ to drivers/ata/, and was updated in 2007 via commit 49f290903935 "ahci: update PCS programming". The quirk sets a port-enable bitmap in the PCS register at offset 0x92. This quirk could be applied generically up until the arrival of the Denverton (DNV) platform. The DNV AHCI controller architecture supports more than 6 ports and along with that the PCS register location and format were updated to allow for more possible ports in the bitmap. DNV AHCI expands the register to 32-bits and moves it to offset 0x94. As it stands there are no known problem reports with existing Linux trying to set bits at offset 0x92 which indicates that the quirk is not applicable. Likely it is not applicable on a wider range of platforms, but it is difficult to discern which platforms if any still depend on the quirk. Rather than try to fix the PCS quirk to consider the DNV register layout instead require explicit opt-in. The assumption is that the OS driver need not touch this register, and platforms can be added with a new boad_ahci_pcs7 board-id when / if problematic platforms are found in the future. The logic in ahci_intel_pcs_quirk() looks for all Intel AHCI instances with "legacy" board-ids and otherwise skips the quirk if the board was matched by class-code. Reported-by: Stephen Douthit <stephend@silicom-usa.com> Cc: Christoph Hellwig <hch@infradead.org> Reviewed-by: Stephen Douthit <stephend@silicom-usa.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Jens Axboe <axboe@kernel.dk>
2019-08-30 07:30:34 +08:00
static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv)
{
const struct pci_device_id *id = pci_match_id(ahci_pci_tbl, pdev);
u16 tmp16;
/*
* Only apply the 6-port PCS quirk for known legacy platforms.
*/
if (!id || id->vendor != PCI_VENDOR_ID_INTEL)
return;
libata/ahci: Fix PCS quirk application Commit c312ef176399 "libata/ahci: Drop PCS quirk for Denverton and beyond" got the polarity wrong on the check for which board-ids should have the quirk applied. The board type board_ahci_pcs7 is defined at the end of the list such that "pcs7" boards can be special cased in the future if they need the quirk. All prior Intel board ids "< board_ahci_pcs7" should proceed with applying the quirk. Reported-by: Andreas Friedrich <afrie@gmx.net> Reported-by: Stephen Douthit <stephend@silicom-usa.com> Fixes: c312ef176399 ("libata/ahci: Drop PCS quirk for Denverton and beyond") Cc: <stable@vger.kernel.org> Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Jens Axboe <axboe@kernel.dk>
2019-10-16 03:54:17 +08:00
/* Skip applying the quirk on Denverton and beyond */
if (((enum board_ids) id->driver_data) >= board_ahci_pcs7)
libata/ahci: Drop PCS quirk for Denverton and beyond The Linux ahci driver has historically implemented a configuration fixup for platforms / platform-firmware that fails to enable the ports prior to OS hand-off at boot. The fixup was originally implemented way back before ahci moved from drivers/scsi/ to drivers/ata/, and was updated in 2007 via commit 49f290903935 "ahci: update PCS programming". The quirk sets a port-enable bitmap in the PCS register at offset 0x92. This quirk could be applied generically up until the arrival of the Denverton (DNV) platform. The DNV AHCI controller architecture supports more than 6 ports and along with that the PCS register location and format were updated to allow for more possible ports in the bitmap. DNV AHCI expands the register to 32-bits and moves it to offset 0x94. As it stands there are no known problem reports with existing Linux trying to set bits at offset 0x92 which indicates that the quirk is not applicable. Likely it is not applicable on a wider range of platforms, but it is difficult to discern which platforms if any still depend on the quirk. Rather than try to fix the PCS quirk to consider the DNV register layout instead require explicit opt-in. The assumption is that the OS driver need not touch this register, and platforms can be added with a new boad_ahci_pcs7 board-id when / if problematic platforms are found in the future. The logic in ahci_intel_pcs_quirk() looks for all Intel AHCI instances with "legacy" board-ids and otherwise skips the quirk if the board was matched by class-code. Reported-by: Stephen Douthit <stephend@silicom-usa.com> Cc: Christoph Hellwig <hch@infradead.org> Reviewed-by: Stephen Douthit <stephend@silicom-usa.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Jens Axboe <axboe@kernel.dk>
2019-08-30 07:30:34 +08:00
return;
/*
* port_map is determined from PORTS_IMPL PCI register which is
* implemented as write or write-once register. If the register
* isn't programmed, ahci automatically generates it from number
* of ports, which is good enough for PCS programming. It is
* otherwise expected that platform firmware enables the ports
* before the OS boots.
*/
pci_read_config_word(pdev, PCS_6, &tmp16);
if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
tmp16 |= hpriv->port_map;
pci_write_config_word(pdev, PCS_6, tmp16);
}
}
ata: ahci: Add sysfs attribute to show remapped NVMe device count Add a new sysfs attribute to show how many NVMe devices are remapped. Userspace like distro installer can use this info to ask user to change the BIOS setting. Signed-off-by: Kai-Heng Feng <kai.heng.feng@canonical.com> Signed-off-by: Jens Axboe <axboe@kernel.dk>
2020-02-07 18:00:16 +08:00
static ssize_t remapped_nvme_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct ata_host *host = dev_get_drvdata(dev);
struct ahci_host_priv *hpriv = host->private_data;
ata: ahci: use sysfs_emit() Use sysfs_emit() instead of sprintf in remapped_nvme_show(). Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
2021-12-02 14:02:17 +08:00
return sysfs_emit(buf, "%u\n", hpriv->remapped_nvme);
ata: ahci: Add sysfs attribute to show remapped NVMe device count Add a new sysfs attribute to show how many NVMe devices are remapped. Userspace like distro installer can use this info to ask user to change the BIOS setting. Signed-off-by: Kai-Heng Feng <kai.heng.feng@canonical.com> Signed-off-by: Jens Axboe <axboe@kernel.dk>
2020-02-07 18:00:16 +08:00
}
static DEVICE_ATTR_RO(remapped_nvme);
libata: update libata LLDs to use devres Update libata LLDs to use devres. Core layer is already converted to support managed LLDs. This patch simplifies initialization and fixes many resource related bugs in init failure and detach path. For example, all converted drivers now handle ata_device_add() failure gracefully without excessive resource rollback code. As most resources are released automatically on driver detach, many drivers don't need or can do with much simpler ->{port|host}_stop(). In general, stop callbacks are need iff port or host needs to be given commands to shut it down. Note that freezing is enough in many cases and ports are automatically frozen before being detached. Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-01-20 15:00:28 +08:00
static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 06:20:36 +08:00
{
ahci: workarounds for mcp65 MCP65 ahci can do NCQ but doesn't set the CAP bit and rev A0 and A1 can't do MSI but have MSI capability. Implement AHCI_HFLAG_YES_NCQ and apply appropriate workarounds. Signed-off-by: Tejun Heo <htejun@gmail.com> Cc: Peer Chen <pchen@nvidia.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2008-06-09 23:13:04 +08:00
unsigned int board_id = ent->driver_data;
struct ata_port_info pi = ahci_port_info[board_id];
libata: convert the remaining SATA drivers to new init model Convert ahci, sata_sil, sata_sil24, sata_svw, sata_qstor, sata_mv, sata_sx4, sata_vsc and sata_inic162x to new init model. Now that host and ap are available during intialization, functions are converted to take either host or ap instead of low level parameters which were inevitable for functions shared between init and other paths. This simplifies code quite a bit. * init_one()'s now follow more consistent init order * ahci_setup_port() and ahci_host_init() collapsed into ahci_init_one() for init order consistency * sata_vsc uses port_info instead of setting fields manually * in sata_svw, k2_board_info converted to port_info (info is now in port flags). port number is honored now. Tested on ICH7/8 AHCI, jmb360, sil3112, 3114, 3124 and 3132. Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-04-17 22:44:08 +08:00
const struct ata_port_info *ppi[] = { &pi, NULL };
libata: update libata LLDs to use devres Update libata LLDs to use devres. Core layer is already converted to support managed LLDs. This patch simplifies initialization and fixes many resource related bugs in init failure and detach path. For example, all converted drivers now handle ata_device_add() failure gracefully without excessive resource rollback code. As most resources are released automatically on driver detach, many drivers don't need or can do with much simpler ->{port|host}_stop(). In general, stop callbacks are need iff port or host needs to be given commands to shut it down. Note that freezing is enough in many cases and ports are automatically frozen before being detached. Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-01-20 15:00:28 +08:00
struct device *dev = &pdev->dev;
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 06:20:36 +08:00
struct ahci_host_priv *hpriv;
libata: convert the remaining SATA drivers to new init model Convert ahci, sata_sil, sata_sil24, sata_svw, sata_qstor, sata_mv, sata_sx4, sata_vsc and sata_inic162x to new init model. Now that host and ap are available during intialization, functions are converted to take either host or ap instead of low level parameters which were inevitable for functions shared between init and other paths. This simplifies code quite a bit. * init_one()'s now follow more consistent init order * ahci_setup_port() and ahci_host_init() collapsed into ahci_init_one() for init order consistency * sata_vsc uses port_info instead of setting fields manually * in sata_svw, k2_board_info converted to port_info (info is now in port flags). port number is honored now. Tested on ICH7/8 AHCI, jmb360, sil3112, 3114, 3124 and 3132. Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-04-17 22:44:08 +08:00
struct ata_host *host;
AHCI: Cleanup checking of multiple MSIs/SLM modes Sharing Last Message (SLM) mode is currently checked in two functions: ahci_host_activate() and ahci_init_interrupts(). This update consolidates SLM mode check with activation of multiple MSIs mode. Signed-off-by: Alexander Gordeev <agordeev@redhat.com> Signed-off-by: Tejun Heo <tj@kernel.org> Cc: linux-ide@vger.kernel.org
2014-09-25 21:13:21 +08:00
int n_ports, i, rc;
ahci: support the STA2X11 I/O Hub The AHCI controller found in the STA2X11 chip uses BAR number 0 instead of 5. Also, the chip's fixup code sets a special DMA mask for all of its PCI functions, and the mask must be preserved here. Signed-off-by: Alessandro Rubini <rubini@gnudd.com> Acked-by: Giancarlo Asnaghi <giancarlo.asnaghi@st.com> Cc: Alan Cox <alan@linux.intel.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2012-01-06 20:33:39 +08:00
int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 06:20:36 +08:00
[libata] ahci: Fix warning: comparison between 'enum <anonymous>' and 'enum <anonymous>' The below patch casts ATA_MAX_QUEUE to int because GCC will give a warning message about the two different enum blocks: CC drivers/ata/ahci.o drivers/ata/ahci.c: In function 'ahci_init_one': drivers/ata/ahci.c:1045:2: warning: comparison between 'enum <anonymous>' and 'enum <anonymous>' Signed-off-by: Justin P. Mattock <justinmattock@gmail.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-07-03 22:29:25 +08:00
WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
[PATCH] ahci: implement NCQ suppport Implement NCQ support. Original implementation is from Jens Axboe. Signed-off-by: Tejun Heo <htejun@gmail.com>
2006-05-15 20:03:55 +08:00
ata: Add and use ata_print_version_once Use a single mechanism to show driver version. Reduces text a tiny bit too. Remove uses of static int printed_version Add and use ata_print_version(const struct device *, const char *ver) and ata_print_version_once. $ size drivers/ata/built-in.* text data bss dec hex filename 544969 73893 116584 735446 b38d6 drivers/ata/built-in.allyesconfig.ata.o 543870 73893 116592 734355 b34ad drivers/ata/built-in.allyesconfig.print_once.o 141328 14689 4220 160237 271ed drivers/ata/built-in.defconfig.ata.o 141212 14689 4220 160121 27179 drivers/ata/built-in.defconfig.print_once.o Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
2011-04-16 06:52:00 +08:00
ata_print_version_once(&pdev->dev, DRV_VERSION);
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 06:20:36 +08:00
ahci, pata_marvell: play nicely together I've been chasing Jeff about this for months. Jeff added the Marvell device identifiers to the ahci driver without making the AHCI driver handle the PATA port. This means a lot of users can't use current kernels and in most distro cases can't even install. This has been going on since March 2008 for the 6121 Marvell, and late 2007 for the 6145!!! This was all pointed out at the time and repeatedly ignored. Bugs assigned to Jeff about this are ignored also. To quote Jeff in email > "Just switch the order of 'ahci' and 'pata_marvell' in > /etc/modprobe.conf, then use Fedora's tools regenerate the initrd. > See? It's not rocket science, and the current configuration can be > easily made to work for Fedora users." (Which isn't trivial, isn't end user, shouldn't be needed, and as it usually breaks at install time is in fact impossible) To quote Jeff in August 2007 > " mv-ahci-pata > Marvell 6121/6141 PATA support. Needs fixing in the 'PATA controller > command' area before it is usable, and can go upstream." Only he add the ids anyway later and caused regressions, adding a further id in March causing more regresions. The actual fix for the moment is very simple. If the user has included the pata_marvell driver let it drive the ports. If they've only selected for SATA support give them the AHCI driver which will run the port a fraction faster. Allow the user to control this decision via ahci.marvell_enable as a module parameter so that distributions can ship 'it works' defaults and smarter users (or config tools) can then flip it over it desired. Signed-off-by: Alan Cox <alan@redhat.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2008-09-03 21:48:34 +08:00
/* The AHCI driver can only drive the SATA ports, the PATA driver
can drive them all so if both drivers are selected make sure
AHCI stays out of the way */
if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
return -ENODEV;
ahci: mcp89: enter AHCI mode under Apple BIOS emulation Apple's BIOS emulation forcibly disables MCP89 AHCI, eg. on Macbook7,1. We can re-enable it, replacing the previous workaround of using ata_generic. tj: whitespace adjustments, dropped inline from is_mcp89_apple() Signed-off-by: James Laird <jhl@mafipulation.org> Signed-off-by: Tejun Heo <tj@kernel.org>
2013-11-19 08:06:38 +08:00
/* Apple BIOS on MCP89 prevents us using AHCI */
if (is_mcp89_apple(pdev))
ahci_mcp89_apple_enable(pdev);
ahci,ata_generic: let ata_generic handle new MBP w/ MCP89 For yet unknown reason, MCP89 on MBP 7,1 doesn't work w/ ahci under linux but the controller doesn't require explicit mode setting and works fine with ata_generic. Make ahci ignore the controller on MBP 7,1 and let ata_generic take it for now. Reported in bko#15923. https://bugzilla.kernel.org/show_bug.cgi?id=15923 NVIDIA is investigating why ahci mode doesn't work. Signed-off-by: Tejun Heo <tj@kernel.org> Cc: Peer Chen <pchen@nvidia.com> Cc: stable@kernel.org Reported-by: Anders Østhus <grapz666@gmail.com> Reported-by: Andreas Graf <andreas_graf@csgraf.de> Reported-by: Benoit Gschwind <gschwind@gnu-log.net> Reported-by: Damien Cassou <damien.cassou@gmail.com> Reported-by: tixetsal@juno.com Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-06-17 17:42:22 +08:00
ahci: let users know that Promise PDC42819 support is limited to SATA devices ahci can drive the Promise PDC42819, but obviously it can only use SATA disks connected to this controller. The controller can actually support SAS disks as well, but we only know how to use it in it's AHCI mode. Add a message to let users know that because ahci is driving their chip they can only use the SATA disks connected to this controller. Signed-off-by: Mark Nelson <mdnelson8@gmail.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-11-22 09:07:41 +08:00
/* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
* At the moment, we can only use the AHCI mode. Let the users know
* that for SAS drives they're out of luck.
*/
if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
ata: Convert dev_printk(KERN_<LEVEL> to dev_<level>( Saves a bit of text as the call takes fewer args. Coalesce a few formats. Convert a few bare printks to pr_cont. $ size drivers/ata/built-in.o* text data bss dec hex filename 558429 73893 117864 750186 b726a drivers/ata/built-in.o.allyesconfig.new 559574 73893 117888 751355 b76fb drivers/ata/built-in.o.allyesconfig.old 149567 14689 4220 168476 2921c drivers/ata/built-in.o.defconfig.new 149851 14689 4220 168760 29338 drivers/ata/built-in.o.defconfig.old Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
2011-04-16 06:51:58 +08:00
dev_info(&pdev->dev,
"PDC42819 can only drive SATA devices with this driver\n");
ahci: let users know that Promise PDC42819 support is limited to SATA devices ahci can drive the Promise PDC42819, but obviously it can only use SATA disks connected to this controller. The controller can actually support SAS disks as well, but we only know how to use it in it's AHCI mode. Add a message to let users know that because ahci is driving their chip they can only use the SATA disks connected to this controller. Signed-off-by: Mark Nelson <mdnelson8@gmail.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-11-22 09:07:41 +08:00
ahci: Add support for Cavium's ThunderX host controller This patch adds support for Cavium's ThunderX host controller. The controller resides on the SoC and is a AHCI compatible SATA controller with one port, compliant with Serial ATA 3.1 and AHCI Revision 1.31. There can exists multiple SATA controllers on the SoC. The controller depends on MSI-X support since the PCI ECAM controller on the SoC does not implement MSI nor lagacy intx interrupt support. Thus, during device initialization, if MSI fails MSI-X will be used to enable the device's interrupts. The controller uses non-standard BAR0 for its register range. The already existing device lookup (vendor and device id) that is already implemented for other host controllers is used to change the PCI BAR. Signed-off-by: Robert Richter <rrichter@cavium.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2015-06-06 01:49:26 +08:00
/* Some devices use non-standard BARs */
ahci: support the STA2X11 I/O Hub The AHCI controller found in the STA2X11 chip uses BAR number 0 instead of 5. Also, the chip's fixup code sets a special DMA mask for all of its PCI functions, and the mask must be preserved here. Signed-off-by: Alessandro Rubini <rubini@gnudd.com> Acked-by: Giancarlo Asnaghi <giancarlo.asnaghi@st.com> Cc: Alan Cox <alan@linux.intel.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2012-01-06 20:33:39 +08:00
if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
[libata] ahci: Add support for Enmotus Bobcat device. Silicon does not support standard AHCI BAR assignment. Add vendor/device exception to force BAR 2. Signed-off-by: Hugh Daschbach <hugh.daschbach@enmotus.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2013-01-05 06:39:09 +08:00
else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
ahci: Add support for Cavium's fifth generation SATA controller This patch adds support for Cavium's fifth generation SATA controller. It is an on-chip controller and complies with AHCI 1.3.1. As the controller uses 64-bit addresses it cannot use the standard AHCI BAR5 and so uses BAR4. Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2017-10-11 13:37:51 +08:00
else if (pdev->vendor == PCI_VENDOR_ID_CAVIUM) {
if (pdev->device == 0xa01c)
ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
if (pdev->device == 0xa084)
ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5;
AHCI: Add support for Loongson 7A1000 SATA controller Loongson 7A1000 SATA controller uses BAR0 as the base address register. Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn> Signed-off-by: Jens Axboe <axboe@kernel.dk>
2020-03-10 20:50:08 +08:00
} else if (pdev->vendor == PCI_VENDOR_ID_LOONGSON) {
if (pdev->device == 0x7a08)
ahci_pci_bar = AHCI_PCI_BAR_LOONGSON;
ahci: Add support for Cavium's fifth generation SATA controller This patch adds support for Cavium's fifth generation SATA controller. It is an on-chip controller and complies with AHCI 1.3.1. As the controller uses 64-bit addresses it cannot use the standard AHCI BAR5 and so uses BAR4. Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2017-10-11 13:37:51 +08:00
}
ahci: support the STA2X11 I/O Hub The AHCI controller found in the STA2X11 chip uses BAR number 0 instead of 5. Also, the chip's fixup code sets a special DMA mask for all of its PCI functions, and the mask must be preserved here. Signed-off-by: Alessandro Rubini <rubini@gnudd.com> Acked-by: Giancarlo Asnaghi <giancarlo.asnaghi@st.com> Cc: Alan Cox <alan@linux.intel.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2012-01-06 20:33:39 +08:00
libata: convert the remaining SATA drivers to new init model Convert ahci, sata_sil, sata_sil24, sata_svw, sata_qstor, sata_mv, sata_sx4, sata_vsc and sata_inic162x to new init model. Now that host and ap are available during intialization, functions are converted to take either host or ap instead of low level parameters which were inevitable for functions shared between init and other paths. This simplifies code quite a bit. * init_one()'s now follow more consistent init order * ahci_setup_port() and ahci_host_init() collapsed into ahci_init_one() for init order consistency * sata_vsc uses port_info instead of setting fields manually * in sata_svw, k2_board_info converted to port_info (info is now in port flags). port number is honored now. Tested on ICH7/8 AHCI, jmb360, sil3112, 3114, 3124 and 3132. Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-04-17 22:44:08 +08:00
/* acquire resources */
libata: update libata LLDs to use devres Update libata LLDs to use devres. Core layer is already converted to support managed LLDs. This patch simplifies initialization and fixes many resource related bugs in init failure and detach path. For example, all converted drivers now handle ata_device_add() failure gracefully without excessive resource rollback code. As most resources are released automatically on driver detach, many drivers don't need or can do with much simpler ->{port|host}_stop(). In general, stop callbacks are need iff port or host needs to be given commands to shut it down. Note that freezing is enough in many cases and ports are automatically frozen before being detached. Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-01-20 15:00:28 +08:00
rc = pcim_enable_device(pdev);
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 06:20:36 +08:00
if (rc)
return rc;
ahci: don't attach if ICH6 is in combined mode ICH6 R/Ms share PCI ID between piix and ahci modes and we've been allowing ahci to attach regardless of how BIOS configured it. However, enabling AHCI mode when the controller is in combined mode can result in unexpected behavior. Don't attach if the controller is in combined mode. Signed-off-by: Tejun Heo <htejun@gmail.com> Cc: Bill Nottingham <notting@redhat.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-12-06 14:09:43 +08:00
if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
(pdev->device == 0x2652 || pdev->device == 0x2653)) {
u8 map;
/* ICH6s share the same PCI ID for both piix and ahci
* modes. Enabling ahci mode while MAP indicates
* combined mode is a bad idea. Yield to ata_piix.
*/
pci_read_config_byte(pdev, ICH_MAP, &map);
if (map & 0x3) {
ata: Convert dev_printk(KERN_<LEVEL> to dev_<level>( Saves a bit of text as the call takes fewer args. Coalesce a few formats. Convert a few bare printks to pr_cont. $ size drivers/ata/built-in.o* text data bss dec hex filename 558429 73893 117864 750186 b726a drivers/ata/built-in.o.allyesconfig.new 559574 73893 117888 751355 b76fb drivers/ata/built-in.o.allyesconfig.old 149567 14689 4220 168476 2921c drivers/ata/built-in.o.defconfig.new 149851 14689 4220 168760 29338 drivers/ata/built-in.o.defconfig.old Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
2011-04-16 06:51:58 +08:00
dev_info(&pdev->dev,
"controller is in combined mode, can't enable AHCI mode\n");
ahci: don't attach if ICH6 is in combined mode ICH6 R/Ms share PCI ID between piix and ahci modes and we've been allowing ahci to attach regardless of how BIOS configured it. However, enabling AHCI mode when the controller is in combined mode can result in unexpected behavior. Don't attach if the controller is in combined mode. Signed-off-by: Tejun Heo <htejun@gmail.com> Cc: Bill Nottingham <notting@redhat.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-12-06 14:09:43 +08:00
return -ENODEV;
}
}
ahci: bail out on ICH6 before using AHCI BAR The check for "combined mode" (which disables ahci support) on ICH6 is done after the first use of AHCI BAR. But if ahci is not enabled AHCI BAR is initialized to 0x00000000. (At least it is on the ICH6-M I tested this on. If I understand the datasheet correctly it should also be on ICH6R.) This apparently makes the call of pcim_iomap_regions_request_all() return -EINVAL. And we end up with ahci: probe of 0000:00:1f.2 failed with error -22 (at warning level) in the logs. So check for "combined mode" before calling pcim_iomap_regions_request_all(). Signed-off-by: Paul Bolle <pebolle@tiscali.nl> Signed-off-by: Tejun Heo <tj@kernel.org>
2013-12-16 18:34:21 +08:00
/* AHCI controllers often implement SFF compatible interface.
* Grab all PCI BARs just in case.
*/
rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
if (rc == -EBUSY)
pcim_pin_device(pdev);
if (rc)
return rc;
libata: update libata LLDs to use devres Update libata LLDs to use devres. Core layer is already converted to support managed LLDs. This patch simplifies initialization and fixes many resource related bugs in init failure and detach path. For example, all converted drivers now handle ata_device_add() failure gracefully without excessive resource rollback code. As most resources are released automatically on driver detach, many drivers don't need or can do with much simpler ->{port|host}_stop(). In general, stop callbacks are need iff port or host needs to be given commands to shut it down. Note that freezing is enough in many cases and ports are automatically frozen before being detached. Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-01-20 15:00:28 +08:00
hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
if (!hpriv)
return -ENOMEM;
ahci: move host flags over to pi.private_data Private pi.flags area is full and we need more private flags. Move host private flags over to pi.private_data. During initialization, these flags are copied to hpriv->flags. Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-09-23 12:19:55 +08:00
hpriv->flags |= (unsigned long)pi.private_data;
ahci: workarounds for mcp65 MCP65 ahci can do NCQ but doesn't set the CAP bit and rev A0 and A1 can't do MSI but have MSI capability. Implement AHCI_HFLAG_YES_NCQ and apply appropriate workarounds. Signed-off-by: Tejun Heo <htejun@gmail.com> Cc: Peer Chen <pchen@nvidia.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2008-06-09 23:13:04 +08:00
/* MCP65 revision A1 and A2 can't do MSI */
if (board_id == board_ahci_mcp65 &&
(pdev->revision == 0xa1 || pdev->revision == 0xa2))
hpriv->flags |= AHCI_HFLAG_NO_MSI;
[libata] ahci: Withdraw IGN_SERR_INTERNAL for SB800 SATA There is an issue in ATI SB600/SB700 SATA that PxSERR.E should not be set on some conditions, which will lead to many SATA ODD error messages. commit 55a61604cd1354e1783364e1c901034f2f474b7d is the workaround. Since SB800 fixed this HW issue, IGN_SERR_INTERNAL should be withdrawn for SB800. Signed-off-by: Shane Huang <shane.huang@amd.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2008-12-30 10:53:41 +08:00
/* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
ahci: disable 64bit DMA by default on SB600s Till now only one board, ASUS M2A-VM, can do 64bit dma with recent BIOSen. Enabling 64bit DMA by default already broke three boards. Enabling 64bit DMA isn't worth these regressions. Disable 64bit DMA by default and enable it only on boards which are known to work. Signed-off-by: Tejun Heo <tj@kernel.org> Reported-by: Gabriele Balducci <balducci@units.it> Reported-by: maierp@informatik.tu-muenchen.de Cc: Shane Huang <shane.huang@amd.com> Cc: stable@kernel.org Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-10-03 17:27:29 +08:00
/* only some SB600s can do 64bit DMA */
if (ahci_sb600_enable_64bit(pdev))
hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
[libata] ahci: Restore SB600 SATA controller 64 bit DMA Community reported one SB600 SATA issue(BZ #9412), which led to 64 bit DMA disablement for all SB600 revisions by driver maintainers with commits c7a42156d99bcea7f8173ba7a6034bbaa2ecb77c and 4cde32fc4b32e96a99063af3183acdfd54c563f0. But the root cause is ASUS M2A-VM system BIOS bug in old revisions like 0901, while forcing into 32bit DMA happens to work as workaround. Now it's time to withdraw 4cde32fc4b32e96a99063af3183acdfd54c563f0 so as to restore the SB600 SATA 64bit DMA capability. This patch is also adding the workaround for M2A-VM old BIOS revisions, but users are suggested to upgrade their system BIOS to the latest one if they meet this issue. Signed-off-by: Shane Huang <shane.huang@amd.com> Cc: Tejun Heo <tj@kernel.org> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-05-27 15:04:43 +08:00
ahci: support the STA2X11 I/O Hub The AHCI controller found in the STA2X11 chip uses BAR number 0 instead of 5. Also, the chip's fixup code sets a special DMA mask for all of its PCI functions, and the mask must be preserved here. Signed-off-by: Alessandro Rubini <rubini@gnudd.com> Acked-by: Giancarlo Asnaghi <giancarlo.asnaghi@st.com> Cc: Alan Cox <alan@linux.intel.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2012-01-06 20:33:39 +08:00
hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
ahci: Get rid of host->iomap usage Currently the driver uses host->iomap to store all the iomapped BARs of a PCI device (while AHCI devices actually use just a single memory window). We're going to teach AHCI to work with non-PCI buses, so there are two options to make this work: 1. "fake" host->iomap array for non-PCI devices, and place the needed address at iomap[AHCI_PCI_BAR]; 2. Get rid of host->iomap usage, instead introduce a private mmio field. This patch implements the second option. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-03-04 01:17:34 +08:00
ahci: warn about remapped NVMe devices Some Intel ahci implementations have a completely broken remapping mode where they hide one or more NVMe devices behind the bar of an AHCI device. Intel refuses to let the OS reprogram the BIOS to switch out of this mode at runtime, and so far we're not come up with another good way to undo the mess that the Chipset people created. So for now the only thing we can do is to alert users about this situation and switch to the faster and much saner so called "AHCI" mode insted of the RAID mode in the BIOS so that the BIOS does not hide the NVMe devices from us. The sitation is even worse as at least one vendor (thanks a lot Lenovo..) has started hardcoding their BIOS into the "RAID" mode even for laptops that don't use AHCI _at all_ and just have a single NVMe device. For now there is an unspported Linux-only BIOS that undoes this braindamage, but we'll have to see if things are getting better or worse from here. Based on an earlier patch from Dan Williams <dan.j.williams@intel.com>. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Tejun Heo <tj@kernel.org>
2016-12-03 02:31:03 +08:00
/* detect remapped nvme devices */
ahci_remap_check(pdev, ahci_pci_bar, hpriv);
ata: ahci: Add sysfs attribute to show remapped NVMe device count Add a new sysfs attribute to show how many NVMe devices are remapped. Userspace like distro installer can use this info to ask user to change the BIOS setting. Signed-off-by: Kai-Heng Feng <kai.heng.feng@canonical.com> Signed-off-by: Jens Axboe <axboe@kernel.dk>
2020-02-07 18:00:16 +08:00
sysfs_add_file_to_group(&pdev->dev.kobj,
&dev_attr_remapped_nvme.attr,
NULL);
ahci: disable DEVSLP for Intel Valleyview On Intel Valleyview SoC, SATA device sleep is not reliable. When DEVSLP is attempted on certain SSDs, port_devslp write would fail and result in malfunction of AHCI controller. AHCI controller may be not shown in PCI enumeration after reset. Complete power source removal may be required to recover from this failure. So we blacklist this device and override host device reported capabilities such that device LPM will only attempt slumber but not DEVSLP. Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com> Acked-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2014-04-16 13:27:11 +08:00
/* must set flag prior to save config in order to take effect */
if (ahci_broken_devslp(pdev))
hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
ahci: Workaround for ThunderX Errata#22536 Due to Errata in ThunderX, HOST_IRQ_STAT should be cleared before leaving the interrupt handler. The patch attempts to satisfy the need. Changes from V2: - removed newfile - code is now under CONFIG_ARM64 Changes from V1: - Rebased on top of libata/for-4.6 - Moved ThunderX intr handler to new file tj: Minor adjustments to comments. Signed-off-by: Tirumalesh Chalamarla <tchalamarla@caviumnetworks.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2016-02-17 04:08:49 +08:00
#ifdef CONFIG_ARM64
ata: ahci: Disable SXS for Hisilicon Kunpeng920 On Hisilicon Kunpeng920, ESP is set to 1 by default for all ports of SATA controller. In some scenarios, some ports are not external SATA ports, and it cause disks connected to these ports to be identified as removable disks. So disable the SXS capability on the software side to prevent users from mistakenly considering non-removable disks as removable disks and performing related operations. Signed-off-by: Xingui Yang <yangxingui@huawei.com> Signed-off-by: Luo Jiaxing <luojiaxing@huawei.com> Reviewed-by: John Garry <john.garry@huawei.com> Link: https://lore.kernel.org/r/1615544676-61926-1-git-send-email-luojiaxing@huawei.com Signed-off-by: Jens Axboe <axboe@kernel.dk>
2021-03-12 18:24:36 +08:00
if (pdev->vendor == PCI_VENDOR_ID_HUAWEI &&
pdev->device == 0xa235 &&
pdev->revision < 0x30)
hpriv->flags |= AHCI_HFLAG_NO_SXS;
ahci: Workaround for ThunderX Errata#22536 Due to Errata in ThunderX, HOST_IRQ_STAT should be cleared before leaving the interrupt handler. The patch attempts to satisfy the need. Changes from V2: - removed newfile - code is now under CONFIG_ARM64 Changes from V1: - Rebased on top of libata/for-4.6 - Moved ThunderX intr handler to new file tj: Minor adjustments to comments. Signed-off-by: Tirumalesh Chalamarla <tchalamarla@caviumnetworks.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2016-02-17 04:08:49 +08:00
if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
hpriv->irq_handler = ahci_thunderx_irq_handler;
#endif
libata: convert the remaining SATA drivers to new init model Convert ahci, sata_sil, sata_sil24, sata_svw, sata_qstor, sata_mv, sata_sx4, sata_vsc and sata_inic162x to new init model. Now that host and ap are available during intialization, functions are converted to take either host or ap instead of low level parameters which were inevitable for functions shared between init and other paths. This simplifies code quite a bit. * init_one()'s now follow more consistent init order * ahci_setup_port() and ahci_host_init() collapsed into ahci_init_one() for init order consistency * sata_vsc uses port_info instead of setting fields manually * in sata_svw, k2_board_info converted to port_info (info is now in port flags). port number is honored now. Tested on ICH7/8 AHCI, jmb360, sil3112, 3114, 3124 and 3132. Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-04-17 22:44:08 +08:00
/* save initial config */
ahci: Factor out PCI specifics from ahci_save_initial_config() Make ahci_save_initial_config() a bit more generic by introducing force_port_map and mask_port_map arguments. Move PCI stuff into ahci_pci_save_initial_config(). Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-03-04 01:17:36 +08:00
ahci_pci_save_initial_config(pdev, hpriv);
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 06:20:36 +08:00
libata: convert the remaining SATA drivers to new init model Convert ahci, sata_sil, sata_sil24, sata_svw, sata_qstor, sata_mv, sata_sx4, sata_vsc and sata_inic162x to new init model. Now that host and ap are available during intialization, functions are converted to take either host or ap instead of low level parameters which were inevitable for functions shared between init and other paths. This simplifies code quite a bit. * init_one()'s now follow more consistent init order * ahci_setup_port() and ahci_host_init() collapsed into ahci_init_one() for init order consistency * sata_vsc uses port_info instead of setting fields manually * in sata_svw, k2_board_info converted to port_info (info is now in port flags). port number is honored now. Tested on ICH7/8 AHCI, jmb360, sil3112, 3114, 3124 and 3132. Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-04-17 22:44:08 +08:00
/* prepare host */
ahci: disable FPDMA auto-activate optimization on NVIDIA AHCI Mike Cui reported that his system with an NVIDIA MCP79 (aka MCP7A) chipset stopped working with 2.6.32. The problem appears to be that 2.6.32 now enables the FPDMA auto-activate optimization in the ahci driver. The drive works fine with this enabled on an Intel AHCI so this appears to be a chipset bug. Since MCP79 is a fairly recent NVIDIA chipset and we don't have any info on whether any other NVIDIA chipsets have this issue, disable FPDMA AA optimization on all NVIDIA AHCI controllers for now. Should address http://bugzilla.kernel.org/show_bug.cgi?id=14922 Signed-off-by: Robert Hancock <hancockrwd@gmail.com> While-we-investigate-issue-this-patch-looks-good-to-me-by: Prajakta Gudadhe <pgudadhe@nvidia.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com> Cc: stable@kernel.org
2010-01-27 12:33:23 +08:00
if (hpriv->cap & HOST_CAP_NCQ) {
pi.flags |= ATA_FLAG_NCQ;
ahci: implement AHCI_HFLAG_NO_FPDMA_AA and update NV quirks It turns out different generations of MCPs have differing quirks. * MCP 65-73 : FPDMA AA broken, lies about PMP support, forgets to report NCQ * MCP 77-79 : FPDMA AA broken, lies about PMP support * MCP 89 : FPDMA AA broken Instead of turngin off FPDMA AA on all NVIDIAs, implement HFLAG_NO_FPDMA_AA, define additional board IDs and apply necessary quirks. This fixes bko#15481 and the list of quirks is verified by Peer Chen. http://bugzilla.kernel.org/show_bug.cgi?id=15481 Signed-off-by: Tejun Heo <tj@kernel.org> Cc: Peer Chen <pchen@nvidia.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-03-30 09:28:32 +08:00
/*
* Auto-activate optimization is supposed to be
* supported on all AHCI controllers indicating NCQ
* capability, but it seems to be broken on some
* chipsets including NVIDIAs.
*/
if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
ahci: disable FPDMA auto-activate optimization on NVIDIA AHCI Mike Cui reported that his system with an NVIDIA MCP79 (aka MCP7A) chipset stopped working with 2.6.32. The problem appears to be that 2.6.32 now enables the FPDMA auto-activate optimization in the ahci driver. The drive works fine with this enabled on an Intel AHCI so this appears to be a chipset bug. Since MCP79 is a fairly recent NVIDIA chipset and we don't have any info on whether any other NVIDIA chipsets have this issue, disable FPDMA AA optimization on all NVIDIA AHCI controllers for now. Should address http://bugzilla.kernel.org/show_bug.cgi?id=14922 Signed-off-by: Robert Hancock <hancockrwd@gmail.com> While-we-investigate-issue-this-patch-looks-good-to-me-by: Prajakta Gudadhe <pgudadhe@nvidia.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com> Cc: stable@kernel.org
2010-01-27 12:33:23 +08:00
pi.flags |= ATA_FLAG_FPDMA_AA;
libata: Add H2D FIS "auxiliary" port flag Add a new port flag, ATA_FLAG_FPDMA_AUX, used to indicate support for transmission of the H2D FIS 'auxiliary' field. Signed-off-by: Marc Carino <marc.ceeeee@gmail.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2013-08-25 14:22:49 +08:00
/*
* All AHCI controllers should be forward-compatible
* with the new auxiliary field. This code should be
* conditionalized if any buggy AHCI controllers are
* encountered.
*/
pi.flags |= ATA_FLAG_FPDMA_AUX;
ahci: disable FPDMA auto-activate optimization on NVIDIA AHCI Mike Cui reported that his system with an NVIDIA MCP79 (aka MCP7A) chipset stopped working with 2.6.32. The problem appears to be that 2.6.32 now enables the FPDMA auto-activate optimization in the ahci driver. The drive works fine with this enabled on an Intel AHCI so this appears to be a chipset bug. Since MCP79 is a fairly recent NVIDIA chipset and we don't have any info on whether any other NVIDIA chipsets have this issue, disable FPDMA AA optimization on all NVIDIA AHCI controllers for now. Should address http://bugzilla.kernel.org/show_bug.cgi?id=14922 Signed-off-by: Robert Hancock <hancockrwd@gmail.com> While-we-investigate-issue-this-patch-looks-good-to-me-by: Prajakta Gudadhe <pgudadhe@nvidia.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com> Cc: stable@kernel.org
2010-01-27 12:33:23 +08:00
}
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 06:20:36 +08:00
ahci: implement PMP support Implement AHCI PMP support. ahci only supports command based switching. Also, for some reason, NCQ over PMP doesn't work now. Other than that, everything works. Tested on ICH9R, JMB360/363 + SIMG3726, 4726 and 5744. Signed-off-by: Tejun Heo <htejun@gmail.com> Cc: Forrest Zhao <forrest.zhao@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-09-23 12:19:54 +08:00
if (hpriv->cap & HOST_CAP_PMP)
pi.flags |= ATA_FLAG_PMP;
ahci: Introduce ahci_set_em_messages() Factor out some ahci_em_messages handling code from ahci_init_one(). We would like to reuse it for non-PCI devices. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-03-04 01:17:45 +08:00
ahci_set_em_messages(hpriv, &pi);
libata/ahci: enclosure management support Add Enclosure Management support to libata and ahci. Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2008-06-04 01:33:55 +08:00
SATA AHCI: Blacklist system that spins off disks during ACPI power off Some notebooks from HP have the problem that their BIOSes attempt to spin down hard drives before entering ACPI system states S4 and S5. This leads to a yo-yo effect during system power-off shutdown and the last phase of hibernation when the disk is first spun down by the kernel and then almost immediately turned on and off by the BIOS. This, in turn, may result in shortening the disk's life times. To prevent this from happening we can blacklist the affected systems using DMI information. Blacklist HP nx6310 that uses the AHCI driver. Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-01-20 03:57:36 +08:00
if (ahci_broken_system_poweroff(pdev)) {
pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
dev_info(&pdev->dev,
"quirky BIOS, skipping spindown on poweroff\n");
}
ahci: Disable LPM on Lenovo 50 series laptops with a too old BIOS There have been several reports of LPM related hard freezes about once a day on multiple Lenovo 50 series models. Strange enough these reports where not disk model specific as LPM issues usually are and some users with the exact same disk + laptop where seeing them while other users where not seeing these issues. It turns out that enabling LPM triggers a firmware bug somewhere, which has been fixed in later BIOS versions. This commit adds a new ahci_broken_lpm() function and a new ATA_FLAG_NO_LPM for dealing with this. The ahci_broken_lpm() function contains DMI match info for the 4 models which are known to be affected by this and the DMI BIOS date field for known good BIOS versions. If the BIOS date is older then the one in the table LPM will be disabled and a warning will be printed. Note the BIOS dates are for known good versions, some older versions may work too, but we don't know for sure, the table is using dates from BIOS versions for which users have confirmed that upgrading to that version makes the problem go away. Unfortunately I've been unable to get hold of the reporter who reported that BIOS version 2.35 fixed the problems on the W541 for him. I've been able to verify the DMI_SYS_VENDOR and DMI_PRODUCT_VERSION from an older dmidecode, but I don't know the exact BIOS date as reported in the DMI. Lenovo keeps a changelog with dates in their release notes, but the dates there are the release dates not the build dates which are in DMI. So I've chosen to set the date to which we compare to one day past the release date of the 2.34 BIOS. I plan to fix this with a follow up commit once I've the necessary info. Cc: stable@vger.kernel.org Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2018-07-01 18:15:46 +08:00
if (ahci_broken_lpm(pdev)) {
pi.flags |= ATA_FLAG_NO_LPM;
dev_warn(&pdev->dev,
"BIOS update required for Link Power Management support\n");
}
ahci: add warning messages for hp laptops with broken suspend Harddisks on HP dv[4-6] and HDX18 fail to come online after resume on earlier BIOSen. Fortunately, HP recently released BIOS updates for all machines to fix the issue. Detect old BIOSen, warn the user to update BIOS on boot and suspend attempts and fail suspend. Kudos to all the bug reporters. Signed-off-by: Tejun Heo <tj@kernel.org> Cc: kernel.org@epperson.homelinux.net Cc: emisca@gmail.com Cc: Gadi Cohen <dragon@wastelands.net> Cc: Paul Swanson <paul@procursa.com> Cc: s@ourada.org Cc: Trevor Davenport <trevor.davenport@gmail.com> Cc: corruptor1972 <steven_tierney@yahoo.co.uk> Cc: Victoria Wilson <mail@vwilson.co.uk> Cc: khiraly <khiraly.list@gmail.com> Cc: Sean <wollombi@gmail.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-05-30 19:50:12 +08:00
if (ahci_broken_suspend(pdev)) {
hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
ata: Convert dev_printk(KERN_<LEVEL> to dev_<level>( Saves a bit of text as the call takes fewer args. Coalesce a few formats. Convert a few bare printks to pr_cont. $ size drivers/ata/built-in.o* text data bss dec hex filename 558429 73893 117864 750186 b726a drivers/ata/built-in.o.allyesconfig.new 559574 73893 117888 751355 b76fb drivers/ata/built-in.o.allyesconfig.old 149567 14689 4220 168476 2921c drivers/ata/built-in.o.defconfig.new 149851 14689 4220 168760 29338 drivers/ata/built-in.o.defconfig.old Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
2011-04-16 06:51:58 +08:00
dev_warn(&pdev->dev,
"BIOS update required for suspend/resume\n");
ahci: add warning messages for hp laptops with broken suspend Harddisks on HP dv[4-6] and HDX18 fail to come online after resume on earlier BIOSen. Fortunately, HP recently released BIOS updates for all machines to fix the issue. Detect old BIOSen, warn the user to update BIOS on boot and suspend attempts and fail suspend. Kudos to all the bug reporters. Signed-off-by: Tejun Heo <tj@kernel.org> Cc: kernel.org@epperson.homelinux.net Cc: emisca@gmail.com Cc: Gadi Cohen <dragon@wastelands.net> Cc: Paul Swanson <paul@procursa.com> Cc: s@ourada.org Cc: Trevor Davenport <trevor.davenport@gmail.com> Cc: corruptor1972 <steven_tierney@yahoo.co.uk> Cc: Victoria Wilson <mail@vwilson.co.uk> Cc: khiraly <khiraly.list@gmail.com> Cc: Sean <wollombi@gmail.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-05-30 19:50:12 +08:00
}
ahci: add workaround for on-board 5723s on some gigabyte boards Some gigabytes have on-board SIMG5723s connected to JMB ahcis. These are used to implement hardware raid. Unfortunately some firmware revisions on these 5723s don't bring the link down when all the downstream ports are unoccupied while not responding to reset protocol which makes libata think that there's device attached to the port but is not responding and retry. This results in painfully wrong boot detection time for these ports when they're empty. This patch quirks those boards such that ahci gives up after the initial timeout. Combined with parallel probing, this gives quick enough probing and also is safe because SIMG5723 will respond to the first try if any of the downstream ports is occupied. Signed-off-by: Tejun Heo <tj@kernel.org> Reported-by: Marc Bowes <marcbowes@gmail.com> Reported-by: Nicolas Mailhot <Nicolas.Mailhot@LaPoste.net> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-08-04 13:30:08 +08:00
if (ahci_broken_online(pdev)) {
hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
dev_info(&pdev->dev,
"online status unreliable, applying workaround\n");
}
ahci: Acer SA5-271 SSD Not Detected Fix (Correction in this resend: fixed function name acer_sa5_271_workaround; fixed the always-true condition in the function; fixed description.) On the Acer Switch Alpha 12 (model number: SA5-271), the internal SSD may not get detected because the port_map and CAP.nr_ports combination causes the driver to skip the port that is actually connected to the SSD. More specifically, either all SATA ports are identified as DUMMY, or all ports get ``link down'' and never get up again. This problem occurs occasionally. When this problem occurs, CAP may hold a value of 0xC734FF00 or 0xC734FF01 and port_map may hold a value of 0x00 or 0x01. When this problem does not occur, CAP holds a value of 0xC734FF02 and port_map may hold a value of 0x07. Overriding the CAP value to 0xC734FF02 and port_map to 0x7 significantly reduces the occurrence of this problem. Link: https://bugzilla.kernel.org/attachment.cgi?id=253091 Signed-off-by: Sui Chen <suichen6@gmail.com> Tested-by: Damian Ivanov <damianatorrpm@gmail.com> Cc: stable@vger.kernel.org Signed-off-by: Tejun Heo <tj@kernel.org>
2017-05-09 20:47:22 +08:00
/* Acer SA5-271 workaround modifies private_data */
acer_sa5_271_workaround(hpriv, pdev);
ahci: fix CAP.NP and PI handling AHCI uses CAP.NP to indicate the number of ports and PI to tell which ports are enabled. The only requirement is that the number of ports indicated by CAP.NP should equal or be higher than the number of enabled ports in PI. CAP.NP and PI carry duplicate information and there have been some interesting cases. Some early AHCI controllers didn't set PI at all and just implement from port 0 to CAP.NP. An ICH8 board which wired four out of six available ports had 3 (4 ports) for CAP.NP and 0x33 for PI. While ESB2 has less bits set in PI than the value in CAP.NP. Till now, ahci driver assumed that PI is invalid if it doesn't match CAP.NP exactly. This violates AHCI standard and the driver ends up accessing unmimplemented ports on ESB2. This patch updates CAP.NP and PI handling such that PI can have less number of bits set than indicated in CAP.NP and the highest port is determined as the maximum port of what CAP.NP and PI indicate. Signed-off-by: Tejun Heo <htejun@gmail.com> Cc: Jan Beulich <jbeulich@novell.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2008-02-06 14:13:51 +08:00
/* CAP.NP sometimes indicate the index of the last enabled
* port, at other times, that of the last possible port, so
* determining the maximum port number requires looking at
* both CAP.NP and port_map.
*/
n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
libata: convert the remaining SATA drivers to new init model Convert ahci, sata_sil, sata_sil24, sata_svw, sata_qstor, sata_mv, sata_sx4, sata_vsc and sata_inic162x to new init model. Now that host and ap are available during intialization, functions are converted to take either host or ap instead of low level parameters which were inevitable for functions shared between init and other paths. This simplifies code quite a bit. * init_one()'s now follow more consistent init order * ahci_setup_port() and ahci_host_init() collapsed into ahci_init_one() for init order consistency * sata_vsc uses port_info instead of setting fields manually * in sata_svw, k2_board_info converted to port_info (info is now in port flags). port number is honored now. Tested on ICH7/8 AHCI, jmb360, sil3112, 3114, 3124 and 3132. Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-04-17 22:44:08 +08:00
if (!host)
return -ENOMEM;
host->private_data = hpriv;
ahci: use pci_alloc_irq_vectors Use the new pci_alloc_irq_vectors API to allocate MSI-X and MSI vectors. The big advantage over the old code is that we can use the same API for MSI and MSI-X, and that we don't need to store the MSI-X vector mapping in driver-private data structures. This first conversion keeps the probe order as-is: MSI-X multi vector, MSI multi vector, MSI single vector, MSI-X single vector and last a single least legacy interrupt line. There is one small change of behavior: we now check the "MSI Revert to Single Message" flag for MSI-X in addition to MSI. Because the API to find the Linux IRQ number for a MSI/MSI-X vector is PCI specific, but libahaci is bus-agnostic I had to a get_irq_vector function pointer to struct ahci_host_priv. The alternative would be to move the multi-vector case of ahci_host_activate to ahci.c and just call ata_host_activate directly from the others users of ahci_host_activate. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Tejun Heo <tj@kernel.org>
2016-09-05 23:21:45 +08:00
if (ahci_init_msi(pdev, n_ports, hpriv) < 0) {
/* legacy intx interrupts */
pci_intx(pdev, 1);
}
ahci: fix the single MSI-X case in ahci_init_one We need to make sure hpriv->irq is set properly if we don't use per-port vectors, so switch from blindly assigning pdev->irq to using pci_irq_vector, which handles all interrupt types correctly. Signed-off-by: Christoph Hellwig <hch@lst.de> Reported-by: Robert Richter <robert.richter@cavium.com> Tested-by: Robert Richter <robert.richter@cavium.com> Tested-by: David Daney <ddaney.cavm@gmail.com> Fixes: 0b9e2988ab22 ("ahci: use pci_alloc_irq_vectors") Signed-off-by: Tejun Heo <tj@kernel.org>
2016-10-25 20:04:34 +08:00
hpriv->irq = pci_irq_vector(pdev, 0);
ahci: Store irq number in struct ahci_host_priv Currently, ahci supports only msi and intx. To also support msix the handling of the irq number need to be changed. The irq number for msix devices is taken from msi_list instead of pci_dev. Thus, the irq number of a device needs to be stored in struct ahci_host_priv now. This allows the host controller to be activated in a generic way. This change is only intended for ahci drivers. For that reason the irq number is stored in struct ahci_host_priv used only by ahci drivers. Thus, the ABI changes only for ahci_host_activate(), but existing ata drivers (about 50) are unaffected and keep unchanged. All users of ahci_host_activate() have been updated. While touching drivers/ata/libahci.c, doing a small code cleanup in ahci_port_start(). Signed-off-by: Robert Richter <rrichter@cavium.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2015-05-31 19:55:18 +08:00
ahci: add a module parameter to ignore the SSS flags for async scanning The SSS flag, which directs the OS to spin up one disk at a time to not have the PSU blow out, sometimes gets set even when not needed. The effect of this is a longer-than-needed boot time. This patch adds a module parameter that makes the driver ignore SSS at least as far as the parallel scan during boot is concerned... Signed-off-by: Arjan van de Ven <arjan@linux.intel.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-01-26 18:05:44 +08:00
if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
libata: Add a per-host flag to opt-in into parallel port probes This patch adds a per host flag that allows drivers to opt in into having its busses scanned in parallel. Drivers that do not set this flag get their ports scanned in the "original" sequence. Signed-off-by: Arjan van de Ven <arjan@linux.intel.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2009-01-10 07:54:07 +08:00
host->flags |= ATA_HOST_PARALLEL_SCAN;
ahci: add a module parameter to ignore the SSS flags for async scanning The SSS flag, which directs the OS to spin up one disk at a time to not have the PSU blow out, sometimes gets set even when not needed. The effect of this is a longer-than-needed boot time. This patch adds a module parameter that makes the driver ignore SSS at least as far as the parallel scan during boot is concerned... Signed-off-by: Arjan van de Ven <arjan@linux.intel.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-01-26 18:05:44 +08:00
else
ahci: use dev_info() instead of printk() Change "raw" printk() call to dev_info() to provide a better message to userspace so it can properly identify the device and not just have to guess. Signed-off-by: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2013-10-05 08:15:16 +08:00
dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
libata: Add a per-host flag to opt-in into parallel port probes This patch adds a per host flag that allows drivers to opt in into having its busses scanned in parallel. Drivers that do not set this flag get their ports scanned in the "original" sequence. Signed-off-by: Arjan van de Ven <arjan@linux.intel.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2009-01-10 07:54:07 +08:00
ata: libata: disallow dev-initiated LPM transitions to unsupported states In AHCI 1.3.1, the register description for CAP.SSC: "When cleared to ‘0’, software must not allow the HBA to initiate transitions to the Slumber state via agressive link power management nor the PxCMD.ICC field in each port, and the PxSCTL.IPM field in each port must be programmed to disallow device initiated Slumber requests." In AHCI 1.3.1, the register description for CAP.PSC: "When cleared to ‘0’, software must not allow the HBA to initiate transitions to the Partial state via agressive link power management nor the PxCMD.ICC field in each port, and the PxSCTL.IPM field in each port must be programmed to disallow device initiated Partial requests." Ensure that we always set the corresponding bits in PxSCTL.IPM, such that a device is not allowed to initiate transitions to power states which are unsupported by the HBA. DevSleep is always initiated by the HBA, however, for completeness, set the corresponding bit in PxSCTL.IPM such that agressive link power management cannot transition to DevSleep if DevSleep is not supported. sata_link_scr_lpm() is used by libahci, ata_piix and libata-pmp. However, only libahci has the ability to read the CAP/CAP2 register to see if these features are supported. Therefore, in order to not introduce any regressions on ata_piix or libata-pmp, create flags that indicate that the respective feature is NOT supported. This way, the behavior for ata_piix and libata-pmp should remain unchanged. This change is based on a patch originally submitted by Runa Guo-oc. Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com> Fixes: 1152b2617a6e ("libata: implement sata_link_scr_lpm() and make ata_dev_set_feature() global") Cc: stable@vger.kernel.org Signed-off-by: Damien Le Moal <dlemoal@kernel.org>
2023-09-05 04:42:56 +08:00
if (!(hpriv->cap & HOST_CAP_PART))
host->flags |= ATA_HOST_NO_PART;
if (!(hpriv->cap & HOST_CAP_SSC))
host->flags |= ATA_HOST_NO_SSC;
if (!(hpriv->cap2 & HOST_CAP2_SDS))
host->flags |= ATA_HOST_NO_DEVSLP;
libata/ahci: enclosure management support Add Enclosure Management support to libata and ahci. Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2008-06-04 01:33:55 +08:00
if (pi.flags & ATA_FLAG_EM)
ahci_reset_em(host);
libata: convert the remaining SATA drivers to new init model Convert ahci, sata_sil, sata_sil24, sata_svw, sata_qstor, sata_mv, sata_sx4, sata_vsc and sata_inic162x to new init model. Now that host and ap are available during intialization, functions are converted to take either host or ap instead of low level parameters which were inevitable for functions shared between init and other paths. This simplifies code quite a bit. * init_one()'s now follow more consistent init order * ahci_setup_port() and ahci_host_init() collapsed into ahci_init_one() for init order consistency * sata_vsc uses port_info instead of setting fields manually * in sata_svw, k2_board_info converted to port_info (info is now in port flags). port number is honored now. Tested on ICH7/8 AHCI, jmb360, sil3112, 3114, 3124 and 3132. Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-04-17 22:44:08 +08:00
for (i = 0; i < host->n_ports; i++) {
[libata] ahci: minor internal cleanups Minor cleanups, in preparation for merging Marvell PATA AHCI support in the future. Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-05-28 20:33:01 +08:00
struct ata_port *ap = host->ports[i];
libata: convert the remaining SATA drivers to new init model Convert ahci, sata_sil, sata_sil24, sata_svw, sata_qstor, sata_mv, sata_sx4, sata_vsc and sata_inic162x to new init model. Now that host and ap are available during intialization, functions are converted to take either host or ap instead of low level parameters which were inevitable for functions shared between init and other paths. This simplifies code quite a bit. * init_one()'s now follow more consistent init order * ahci_setup_port() and ahci_host_init() collapsed into ahci_init_one() for init order consistency * sata_vsc uses port_info instead of setting fields manually * in sata_svw, k2_board_info converted to port_info (info is now in port flags). port number is honored now. Tested on ICH7/8 AHCI, jmb360, sil3112, 3114, 3124 and 3132. Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-04-17 22:44:08 +08:00
ahci: support the STA2X11 I/O Hub The AHCI controller found in the STA2X11 chip uses BAR number 0 instead of 5. Also, the chip's fixup code sets a special DMA mask for all of its PCI functions, and the mask must be preserved here. Signed-off-by: Alessandro Rubini <rubini@gnudd.com> Acked-by: Giancarlo Asnaghi <giancarlo.asnaghi@st.com> Cc: Alan Cox <alan@linux.intel.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2012-01-06 20:33:39 +08:00
ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
ata_port_pbar_desc(ap, ahci_pci_bar,
libata: implement and use ata_port_desc() to report port configuration Currently, port configuration reporting has the following problems. * iomapped address is reported instead of raw address * report contains irrelevant fields or lacks necessary fields for non-SFF controllers. * host->irq/irq2 are there just for reporting and hacky. This patch implements and uses ata_port_desc() and ata_port_pbar_desc(). ata_port_desc() is almost identical to ata_ehi_push_desc() except that it takes @ap instead of @ehi, has no locking requirement, can only be used during host initialization and " " is used as separator instead of ", ". ata_port_pbar_desc() is a helper to ease reporting of a PCI BAR or an offsetted address into it. LLD pushes whatever description it wants using the above two functions. The accumulated description is printed on host registration after "[S/P]ATA max MAX_XFERMODE ". SFF init helpers and ata_host_activate() automatically add descriptions for addresses and irq respectively, so only LLDs which isn't standard SFF need to add custom descriptions. In many cases, such controllers need to report different things anyway. Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-08-18 12:14:55 +08:00
0x100 + ap->port_no * 0x80, "port");
libata/ahci: enclosure management support Add Enclosure Management support to libata and ahci. Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2008-06-04 01:33:55 +08:00
/* set enclosure management message type */
if (ap->flags & ATA_FLAG_EM)
ahci: EM message type auto detect Detect enclosure management message type automatically at driver initialization, instead of using module parameter "ahci_em_messages". Signed-off-by: Harry Zhang <harry.zhang@amd.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-04-23 17:27:19 +08:00
ap->em_message_type = hpriv->em_msg_type;
libata/ahci: enclosure management support Add Enclosure Management support to libata and ahci. Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2008-06-04 01:33:55 +08:00
ata: ahci: move marking of external port earlier Move the marking of an external port earlier in the call chain. This is needed for further cleanups. No functional change intended. Tested-by: Damien Le Moal <dlemoal@kernel.org> Tested-by: Jian-Hong Pan <jhp@endlessos.org> Reviewed-by: Damien Le Moal <dlemoal@kernel.org> Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Niklas Cassel <cassel@kernel.org>
2024-02-07 05:13:42 +08:00
ahci_mark_external_port(ap);
ata: ahci: drop hpriv param from ahci_update_initial_lpm_policy() There is no need for ahci_update_initial_lpm_policy() to take hpriv as a parameter, it can easily be derived from the ata_port. Tested-by: Damien Le Moal <dlemoal@kernel.org> Tested-by: Jian-Hong Pan <jhp@endlessos.org> Acked-by: Jian-Hong Pan <jhp@endlessos.org> Reviewed-by: Damien Le Moal <dlemoal@kernel.org> Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Niklas Cassel <cassel@kernel.org>
2024-02-07 05:13:44 +08:00
ahci_update_initial_lpm_policy(ap);
libata/ahci: enclosure management support Add Enclosure Management support to libata and ahci. Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2008-06-04 01:33:55 +08:00
[libata] ahci: minor internal cleanups Minor cleanups, in preparation for merging Marvell PATA AHCI support in the future. Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-05-28 20:33:01 +08:00
/* disabled/not-implemented port */
libata: don't use ap->ioaddr in non-SFF drivers ap->ioaddr is to carry addresses for TF and BMDMA registers of a SFF controller, don't abuse it in non-SFF controllers. Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-04-07 21:47:21 +08:00
if (!(hpriv->port_map & (1 << i)))
[libata] ahci: minor internal cleanups Minor cleanups, in preparation for merging Marvell PATA AHCI support in the future. Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-05-28 20:33:01 +08:00
ap->ops = &ata_dummy_port_ops;
libata: convert the remaining SATA drivers to new init model Convert ahci, sata_sil, sata_sil24, sata_svw, sata_qstor, sata_mv, sata_sx4, sata_vsc and sata_inic162x to new init model. Now that host and ap are available during intialization, functions are converted to take either host or ap instead of low level parameters which were inevitable for functions shared between init and other paths. This simplifies code quite a bit. * init_one()'s now follow more consistent init order * ahci_setup_port() and ahci_host_init() collapsed into ahci_init_one() for init order consistency * sata_vsc uses port_info instead of setting fields manually * in sata_svw, k2_board_info converted to port_info (info is now in port flags). port number is honored now. Tested on ICH7/8 AHCI, jmb360, sil3112, 3114, 3124 and 3132. Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-04-17 22:44:08 +08:00
}
ahci: implement ata_save/restore_initial_config() There are several registers which describe how the controller is configured. These registers are sometimes implemented as r/w registers which are configured by firmware and get cleared on controller reset or after suspend/resume cycle. ahci saved and restored those values inside ahci_reset_controller() which is a bit messy and doesn't work over suspend/resume cycle. This patch implements ahci_save/restore_initial_config(). The save function is called during driver initialization and saves cap and port_map to hpriv. The restore function is called after the controller is reset to restore the initial values. Sometimes the initial firmware values are inconsistent and need to be fixed up. This is handled by ahci_save_initial_config(). For this, there are two versions of saved registers. One to write back to the hardware register, the other to use during driver operation. This is necessary to keep ahci's behavior unchanged (write back fixed up port_map while keeping cap as-is). This patch makes ahci save the register values once before the first controller reset, not after it's been reset. Also, the same stored values are used written back after each reset, so the register values are properly recovered after suspend/resume cycle. Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-03-18 21:15:33 +08:00
ahci: ahci: implement workaround for ASUS P5W-DH Deluxe ahci_broken_hardreset(), take #2 P5W-DH Deluxe has ICH9 which doesn't have PMP support but SIMG 4726 hardwired to the second port of AHCI controller at PCI device 1f.2. The 4726 doesn't work as PMP but as a storage processor which can do hardware RAID on downstream ports. When no device is attached to the downstream port of the 4726, pseudo ATA device for configuration appears. Unfortunately, ATA emulation on the device is very lousy and causes long hang during boot. This patch implements workaround for the board. If the mainboard is P5W-DH Deluxe (matched using DMI), only hardreset is used on the second port of AHCI controller @ 1f.2 and the hardreset doesn't depend on receiving the first FIS and just proceed to IDENTIFY. This workaround fixes bugzilla #8923. http://bugzilla.kernel.org/show_bug.cgi?id=8923 Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-10-25 13:59:16 +08:00
/* apply workaround for ASUS P5W DH Deluxe mainboard */
ahci_p5wdh_workaround(host);
ahci: filter FPDMA non-zero offset enable for Aspire 3810T Curiously, Aspire 3810T issues many SATA feature enable commands via _GTF, of which one is invalid and another is not supported by the drive. In the process, it also enables FPDMA non-zero offset. However, the feature also needs to be supported and enabled from the controller and it's wrong to enable it from _GTF unless the controller can do it by default. Currently, this ends up enabling FPDMA non-zero offset only on the drive side leading to NCQ command failures and eventual disabling of NCQ. This patch makes libata filter out FPDMA non-zero offset enable for the machine. This was reported by Marcus Meissner in bnc#522790. https://bugzilla.novell.com/show_bug.cgi?id=522790 Reported-by: Marcus Meissner <meissner@novell.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2009-09-16 03:18:03 +08:00
/* apply gtf filter quirk */
ahci_gtf_filter_workaround(host);
libata: convert the remaining SATA drivers to new init model Convert ahci, sata_sil, sata_sil24, sata_svw, sata_qstor, sata_mv, sata_sx4, sata_vsc and sata_inic162x to new init model. Now that host and ap are available during intialization, functions are converted to take either host or ap instead of low level parameters which were inevitable for functions shared between init and other paths. This simplifies code quite a bit. * init_one()'s now follow more consistent init order * ahci_setup_port() and ahci_host_init() collapsed into ahci_init_one() for init order consistency * sata_vsc uses port_info instead of setting fields manually * in sata_svw, k2_board_info converted to port_info (info is now in port flags). port number is honored now. Tested on ICH7/8 AHCI, jmb360, sil3112, 3114, 3124 and 3132. Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-04-17 22:44:08 +08:00
/* initialize adapter */
ahci: add 43-bit DMA address quirk for ASMedia ASM1061 controllers With one of the on-board ASM1061 AHCI controllers (1b21:0612) on an ASUSTeK Pro WS WRX80E-SAGE SE WIFI mainboard, a controller hang was observed that was immediately preceded by the following kernel messages: ahci 0000:28:00.0: Using 64-bit DMA addresses ahci 0000:28:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0035 address=0x7fffff00000 flags=0x0000] ahci 0000:28:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0035 address=0x7fffff00300 flags=0x0000] ahci 0000:28:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0035 address=0x7fffff00380 flags=0x0000] ahci 0000:28:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0035 address=0x7fffff00400 flags=0x0000] ahci 0000:28:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0035 address=0x7fffff00680 flags=0x0000] ahci 0000:28:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0035 address=0x7fffff00700 flags=0x0000] The first message is produced by code in drivers/iommu/dma-iommu.c which is accompanied by the following comment that seems to apply: /* * Try to use all the 32-bit PCI addresses first. The original SAC vs. * DAC reasoning loses relevance with PCIe, but enough hardware and * firmware bugs are still lurking out there that it's safest not to * venture into the 64-bit space until necessary. * * If your device goes wrong after seeing the notice then likely either * its driver is not setting DMA masks accurately, the hardware has * some inherent bug in handling >32-bit addresses, or not all the * expected address bits are wired up between the device and the IOMMU. */ Asking the ASM1061 on a discrete PCIe card to DMA from I/O virtual address 0xffffffff00000000 produces the following I/O page faults: vfio-pci 0000:07:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0021 address=0x7ff00000000 flags=0x0010] vfio-pci 0000:07:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0021 address=0x7ff00000500 flags=0x0010] Note that the upper 21 bits of the logged DMA address are zero. (When asking a different PCIe device in the same PCIe slot to DMA to the same I/O virtual address, we do see all the upper 32 bits of the DMA address as 1, so this is not an issue with the chipset or IOMMU configuration on the test system.) Also, hacking libahci to always set the upper 21 bits of all DMA addresses to 1 produces no discernible effect on the behavior of the ASM1061, and mkfs/mount/scrub/etc work as without this hack. This all strongly suggests that the ASM1061 has a 43 bit DMA address limit, and this commit therefore adds a quirk to deal with this limit. This issue probably applies to (some of) the other supported ASMedia parts as well, but we limit it to the PCI IDs known to refer to ASM1061 parts, as that's the only part we know for sure to be affected by this issue at this point. Link: https://lore.kernel.org/linux-ide/ZaZ2PIpEId-rl6jv@wantstofly.org/ Signed-off-by: Lennert Buytenhek <kernel@wantstofly.org> [cassel: drop date from error messages in commit log] Signed-off-by: Niklas Cassel <cassel@kernel.org>
2024-01-25 23:04:01 +08:00
rc = ahci_configure_dma_masks(pdev, hpriv);
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 06:20:36 +08:00
if (rc)
libata: update libata LLDs to use devres Update libata LLDs to use devres. Core layer is already converted to support managed LLDs. This patch simplifies initialization and fixes many resource related bugs in init failure and detach path. For example, all converted drivers now handle ata_device_add() failure gracefully without excessive resource rollback code. As most resources are released automatically on driver detach, many drivers don't need or can do with much simpler ->{port|host}_stop(). In general, stop callbacks are need iff port or host needs to be given commands to shut it down. Note that freezing is enough in many cases and ports are automatically frozen before being detached. Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-01-20 15:00:28 +08:00
return rc;
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 06:20:36 +08:00
ata: ahci: Fix PCS quirk application for suspend Since kernel 5.3.4 my laptop (ICH8M controller) does not see Kingston SV300S37A60G SSD disk connected into a SATA connector on wake from suspend. The problem was introduced in c312ef176399 ("libata/ahci: Drop PCS quirk for Denverton and beyond"): the quirk is not applied on wake from suspend as it originally was. It is worth to mention the commit contained another bug: the quirk is not applied at all to controllers which require it. The fix commit 09d6ac8dc51a ("libata/ahci: Fix PCS quirk application") landed in 5.3.8. So testing my patch anywhere between commits c312ef176399 and 09d6ac8dc51a is pointless. Not all disks trigger the problem. For example nothing bad happens with Western Digital WD5000LPCX HDD. Test hardware: - Acer 5920G with ICH8M SATA controller - sda: some SATA HDD connnected into the DVD drive IDE port with a SATA-IDE caddy. It is a boot disk - sdb: Kingston SV300S37A60G SSD connected into the only SATA port Sample "dmesg --notime | grep -E '^(sd |ata)'" output on wake: sd 0:0:0:0: [sda] Starting disk sd 2:0:0:0: [sdb] Starting disk ata4: SATA link down (SStatus 4 SControl 300) ata3: SATA link down (SStatus 4 SControl 300) ata1.00: ACPI cmd ef/03:0c:00:00:00:a0 (SET FEATURES) filtered out ata1.00: ACPI cmd ef/03:42:00:00:00:a0 (SET FEATURES) filtered out ata1: FORCE: cable set to 80c ata5: SATA link down (SStatus 0 SControl 300) ata3: SATA link down (SStatus 4 SControl 300) ata3: SATA link down (SStatus 4 SControl 300) ata3.00: disabled sd 2:0:0:0: rejecting I/O to offline device ata3.00: detaching (SCSI 2:0:0:0) sd 2:0:0:0: [sdb] Start/Stop Unit failed: Result: hostbyte=DID_NO_CONNECT driverbyte=DRIVER_OK sd 2:0:0:0: [sdb] Synchronizing SCSI cache sd 2:0:0:0: [sdb] Synchronize Cache(10) failed: Result: hostbyte=DID_BAD_TARGET driverbyte=DRIVER_OK sd 2:0:0:0: [sdb] Stopping disk sd 2:0:0:0: [sdb] Start/Stop Unit failed: Result: hostbyte=DID_BAD_TARGET driverbyte=DRIVER_OK Commit c312ef176399 dropped ahci_pci_reset_controller() which internally calls ahci_reset_controller() and applies the PCS quirk if needed after that. It was called each time a reset was required instead of just ahci_reset_controller(). This patch puts the function back in place. Fixes: c312ef176399 ("libata/ahci: Drop PCS quirk for Denverton and beyond") Signed-off-by: Adam Vodopjan <grozzly@protonmail.com> Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
2022-12-09 17:26:34 +08:00
rc = ahci_pci_reset_controller(host);
libata: convert the remaining SATA drivers to new init model Convert ahci, sata_sil, sata_sil24, sata_svw, sata_qstor, sata_mv, sata_sx4, sata_vsc and sata_inic162x to new init model. Now that host and ap are available during intialization, functions are converted to take either host or ap instead of low level parameters which were inevitable for functions shared between init and other paths. This simplifies code quite a bit. * init_one()'s now follow more consistent init order * ahci_setup_port() and ahci_host_init() collapsed into ahci_init_one() for init order consistency * sata_vsc uses port_info instead of setting fields manually * in sata_svw, k2_board_info converted to port_info (info is now in port flags). port number is honored now. Tested on ICH7/8 AHCI, jmb360, sil3112, 3114, 3124 and 3132. Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-04-17 22:44:08 +08:00
if (rc)
return rc;
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 06:20:36 +08:00
ahci: Factor out PCI specifics from ahci_init_controller() Move PCI stuff into ahci_pci_init_controller(). Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-03-04 01:17:42 +08:00
ahci_pci_init_controller(host);
ahci: Factor out PCI specifics from ahci_print_info() Introduce ahci_pci_print_info() that now handles PCI stuff. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-03-04 01:17:43 +08:00
ahci_pci_print_info(host);
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 06:20:36 +08:00
libata: convert the remaining SATA drivers to new init model Convert ahci, sata_sil, sata_sil24, sata_svw, sata_qstor, sata_mv, sata_sx4, sata_vsc and sata_inic162x to new init model. Now that host and ap are available during intialization, functions are converted to take either host or ap instead of low level parameters which were inevitable for functions shared between init and other paths. This simplifies code quite a bit. * init_one()'s now follow more consistent init order * ahci_setup_port() and ahci_host_init() collapsed into ahci_init_one() for init order consistency * sata_vsc uses port_info instead of setting fields manually * in sata_svw, k2_board_info converted to port_info (info is now in port flags). port number is honored now. Tested on ICH7/8 AHCI, jmb360, sil3112, 3114, 3124 and 3132. Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-04-17 22:44:08 +08:00
pci_set_master(pdev);
AHCI: Support multiple MSIs Take advantage of multiple MSIs implementation on x86 - on systems with IRQ remapping AHCI ports not only get assigned separate MSI vectors - but also separate IRQs. As result, interrupts generated by different ports could be serviced on different CPUs rather than on a single one. In cases when number of allocated MSIs is less than requested the Sharing Last MSI mode does not get used, no matter implemented in hardware or not. Instead, the driver assumes the advantage of multiple MSIs is negated and falls back to the single MSI mode as if MRSM bit was set (some Intel chips implement this strategy anyway - MRSM bit gets set even if the number of allocated MSIs exceeds the number of implemented ports). Signed-off-by: Alexander Gordeev <agordeev@redhat.com> Acked-by: Jeff Garzik <jgarzik@redhat.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Suresh Siddha <suresh.b.siddha@intel.com> Cc: Yinghai Lu <yinghai@kernel.org> Cc: Matthew Wilcox <willy@linux.intel.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Thomas Gleixner <tglx@linutronix.de> Link: http://lkml.kernel.org/r/15bf7ee314dd55f21ec7d2a01c47613cd8190a7c.1353324359.git.agordeev@redhat.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
2012-11-19 23:02:48 +08:00
ahci: Add runtime PM support for the host controller This patch adds runtime PM support for the AHCI host controller driver so that the host controller is powered down when all SATA ports are runtime suspended. Powering down the AHCI host controller can reduce power consumption and possibly allow the CPU to enter lower power idle states (S0ix) during runtime. Runtime PM is blocked by default and needs to be unblocked from userspace as needed (via power/* sysfs nodes). Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2016-02-18 16:54:17 +08:00
rc = ahci_host_activate(host, &ahci_sht);
if (rc)
return rc;
pm_runtime_put_noidle(&pdev->dev);
return 0;
}
ata: ahci: Add shutdown to freeze hardware resources of ahci device_shutdown() called from reboot or power_shutdown expect all devices to be shutdown. Same is true for even ahci pci driver. As no ahci shutdown function is implemented, the ata subsystem always remains alive with DMA & interrupt support. File system related calls should not be honored after device_shutdown(). So defining ahci pci driver shutdown to freeze hardware (mask interrupt, stop DMA engine and free DMA resources). Signed-off-by: Prabhakar Kushwaha <pkushwaha@marvell.com> Signed-off-by: Jens Axboe <axboe@kernel.dk>
2020-01-25 11:37:29 +08:00
static void ahci_shutdown_one(struct pci_dev *pdev)
{
ata_pci_shutdown_one(pdev);
}
ahci: Add runtime PM support for the host controller This patch adds runtime PM support for the AHCI host controller driver so that the host controller is powered down when all SATA ports are runtime suspended. Powering down the AHCI host controller can reduce power consumption and possibly allow the CPU to enter lower power idle states (S0ix) during runtime. Runtime PM is blocked by default and needs to be unblocked from userspace as needed (via power/* sysfs nodes). Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2016-02-18 16:54:17 +08:00
static void ahci_remove_one(struct pci_dev *pdev)
{
ata: ahci: Add sysfs attribute to show remapped NVMe device count Add a new sysfs attribute to show how many NVMe devices are remapped. Userspace like distro installer can use this info to ask user to change the BIOS setting. Signed-off-by: Kai-Heng Feng <kai.heng.feng@canonical.com> Signed-off-by: Jens Axboe <axboe@kernel.dk>
2020-02-07 18:00:16 +08:00
sysfs_remove_file_from_group(&pdev->dev.kobj,
&dev_attr_remapped_nvme.attr,
NULL);
ahci: Add runtime PM support for the host controller This patch adds runtime PM support for the AHCI host controller driver so that the host controller is powered down when all SATA ports are runtime suspended. Powering down the AHCI host controller can reduce power consumption and possibly allow the CPU to enter lower power idle states (S0ix) during runtime. Runtime PM is blocked by default and needs to be unblocked from userspace as needed (via power/* sysfs nodes). Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2016-02-18 16:54:17 +08:00
pm_runtime_get_noresume(&pdev->dev);
ata_pci_remove_one(pdev);
[libata ahci] support PCI MSI interrupt vector
2005-05-13 03:03:42 +08:00
}
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 06:20:36 +08:00
ata: use module_pci_driver This patch converts the drivers in drivers/ata/* to use module_pci_driver() macro which makes the code smaller and a bit simpler. Signed-off-by: Axel Lin <axel.lin@gmail.com> Cc: Alan Cox <alan@linux.intel.com> Cc: Jeff Garzik <jgarzik@pobox.com> Cc: Mikael Pettersson <mikpe@it.uu.se> Cc: Mark Lord <kernel@teksavvy.com> Cc: Jeremy Higdon <jeremy@sgi.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2012-04-19 13:43:05 +08:00
module_pci_driver(ahci_pci_driver);
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 06:20:36 +08:00
MODULE_AUTHOR("Jeff Garzik");
MODULE_DESCRIPTION("AHCI SATA low-level driver");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
libata: release prep (bump versions, etc.) - bump versions where necessary - remove two duplicated+outdated doc comments - add MODULE_VERSION() to AHCI driver
2005-08-23 14:53:51 +08:00
MODULE_VERSION(DRV_VERSION);
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