2015-07-31 03:17:43 +08:00
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/*
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IB/{hfi1, rdmavt, qib}: Implement CQ completion vector support
Currently the driver doesn't support completion vectors. These
are used to indicate which sets of CQs should be grouped together
into the same vector. A vector is a CQ processing thread that
runs on a specific CPU.
If an application has several CQs bound to different completion
vectors, and each completion vector runs on different CPUs, then
the completion queue workload is balanced. This helps scale as more
nodes are used.
Implement CQ completion vector support using a global workqueue
where a CQ entry is queued to the CPU corresponding to the CQ's
completion vector. Since the workqueue is global, it's guaranteed
to always be there when queueing CQ entries; Therefore, the RCU
locking for cq->rdi->worker in the hot path is superfluous.
Each completion vector is assigned to a different CPU. The number of
completion vectors available is computed by taking the number of
online, physical CPUs from the local NUMA node and subtracting the
CPUs used for kernel receive queues and the general interrupt.
Special use cases:
* If there are no CPUs left for completion vectors, the same CPU
for the general interrupt is used; Therefore, there would only
be one completion vector available.
* For multi-HFI systems, the number of completion vectors available
for each device is the total number of completion vectors in
the local NUMA node divided by the number of devices in the same
NUMA node. If there's a division remainder, the first device to
get initialized gets an extra completion vector.
Upon a CQ creation, an invalid completion vector could be specified.
Handle it as follows:
* If the completion vector is less than 0, set it to 0.
* Set the completion vector to the result of the passed completion
vector moded with the number of device completion vectors
available.
Reviewed-by: Mike Marciniszyn <mike.marciniszyn@intel.com>
Signed-off-by: Sebastian Sanchez <sebastian.sanchez@intel.com>
Signed-off-by: Dennis Dalessandro <dennis.dalessandro@intel.com>
Signed-off-by: Doug Ledford <dledford@redhat.com>
2018-05-02 21:43:55 +08:00
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* Copyright(c) 2015 - 2018 Intel Corporation.
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2015-07-31 03:17:43 +08:00
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*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* GPL LICENSE SUMMARY
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* BSD LICENSE
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* - Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* - Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* - Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#define CREATE_TRACE_POINTS
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#include "trace.h"
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2019-01-24 11:30:28 +08:00
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#include "exp_rcv.h"
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2015-07-31 03:17:43 +08:00
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2017-08-05 04:54:29 +08:00
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static u8 __get_ib_hdr_len(struct ib_header *hdr)
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2015-07-31 03:17:43 +08:00
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{
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2016-09-06 19:35:05 +08:00
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struct ib_other_headers *ohdr;
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2015-07-31 03:17:43 +08:00
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u8 opcode;
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2017-04-10 01:16:22 +08:00
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if (ib_get_lnh(hdr) == HFI1_LRH_BTH)
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2015-07-31 03:17:43 +08:00
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ohdr = &hdr->u.oth;
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else
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ohdr = &hdr->u.l.oth;
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2017-04-10 01:16:22 +08:00
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opcode = ib_bth_get_opcode(ohdr);
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2015-07-31 03:17:43 +08:00
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return hdr_len_by_opcode[opcode] == 0 ?
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0 : hdr_len_by_opcode[opcode] - (12 + 8);
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}
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2017-08-05 04:54:29 +08:00
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static u8 __get_16b_hdr_len(struct hfi1_16b_header *hdr)
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{
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2018-05-16 09:28:22 +08:00
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struct ib_other_headers *ohdr = NULL;
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2017-08-05 04:54:29 +08:00
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u8 opcode;
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2018-05-16 09:28:22 +08:00
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u8 l4 = hfi1_16B_get_l4(hdr);
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if (l4 == OPA_16B_L4_FM) {
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opcode = IB_OPCODE_UD_SEND_ONLY;
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return (8 + 8); /* No BTH */
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}
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2017-08-05 04:54:29 +08:00
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2018-05-16 09:28:22 +08:00
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if (l4 == OPA_16B_L4_IB_LOCAL)
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2017-08-05 04:54:29 +08:00
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ohdr = &hdr->u.oth;
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else
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ohdr = &hdr->u.l.oth;
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2018-05-16 09:28:22 +08:00
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2017-08-05 04:54:29 +08:00
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opcode = ib_bth_get_opcode(ohdr);
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return hdr_len_by_opcode[opcode] == 0 ?
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0 : hdr_len_by_opcode[opcode] - (12 + 8 + 8);
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}
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u8 hfi1_trace_packet_hdr_len(struct hfi1_packet *packet)
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{
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if (packet->etype != RHF_RCV_TYPE_BYPASS)
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return __get_ib_hdr_len(packet->hdr);
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else
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return __get_16b_hdr_len(packet->hdr);
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}
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u8 hfi1_trace_opa_hdr_len(struct hfi1_opa_header *opa_hdr)
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{
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if (!opa_hdr->hdr_type)
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return __get_ib_hdr_len(&opa_hdr->ibh);
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else
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return __get_16b_hdr_len(&opa_hdr->opah);
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}
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2017-09-26 22:01:09 +08:00
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const char *hfi1_trace_get_packet_l4_str(u8 l4)
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2017-05-13 00:20:08 +08:00
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{
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2017-09-26 22:01:09 +08:00
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if (l4)
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return "16B";
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else
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return "9B";
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}
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2017-08-05 04:54:29 +08:00
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2017-09-26 22:01:09 +08:00
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const char *hfi1_trace_get_packet_l2_str(u8 l2)
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{
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switch (l2) {
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2017-08-05 04:54:29 +08:00
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case 0:
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return "0";
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case 1:
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return "1";
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case 2:
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return "16B";
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case 3:
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return "9B";
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}
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return "";
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}
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2017-05-13 00:20:08 +08:00
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#define IMM_PRN "imm:%d"
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#define RETH_PRN "reth vaddr:0x%.16llx rkey:0x%.8x dlen:0x%.8x"
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#define AETH_PRN "aeth syn:0x%.2x %s msn:0x%.8x"
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#define DETH_PRN "deth qkey:0x%.8x sqpn:0x%.6x"
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#define IETH_PRN "ieth rkey:0x%.8x"
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#define ATOMICACKETH_PRN "origdata:%llx"
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#define ATOMICETH_PRN "vaddr:0x%llx rkey:0x%.8x sdata:%llx cdata:%llx"
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2019-01-24 11:32:44 +08:00
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#define TID_RDMA_KDETH "kdeth0 0x%x kdeth1 0x%x"
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#define TID_RDMA_KDETH_DATA "kdeth0 0x%x: kver %u sh %u intr %u tidctrl %u tid %x offset %x kdeth1 0x%x: jkey %x"
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#define TID_READ_REQ_PRN "tid_flow_psn 0x%x tid_flow_qp 0x%x verbs_qp 0x%x"
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#define TID_READ_RSP_PRN "verbs_qp 0x%x"
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2019-01-24 13:52:09 +08:00
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#define TID_WRITE_REQ_PRN "original_qp 0x%x"
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#define TID_WRITE_RSP_PRN "tid_flow_psn 0x%x tid_flow_qp 0x%x verbs_qp 0x%x"
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#define TID_WRITE_DATA_PRN "verbs_qp 0x%x"
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#define TID_ACK_PRN "tid_flow_psn 0x%x verbs_psn 0x%x tid_flow_qp 0x%x verbs_qp 0x%x"
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#define TID_RESYNC_PRN "verbs_qp 0x%x"
|
2015-07-31 03:17:43 +08:00
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#define OP(transport, op) IB_OPCODE_## transport ## _ ## op
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2015-12-02 04:38:12 +08:00
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static const char *parse_syndrome(u8 syndrome)
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{
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switch (syndrome >> 5) {
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case 0:
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return "ACK";
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case 1:
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return "RNRNAK";
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case 3:
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return "NAK";
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}
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return "";
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}
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2017-08-05 04:54:29 +08:00
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void hfi1_trace_parse_9b_bth(struct ib_other_headers *ohdr,
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2018-02-02 02:46:38 +08:00
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u8 *ack, bool *becn, bool *fecn, u8 *mig,
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2017-08-05 04:54:29 +08:00
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u8 *se, u8 *pad, u8 *opcode, u8 *tver,
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u16 *pkey, u32 *psn, u32 *qpn)
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2017-05-13 00:20:08 +08:00
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{
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*ack = ib_bth_get_ackreq(ohdr);
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*becn = ib_bth_get_becn(ohdr);
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*fecn = ib_bth_get_fecn(ohdr);
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*mig = ib_bth_get_migreq(ohdr);
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*se = ib_bth_get_se(ohdr);
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*pad = ib_bth_get_pad(ohdr);
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*opcode = ib_bth_get_opcode(ohdr);
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*tver = ib_bth_get_tver(ohdr);
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*pkey = ib_bth_get_pkey(ohdr);
|
2017-10-10 03:38:12 +08:00
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*psn = mask_psn(ib_bth_get_psn(ohdr));
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2017-05-13 00:20:08 +08:00
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*qpn = ib_bth_get_qpn(ohdr);
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}
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2017-08-05 04:54:29 +08:00
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void hfi1_trace_parse_16b_bth(struct ib_other_headers *ohdr,
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u8 *ack, u8 *mig, u8 *opcode,
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u8 *pad, u8 *se, u8 *tver,
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u32 *psn, u32 *qpn)
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{
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*ack = ib_bth_get_ackreq(ohdr);
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*mig = ib_bth_get_migreq(ohdr);
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*opcode = ib_bth_get_opcode(ohdr);
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*pad = ib_bth_get_pad(ohdr);
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*se = ib_bth_get_se(ohdr);
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*tver = ib_bth_get_tver(ohdr);
|
2017-10-10 03:38:12 +08:00
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*psn = mask_psn(ib_bth_get_psn(ohdr));
|
2017-08-05 04:54:29 +08:00
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*qpn = ib_bth_get_qpn(ohdr);
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}
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|
2017-05-13 00:20:08 +08:00
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void hfi1_trace_parse_9b_hdr(struct ib_header *hdr, bool sc5,
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u8 *lnh, u8 *lver, u8 *sl, u8 *sc,
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u16 *len, u32 *dlid, u32 *slid)
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{
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*lnh = ib_get_lnh(hdr);
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*lver = ib_get_lver(hdr);
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*sl = ib_get_sl(hdr);
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*sc = ib_get_sc(hdr) | (sc5 << 4);
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*len = ib_get_len(hdr);
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*dlid = ib_get_dlid(hdr);
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*slid = ib_get_slid(hdr);
|
2017-08-05 04:54:29 +08:00
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}
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void hfi1_trace_parse_16b_hdr(struct hfi1_16b_header *hdr,
|
2018-02-02 02:46:38 +08:00
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u8 *age, bool *becn, bool *fecn,
|
2017-08-05 04:54:29 +08:00
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u8 *l4, u8 *rc, u8 *sc,
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u16 *entropy, u16 *len, u16 *pkey,
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u32 *dlid, u32 *slid)
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{
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*age = hfi1_16B_get_age(hdr);
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*becn = hfi1_16B_get_becn(hdr);
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*fecn = hfi1_16B_get_fecn(hdr);
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*l4 = hfi1_16B_get_l4(hdr);
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*rc = hfi1_16B_get_rc(hdr);
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*sc = hfi1_16B_get_sc(hdr);
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*entropy = hfi1_16B_get_entropy(hdr);
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*len = hfi1_16B_get_len(hdr);
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*pkey = hfi1_16B_get_pkey(hdr);
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*dlid = hfi1_16B_get_dlid(hdr);
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*slid = hfi1_16B_get_slid(hdr);
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}
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#define LRH_PRN "len:%d sc:%d dlid:0x%.4x slid:0x%.4x "
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#define LRH_9B_PRN "lnh:%d,%s lver:%d sl:%d"
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#define LRH_16B_PRN "age:%d becn:%d fecn:%d l4:%d " \
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"rc:%d sc:%d pkey:0x%.4x entropy:0x%.4x"
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|
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|
|
const char *hfi1_trace_fmt_lrh(struct trace_seq *p, bool bypass,
|
2018-02-02 02:46:38 +08:00
|
|
|
u8 age, bool becn, bool fecn, u8 l4,
|
2017-08-05 04:54:29 +08:00
|
|
|
u8 lnh, const char *lnh_name, u8 lver,
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|
|
u8 rc, u8 sc, u8 sl, u16 entropy,
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|
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u16 len, u16 pkey, u32 dlid, u32 slid)
|
|
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|
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{
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|
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|
|
const char *ret = trace_seq_buffer_ptr(p);
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|
|
trace_seq_printf(p, LRH_PRN, len, sc, dlid, slid);
|
|
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|
|
if (bypass)
|
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|
|
trace_seq_printf(p, LRH_16B_PRN,
|
|
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|
|
age, becn, fecn, l4, rc, sc, pkey, entropy);
|
|
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else
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|
|
trace_seq_printf(p, LRH_9B_PRN,
|
|
|
|
|
lnh, lnh_name, lver, sl);
|
|
|
|
|
trace_seq_putc(p, 0);
|
|
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|
return ret;
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}
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|
|
#define BTH_9B_PRN \
|
|
|
|
|
"op:0x%.2x,%s se:%d m:%d pad:%d tver:%d pkey:0x%.4x " \
|
|
|
|
|
"f:%d b:%d qpn:0x%.6x a:%d psn:0x%.8x"
|
|
|
|
|
#define BTH_16B_PRN \
|
|
|
|
|
"op:0x%.2x,%s se:%d m:%d pad:%d tver:%d " \
|
|
|
|
|
"qpn:0x%.6x a:%d psn:0x%.8x"
|
2018-05-16 09:28:22 +08:00
|
|
|
#define L4_FM_16B_PRN \
|
|
|
|
|
"op:0x%.2x,%s dest_qpn:0x%.6x src_qpn:0x%.6x"
|
|
|
|
|
const char *hfi1_trace_fmt_rest(struct trace_seq *p, bool bypass, u8 l4,
|
|
|
|
|
u8 ack, bool becn, bool fecn, u8 mig,
|
|
|
|
|
u8 se, u8 pad, u8 opcode, const char *opname,
|
|
|
|
|
u8 tver, u16 pkey, u32 psn, u32 qpn,
|
|
|
|
|
u32 dest_qpn, u32 src_qpn)
|
2017-08-05 04:54:29 +08:00
|
|
|
{
|
|
|
|
|
const char *ret = trace_seq_buffer_ptr(p);
|
|
|
|
|
|
|
|
|
|
if (bypass)
|
2018-05-16 09:28:22 +08:00
|
|
|
if (l4 == OPA_16B_L4_FM)
|
|
|
|
|
trace_seq_printf(p, L4_FM_16B_PRN,
|
|
|
|
|
opcode, opname, dest_qpn, src_qpn);
|
|
|
|
|
else
|
|
|
|
|
trace_seq_printf(p, BTH_16B_PRN,
|
|
|
|
|
opcode, opname,
|
|
|
|
|
se, mig, pad, tver, qpn, ack, psn);
|
2017-05-13 00:20:08 +08:00
|
|
|
|
|
|
|
|
else
|
2017-08-05 04:54:29 +08:00
|
|
|
trace_seq_printf(p, BTH_9B_PRN,
|
|
|
|
|
opcode, opname,
|
|
|
|
|
se, mig, pad, tver, pkey, fecn, becn,
|
|
|
|
|
qpn, ack, psn);
|
|
|
|
|
trace_seq_putc(p, 0);
|
|
|
|
|
|
|
|
|
|
return ret;
|
2017-05-13 00:20:08 +08:00
|
|
|
}
|
|
|
|
|
|
2015-07-31 03:17:43 +08:00
|
|
|
const char *parse_everbs_hdrs(
|
|
|
|
|
struct trace_seq *p,
|
2018-05-16 09:28:22 +08:00
|
|
|
u8 opcode, u8 l4, u32 dest_qpn, u32 src_qpn,
|
2015-07-31 03:17:43 +08:00
|
|
|
void *ehdrs)
|
|
|
|
|
{
|
|
|
|
|
union ib_ehdrs *eh = ehdrs;
|
|
|
|
|
const char *ret = trace_seq_buffer_ptr(p);
|
|
|
|
|
|
2018-05-16 09:28:22 +08:00
|
|
|
if (l4 == OPA_16B_L4_FM) {
|
|
|
|
|
trace_seq_printf(p, "mgmt pkt");
|
|
|
|
|
goto out;
|
|
|
|
|
}
|
|
|
|
|
|
2015-07-31 03:17:43 +08:00
|
|
|
switch (opcode) {
|
|
|
|
|
/* imm */
|
|
|
|
|
case OP(RC, SEND_LAST_WITH_IMMEDIATE):
|
|
|
|
|
case OP(UC, SEND_LAST_WITH_IMMEDIATE):
|
|
|
|
|
case OP(RC, SEND_ONLY_WITH_IMMEDIATE):
|
|
|
|
|
case OP(UC, SEND_ONLY_WITH_IMMEDIATE):
|
|
|
|
|
case OP(RC, RDMA_WRITE_LAST_WITH_IMMEDIATE):
|
|
|
|
|
case OP(UC, RDMA_WRITE_LAST_WITH_IMMEDIATE):
|
|
|
|
|
trace_seq_printf(p, IMM_PRN,
|
2016-02-15 12:21:52 +08:00
|
|
|
be32_to_cpu(eh->imm_data));
|
2015-07-31 03:17:43 +08:00
|
|
|
break;
|
|
|
|
|
/* reth + imm */
|
|
|
|
|
case OP(RC, RDMA_WRITE_ONLY_WITH_IMMEDIATE):
|
|
|
|
|
case OP(UC, RDMA_WRITE_ONLY_WITH_IMMEDIATE):
|
|
|
|
|
trace_seq_printf(p, RETH_PRN " " IMM_PRN,
|
2016-09-06 19:35:05 +08:00
|
|
|
get_ib_reth_vaddr(&eh->rc.reth),
|
2016-02-15 12:21:52 +08:00
|
|
|
be32_to_cpu(eh->rc.reth.rkey),
|
|
|
|
|
be32_to_cpu(eh->rc.reth.length),
|
|
|
|
|
be32_to_cpu(eh->rc.imm_data));
|
2015-07-31 03:17:43 +08:00
|
|
|
break;
|
|
|
|
|
/* reth */
|
|
|
|
|
case OP(RC, RDMA_READ_REQUEST):
|
|
|
|
|
case OP(RC, RDMA_WRITE_FIRST):
|
|
|
|
|
case OP(UC, RDMA_WRITE_FIRST):
|
|
|
|
|
case OP(RC, RDMA_WRITE_ONLY):
|
|
|
|
|
case OP(UC, RDMA_WRITE_ONLY):
|
|
|
|
|
trace_seq_printf(p, RETH_PRN,
|
2016-09-06 19:35:05 +08:00
|
|
|
get_ib_reth_vaddr(&eh->rc.reth),
|
2016-02-15 12:21:52 +08:00
|
|
|
be32_to_cpu(eh->rc.reth.rkey),
|
|
|
|
|
be32_to_cpu(eh->rc.reth.length));
|
2015-07-31 03:17:43 +08:00
|
|
|
break;
|
|
|
|
|
case OP(RC, RDMA_READ_RESPONSE_FIRST):
|
|
|
|
|
case OP(RC, RDMA_READ_RESPONSE_LAST):
|
|
|
|
|
case OP(RC, RDMA_READ_RESPONSE_ONLY):
|
|
|
|
|
case OP(RC, ACKNOWLEDGE):
|
2015-12-02 04:38:12 +08:00
|
|
|
trace_seq_printf(p, AETH_PRN, be32_to_cpu(eh->aeth) >> 24,
|
|
|
|
|
parse_syndrome(be32_to_cpu(eh->aeth) >> 24),
|
2017-02-08 21:28:25 +08:00
|
|
|
be32_to_cpu(eh->aeth) & IB_MSN_MASK);
|
2015-07-31 03:17:43 +08:00
|
|
|
break;
|
2019-01-24 13:52:09 +08:00
|
|
|
case OP(TID_RDMA, WRITE_REQ):
|
|
|
|
|
trace_seq_printf(p, TID_RDMA_KDETH " " RETH_PRN " "
|
|
|
|
|
TID_WRITE_REQ_PRN,
|
|
|
|
|
le32_to_cpu(eh->tid_rdma.w_req.kdeth0),
|
|
|
|
|
le32_to_cpu(eh->tid_rdma.w_req.kdeth1),
|
|
|
|
|
ib_u64_get(&eh->tid_rdma.w_req.reth.vaddr),
|
|
|
|
|
be32_to_cpu(eh->tid_rdma.w_req.reth.rkey),
|
|
|
|
|
be32_to_cpu(eh->tid_rdma.w_req.reth.length),
|
|
|
|
|
be32_to_cpu(eh->tid_rdma.w_req.verbs_qp));
|
|
|
|
|
break;
|
|
|
|
|
case OP(TID_RDMA, WRITE_RESP):
|
|
|
|
|
trace_seq_printf(p, TID_RDMA_KDETH " " AETH_PRN " "
|
|
|
|
|
TID_WRITE_RSP_PRN,
|
|
|
|
|
le32_to_cpu(eh->tid_rdma.w_rsp.kdeth0),
|
|
|
|
|
le32_to_cpu(eh->tid_rdma.w_rsp.kdeth1),
|
|
|
|
|
be32_to_cpu(eh->tid_rdma.w_rsp.aeth) >> 24,
|
|
|
|
|
parse_syndrome(/* aeth */
|
|
|
|
|
be32_to_cpu(eh->tid_rdma.w_rsp.aeth)
|
|
|
|
|
>> 24),
|
|
|
|
|
(be32_to_cpu(eh->tid_rdma.w_rsp.aeth) &
|
|
|
|
|
IB_MSN_MASK),
|
|
|
|
|
be32_to_cpu(eh->tid_rdma.w_rsp.tid_flow_psn),
|
|
|
|
|
be32_to_cpu(eh->tid_rdma.w_rsp.tid_flow_qp),
|
|
|
|
|
be32_to_cpu(eh->tid_rdma.w_rsp.verbs_qp));
|
|
|
|
|
break;
|
|
|
|
|
case OP(TID_RDMA, WRITE_DATA_LAST):
|
|
|
|
|
case OP(TID_RDMA, WRITE_DATA):
|
|
|
|
|
trace_seq_printf(p, TID_RDMA_KDETH_DATA " " TID_WRITE_DATA_PRN,
|
|
|
|
|
le32_to_cpu(eh->tid_rdma.w_data.kdeth0),
|
|
|
|
|
KDETH_GET(eh->tid_rdma.w_data.kdeth0, KVER),
|
|
|
|
|
KDETH_GET(eh->tid_rdma.w_data.kdeth0, SH),
|
|
|
|
|
KDETH_GET(eh->tid_rdma.w_data.kdeth0, INTR),
|
|
|
|
|
KDETH_GET(eh->tid_rdma.w_data.kdeth0, TIDCTRL),
|
|
|
|
|
KDETH_GET(eh->tid_rdma.w_data.kdeth0, TID),
|
|
|
|
|
KDETH_GET(eh->tid_rdma.w_data.kdeth0, OFFSET),
|
|
|
|
|
le32_to_cpu(eh->tid_rdma.w_data.kdeth1),
|
|
|
|
|
KDETH_GET(eh->tid_rdma.w_data.kdeth1, JKEY),
|
|
|
|
|
be32_to_cpu(eh->tid_rdma.w_data.verbs_qp));
|
|
|
|
|
break;
|
2019-01-24 11:32:44 +08:00
|
|
|
case OP(TID_RDMA, READ_REQ):
|
|
|
|
|
trace_seq_printf(p, TID_RDMA_KDETH " " RETH_PRN " "
|
|
|
|
|
TID_READ_REQ_PRN,
|
|
|
|
|
le32_to_cpu(eh->tid_rdma.r_req.kdeth0),
|
|
|
|
|
le32_to_cpu(eh->tid_rdma.r_req.kdeth1),
|
|
|
|
|
ib_u64_get(&eh->tid_rdma.r_req.reth.vaddr),
|
|
|
|
|
be32_to_cpu(eh->tid_rdma.r_req.reth.rkey),
|
|
|
|
|
be32_to_cpu(eh->tid_rdma.r_req.reth.length),
|
|
|
|
|
be32_to_cpu(eh->tid_rdma.r_req.tid_flow_psn),
|
|
|
|
|
be32_to_cpu(eh->tid_rdma.r_req.tid_flow_qp),
|
|
|
|
|
be32_to_cpu(eh->tid_rdma.r_req.verbs_qp));
|
|
|
|
|
break;
|
|
|
|
|
case OP(TID_RDMA, READ_RESP):
|
|
|
|
|
trace_seq_printf(p, TID_RDMA_KDETH_DATA " " AETH_PRN " "
|
|
|
|
|
TID_READ_RSP_PRN,
|
|
|
|
|
le32_to_cpu(eh->tid_rdma.r_rsp.kdeth0),
|
|
|
|
|
KDETH_GET(eh->tid_rdma.r_rsp.kdeth0, KVER),
|
|
|
|
|
KDETH_GET(eh->tid_rdma.r_rsp.kdeth0, SH),
|
|
|
|
|
KDETH_GET(eh->tid_rdma.r_rsp.kdeth0, INTR),
|
|
|
|
|
KDETH_GET(eh->tid_rdma.r_rsp.kdeth0, TIDCTRL),
|
|
|
|
|
KDETH_GET(eh->tid_rdma.r_rsp.kdeth0, TID),
|
|
|
|
|
KDETH_GET(eh->tid_rdma.r_rsp.kdeth0, OFFSET),
|
|
|
|
|
le32_to_cpu(eh->tid_rdma.r_rsp.kdeth1),
|
|
|
|
|
KDETH_GET(eh->tid_rdma.r_rsp.kdeth1, JKEY),
|
|
|
|
|
be32_to_cpu(eh->tid_rdma.r_rsp.aeth) >> 24,
|
|
|
|
|
parse_syndrome(/* aeth */
|
|
|
|
|
be32_to_cpu(eh->tid_rdma.r_rsp.aeth)
|
|
|
|
|
>> 24),
|
|
|
|
|
(be32_to_cpu(eh->tid_rdma.r_rsp.aeth) &
|
|
|
|
|
IB_MSN_MASK),
|
|
|
|
|
be32_to_cpu(eh->tid_rdma.r_rsp.verbs_qp));
|
|
|
|
|
break;
|
2019-01-24 13:52:09 +08:00
|
|
|
case OP(TID_RDMA, ACK):
|
|
|
|
|
trace_seq_printf(p, TID_RDMA_KDETH " " AETH_PRN " "
|
|
|
|
|
TID_ACK_PRN,
|
|
|
|
|
le32_to_cpu(eh->tid_rdma.ack.kdeth0),
|
|
|
|
|
le32_to_cpu(eh->tid_rdma.ack.kdeth1),
|
|
|
|
|
be32_to_cpu(eh->tid_rdma.ack.aeth) >> 24,
|
|
|
|
|
parse_syndrome(/* aeth */
|
|
|
|
|
be32_to_cpu(eh->tid_rdma.ack.aeth)
|
|
|
|
|
>> 24),
|
|
|
|
|
(be32_to_cpu(eh->tid_rdma.ack.aeth) &
|
|
|
|
|
IB_MSN_MASK),
|
|
|
|
|
be32_to_cpu(eh->tid_rdma.ack.tid_flow_psn),
|
|
|
|
|
be32_to_cpu(eh->tid_rdma.ack.verbs_psn),
|
|
|
|
|
be32_to_cpu(eh->tid_rdma.ack.tid_flow_qp),
|
|
|
|
|
be32_to_cpu(eh->tid_rdma.ack.verbs_qp));
|
|
|
|
|
break;
|
|
|
|
|
case OP(TID_RDMA, RESYNC):
|
|
|
|
|
trace_seq_printf(p, TID_RDMA_KDETH " " TID_RESYNC_PRN,
|
|
|
|
|
le32_to_cpu(eh->tid_rdma.resync.kdeth0),
|
|
|
|
|
le32_to_cpu(eh->tid_rdma.resync.kdeth1),
|
|
|
|
|
be32_to_cpu(eh->tid_rdma.resync.verbs_qp));
|
|
|
|
|
break;
|
2015-07-31 03:17:43 +08:00
|
|
|
/* aeth + atomicacketh */
|
|
|
|
|
case OP(RC, ATOMIC_ACKNOWLEDGE):
|
|
|
|
|
trace_seq_printf(p, AETH_PRN " " ATOMICACKETH_PRN,
|
2015-12-02 04:38:12 +08:00
|
|
|
be32_to_cpu(eh->at.aeth) >> 24,
|
|
|
|
|
parse_syndrome(be32_to_cpu(eh->at.aeth) >> 24),
|
2017-02-08 21:28:25 +08:00
|
|
|
be32_to_cpu(eh->at.aeth) & IB_MSN_MASK,
|
2016-09-06 19:35:05 +08:00
|
|
|
ib_u64_get(&eh->at.atomic_ack_eth));
|
2015-07-31 03:17:43 +08:00
|
|
|
break;
|
|
|
|
|
/* atomiceth */
|
|
|
|
|
case OP(RC, COMPARE_SWAP):
|
|
|
|
|
case OP(RC, FETCH_ADD):
|
|
|
|
|
trace_seq_printf(p, ATOMICETH_PRN,
|
2016-09-06 19:35:05 +08:00
|
|
|
get_ib_ateth_vaddr(&eh->atomic_eth),
|
2016-02-15 12:21:52 +08:00
|
|
|
eh->atomic_eth.rkey,
|
2016-09-06 19:35:05 +08:00
|
|
|
get_ib_ateth_swap(&eh->atomic_eth),
|
|
|
|
|
get_ib_ateth_compare(&eh->atomic_eth));
|
2015-07-31 03:17:43 +08:00
|
|
|
break;
|
|
|
|
|
/* deth */
|
|
|
|
|
case OP(UD, SEND_ONLY):
|
|
|
|
|
case OP(UD, SEND_ONLY_WITH_IMMEDIATE):
|
|
|
|
|
trace_seq_printf(p, DETH_PRN,
|
2016-02-15 12:21:52 +08:00
|
|
|
be32_to_cpu(eh->ud.deth[0]),
|
|
|
|
|
be32_to_cpu(eh->ud.deth[1]) & RVT_QPN_MASK);
|
2015-07-31 03:17:43 +08:00
|
|
|
break;
|
2016-05-25 03:50:17 +08:00
|
|
|
/* ieth */
|
|
|
|
|
case OP(RC, SEND_LAST_WITH_INVALIDATE):
|
|
|
|
|
case OP(RC, SEND_ONLY_WITH_INVALIDATE):
|
|
|
|
|
trace_seq_printf(p, IETH_PRN,
|
|
|
|
|
be32_to_cpu(eh->ieth));
|
|
|
|
|
break;
|
2015-07-31 03:17:43 +08:00
|
|
|
}
|
2018-05-16 09:28:22 +08:00
|
|
|
out:
|
2015-07-31 03:17:43 +08:00
|
|
|
trace_seq_putc(p, 0);
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
const char *parse_sdma_flags(
|
|
|
|
|
struct trace_seq *p,
|
|
|
|
|
u64 desc0, u64 desc1)
|
|
|
|
|
{
|
|
|
|
|
const char *ret = trace_seq_buffer_ptr(p);
|
|
|
|
|
char flags[5] = { 'x', 'x', 'x', 'x', 0 };
|
|
|
|
|
|
|
|
|
|
flags[0] = (desc1 & SDMA_DESC1_INT_REQ_FLAG) ? 'I' : '-';
|
|
|
|
|
flags[1] = (desc1 & SDMA_DESC1_HEAD_TO_HOST_FLAG) ? 'H' : '-';
|
|
|
|
|
flags[2] = (desc0 & SDMA_DESC0_FIRST_DESC_FLAG) ? 'F' : '-';
|
|
|
|
|
flags[3] = (desc0 & SDMA_DESC0_LAST_DESC_FLAG) ? 'L' : '-';
|
|
|
|
|
trace_seq_printf(p, "%s", flags);
|
|
|
|
|
if (desc0 & SDMA_DESC0_FIRST_DESC_FLAG)
|
|
|
|
|
trace_seq_printf(p, " amode:%u aidx:%u alen:%u",
|
2016-02-15 12:21:52 +08:00
|
|
|
(u8)((desc1 >> SDMA_DESC1_HEADER_MODE_SHIFT) &
|
|
|
|
|
SDMA_DESC1_HEADER_MODE_MASK),
|
|
|
|
|
(u8)((desc1 >> SDMA_DESC1_HEADER_INDEX_SHIFT) &
|
|
|
|
|
SDMA_DESC1_HEADER_INDEX_MASK),
|
|
|
|
|
(u8)((desc1 >> SDMA_DESC1_HEADER_DWS_SHIFT) &
|
|
|
|
|
SDMA_DESC1_HEADER_DWS_MASK));
|
2015-07-31 03:17:43 +08:00
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
const char *print_u32_array(
|
|
|
|
|
struct trace_seq *p,
|
|
|
|
|
u32 *arr, int len)
|
|
|
|
|
{
|
|
|
|
|
int i;
|
|
|
|
|
const char *ret = trace_seq_buffer_ptr(p);
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < len ; i++)
|
|
|
|
|
trace_seq_printf(p, "%s%#x", i == 0 ? "" : " ", arr[i]);
|
|
|
|
|
trace_seq_putc(p, 0);
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
2019-01-24 11:30:28 +08:00
|
|
|
u8 hfi1_trace_get_tid_ctrl(u32 ent)
|
|
|
|
|
{
|
|
|
|
|
return EXP_TID_GET(ent, CTRL);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
u16 hfi1_trace_get_tid_len(u32 ent)
|
|
|
|
|
{
|
|
|
|
|
return EXP_TID_GET(ent, LEN);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
u16 hfi1_trace_get_tid_idx(u32 ent)
|
|
|
|
|
{
|
|
|
|
|
return EXP_TID_GET(ent, IDX);
|
|
|
|
|
}
|
|
|
|
|
|
IB/{hfi1, rdmavt, qib}: Implement CQ completion vector support
Currently the driver doesn't support completion vectors. These
are used to indicate which sets of CQs should be grouped together
into the same vector. A vector is a CQ processing thread that
runs on a specific CPU.
If an application has several CQs bound to different completion
vectors, and each completion vector runs on different CPUs, then
the completion queue workload is balanced. This helps scale as more
nodes are used.
Implement CQ completion vector support using a global workqueue
where a CQ entry is queued to the CPU corresponding to the CQ's
completion vector. Since the workqueue is global, it's guaranteed
to always be there when queueing CQ entries; Therefore, the RCU
locking for cq->rdi->worker in the hot path is superfluous.
Each completion vector is assigned to a different CPU. The number of
completion vectors available is computed by taking the number of
online, physical CPUs from the local NUMA node and subtracting the
CPUs used for kernel receive queues and the general interrupt.
Special use cases:
* If there are no CPUs left for completion vectors, the same CPU
for the general interrupt is used; Therefore, there would only
be one completion vector available.
* For multi-HFI systems, the number of completion vectors available
for each device is the total number of completion vectors in
the local NUMA node divided by the number of devices in the same
NUMA node. If there's a division remainder, the first device to
get initialized gets an extra completion vector.
Upon a CQ creation, an invalid completion vector could be specified.
Handle it as follows:
* If the completion vector is less than 0, set it to 0.
* Set the completion vector to the result of the passed completion
vector moded with the number of device completion vectors
available.
Reviewed-by: Mike Marciniszyn <mike.marciniszyn@intel.com>
Signed-off-by: Sebastian Sanchez <sebastian.sanchez@intel.com>
Signed-off-by: Dennis Dalessandro <dennis.dalessandro@intel.com>
Signed-off-by: Doug Ledford <dledford@redhat.com>
2018-05-02 21:43:55 +08:00
|
|
|
__hfi1_trace_fn(AFFINITY);
|
2015-07-31 03:17:43 +08:00
|
|
|
__hfi1_trace_fn(PKT);
|
|
|
|
|
__hfi1_trace_fn(PROC);
|
|
|
|
|
__hfi1_trace_fn(SDMA);
|
|
|
|
|
__hfi1_trace_fn(LINKVERB);
|
|
|
|
|
__hfi1_trace_fn(DEBUG);
|
|
|
|
|
__hfi1_trace_fn(SNOOP);
|
|
|
|
|
__hfi1_trace_fn(CNTR);
|
|
|
|
|
__hfi1_trace_fn(PIO);
|
|
|
|
|
__hfi1_trace_fn(DC8051);
|
|
|
|
|
__hfi1_trace_fn(FIRMWARE);
|
|
|
|
|
__hfi1_trace_fn(RCVCTRL);
|
|
|
|
|
__hfi1_trace_fn(TID);
|
2016-03-09 03:14:59 +08:00
|
|
|
__hfi1_trace_fn(MMU);
|
2016-05-19 20:26:37 +08:00
|
|
|
__hfi1_trace_fn(IOCTL);
|
