2020-02-21 05:07:59 +08:00
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// SPDX-License-Identifier: GPL-2.0
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// TLV320ADCX140 Sound driver
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2020-07-19 23:38:22 +08:00
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// Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
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2020-02-21 05:07:59 +08:00
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/pm.h>
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#include <linux/i2c.h>
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#include <linux/gpio/consumer.h>
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#include <linux/regulator/consumer.h>
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#include <linux/acpi.h>
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#include <linux/of.h>
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#include <linux/slab.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#include <sound/initval.h>
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#include <sound/tlv.h>
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#include "tlv320adcx140.h"
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struct adcx140_priv {
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struct snd_soc_component *component;
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struct regulator *supply_areg;
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struct gpio_desc *gpio_reset;
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struct regmap *regmap;
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struct device *dev;
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2020-09-16 03:06:01 +08:00
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bool micbias_vg;
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2022-08-15 19:27:15 +08:00
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bool phase_calib_on;
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2020-02-21 05:07:59 +08:00
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unsigned int dai_fmt;
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unsigned int slot_width;
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};
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2020-07-29 00:08:33 +08:00
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static const char * const gpo_config_names[] = {
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"ti,gpo-config-1",
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"ti,gpo-config-2",
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"ti,gpo-config-3",
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"ti,gpo-config-4",
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};
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2020-02-21 05:07:59 +08:00
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static const struct reg_default adcx140_reg_defaults[] = {
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{ ADCX140_PAGE_SELECT, 0x00 },
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{ ADCX140_SW_RESET, 0x00 },
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{ ADCX140_SLEEP_CFG, 0x00 },
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{ ADCX140_SHDN_CFG, 0x05 },
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{ ADCX140_ASI_CFG0, 0x30 },
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{ ADCX140_ASI_CFG1, 0x00 },
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{ ADCX140_ASI_CFG2, 0x00 },
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{ ADCX140_ASI_CH1, 0x00 },
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{ ADCX140_ASI_CH2, 0x01 },
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{ ADCX140_ASI_CH3, 0x02 },
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{ ADCX140_ASI_CH4, 0x03 },
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{ ADCX140_ASI_CH5, 0x04 },
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{ ADCX140_ASI_CH6, 0x05 },
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{ ADCX140_ASI_CH7, 0x06 },
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{ ADCX140_ASI_CH8, 0x07 },
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{ ADCX140_MST_CFG0, 0x02 },
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{ ADCX140_MST_CFG1, 0x48 },
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{ ADCX140_ASI_STS, 0xff },
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{ ADCX140_CLK_SRC, 0x10 },
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{ ADCX140_PDMCLK_CFG, 0x40 },
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{ ADCX140_PDM_CFG, 0x00 },
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{ ADCX140_GPIO_CFG0, 0x22 },
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2020-07-29 00:08:33 +08:00
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{ ADCX140_GPO_CFG0, 0x00 },
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2020-02-21 05:07:59 +08:00
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{ ADCX140_GPO_CFG1, 0x00 },
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{ ADCX140_GPO_CFG2, 0x00 },
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{ ADCX140_GPO_CFG3, 0x00 },
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{ ADCX140_GPO_VAL, 0x00 },
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{ ADCX140_GPIO_MON, 0x00 },
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{ ADCX140_GPI_CFG0, 0x00 },
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{ ADCX140_GPI_CFG1, 0x00 },
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{ ADCX140_GPI_MON, 0x00 },
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{ ADCX140_INT_CFG, 0x00 },
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{ ADCX140_INT_MASK0, 0xff },
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{ ADCX140_INT_LTCH0, 0x00 },
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{ ADCX140_BIAS_CFG, 0x00 },
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{ ADCX140_CH1_CFG0, 0x00 },
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{ ADCX140_CH1_CFG1, 0x00 },
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{ ADCX140_CH1_CFG2, 0xc9 },
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{ ADCX140_CH1_CFG3, 0x80 },
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{ ADCX140_CH1_CFG4, 0x00 },
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{ ADCX140_CH2_CFG0, 0x00 },
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{ ADCX140_CH2_CFG1, 0x00 },
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{ ADCX140_CH2_CFG2, 0xc9 },
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{ ADCX140_CH2_CFG3, 0x80 },
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{ ADCX140_CH2_CFG4, 0x00 },
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{ ADCX140_CH3_CFG0, 0x00 },
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{ ADCX140_CH3_CFG1, 0x00 },
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{ ADCX140_CH3_CFG2, 0xc9 },
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{ ADCX140_CH3_CFG3, 0x80 },
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{ ADCX140_CH3_CFG4, 0x00 },
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{ ADCX140_CH4_CFG0, 0x00 },
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{ ADCX140_CH4_CFG1, 0x00 },
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{ ADCX140_CH4_CFG2, 0xc9 },
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{ ADCX140_CH4_CFG3, 0x80 },
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{ ADCX140_CH4_CFG4, 0x00 },
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{ ADCX140_CH5_CFG2, 0xc9 },
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{ ADCX140_CH5_CFG3, 0x80 },
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{ ADCX140_CH5_CFG4, 0x00 },
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{ ADCX140_CH6_CFG2, 0xc9 },
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{ ADCX140_CH6_CFG3, 0x80 },
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{ ADCX140_CH6_CFG4, 0x00 },
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{ ADCX140_CH7_CFG2, 0xc9 },
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{ ADCX140_CH7_CFG3, 0x80 },
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{ ADCX140_CH7_CFG4, 0x00 },
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{ ADCX140_CH8_CFG2, 0xc9 },
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{ ADCX140_CH8_CFG3, 0x80 },
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{ ADCX140_CH8_CFG4, 0x00 },
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{ ADCX140_DSP_CFG0, 0x01 },
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{ ADCX140_DSP_CFG1, 0x40 },
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{ ADCX140_DRE_CFG0, 0x7b },
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2020-02-22 02:13:57 +08:00
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{ ADCX140_AGC_CFG0, 0xe7 },
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2020-02-21 05:07:59 +08:00
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{ ADCX140_IN_CH_EN, 0xf0 },
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{ ADCX140_ASI_OUT_CH_EN, 0x00 },
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{ ADCX140_PWR_CFG, 0x00 },
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{ ADCX140_DEV_STS0, 0x00 },
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{ ADCX140_DEV_STS1, 0x80 },
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};
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static const struct regmap_range_cfg adcx140_ranges[] = {
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{
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.range_min = 0,
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.range_max = 12 * 128,
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.selector_reg = ADCX140_PAGE_SELECT,
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.selector_mask = 0xff,
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.selector_shift = 0,
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.window_start = 0,
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.window_len = 128,
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},
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};
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static bool adcx140_volatile(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case ADCX140_SW_RESET:
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case ADCX140_DEV_STS0:
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case ADCX140_DEV_STS1:
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case ADCX140_ASI_STS:
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return true;
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default:
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return false;
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}
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}
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static const struct regmap_config adcx140_i2c_regmap = {
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.reg_bits = 8,
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.val_bits = 8,
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.reg_defaults = adcx140_reg_defaults,
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.num_reg_defaults = ARRAY_SIZE(adcx140_reg_defaults),
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.cache_type = REGCACHE_FLAT,
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.ranges = adcx140_ranges,
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.num_ranges = ARRAY_SIZE(adcx140_ranges),
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.max_register = 12 * 128,
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.volatile_reg = adcx140_volatile,
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};
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/* Digital Volume control. From -100 to 27 dB in 0.5 dB steps */
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2020-09-08 17:04:17 +08:00
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static DECLARE_TLV_DB_SCALE(dig_vol_tlv, -10050, 50, 0);
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2020-02-21 05:07:59 +08:00
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/* ADC gain. From 0 to 42 dB in 1 dB steps */
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static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 100, 0);
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2020-02-22 02:13:57 +08:00
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/* DRE Level. From -12 dB to -66 dB in 1 dB steps */
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static DECLARE_TLV_DB_SCALE(dre_thresh_tlv, -6600, 100, 0);
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/* DRE Max Gain. From 2 dB to 26 dB in 2 dB steps */
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static DECLARE_TLV_DB_SCALE(dre_gain_tlv, 200, 200, 0);
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/* AGC Level. From -6 dB to -36 dB in 2 dB steps */
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static DECLARE_TLV_DB_SCALE(agc_thresh_tlv, -3600, 200, 0);
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/* AGC Max Gain. From 3 dB to 42 dB in 3 dB steps */
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static DECLARE_TLV_DB_SCALE(agc_gain_tlv, 300, 300, 0);
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2020-02-22 02:13:58 +08:00
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static const char * const decimation_filter_text[] = {
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"Linear Phase", "Low Latency", "Ultra-low Latency"
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};
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static SOC_ENUM_SINGLE_DECL(decimation_filter_enum, ADCX140_DSP_CFG0, 4,
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decimation_filter_text);
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static const struct snd_kcontrol_new decimation_filter_controls[] = {
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SOC_DAPM_ENUM("Decimation Filter", decimation_filter_enum),
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};
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2020-05-14 20:33:36 +08:00
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static const char * const pdmclk_text[] = {
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"2.8224 MHz", "1.4112 MHz", "705.6 kHz", "5.6448 MHz"
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};
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static SOC_ENUM_SINGLE_DECL(pdmclk_select_enum, ADCX140_PDMCLK_CFG, 0,
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pdmclk_text);
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static const struct snd_kcontrol_new pdmclk_div_controls[] = {
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SOC_DAPM_ENUM("PDM Clk Divider Select", pdmclk_select_enum),
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};
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2020-02-21 05:07:59 +08:00
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static const char * const resistor_text[] = {
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"2.5 kOhm", "10 kOhm", "20 kOhm"
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};
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static SOC_ENUM_SINGLE_DECL(in1_resistor_enum, ADCX140_CH1_CFG0, 2,
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resistor_text);
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static SOC_ENUM_SINGLE_DECL(in2_resistor_enum, ADCX140_CH2_CFG0, 2,
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resistor_text);
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static SOC_ENUM_SINGLE_DECL(in3_resistor_enum, ADCX140_CH3_CFG0, 2,
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resistor_text);
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static SOC_ENUM_SINGLE_DECL(in4_resistor_enum, ADCX140_CH4_CFG0, 2,
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resistor_text);
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static const struct snd_kcontrol_new in1_resistor_controls[] = {
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SOC_DAPM_ENUM("CH1 Resistor Select", in1_resistor_enum),
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};
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static const struct snd_kcontrol_new in2_resistor_controls[] = {
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SOC_DAPM_ENUM("CH2 Resistor Select", in2_resistor_enum),
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};
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static const struct snd_kcontrol_new in3_resistor_controls[] = {
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SOC_DAPM_ENUM("CH3 Resistor Select", in3_resistor_enum),
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};
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static const struct snd_kcontrol_new in4_resistor_controls[] = {
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SOC_DAPM_ENUM("CH4 Resistor Select", in4_resistor_enum),
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};
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/* Analog/Digital Selection */
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2020-07-29 00:43:39 +08:00
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static const char * const adcx140_mic_sel_text[] = {"Analog", "Line In", "Digital"};
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static const char * const adcx140_analog_sel_text[] = {"Analog", "Line In"};
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2020-02-21 05:07:59 +08:00
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static SOC_ENUM_SINGLE_DECL(adcx140_mic1p_enum,
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ADCX140_CH1_CFG0, 5,
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adcx140_mic_sel_text);
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static const struct snd_kcontrol_new adcx140_dapm_mic1p_control =
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SOC_DAPM_ENUM("MIC1P MUX", adcx140_mic1p_enum);
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static SOC_ENUM_SINGLE_DECL(adcx140_mic1_analog_enum,
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ADCX140_CH1_CFG0, 7,
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adcx140_analog_sel_text);
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static const struct snd_kcontrol_new adcx140_dapm_mic1_analog_control =
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SOC_DAPM_ENUM("MIC1 Analog MUX", adcx140_mic1_analog_enum);
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static SOC_ENUM_SINGLE_DECL(adcx140_mic1m_enum,
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ADCX140_CH1_CFG0, 5,
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adcx140_mic_sel_text);
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static const struct snd_kcontrol_new adcx140_dapm_mic1m_control =
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SOC_DAPM_ENUM("MIC1M MUX", adcx140_mic1m_enum);
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static SOC_ENUM_SINGLE_DECL(adcx140_mic2p_enum,
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ADCX140_CH2_CFG0, 5,
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adcx140_mic_sel_text);
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static const struct snd_kcontrol_new adcx140_dapm_mic2p_control =
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SOC_DAPM_ENUM("MIC2P MUX", adcx140_mic2p_enum);
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static SOC_ENUM_SINGLE_DECL(adcx140_mic2_analog_enum,
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ADCX140_CH2_CFG0, 7,
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adcx140_analog_sel_text);
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static const struct snd_kcontrol_new adcx140_dapm_mic2_analog_control =
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SOC_DAPM_ENUM("MIC2 Analog MUX", adcx140_mic2_analog_enum);
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static SOC_ENUM_SINGLE_DECL(adcx140_mic2m_enum,
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ADCX140_CH2_CFG0, 5,
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adcx140_mic_sel_text);
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static const struct snd_kcontrol_new adcx140_dapm_mic2m_control =
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SOC_DAPM_ENUM("MIC2M MUX", adcx140_mic2m_enum);
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static SOC_ENUM_SINGLE_DECL(adcx140_mic3p_enum,
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ADCX140_CH3_CFG0, 5,
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adcx140_mic_sel_text);
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static const struct snd_kcontrol_new adcx140_dapm_mic3p_control =
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|
SOC_DAPM_ENUM("MIC3P MUX", adcx140_mic3p_enum);
|
|
|
|
|
|
|
|
|
|
static SOC_ENUM_SINGLE_DECL(adcx140_mic3_analog_enum,
|
|
|
|
|
ADCX140_CH3_CFG0, 7,
|
|
|
|
|
adcx140_analog_sel_text);
|
|
|
|
|
|
|
|
|
|
static const struct snd_kcontrol_new adcx140_dapm_mic3_analog_control =
|
|
|
|
|
SOC_DAPM_ENUM("MIC3 Analog MUX", adcx140_mic3_analog_enum);
|
|
|
|
|
|
|
|
|
|
static SOC_ENUM_SINGLE_DECL(adcx140_mic3m_enum,
|
|
|
|
|
ADCX140_CH3_CFG0, 5,
|
|
|
|
|
adcx140_mic_sel_text);
|
|
|
|
|
|
|
|
|
|
static const struct snd_kcontrol_new adcx140_dapm_mic3m_control =
|
|
|
|
|
SOC_DAPM_ENUM("MIC3M MUX", adcx140_mic3m_enum);
|
|
|
|
|
|
|
|
|
|
static SOC_ENUM_SINGLE_DECL(adcx140_mic4p_enum,
|
|
|
|
|
ADCX140_CH4_CFG0, 5,
|
|
|
|
|
adcx140_mic_sel_text);
|
|
|
|
|
|
|
|
|
|
static const struct snd_kcontrol_new adcx140_dapm_mic4p_control =
|
|
|
|
|
SOC_DAPM_ENUM("MIC4P MUX", adcx140_mic4p_enum);
|
|
|
|
|
|
|
|
|
|
static SOC_ENUM_SINGLE_DECL(adcx140_mic4_analog_enum,
|
|
|
|
|
ADCX140_CH4_CFG0, 7,
|
|
|
|
|
adcx140_analog_sel_text);
|
|
|
|
|
|
|
|
|
|
static const struct snd_kcontrol_new adcx140_dapm_mic4_analog_control =
|
|
|
|
|
SOC_DAPM_ENUM("MIC4 Analog MUX", adcx140_mic4_analog_enum);
|
|
|
|
|
|
|
|
|
|
static SOC_ENUM_SINGLE_DECL(adcx140_mic4m_enum,
|
|
|
|
|
ADCX140_CH4_CFG0, 5,
|
|
|
|
|
adcx140_mic_sel_text);
|
|
|
|
|
|
|
|
|
|
static const struct snd_kcontrol_new adcx140_dapm_mic4m_control =
|
|
|
|
|
SOC_DAPM_ENUM("MIC4M MUX", adcx140_mic4m_enum);
|
|
|
|
|
|
|
|
|
|
static const struct snd_kcontrol_new adcx140_dapm_ch1_en_switch =
|
|
|
|
|
SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 7, 1, 0);
|
|
|
|
|
static const struct snd_kcontrol_new adcx140_dapm_ch2_en_switch =
|
|
|
|
|
SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 6, 1, 0);
|
|
|
|
|
static const struct snd_kcontrol_new adcx140_dapm_ch3_en_switch =
|
|
|
|
|
SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 5, 1, 0);
|
|
|
|
|
static const struct snd_kcontrol_new adcx140_dapm_ch4_en_switch =
|
|
|
|
|
SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 4, 1, 0);
|
2020-07-10 02:51:28 +08:00
|
|
|
static const struct snd_kcontrol_new adcx140_dapm_ch5_en_switch =
|
|
|
|
|
SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 3, 1, 0);
|
|
|
|
|
static const struct snd_kcontrol_new adcx140_dapm_ch6_en_switch =
|
|
|
|
|
SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 2, 1, 0);
|
|
|
|
|
static const struct snd_kcontrol_new adcx140_dapm_ch7_en_switch =
|
|
|
|
|
SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 1, 1, 0);
|
|
|
|
|
static const struct snd_kcontrol_new adcx140_dapm_ch8_en_switch =
|
|
|
|
|
SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 0, 1, 0);
|
2020-02-21 05:07:59 +08:00
|
|
|
|
2020-02-22 02:13:57 +08:00
|
|
|
static const struct snd_kcontrol_new adcx140_dapm_ch1_dre_en_switch =
|
|
|
|
|
SOC_DAPM_SINGLE("Switch", ADCX140_CH1_CFG0, 0, 1, 0);
|
|
|
|
|
static const struct snd_kcontrol_new adcx140_dapm_ch2_dre_en_switch =
|
|
|
|
|
SOC_DAPM_SINGLE("Switch", ADCX140_CH2_CFG0, 0, 1, 0);
|
|
|
|
|
static const struct snd_kcontrol_new adcx140_dapm_ch3_dre_en_switch =
|
|
|
|
|
SOC_DAPM_SINGLE("Switch", ADCX140_CH3_CFG0, 0, 1, 0);
|
|
|
|
|
static const struct snd_kcontrol_new adcx140_dapm_ch4_dre_en_switch =
|
|
|
|
|
SOC_DAPM_SINGLE("Switch", ADCX140_CH4_CFG0, 0, 1, 0);
|
|
|
|
|
|
|
|
|
|
static const struct snd_kcontrol_new adcx140_dapm_dre_en_switch =
|
|
|
|
|
SOC_DAPM_SINGLE("Switch", ADCX140_DSP_CFG1, 3, 1, 0);
|
|
|
|
|
|
2020-02-21 05:07:59 +08:00
|
|
|
/* Output Mixer */
|
|
|
|
|
static const struct snd_kcontrol_new adcx140_output_mixer_controls[] = {
|
|
|
|
|
SOC_DAPM_SINGLE("Digital CH1 Switch", 0, 0, 0, 0),
|
|
|
|
|
SOC_DAPM_SINGLE("Digital CH2 Switch", 0, 0, 0, 0),
|
|
|
|
|
SOC_DAPM_SINGLE("Digital CH3 Switch", 0, 0, 0, 0),
|
|
|
|
|
SOC_DAPM_SINGLE("Digital CH4 Switch", 0, 0, 0, 0),
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static const struct snd_soc_dapm_widget adcx140_dapm_widgets[] = {
|
|
|
|
|
/* Analog Differential Inputs */
|
|
|
|
|
SND_SOC_DAPM_INPUT("MIC1P"),
|
|
|
|
|
SND_SOC_DAPM_INPUT("MIC1M"),
|
|
|
|
|
SND_SOC_DAPM_INPUT("MIC2P"),
|
|
|
|
|
SND_SOC_DAPM_INPUT("MIC2M"),
|
|
|
|
|
SND_SOC_DAPM_INPUT("MIC3P"),
|
|
|
|
|
SND_SOC_DAPM_INPUT("MIC3M"),
|
|
|
|
|
SND_SOC_DAPM_INPUT("MIC4P"),
|
|
|
|
|
SND_SOC_DAPM_INPUT("MIC4M"),
|
|
|
|
|
|
|
|
|
|
SND_SOC_DAPM_OUTPUT("CH1_OUT"),
|
|
|
|
|
SND_SOC_DAPM_OUTPUT("CH2_OUT"),
|
|
|
|
|
SND_SOC_DAPM_OUTPUT("CH3_OUT"),
|
|
|
|
|
SND_SOC_DAPM_OUTPUT("CH4_OUT"),
|
|
|
|
|
SND_SOC_DAPM_OUTPUT("CH5_OUT"),
|
|
|
|
|
SND_SOC_DAPM_OUTPUT("CH6_OUT"),
|
|
|
|
|
SND_SOC_DAPM_OUTPUT("CH7_OUT"),
|
|
|
|
|
SND_SOC_DAPM_OUTPUT("CH8_OUT"),
|
|
|
|
|
|
|
|
|
|
SND_SOC_DAPM_MIXER("Output Mixer", SND_SOC_NOPM, 0, 0,
|
|
|
|
|
&adcx140_output_mixer_controls[0],
|
|
|
|
|
ARRAY_SIZE(adcx140_output_mixer_controls)),
|
|
|
|
|
|
|
|
|
|
/* Input Selection to MIC_PGA */
|
|
|
|
|
SND_SOC_DAPM_MUX("MIC1P Input Mux", SND_SOC_NOPM, 0, 0,
|
|
|
|
|
&adcx140_dapm_mic1p_control),
|
|
|
|
|
SND_SOC_DAPM_MUX("MIC2P Input Mux", SND_SOC_NOPM, 0, 0,
|
|
|
|
|
&adcx140_dapm_mic2p_control),
|
|
|
|
|
SND_SOC_DAPM_MUX("MIC3P Input Mux", SND_SOC_NOPM, 0, 0,
|
|
|
|
|
&adcx140_dapm_mic3p_control),
|
|
|
|
|
SND_SOC_DAPM_MUX("MIC4P Input Mux", SND_SOC_NOPM, 0, 0,
|
|
|
|
|
&adcx140_dapm_mic4p_control),
|
|
|
|
|
|
|
|
|
|
/* Input Selection to MIC_PGA */
|
|
|
|
|
SND_SOC_DAPM_MUX("MIC1 Analog Mux", SND_SOC_NOPM, 0, 0,
|
|
|
|
|
&adcx140_dapm_mic1_analog_control),
|
|
|
|
|
SND_SOC_DAPM_MUX("MIC2 Analog Mux", SND_SOC_NOPM, 0, 0,
|
|
|
|
|
&adcx140_dapm_mic2_analog_control),
|
|
|
|
|
SND_SOC_DAPM_MUX("MIC3 Analog Mux", SND_SOC_NOPM, 0, 0,
|
|
|
|
|
&adcx140_dapm_mic3_analog_control),
|
|
|
|
|
SND_SOC_DAPM_MUX("MIC4 Analog Mux", SND_SOC_NOPM, 0, 0,
|
|
|
|
|
&adcx140_dapm_mic4_analog_control),
|
|
|
|
|
|
|
|
|
|
SND_SOC_DAPM_MUX("MIC1M Input Mux", SND_SOC_NOPM, 0, 0,
|
|
|
|
|
&adcx140_dapm_mic1m_control),
|
|
|
|
|
SND_SOC_DAPM_MUX("MIC2M Input Mux", SND_SOC_NOPM, 0, 0,
|
|
|
|
|
&adcx140_dapm_mic2m_control),
|
|
|
|
|
SND_SOC_DAPM_MUX("MIC3M Input Mux", SND_SOC_NOPM, 0, 0,
|
|
|
|
|
&adcx140_dapm_mic3m_control),
|
|
|
|
|
SND_SOC_DAPM_MUX("MIC4M Input Mux", SND_SOC_NOPM, 0, 0,
|
|
|
|
|
&adcx140_dapm_mic4m_control),
|
|
|
|
|
|
|
|
|
|
SND_SOC_DAPM_PGA("MIC_GAIN_CTL_CH1", SND_SOC_NOPM, 0, 0, NULL, 0),
|
|
|
|
|
SND_SOC_DAPM_PGA("MIC_GAIN_CTL_CH2", SND_SOC_NOPM, 0, 0, NULL, 0),
|
|
|
|
|
SND_SOC_DAPM_PGA("MIC_GAIN_CTL_CH3", SND_SOC_NOPM, 0, 0, NULL, 0),
|
|
|
|
|
SND_SOC_DAPM_PGA("MIC_GAIN_CTL_CH4", SND_SOC_NOPM, 0, 0, NULL, 0),
|
|
|
|
|
|
|
|
|
|
SND_SOC_DAPM_ADC("CH1_ADC", "CH1 Capture", ADCX140_IN_CH_EN, 7, 0),
|
|
|
|
|
SND_SOC_DAPM_ADC("CH2_ADC", "CH2 Capture", ADCX140_IN_CH_EN, 6, 0),
|
|
|
|
|
SND_SOC_DAPM_ADC("CH3_ADC", "CH3 Capture", ADCX140_IN_CH_EN, 5, 0),
|
|
|
|
|
SND_SOC_DAPM_ADC("CH4_ADC", "CH4 Capture", ADCX140_IN_CH_EN, 4, 0),
|
|
|
|
|
|
2020-08-28 19:28:55 +08:00
|
|
|
SND_SOC_DAPM_ADC("CH1_DIG", "CH1 Capture", ADCX140_IN_CH_EN, 7, 0),
|
|
|
|
|
SND_SOC_DAPM_ADC("CH2_DIG", "CH2 Capture", ADCX140_IN_CH_EN, 6, 0),
|
|
|
|
|
SND_SOC_DAPM_ADC("CH3_DIG", "CH3 Capture", ADCX140_IN_CH_EN, 5, 0),
|
|
|
|
|
SND_SOC_DAPM_ADC("CH4_DIG", "CH4 Capture", ADCX140_IN_CH_EN, 4, 0),
|
|
|
|
|
SND_SOC_DAPM_ADC("CH5_DIG", "CH5 Capture", ADCX140_IN_CH_EN, 3, 0),
|
|
|
|
|
SND_SOC_DAPM_ADC("CH6_DIG", "CH6 Capture", ADCX140_IN_CH_EN, 2, 0),
|
|
|
|
|
SND_SOC_DAPM_ADC("CH7_DIG", "CH7 Capture", ADCX140_IN_CH_EN, 1, 0),
|
|
|
|
|
SND_SOC_DAPM_ADC("CH8_DIG", "CH8 Capture", ADCX140_IN_CH_EN, 0, 0),
|
|
|
|
|
|
|
|
|
|
|
2020-02-21 05:07:59 +08:00
|
|
|
SND_SOC_DAPM_SWITCH("CH1_ASI_EN", SND_SOC_NOPM, 0, 0,
|
|
|
|
|
&adcx140_dapm_ch1_en_switch),
|
|
|
|
|
SND_SOC_DAPM_SWITCH("CH2_ASI_EN", SND_SOC_NOPM, 0, 0,
|
|
|
|
|
&adcx140_dapm_ch2_en_switch),
|
|
|
|
|
SND_SOC_DAPM_SWITCH("CH3_ASI_EN", SND_SOC_NOPM, 0, 0,
|
|
|
|
|
&adcx140_dapm_ch3_en_switch),
|
|
|
|
|
SND_SOC_DAPM_SWITCH("CH4_ASI_EN", SND_SOC_NOPM, 0, 0,
|
|
|
|
|
&adcx140_dapm_ch4_en_switch),
|
|
|
|
|
|
2020-07-10 02:51:28 +08:00
|
|
|
SND_SOC_DAPM_SWITCH("CH5_ASI_EN", SND_SOC_NOPM, 0, 0,
|
|
|
|
|
&adcx140_dapm_ch5_en_switch),
|
|
|
|
|
SND_SOC_DAPM_SWITCH("CH6_ASI_EN", SND_SOC_NOPM, 0, 0,
|
|
|
|
|
&adcx140_dapm_ch6_en_switch),
|
|
|
|
|
SND_SOC_DAPM_SWITCH("CH7_ASI_EN", SND_SOC_NOPM, 0, 0,
|
|
|
|
|
&adcx140_dapm_ch7_en_switch),
|
|
|
|
|
SND_SOC_DAPM_SWITCH("CH8_ASI_EN", SND_SOC_NOPM, 0, 0,
|
|
|
|
|
&adcx140_dapm_ch8_en_switch),
|
|
|
|
|
|
2020-02-22 02:13:57 +08:00
|
|
|
SND_SOC_DAPM_SWITCH("DRE_ENABLE", SND_SOC_NOPM, 0, 0,
|
|
|
|
|
&adcx140_dapm_dre_en_switch),
|
|
|
|
|
|
|
|
|
|
SND_SOC_DAPM_SWITCH("CH1_DRE_EN", SND_SOC_NOPM, 0, 0,
|
|
|
|
|
&adcx140_dapm_ch1_dre_en_switch),
|
|
|
|
|
SND_SOC_DAPM_SWITCH("CH2_DRE_EN", SND_SOC_NOPM, 0, 0,
|
|
|
|
|
&adcx140_dapm_ch2_dre_en_switch),
|
|
|
|
|
SND_SOC_DAPM_SWITCH("CH3_DRE_EN", SND_SOC_NOPM, 0, 0,
|
|
|
|
|
&adcx140_dapm_ch3_dre_en_switch),
|
|
|
|
|
SND_SOC_DAPM_SWITCH("CH4_DRE_EN", SND_SOC_NOPM, 0, 0,
|
|
|
|
|
&adcx140_dapm_ch4_dre_en_switch),
|
|
|
|
|
|
2020-02-21 05:07:59 +08:00
|
|
|
SND_SOC_DAPM_MUX("IN1 Analog Mic Resistor", SND_SOC_NOPM, 0, 0,
|
|
|
|
|
in1_resistor_controls),
|
|
|
|
|
SND_SOC_DAPM_MUX("IN2 Analog Mic Resistor", SND_SOC_NOPM, 0, 0,
|
|
|
|
|
in2_resistor_controls),
|
|
|
|
|
SND_SOC_DAPM_MUX("IN3 Analog Mic Resistor", SND_SOC_NOPM, 0, 0,
|
|
|
|
|
in3_resistor_controls),
|
|
|
|
|
SND_SOC_DAPM_MUX("IN4 Analog Mic Resistor", SND_SOC_NOPM, 0, 0,
|
|
|
|
|
in4_resistor_controls),
|
2020-02-22 02:13:58 +08:00
|
|
|
|
2020-05-14 20:33:36 +08:00
|
|
|
SND_SOC_DAPM_MUX("PDM Clk Div Select", SND_SOC_NOPM, 0, 0,
|
|
|
|
|
pdmclk_div_controls),
|
|
|
|
|
|
2020-02-22 02:13:58 +08:00
|
|
|
SND_SOC_DAPM_MUX("Decimation Filter", SND_SOC_NOPM, 0, 0,
|
|
|
|
|
decimation_filter_controls),
|
2020-02-21 05:07:59 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static const struct snd_soc_dapm_route adcx140_audio_map[] = {
|
|
|
|
|
/* Outputs */
|
|
|
|
|
{"CH1_OUT", NULL, "Output Mixer"},
|
|
|
|
|
{"CH2_OUT", NULL, "Output Mixer"},
|
|
|
|
|
{"CH3_OUT", NULL, "Output Mixer"},
|
|
|
|
|
{"CH4_OUT", NULL, "Output Mixer"},
|
|
|
|
|
|
|
|
|
|
{"CH1_ASI_EN", "Switch", "CH1_ADC"},
|
|
|
|
|
{"CH2_ASI_EN", "Switch", "CH2_ADC"},
|
|
|
|
|
{"CH3_ASI_EN", "Switch", "CH3_ADC"},
|
|
|
|
|
{"CH4_ASI_EN", "Switch", "CH4_ADC"},
|
|
|
|
|
|
2020-08-28 19:28:55 +08:00
|
|
|
{"CH1_ASI_EN", "Switch", "CH1_DIG"},
|
|
|
|
|
{"CH2_ASI_EN", "Switch", "CH2_DIG"},
|
|
|
|
|
{"CH3_ASI_EN", "Switch", "CH3_DIG"},
|
|
|
|
|
{"CH4_ASI_EN", "Switch", "CH4_DIG"},
|
|
|
|
|
{"CH5_ASI_EN", "Switch", "CH5_DIG"},
|
|
|
|
|
{"CH6_ASI_EN", "Switch", "CH6_DIG"},
|
|
|
|
|
{"CH7_ASI_EN", "Switch", "CH7_DIG"},
|
|
|
|
|
{"CH8_ASI_EN", "Switch", "CH8_DIG"},
|
|
|
|
|
|
2020-07-10 02:51:28 +08:00
|
|
|
{"CH5_ASI_EN", "Switch", "CH5_OUT"},
|
|
|
|
|
{"CH6_ASI_EN", "Switch", "CH6_OUT"},
|
|
|
|
|
{"CH7_ASI_EN", "Switch", "CH7_OUT"},
|
|
|
|
|
{"CH8_ASI_EN", "Switch", "CH8_OUT"},
|
|
|
|
|
|
2020-02-22 02:13:58 +08:00
|
|
|
{"Decimation Filter", "Linear Phase", "DRE_ENABLE"},
|
|
|
|
|
{"Decimation Filter", "Low Latency", "DRE_ENABLE"},
|
|
|
|
|
{"Decimation Filter", "Ultra-low Latency", "DRE_ENABLE"},
|
|
|
|
|
|
2020-02-22 02:13:57 +08:00
|
|
|
{"DRE_ENABLE", "Switch", "CH1_DRE_EN"},
|
|
|
|
|
{"DRE_ENABLE", "Switch", "CH2_DRE_EN"},
|
|
|
|
|
{"DRE_ENABLE", "Switch", "CH3_DRE_EN"},
|
|
|
|
|
{"DRE_ENABLE", "Switch", "CH4_DRE_EN"},
|
|
|
|
|
|
|
|
|
|
{"CH1_DRE_EN", "Switch", "CH1_ADC"},
|
|
|
|
|
{"CH2_DRE_EN", "Switch", "CH2_ADC"},
|
|
|
|
|
{"CH3_DRE_EN", "Switch", "CH3_ADC"},
|
|
|
|
|
{"CH4_DRE_EN", "Switch", "CH4_ADC"},
|
|
|
|
|
|
2020-02-21 05:07:59 +08:00
|
|
|
/* Mic input */
|
|
|
|
|
{"CH1_ADC", NULL, "MIC_GAIN_CTL_CH1"},
|
|
|
|
|
{"CH2_ADC", NULL, "MIC_GAIN_CTL_CH2"},
|
|
|
|
|
{"CH3_ADC", NULL, "MIC_GAIN_CTL_CH3"},
|
|
|
|
|
{"CH4_ADC", NULL, "MIC_GAIN_CTL_CH4"},
|
|
|
|
|
|
|
|
|
|
{"MIC_GAIN_CTL_CH1", NULL, "IN1 Analog Mic Resistor"},
|
|
|
|
|
{"MIC_GAIN_CTL_CH1", NULL, "IN1 Analog Mic Resistor"},
|
|
|
|
|
{"MIC_GAIN_CTL_CH2", NULL, "IN2 Analog Mic Resistor"},
|
|
|
|
|
{"MIC_GAIN_CTL_CH2", NULL, "IN2 Analog Mic Resistor"},
|
|
|
|
|
{"MIC_GAIN_CTL_CH3", NULL, "IN3 Analog Mic Resistor"},
|
|
|
|
|
{"MIC_GAIN_CTL_CH3", NULL, "IN3 Analog Mic Resistor"},
|
|
|
|
|
{"MIC_GAIN_CTL_CH4", NULL, "IN4 Analog Mic Resistor"},
|
|
|
|
|
{"MIC_GAIN_CTL_CH4", NULL, "IN4 Analog Mic Resistor"},
|
|
|
|
|
|
|
|
|
|
{"IN1 Analog Mic Resistor", "2.5 kOhm", "MIC1P Input Mux"},
|
|
|
|
|
{"IN1 Analog Mic Resistor", "10 kOhm", "MIC1P Input Mux"},
|
|
|
|
|
{"IN1 Analog Mic Resistor", "20 kOhm", "MIC1P Input Mux"},
|
|
|
|
|
|
|
|
|
|
{"IN1 Analog Mic Resistor", "2.5 kOhm", "MIC1M Input Mux"},
|
|
|
|
|
{"IN1 Analog Mic Resistor", "10 kOhm", "MIC1M Input Mux"},
|
|
|
|
|
{"IN1 Analog Mic Resistor", "20 kOhm", "MIC1M Input Mux"},
|
|
|
|
|
|
|
|
|
|
{"IN2 Analog Mic Resistor", "2.5 kOhm", "MIC2P Input Mux"},
|
|
|
|
|
{"IN2 Analog Mic Resistor", "10 kOhm", "MIC2P Input Mux"},
|
|
|
|
|
{"IN2 Analog Mic Resistor", "20 kOhm", "MIC2P Input Mux"},
|
|
|
|
|
|
|
|
|
|
{"IN2 Analog Mic Resistor", "2.5 kOhm", "MIC2M Input Mux"},
|
|
|
|
|
{"IN2 Analog Mic Resistor", "10 kOhm", "MIC2M Input Mux"},
|
|
|
|
|
{"IN2 Analog Mic Resistor", "20 kOhm", "MIC2M Input Mux"},
|
|
|
|
|
|
|
|
|
|
{"IN3 Analog Mic Resistor", "2.5 kOhm", "MIC3P Input Mux"},
|
|
|
|
|
{"IN3 Analog Mic Resistor", "10 kOhm", "MIC3P Input Mux"},
|
|
|
|
|
{"IN3 Analog Mic Resistor", "20 kOhm", "MIC3P Input Mux"},
|
|
|
|
|
|
|
|
|
|
{"IN3 Analog Mic Resistor", "2.5 kOhm", "MIC3M Input Mux"},
|
|
|
|
|
{"IN3 Analog Mic Resistor", "10 kOhm", "MIC3M Input Mux"},
|
|
|
|
|
{"IN3 Analog Mic Resistor", "20 kOhm", "MIC3M Input Mux"},
|
|
|
|
|
|
|
|
|
|
{"IN4 Analog Mic Resistor", "2.5 kOhm", "MIC4P Input Mux"},
|
|
|
|
|
{"IN4 Analog Mic Resistor", "10 kOhm", "MIC4P Input Mux"},
|
|
|
|
|
{"IN4 Analog Mic Resistor", "20 kOhm", "MIC4P Input Mux"},
|
|
|
|
|
|
|
|
|
|
{"IN4 Analog Mic Resistor", "2.5 kOhm", "MIC4M Input Mux"},
|
|
|
|
|
{"IN4 Analog Mic Resistor", "10 kOhm", "MIC4M Input Mux"},
|
|
|
|
|
{"IN4 Analog Mic Resistor", "20 kOhm", "MIC4M Input Mux"},
|
|
|
|
|
|
2020-05-14 20:33:36 +08:00
|
|
|
{"PDM Clk Div Select", "2.8224 MHz", "MIC1P Input Mux"},
|
|
|
|
|
{"PDM Clk Div Select", "1.4112 MHz", "MIC1P Input Mux"},
|
|
|
|
|
{"PDM Clk Div Select", "705.6 kHz", "MIC1P Input Mux"},
|
|
|
|
|
{"PDM Clk Div Select", "5.6448 MHz", "MIC1P Input Mux"},
|
|
|
|
|
|
2020-08-28 19:28:55 +08:00
|
|
|
{"MIC1P Input Mux", NULL, "CH1_DIG"},
|
|
|
|
|
{"MIC1M Input Mux", NULL, "CH2_DIG"},
|
|
|
|
|
{"MIC2P Input Mux", NULL, "CH3_DIG"},
|
|
|
|
|
{"MIC2M Input Mux", NULL, "CH4_DIG"},
|
|
|
|
|
{"MIC3P Input Mux", NULL, "CH5_DIG"},
|
|
|
|
|
{"MIC3M Input Mux", NULL, "CH6_DIG"},
|
|
|
|
|
{"MIC4P Input Mux", NULL, "CH7_DIG"},
|
|
|
|
|
{"MIC4M Input Mux", NULL, "CH8_DIG"},
|
|
|
|
|
|
2020-02-21 05:07:59 +08:00
|
|
|
{"MIC1 Analog Mux", "Line In", "MIC1P"},
|
|
|
|
|
{"MIC2 Analog Mux", "Line In", "MIC2P"},
|
|
|
|
|
{"MIC3 Analog Mux", "Line In", "MIC3P"},
|
|
|
|
|
{"MIC4 Analog Mux", "Line In", "MIC4P"},
|
|
|
|
|
|
|
|
|
|
{"MIC1P Input Mux", "Analog", "MIC1P"},
|
|
|
|
|
{"MIC1M Input Mux", "Analog", "MIC1M"},
|
|
|
|
|
{"MIC2P Input Mux", "Analog", "MIC2P"},
|
|
|
|
|
{"MIC2M Input Mux", "Analog", "MIC2M"},
|
|
|
|
|
{"MIC3P Input Mux", "Analog", "MIC3P"},
|
|
|
|
|
{"MIC3M Input Mux", "Analog", "MIC3M"},
|
|
|
|
|
{"MIC4P Input Mux", "Analog", "MIC4P"},
|
|
|
|
|
{"MIC4M Input Mux", "Analog", "MIC4M"},
|
2020-08-28 19:28:55 +08:00
|
|
|
|
|
|
|
|
{"MIC1P Input Mux", "Digital", "MIC1P"},
|
|
|
|
|
{"MIC1M Input Mux", "Digital", "MIC1M"},
|
|
|
|
|
{"MIC2P Input Mux", "Digital", "MIC2P"},
|
|
|
|
|
{"MIC2M Input Mux", "Digital", "MIC2M"},
|
|
|
|
|
{"MIC3P Input Mux", "Digital", "MIC3P"},
|
|
|
|
|
{"MIC3M Input Mux", "Digital", "MIC3M"},
|
|
|
|
|
{"MIC4P Input Mux", "Digital", "MIC4P"},
|
|
|
|
|
{"MIC4M Input Mux", "Digital", "MIC4M"},
|
2020-02-21 05:07:59 +08:00
|
|
|
};
|
|
|
|
|
|
2022-08-15 19:27:15 +08:00
|
|
|
#define ADCX140_PHASE_CALIB_SWITCH(xname) {\
|
|
|
|
|
.iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
|
|
|
|
|
.access = SNDRV_CTL_ELEM_ACCESS_READWRITE,\
|
|
|
|
|
.info = adcx140_phase_calib_info, \
|
|
|
|
|
.get = adcx140_phase_calib_get, \
|
|
|
|
|
.put = adcx140_phase_calib_put}
|
|
|
|
|
|
|
|
|
|
static int adcx140_phase_calib_info(struct snd_kcontrol *kcontrol,
|
|
|
|
|
struct snd_ctl_elem_info *uinfo)
|
|
|
|
|
{
|
|
|
|
|
uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
|
|
|
|
|
uinfo->count = 1;
|
|
|
|
|
uinfo->value.integer.min = 0;
|
|
|
|
|
uinfo->value.integer.max = 1;
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int adcx140_phase_calib_get(struct snd_kcontrol *kcontrol,
|
|
|
|
|
struct snd_ctl_elem_value *value)
|
|
|
|
|
{
|
|
|
|
|
struct snd_soc_component *codec =
|
|
|
|
|
snd_soc_kcontrol_component(kcontrol);
|
|
|
|
|
struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(codec);
|
|
|
|
|
|
|
|
|
|
value->value.integer.value[0] = adcx140->phase_calib_on ? 1 : 0;
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int adcx140_phase_calib_put(struct snd_kcontrol *kcontrol,
|
|
|
|
|
struct snd_ctl_elem_value *value)
|
|
|
|
|
{
|
|
|
|
|
struct snd_soc_component *codec
|
|
|
|
|
= snd_soc_kcontrol_component(kcontrol);
|
|
|
|
|
struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(codec);
|
|
|
|
|
|
|
|
|
|
bool v = value->value.integer.value[0] ? true : false;
|
|
|
|
|
|
|
|
|
|
if (adcx140->phase_calib_on != v) {
|
|
|
|
|
adcx140->phase_calib_on = v;
|
|
|
|
|
return 1;
|
|
|
|
|
}
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2020-02-21 05:07:59 +08:00
|
|
|
static const struct snd_kcontrol_new adcx140_snd_controls[] = {
|
|
|
|
|
SOC_SINGLE_TLV("Analog CH1 Mic Gain Volume", ADCX140_CH1_CFG1, 2, 42, 0,
|
|
|
|
|
adc_tlv),
|
2020-04-28 04:36:08 +08:00
|
|
|
SOC_SINGLE_TLV("Analog CH2 Mic Gain Volume", ADCX140_CH2_CFG1, 2, 42, 0,
|
2020-02-21 05:07:59 +08:00
|
|
|
adc_tlv),
|
2020-04-28 04:36:08 +08:00
|
|
|
SOC_SINGLE_TLV("Analog CH3 Mic Gain Volume", ADCX140_CH3_CFG1, 2, 42, 0,
|
2020-02-21 05:07:59 +08:00
|
|
|
adc_tlv),
|
2020-04-28 04:36:08 +08:00
|
|
|
SOC_SINGLE_TLV("Analog CH4 Mic Gain Volume", ADCX140_CH4_CFG1, 2, 42, 0,
|
2020-02-21 05:07:59 +08:00
|
|
|
adc_tlv),
|
|
|
|
|
|
2020-02-22 02:13:57 +08:00
|
|
|
SOC_SINGLE_TLV("DRE Threshold", ADCX140_DRE_CFG0, 4, 9, 0,
|
|
|
|
|
dre_thresh_tlv),
|
|
|
|
|
SOC_SINGLE_TLV("DRE Max Gain", ADCX140_DRE_CFG0, 0, 12, 0,
|
|
|
|
|
dre_gain_tlv),
|
|
|
|
|
|
|
|
|
|
SOC_SINGLE_TLV("AGC Threshold", ADCX140_AGC_CFG0, 4, 15, 0,
|
|
|
|
|
agc_thresh_tlv),
|
|
|
|
|
SOC_SINGLE_TLV("AGC Max Gain", ADCX140_AGC_CFG0, 0, 13, 0,
|
|
|
|
|
agc_gain_tlv),
|
|
|
|
|
|
2020-02-21 05:07:59 +08:00
|
|
|
SOC_SINGLE_TLV("Digital CH1 Out Volume", ADCX140_CH1_CFG2,
|
|
|
|
|
0, 0xff, 0, dig_vol_tlv),
|
|
|
|
|
SOC_SINGLE_TLV("Digital CH2 Out Volume", ADCX140_CH2_CFG2,
|
|
|
|
|
0, 0xff, 0, dig_vol_tlv),
|
|
|
|
|
SOC_SINGLE_TLV("Digital CH3 Out Volume", ADCX140_CH3_CFG2,
|
|
|
|
|
0, 0xff, 0, dig_vol_tlv),
|
|
|
|
|
SOC_SINGLE_TLV("Digital CH4 Out Volume", ADCX140_CH4_CFG2,
|
|
|
|
|
0, 0xff, 0, dig_vol_tlv),
|
|
|
|
|
SOC_SINGLE_TLV("Digital CH5 Out Volume", ADCX140_CH5_CFG2,
|
|
|
|
|
0, 0xff, 0, dig_vol_tlv),
|
|
|
|
|
SOC_SINGLE_TLV("Digital CH6 Out Volume", ADCX140_CH6_CFG2,
|
|
|
|
|
0, 0xff, 0, dig_vol_tlv),
|
|
|
|
|
SOC_SINGLE_TLV("Digital CH7 Out Volume", ADCX140_CH7_CFG2,
|
|
|
|
|
0, 0xff, 0, dig_vol_tlv),
|
|
|
|
|
SOC_SINGLE_TLV("Digital CH8 Out Volume", ADCX140_CH8_CFG2,
|
|
|
|
|
0, 0xff, 0, dig_vol_tlv),
|
2022-08-15 19:27:15 +08:00
|
|
|
ADCX140_PHASE_CALIB_SWITCH("Phase Calibration Switch"),
|
2020-02-21 05:07:59 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static int adcx140_reset(struct adcx140_priv *adcx140)
|
|
|
|
|
{
|
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
|
|
if (adcx140->gpio_reset) {
|
|
|
|
|
gpiod_direction_output(adcx140->gpio_reset, 0);
|
|
|
|
|
/* 8.4.1: wait for hw shutdown (25ms) + >= 1ms */
|
|
|
|
|
usleep_range(30000, 100000);
|
|
|
|
|
gpiod_direction_output(adcx140->gpio_reset, 1);
|
|
|
|
|
} else {
|
|
|
|
|
ret = regmap_write(adcx140->regmap, ADCX140_SW_RESET,
|
2020-07-29 00:43:39 +08:00
|
|
|
ADCX140_RESET);
|
2020-02-21 05:07:59 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* 8.4.2: wait >= 10 ms after entering sleep mode. */
|
|
|
|
|
usleep_range(10000, 100000);
|
|
|
|
|
|
2020-05-27 01:52:47 +08:00
|
|
|
return ret;
|
2020-02-21 05:07:59 +08:00
|
|
|
}
|
|
|
|
|
|
2020-09-16 03:06:01 +08:00
|
|
|
static void adcx140_pwr_ctrl(struct adcx140_priv *adcx140, bool power_state)
|
|
|
|
|
{
|
|
|
|
|
int pwr_ctrl = 0;
|
2022-08-15 19:27:15 +08:00
|
|
|
int ret = 0;
|
|
|
|
|
struct snd_soc_component *component = adcx140->component;
|
2020-09-16 03:06:01 +08:00
|
|
|
|
|
|
|
|
if (power_state)
|
|
|
|
|
pwr_ctrl = ADCX140_PWR_CFG_ADC_PDZ | ADCX140_PWR_CFG_PLL_PDZ;
|
|
|
|
|
|
|
|
|
|
if (adcx140->micbias_vg && power_state)
|
|
|
|
|
pwr_ctrl |= ADCX140_PWR_CFG_BIAS_PDZ;
|
|
|
|
|
|
2022-08-15 19:27:15 +08:00
|
|
|
if (pwr_ctrl) {
|
|
|
|
|
ret = regmap_write(adcx140->regmap, ADCX140_PHASE_CALIB,
|
|
|
|
|
adcx140->phase_calib_on ? 0x00 : 0x40);
|
|
|
|
|
if (ret)
|
|
|
|
|
dev_err(component->dev, "%s: register write error %d\n",
|
|
|
|
|
__func__, ret);
|
|
|
|
|
}
|
|
|
|
|
|
2020-09-16 03:06:01 +08:00
|
|
|
regmap_update_bits(adcx140->regmap, ADCX140_PWR_CFG,
|
|
|
|
|
ADCX140_PWR_CTRL_MSK, pwr_ctrl);
|
|
|
|
|
}
|
|
|
|
|
|
2020-02-21 05:07:59 +08:00
|
|
|
static int adcx140_hw_params(struct snd_pcm_substream *substream,
|
|
|
|
|
struct snd_pcm_hw_params *params,
|
|
|
|
|
struct snd_soc_dai *dai)
|
|
|
|
|
{
|
|
|
|
|
struct snd_soc_component *component = dai->component;
|
2020-09-16 03:06:01 +08:00
|
|
|
struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(component);
|
2020-02-21 05:07:59 +08:00
|
|
|
u8 data = 0;
|
|
|
|
|
|
|
|
|
|
switch (params_width(params)) {
|
|
|
|
|
case 16:
|
|
|
|
|
data = ADCX140_16_BIT_WORD;
|
|
|
|
|
break;
|
|
|
|
|
case 20:
|
|
|
|
|
data = ADCX140_20_BIT_WORD;
|
|
|
|
|
break;
|
|
|
|
|
case 24:
|
|
|
|
|
data = ADCX140_24_BIT_WORD;
|
|
|
|
|
break;
|
|
|
|
|
case 32:
|
|
|
|
|
data = ADCX140_32_BIT_WORD;
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
dev_err(component->dev, "%s: Unsupported width %d\n",
|
|
|
|
|
__func__, params_width(params));
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
2020-09-16 03:06:01 +08:00
|
|
|
adcx140_pwr_ctrl(adcx140, false);
|
|
|
|
|
|
2020-02-21 05:07:59 +08:00
|
|
|
snd_soc_component_update_bits(component, ADCX140_ASI_CFG0,
|
|
|
|
|
ADCX140_WORD_LEN_MSK, data);
|
|
|
|
|
|
2020-09-16 03:06:01 +08:00
|
|
|
adcx140_pwr_ctrl(adcx140, true);
|
|
|
|
|
|
2020-02-21 05:07:59 +08:00
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int adcx140_set_dai_fmt(struct snd_soc_dai *codec_dai,
|
|
|
|
|
unsigned int fmt)
|
|
|
|
|
{
|
|
|
|
|
struct snd_soc_component *component = codec_dai->component;
|
|
|
|
|
struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(component);
|
|
|
|
|
u8 iface_reg1 = 0;
|
|
|
|
|
u8 iface_reg2 = 0;
|
2020-07-10 02:51:29 +08:00
|
|
|
int offset = 0;
|
2020-09-16 03:06:02 +08:00
|
|
|
bool inverted_bclk = false;
|
2020-02-21 05:07:59 +08:00
|
|
|
|
|
|
|
|
/* set master/slave audio interface */
|
2022-06-02 21:53:10 +08:00
|
|
|
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
|
|
|
|
|
case SND_SOC_DAIFMT_CBP_CFP:
|
2020-02-21 05:07:59 +08:00
|
|
|
iface_reg2 |= ADCX140_BCLK_FSYNC_MASTER;
|
|
|
|
|
break;
|
2022-06-02 21:53:10 +08:00
|
|
|
case SND_SOC_DAIFMT_CBC_CFC:
|
2020-02-21 05:07:59 +08:00
|
|
|
break;
|
|
|
|
|
default:
|
2022-06-02 21:53:10 +08:00
|
|
|
dev_err(component->dev, "Invalid DAI clock provider\n");
|
2020-02-21 05:07:59 +08:00
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* interface format */
|
|
|
|
|
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
|
|
|
|
|
case SND_SOC_DAIFMT_I2S:
|
|
|
|
|
iface_reg1 |= ADCX140_I2S_MODE_BIT;
|
|
|
|
|
break;
|
|
|
|
|
case SND_SOC_DAIFMT_LEFT_J:
|
|
|
|
|
iface_reg1 |= ADCX140_LEFT_JUST_BIT;
|
|
|
|
|
break;
|
|
|
|
|
case SND_SOC_DAIFMT_DSP_A:
|
2020-09-16 03:06:02 +08:00
|
|
|
offset = 1;
|
|
|
|
|
inverted_bclk = true;
|
2020-07-10 02:51:29 +08:00
|
|
|
break;
|
2020-02-21 05:07:59 +08:00
|
|
|
case SND_SOC_DAIFMT_DSP_B:
|
2020-09-16 03:06:02 +08:00
|
|
|
inverted_bclk = true;
|
2020-02-21 05:07:59 +08:00
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
dev_err(component->dev, "Invalid DAI interface format\n");
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
2020-09-16 03:06:02 +08:00
|
|
|
/* signal polarity */
|
|
|
|
|
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
|
|
|
|
|
case SND_SOC_DAIFMT_IB_NF:
|
|
|
|
|
case SND_SOC_DAIFMT_IB_IF:
|
|
|
|
|
inverted_bclk = !inverted_bclk;
|
|
|
|
|
break;
|
|
|
|
|
case SND_SOC_DAIFMT_NB_IF:
|
|
|
|
|
iface_reg1 |= ADCX140_FSYNCINV_BIT;
|
|
|
|
|
break;
|
|
|
|
|
case SND_SOC_DAIFMT_NB_NF:
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
dev_err(component->dev, "Invalid DAI clock signal polarity\n");
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (inverted_bclk)
|
|
|
|
|
iface_reg1 |= ADCX140_BCLKINV_BIT;
|
|
|
|
|
|
2020-02-21 05:07:59 +08:00
|
|
|
adcx140->dai_fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
|
|
|
|
|
|
2020-09-16 03:06:01 +08:00
|
|
|
adcx140_pwr_ctrl(adcx140, false);
|
|
|
|
|
|
2020-02-21 05:07:59 +08:00
|
|
|
snd_soc_component_update_bits(component, ADCX140_ASI_CFG0,
|
|
|
|
|
ADCX140_FSYNCINV_BIT |
|
|
|
|
|
ADCX140_BCLKINV_BIT |
|
|
|
|
|
ADCX140_ASI_FORMAT_MSK,
|
|
|
|
|
iface_reg1);
|
|
|
|
|
snd_soc_component_update_bits(component, ADCX140_MST_CFG0,
|
|
|
|
|
ADCX140_BCLK_FSYNC_MASTER, iface_reg2);
|
|
|
|
|
|
2020-07-10 02:51:29 +08:00
|
|
|
/* Configure data offset */
|
|
|
|
|
snd_soc_component_update_bits(component, ADCX140_ASI_CFG1,
|
|
|
|
|
ADCX140_TX_OFFSET_MASK, offset);
|
|
|
|
|
|
2020-09-16 03:06:01 +08:00
|
|
|
adcx140_pwr_ctrl(adcx140, true);
|
2020-07-10 02:51:29 +08:00
|
|
|
|
2020-02-21 05:07:59 +08:00
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int adcx140_set_dai_tdm_slot(struct snd_soc_dai *codec_dai,
|
|
|
|
|
unsigned int tx_mask, unsigned int rx_mask,
|
|
|
|
|
int slots, int slot_width)
|
|
|
|
|
{
|
|
|
|
|
struct snd_soc_component *component = codec_dai->component;
|
|
|
|
|
struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(component);
|
|
|
|
|
|
2022-06-24 18:57:16 +08:00
|
|
|
/*
|
|
|
|
|
* The chip itself supports arbitrary masks, but the driver currently
|
|
|
|
|
* only supports adjacent slots beginning at the first slot.
|
|
|
|
|
*/
|
|
|
|
|
if (tx_mask != GENMASK(__fls(tx_mask), 0)) {
|
|
|
|
|
dev_err(component->dev, "Only lower adjacent slots are supported\n");
|
2020-02-21 05:07:59 +08:00
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
switch (slot_width) {
|
|
|
|
|
case 16:
|
|
|
|
|
case 20:
|
|
|
|
|
case 24:
|
|
|
|
|
case 32:
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
dev_err(component->dev, "Unsupported slot width %d\n", slot_width);
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
adcx140->slot_width = slot_width;
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static const struct snd_soc_dai_ops adcx140_dai_ops = {
|
|
|
|
|
.hw_params = adcx140_hw_params,
|
|
|
|
|
.set_fmt = adcx140_set_dai_fmt,
|
|
|
|
|
.set_tdm_slot = adcx140_set_dai_tdm_slot,
|
|
|
|
|
};
|
|
|
|
|
|
2020-07-29 00:08:33 +08:00
|
|
|
static int adcx140_configure_gpo(struct adcx140_priv *adcx140)
|
|
|
|
|
{
|
|
|
|
|
u32 gpo_outputs[ADCX140_NUM_GPOS];
|
|
|
|
|
u32 gpo_output_val = 0;
|
|
|
|
|
int ret;
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < ADCX140_NUM_GPOS; i++) {
|
|
|
|
|
ret = device_property_read_u32_array(adcx140->dev,
|
|
|
|
|
gpo_config_names[i],
|
|
|
|
|
gpo_outputs,
|
|
|
|
|
ADCX140_NUM_GPO_CFGS);
|
|
|
|
|
if (ret)
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
if (gpo_outputs[0] > ADCX140_GPO_CFG_MAX) {
|
|
|
|
|
dev_err(adcx140->dev, "GPO%d config out of range\n", i + 1);
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (gpo_outputs[1] > ADCX140_GPO_DRV_MAX) {
|
|
|
|
|
dev_err(adcx140->dev, "GPO%d drive out of range\n", i + 1);
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
gpo_output_val = gpo_outputs[0] << ADCX140_GPO_SHIFT |
|
|
|
|
|
gpo_outputs[1];
|
2020-07-30 22:24:18 +08:00
|
|
|
ret = regmap_write(adcx140->regmap, ADCX140_GPO_CFG0 + i,
|
2020-07-29 00:08:33 +08:00
|
|
|
gpo_output_val);
|
|
|
|
|
if (ret)
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
ASoC: tlv320adcx140: Add support for configuring GPIO pin
Add support to configure the GPIO pin to the specific configuration.
The GPIO pin can be configured as GPO, IRQ, SDOUT2, PDMCLK, MICBASE_EN,
GPI, MCLK, SDIN, PDMDIN1, PDMDIN2, PDMDIN3 or PDMDIN4 and the output
drive can be configured with various configuration.
Signed-off-by: Camel Guo <camelg@axis.com>
Link: https://lore.kernel.org/r/20200918114025.18205-2-camel.guo@axis.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2020-09-18 19:40:25 +08:00
|
|
|
static int adcx140_configure_gpio(struct adcx140_priv *adcx140)
|
|
|
|
|
{
|
|
|
|
|
int gpio_count = 0;
|
|
|
|
|
u32 gpio_outputs[ADCX140_NUM_GPIO_CFGS];
|
|
|
|
|
u32 gpio_output_val = 0;
|
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
|
|
gpio_count = device_property_count_u32(adcx140->dev,
|
|
|
|
|
"ti,gpio-config");
|
ASoC: tlv320adcx140: fix 'ti,gpio-config' DT property init
When the 'ti,gpio-config' property is not defined, the
device_property_count_u32() will return an error, rather than zero.
The current check, only handles a return value of zero, which assumes that
the property is defined and has nothing defined.
This change extends the check to also check for an error case (most likely
to be hit by the case that the 'ti,gpio-config' is not defined).
In case that the 'ti,gpio-config' and the returned 'gpio_count' is not
correct, there is a 'if (gpio_count != ADCX140_NUM_GPIO_CFGS)' check, a few
lines lower that will return -EINVAL.
This means that someone tried to define 'ti,gpio-config', but with the
wrong number of GPIOs.
Fixes: d5214321498a ("ASoC: tlv320adcx140: Add support for configuring GPIO pin")
Signed-off-by: Steffen Aschbacher <steffen.aschbacher@stihl.de>
Signed-off-by: Alexandru Ardelean <alex@shruggie.ro>
Link: https://lore.kernel.org/r/20230213073805.14640-1-alex@shruggie.ro
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-02-13 15:38:05 +08:00
|
|
|
if (gpio_count <= 0)
|
ASoC: tlv320adcx140: Add support for configuring GPIO pin
Add support to configure the GPIO pin to the specific configuration.
The GPIO pin can be configured as GPO, IRQ, SDOUT2, PDMCLK, MICBASE_EN,
GPI, MCLK, SDIN, PDMDIN1, PDMDIN2, PDMDIN3 or PDMDIN4 and the output
drive can be configured with various configuration.
Signed-off-by: Camel Guo <camelg@axis.com>
Link: https://lore.kernel.org/r/20200918114025.18205-2-camel.guo@axis.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2020-09-18 19:40:25 +08:00
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
if (gpio_count != ADCX140_NUM_GPIO_CFGS)
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
|
|
ret = device_property_read_u32_array(adcx140->dev, "ti,gpio-config",
|
|
|
|
|
gpio_outputs, gpio_count);
|
|
|
|
|
if (ret)
|
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
|
|
if (gpio_outputs[0] > ADCX140_GPIO_CFG_MAX) {
|
|
|
|
|
dev_err(adcx140->dev, "GPIO config out of range\n");
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (gpio_outputs[1] > ADCX140_GPIO_DRV_MAX) {
|
|
|
|
|
dev_err(adcx140->dev, "GPIO drive out of range\n");
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
gpio_output_val = gpio_outputs[0] << ADCX140_GPIO_SHIFT
|
|
|
|
|
| gpio_outputs[1];
|
|
|
|
|
|
|
|
|
|
return regmap_write(adcx140->regmap, ADCX140_GPIO_CFG0, gpio_output_val);
|
|
|
|
|
}
|
|
|
|
|
|
2020-02-21 05:07:59 +08:00
|
|
|
static int adcx140_codec_probe(struct snd_soc_component *component)
|
|
|
|
|
{
|
|
|
|
|
struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(component);
|
|
|
|
|
int sleep_cfg_val = ADCX140_WAKE_DEV;
|
2020-05-13 22:28:07 +08:00
|
|
|
u32 bias_source;
|
|
|
|
|
u32 vref_source;
|
|
|
|
|
u8 bias_cfg;
|
2020-05-14 20:33:38 +08:00
|
|
|
int pdm_count;
|
|
|
|
|
u32 pdm_edges[ADCX140_NUM_PDM_EDGES];
|
|
|
|
|
u32 pdm_edge_val = 0;
|
2020-05-27 04:09:17 +08:00
|
|
|
int gpi_count;
|
|
|
|
|
u32 gpi_inputs[ADCX140_NUM_GPI_PINS];
|
|
|
|
|
u32 gpi_input_val = 0;
|
2020-05-14 20:33:38 +08:00
|
|
|
int i;
|
2020-02-21 05:07:59 +08:00
|
|
|
int ret;
|
2020-09-16 03:06:04 +08:00
|
|
|
bool tx_high_z;
|
2020-02-21 05:07:59 +08:00
|
|
|
|
2020-05-13 22:28:07 +08:00
|
|
|
ret = device_property_read_u32(adcx140->dev, "ti,mic-bias-source",
|
2020-02-21 05:07:59 +08:00
|
|
|
&bias_source);
|
2020-09-16 03:06:01 +08:00
|
|
|
if (ret || bias_source > ADCX140_MIC_BIAS_VAL_AVDD) {
|
2020-02-21 05:07:59 +08:00
|
|
|
bias_source = ADCX140_MIC_BIAS_VAL_VREF;
|
2020-09-16 03:06:01 +08:00
|
|
|
adcx140->micbias_vg = false;
|
|
|
|
|
} else {
|
|
|
|
|
adcx140->micbias_vg = true;
|
2020-02-21 05:07:59 +08:00
|
|
|
}
|
|
|
|
|
|
2020-05-13 22:28:07 +08:00
|
|
|
ret = device_property_read_u32(adcx140->dev, "ti,vref-source",
|
2020-02-21 05:07:59 +08:00
|
|
|
&vref_source);
|
|
|
|
|
if (ret)
|
|
|
|
|
vref_source = ADCX140_MIC_BIAS_VREF_275V;
|
|
|
|
|
|
2020-05-27 01:52:47 +08:00
|
|
|
if (vref_source > ADCX140_MIC_BIAS_VREF_1375V) {
|
2020-02-21 05:07:59 +08:00
|
|
|
dev_err(adcx140->dev, "Mic Bias source value is invalid\n");
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
2020-05-13 22:28:07 +08:00
|
|
|
bias_cfg = bias_source << ADCX140_MIC_BIAS_SHIFT | vref_source;
|
2020-02-21 05:07:59 +08:00
|
|
|
|
2020-07-30 22:24:19 +08:00
|
|
|
ret = adcx140_reset(adcx140);
|
|
|
|
|
if (ret)
|
|
|
|
|
goto out;
|
|
|
|
|
|
2020-09-08 16:35:21 +08:00
|
|
|
if (adcx140->supply_areg == NULL)
|
|
|
|
|
sleep_cfg_val |= ADCX140_AREG_INTERNAL;
|
|
|
|
|
|
|
|
|
|
ret = regmap_write(adcx140->regmap, ADCX140_SLEEP_CFG, sleep_cfg_val);
|
|
|
|
|
if (ret) {
|
|
|
|
|
dev_err(adcx140->dev, "setting sleep config failed %d\n", ret);
|
|
|
|
|
goto out;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* 8.4.3: Wait >= 1ms after entering active mode. */
|
|
|
|
|
usleep_range(1000, 100000);
|
|
|
|
|
|
2020-05-14 20:33:38 +08:00
|
|
|
pdm_count = device_property_count_u32(adcx140->dev,
|
|
|
|
|
"ti,pdm-edge-select");
|
|
|
|
|
if (pdm_count <= ADCX140_NUM_PDM_EDGES && pdm_count > 0) {
|
|
|
|
|
ret = device_property_read_u32_array(adcx140->dev,
|
|
|
|
|
"ti,pdm-edge-select",
|
|
|
|
|
pdm_edges, pdm_count);
|
|
|
|
|
if (ret)
|
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < pdm_count; i++)
|
|
|
|
|
pdm_edge_val |= pdm_edges[i] << (ADCX140_PDM_EDGE_SHIFT - i);
|
|
|
|
|
|
|
|
|
|
ret = regmap_write(adcx140->regmap, ADCX140_PDM_CFG,
|
|
|
|
|
pdm_edge_val);
|
|
|
|
|
if (ret)
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
2020-05-27 04:09:17 +08:00
|
|
|
gpi_count = device_property_count_u32(adcx140->dev, "ti,gpi-config");
|
|
|
|
|
if (gpi_count <= ADCX140_NUM_GPI_PINS && gpi_count > 0) {
|
|
|
|
|
ret = device_property_read_u32_array(adcx140->dev,
|
|
|
|
|
"ti,gpi-config",
|
|
|
|
|
gpi_inputs, gpi_count);
|
|
|
|
|
if (ret)
|
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
|
|
gpi_input_val = gpi_inputs[ADCX140_GPI1_INDEX] << ADCX140_GPI_SHIFT |
|
|
|
|
|
gpi_inputs[ADCX140_GPI2_INDEX];
|
|
|
|
|
|
|
|
|
|
ret = regmap_write(adcx140->regmap, ADCX140_GPI_CFG0,
|
|
|
|
|
gpi_input_val);
|
|
|
|
|
if (ret)
|
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
|
|
gpi_input_val = gpi_inputs[ADCX140_GPI3_INDEX] << ADCX140_GPI_SHIFT |
|
|
|
|
|
gpi_inputs[ADCX140_GPI4_INDEX];
|
|
|
|
|
|
|
|
|
|
ret = regmap_write(adcx140->regmap, ADCX140_GPI_CFG1,
|
|
|
|
|
gpi_input_val);
|
|
|
|
|
if (ret)
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
ASoC: tlv320adcx140: Add support for configuring GPIO pin
Add support to configure the GPIO pin to the specific configuration.
The GPIO pin can be configured as GPO, IRQ, SDOUT2, PDMCLK, MICBASE_EN,
GPI, MCLK, SDIN, PDMDIN1, PDMDIN2, PDMDIN3 or PDMDIN4 and the output
drive can be configured with various configuration.
Signed-off-by: Camel Guo <camelg@axis.com>
Link: https://lore.kernel.org/r/20200918114025.18205-2-camel.guo@axis.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2020-09-18 19:40:25 +08:00
|
|
|
ret = adcx140_configure_gpio(adcx140);
|
|
|
|
|
if (ret)
|
|
|
|
|
return ret;
|
|
|
|
|
|
2020-07-29 00:08:33 +08:00
|
|
|
ret = adcx140_configure_gpo(adcx140);
|
|
|
|
|
if (ret)
|
|
|
|
|
goto out;
|
|
|
|
|
|
2020-02-21 05:07:59 +08:00
|
|
|
ret = regmap_update_bits(adcx140->regmap, ADCX140_BIAS_CFG,
|
|
|
|
|
ADCX140_MIC_BIAS_VAL_MSK |
|
2020-05-13 22:28:07 +08:00
|
|
|
ADCX140_MIC_BIAS_VREF_MSK, bias_cfg);
|
2020-02-21 05:07:59 +08:00
|
|
|
if (ret)
|
|
|
|
|
dev_err(adcx140->dev, "setting MIC bias failed %d\n", ret);
|
2020-09-16 03:06:01 +08:00
|
|
|
|
2020-09-16 03:06:04 +08:00
|
|
|
tx_high_z = device_property_read_bool(adcx140->dev, "ti,asi-tx-drive");
|
|
|
|
|
if (tx_high_z) {
|
|
|
|
|
ret = regmap_update_bits(adcx140->regmap, ADCX140_ASI_CFG0,
|
|
|
|
|
ADCX140_TX_FILL, ADCX140_TX_FILL);
|
|
|
|
|
if (ret) {
|
|
|
|
|
dev_err(adcx140->dev, "Setting Tx drive failed %d\n", ret);
|
|
|
|
|
goto out;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2020-09-16 03:06:01 +08:00
|
|
|
adcx140_pwr_ctrl(adcx140, true);
|
2020-02-21 05:07:59 +08:00
|
|
|
out:
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int adcx140_set_bias_level(struct snd_soc_component *component,
|
|
|
|
|
enum snd_soc_bias_level level)
|
|
|
|
|
{
|
|
|
|
|
struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(component);
|
|
|
|
|
|
|
|
|
|
switch (level) {
|
|
|
|
|
case SND_SOC_BIAS_ON:
|
|
|
|
|
case SND_SOC_BIAS_PREPARE:
|
|
|
|
|
case SND_SOC_BIAS_STANDBY:
|
2020-09-16 03:06:01 +08:00
|
|
|
adcx140_pwr_ctrl(adcx140, true);
|
2020-02-21 05:07:59 +08:00
|
|
|
break;
|
|
|
|
|
case SND_SOC_BIAS_OFF:
|
2020-09-16 03:06:01 +08:00
|
|
|
adcx140_pwr_ctrl(adcx140, false);
|
2020-02-21 05:07:59 +08:00
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
2020-09-16 03:06:01 +08:00
|
|
|
return 0;
|
2020-02-21 05:07:59 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static const struct snd_soc_component_driver soc_codec_driver_adcx140 = {
|
|
|
|
|
.probe = adcx140_codec_probe,
|
|
|
|
|
.set_bias_level = adcx140_set_bias_level,
|
|
|
|
|
.controls = adcx140_snd_controls,
|
|
|
|
|
.num_controls = ARRAY_SIZE(adcx140_snd_controls),
|
|
|
|
|
.dapm_widgets = adcx140_dapm_widgets,
|
|
|
|
|
.num_dapm_widgets = ARRAY_SIZE(adcx140_dapm_widgets),
|
|
|
|
|
.dapm_routes = adcx140_audio_map,
|
|
|
|
|
.num_dapm_routes = ARRAY_SIZE(adcx140_audio_map),
|
|
|
|
|
.suspend_bias_off = 1,
|
|
|
|
|
.idle_bias_on = 0,
|
|
|
|
|
.use_pmdown_time = 1,
|
|
|
|
|
.endianness = 1,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static struct snd_soc_dai_driver adcx140_dai_driver[] = {
|
|
|
|
|
{
|
|
|
|
|
.name = "tlv320adcx140-codec",
|
|
|
|
|
.capture = {
|
|
|
|
|
.stream_name = "Capture",
|
|
|
|
|
.channels_min = 2,
|
|
|
|
|
.channels_max = ADCX140_MAX_CHANNELS,
|
|
|
|
|
.rates = ADCX140_RATES,
|
|
|
|
|
.formats = ADCX140_FORMATS,
|
|
|
|
|
},
|
|
|
|
|
.ops = &adcx140_dai_ops,
|
2021-01-15 12:54:17 +08:00
|
|
|
.symmetric_rate = 1,
|
2020-02-21 05:07:59 +08:00
|
|
|
}
|
|
|
|
|
};
|
|
|
|
|
|
2020-11-26 00:44:44 +08:00
|
|
|
#ifdef CONFIG_OF
|
2020-02-21 05:07:59 +08:00
|
|
|
static const struct of_device_id tlv320adcx140_of_match[] = {
|
|
|
|
|
{ .compatible = "ti,tlv320adc3140" },
|
|
|
|
|
{ .compatible = "ti,tlv320adc5140" },
|
|
|
|
|
{ .compatible = "ti,tlv320adc6140" },
|
|
|
|
|
{},
|
|
|
|
|
};
|
|
|
|
|
MODULE_DEVICE_TABLE(of, tlv320adcx140_of_match);
|
2020-11-26 00:44:44 +08:00
|
|
|
#endif
|
2020-02-21 05:07:59 +08:00
|
|
|
|
2022-05-10 13:30:31 +08:00
|
|
|
static void adcx140_disable_regulator(void *arg)
|
|
|
|
|
{
|
|
|
|
|
struct adcx140_priv *adcx140 = arg;
|
|
|
|
|
|
|
|
|
|
regulator_disable(adcx140->supply_areg);
|
|
|
|
|
}
|
|
|
|
|
|
2022-04-06 00:58:34 +08:00
|
|
|
static int adcx140_i2c_probe(struct i2c_client *i2c)
|
2020-02-21 05:07:59 +08:00
|
|
|
{
|
|
|
|
|
struct adcx140_priv *adcx140;
|
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
|
|
adcx140 = devm_kzalloc(&i2c->dev, sizeof(*adcx140), GFP_KERNEL);
|
|
|
|
|
if (!adcx140)
|
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
2022-08-15 19:27:15 +08:00
|
|
|
adcx140->phase_calib_on = false;
|
2020-09-01 21:57:35 +08:00
|
|
|
adcx140->dev = &i2c->dev;
|
|
|
|
|
|
2020-02-21 05:07:59 +08:00
|
|
|
adcx140->gpio_reset = devm_gpiod_get_optional(adcx140->dev,
|
|
|
|
|
"reset", GPIOD_OUT_LOW);
|
|
|
|
|
if (IS_ERR(adcx140->gpio_reset))
|
|
|
|
|
dev_info(&i2c->dev, "Reset GPIO not defined\n");
|
|
|
|
|
|
|
|
|
|
adcx140->supply_areg = devm_regulator_get_optional(adcx140->dev,
|
|
|
|
|
"areg");
|
|
|
|
|
if (IS_ERR(adcx140->supply_areg)) {
|
|
|
|
|
if (PTR_ERR(adcx140->supply_areg) == -EPROBE_DEFER)
|
|
|
|
|
return -EPROBE_DEFER;
|
2020-07-29 00:43:39 +08:00
|
|
|
|
|
|
|
|
adcx140->supply_areg = NULL;
|
2020-02-21 05:07:59 +08:00
|
|
|
} else {
|
|
|
|
|
ret = regulator_enable(adcx140->supply_areg);
|
|
|
|
|
if (ret) {
|
|
|
|
|
dev_err(adcx140->dev, "Failed to enable areg\n");
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
2022-05-10 13:30:31 +08:00
|
|
|
|
|
|
|
|
ret = devm_add_action_or_reset(&i2c->dev, adcx140_disable_regulator, adcx140);
|
|
|
|
|
if (ret)
|
|
|
|
|
return ret;
|
2020-02-21 05:07:59 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
adcx140->regmap = devm_regmap_init_i2c(i2c, &adcx140_i2c_regmap);
|
|
|
|
|
if (IS_ERR(adcx140->regmap)) {
|
|
|
|
|
ret = PTR_ERR(adcx140->regmap);
|
|
|
|
|
dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
|
|
|
|
|
ret);
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
2020-09-01 21:57:35 +08:00
|
|
|
|
2020-02-21 05:07:59 +08:00
|
|
|
i2c_set_clientdata(i2c, adcx140);
|
|
|
|
|
|
|
|
|
|
return devm_snd_soc_register_component(&i2c->dev,
|
|
|
|
|
&soc_codec_driver_adcx140,
|
|
|
|
|
adcx140_dai_driver, 1);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static const struct i2c_device_id adcx140_i2c_id[] = {
|
|
|
|
|
{ "tlv320adc3140", 0 },
|
|
|
|
|
{ "tlv320adc5140", 1 },
|
|
|
|
|
{ "tlv320adc6140", 2 },
|
|
|
|
|
{}
|
|
|
|
|
};
|
|
|
|
|
MODULE_DEVICE_TABLE(i2c, adcx140_i2c_id);
|
|
|
|
|
|
|
|
|
|
static struct i2c_driver adcx140_i2c_driver = {
|
|
|
|
|
.driver = {
|
|
|
|
|
.name = "tlv320adcx140-codec",
|
|
|
|
|
.of_match_table = of_match_ptr(tlv320adcx140_of_match),
|
|
|
|
|
},
|
2023-04-25 17:57:16 +08:00
|
|
|
.probe = adcx140_i2c_probe,
|
2020-02-21 05:07:59 +08:00
|
|
|
.id_table = adcx140_i2c_id,
|
|
|
|
|
};
|
|
|
|
|
module_i2c_driver(adcx140_i2c_driver);
|
|
|
|
|
|
|
|
|
|
MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com>");
|
|
|
|
|
MODULE_DESCRIPTION("ASoC TLV320ADCX140 CODEC Driver");
|
|
|
|
|
MODULE_LICENSE("GPL v2");
|
