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https://git.kernel.org/pub/scm/bluetooth/bluez.git
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01084686e1
In the case of scale factors calculation optimizations, the inline assembly code has instructions which update flags register, but "cc" was not mentioned in the clobber list. When optimizing code, gcc theoretically is allowed to do a comparison before the inline assembly block, and a conditional branch after it which would lead to a problem if the flags register gets clobbered. While this is apparently not happening in practice with the current versions of gcc, the clobber list needs to be corrected. Regarding the other inline assembly blocks. While most likely it is actually unnecessary based on quick review, "cc" is also added there to the clobber list because it should have no impact on performance in practice. It's kind of cargo cult, but relieves us from the need to track the potential updates of flags register in all these places.
376 lines
10 KiB
C
376 lines
10 KiB
C
/*
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*
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* Bluetooth low-complexity, subband codec (SBC) library
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*
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* Copyright (C) 2008-2010 Nokia Corporation
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* Copyright (C) 2004-2010 Marcel Holtmann <marcel@holtmann.org>
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* Copyright (C) 2004-2005 Henryk Ploetz <henryk@ploetzli.ch>
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* Copyright (C) 2005-2006 Brad Midgley <bmidgley@xmission.com>
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*
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*
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*/
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#include <stdint.h>
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#include <limits.h>
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#include "sbc.h"
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#include "sbc_math.h"
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#include "sbc_tables.h"
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#include "sbc_primitives_mmx.h"
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/*
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* MMX optimizations
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*/
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#ifdef SBC_BUILD_WITH_MMX_SUPPORT
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static inline void sbc_analyze_four_mmx(const int16_t *in, int32_t *out,
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const FIXED_T *consts)
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{
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static const SBC_ALIGNED int32_t round_c[2] = {
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1 << (SBC_PROTO_FIXED4_SCALE - 1),
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1 << (SBC_PROTO_FIXED4_SCALE - 1),
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};
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asm volatile (
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"movq (%0), %%mm0\n"
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"movq 8(%0), %%mm1\n"
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"pmaddwd (%1), %%mm0\n"
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"pmaddwd 8(%1), %%mm1\n"
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"paddd (%2), %%mm0\n"
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"paddd (%2), %%mm1\n"
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"\n"
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"movq 16(%0), %%mm2\n"
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"movq 24(%0), %%mm3\n"
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"pmaddwd 16(%1), %%mm2\n"
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"pmaddwd 24(%1), %%mm3\n"
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"paddd %%mm2, %%mm0\n"
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"paddd %%mm3, %%mm1\n"
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"\n"
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"movq 32(%0), %%mm2\n"
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"movq 40(%0), %%mm3\n"
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"pmaddwd 32(%1), %%mm2\n"
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"pmaddwd 40(%1), %%mm3\n"
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"paddd %%mm2, %%mm0\n"
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"paddd %%mm3, %%mm1\n"
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"\n"
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"movq 48(%0), %%mm2\n"
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"movq 56(%0), %%mm3\n"
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"pmaddwd 48(%1), %%mm2\n"
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"pmaddwd 56(%1), %%mm3\n"
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"paddd %%mm2, %%mm0\n"
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"paddd %%mm3, %%mm1\n"
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"\n"
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"movq 64(%0), %%mm2\n"
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"movq 72(%0), %%mm3\n"
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"pmaddwd 64(%1), %%mm2\n"
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"pmaddwd 72(%1), %%mm3\n"
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"paddd %%mm2, %%mm0\n"
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"paddd %%mm3, %%mm1\n"
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"\n"
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"psrad %4, %%mm0\n"
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"psrad %4, %%mm1\n"
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"packssdw %%mm0, %%mm0\n"
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"packssdw %%mm1, %%mm1\n"
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"\n"
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"movq %%mm0, %%mm2\n"
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"pmaddwd 80(%1), %%mm0\n"
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"pmaddwd 88(%1), %%mm2\n"
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"\n"
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"movq %%mm1, %%mm3\n"
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"pmaddwd 96(%1), %%mm1\n"
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"pmaddwd 104(%1), %%mm3\n"
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"paddd %%mm1, %%mm0\n"
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"paddd %%mm3, %%mm2\n"
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"\n"
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"movq %%mm0, (%3)\n"
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"movq %%mm2, 8(%3)\n"
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:
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: "r" (in), "r" (consts), "r" (&round_c), "r" (out),
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"i" (SBC_PROTO_FIXED4_SCALE)
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: "cc", "memory");
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}
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static inline void sbc_analyze_eight_mmx(const int16_t *in, int32_t *out,
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const FIXED_T *consts)
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{
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static const SBC_ALIGNED int32_t round_c[2] = {
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1 << (SBC_PROTO_FIXED8_SCALE - 1),
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1 << (SBC_PROTO_FIXED8_SCALE - 1),
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};
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asm volatile (
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"movq (%0), %%mm0\n"
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"movq 8(%0), %%mm1\n"
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"movq 16(%0), %%mm2\n"
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"movq 24(%0), %%mm3\n"
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"pmaddwd (%1), %%mm0\n"
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"pmaddwd 8(%1), %%mm1\n"
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"pmaddwd 16(%1), %%mm2\n"
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"pmaddwd 24(%1), %%mm3\n"
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"paddd (%2), %%mm0\n"
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"paddd (%2), %%mm1\n"
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"paddd (%2), %%mm2\n"
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"paddd (%2), %%mm3\n"
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"\n"
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"movq 32(%0), %%mm4\n"
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"movq 40(%0), %%mm5\n"
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"movq 48(%0), %%mm6\n"
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"movq 56(%0), %%mm7\n"
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"pmaddwd 32(%1), %%mm4\n"
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"pmaddwd 40(%1), %%mm5\n"
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"pmaddwd 48(%1), %%mm6\n"
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"pmaddwd 56(%1), %%mm7\n"
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"paddd %%mm4, %%mm0\n"
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"paddd %%mm5, %%mm1\n"
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"paddd %%mm6, %%mm2\n"
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"paddd %%mm7, %%mm3\n"
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"\n"
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"movq 64(%0), %%mm4\n"
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"movq 72(%0), %%mm5\n"
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"movq 80(%0), %%mm6\n"
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"movq 88(%0), %%mm7\n"
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"pmaddwd 64(%1), %%mm4\n"
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"pmaddwd 72(%1), %%mm5\n"
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"pmaddwd 80(%1), %%mm6\n"
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"pmaddwd 88(%1), %%mm7\n"
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"paddd %%mm4, %%mm0\n"
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"paddd %%mm5, %%mm1\n"
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"paddd %%mm6, %%mm2\n"
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"paddd %%mm7, %%mm3\n"
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"\n"
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"movq 96(%0), %%mm4\n"
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"movq 104(%0), %%mm5\n"
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"movq 112(%0), %%mm6\n"
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"movq 120(%0), %%mm7\n"
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"pmaddwd 96(%1), %%mm4\n"
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"pmaddwd 104(%1), %%mm5\n"
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"pmaddwd 112(%1), %%mm6\n"
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"pmaddwd 120(%1), %%mm7\n"
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"paddd %%mm4, %%mm0\n"
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"paddd %%mm5, %%mm1\n"
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"paddd %%mm6, %%mm2\n"
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"paddd %%mm7, %%mm3\n"
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"\n"
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"movq 128(%0), %%mm4\n"
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"movq 136(%0), %%mm5\n"
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"movq 144(%0), %%mm6\n"
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"movq 152(%0), %%mm7\n"
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"pmaddwd 128(%1), %%mm4\n"
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"pmaddwd 136(%1), %%mm5\n"
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"pmaddwd 144(%1), %%mm6\n"
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"pmaddwd 152(%1), %%mm7\n"
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"paddd %%mm4, %%mm0\n"
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"paddd %%mm5, %%mm1\n"
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"paddd %%mm6, %%mm2\n"
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"paddd %%mm7, %%mm3\n"
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"\n"
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"psrad %4, %%mm0\n"
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"psrad %4, %%mm1\n"
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"psrad %4, %%mm2\n"
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"psrad %4, %%mm3\n"
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"\n"
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"packssdw %%mm0, %%mm0\n"
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"packssdw %%mm1, %%mm1\n"
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"packssdw %%mm2, %%mm2\n"
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"packssdw %%mm3, %%mm3\n"
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"\n"
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"movq %%mm0, %%mm4\n"
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"movq %%mm0, %%mm5\n"
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"pmaddwd 160(%1), %%mm4\n"
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"pmaddwd 168(%1), %%mm5\n"
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"\n"
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"movq %%mm1, %%mm6\n"
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"movq %%mm1, %%mm7\n"
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"pmaddwd 192(%1), %%mm6\n"
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"pmaddwd 200(%1), %%mm7\n"
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"paddd %%mm6, %%mm4\n"
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"paddd %%mm7, %%mm5\n"
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"\n"
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"movq %%mm2, %%mm6\n"
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"movq %%mm2, %%mm7\n"
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"pmaddwd 224(%1), %%mm6\n"
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"pmaddwd 232(%1), %%mm7\n"
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"paddd %%mm6, %%mm4\n"
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"paddd %%mm7, %%mm5\n"
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"\n"
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"movq %%mm3, %%mm6\n"
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"movq %%mm3, %%mm7\n"
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"pmaddwd 256(%1), %%mm6\n"
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"pmaddwd 264(%1), %%mm7\n"
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"paddd %%mm6, %%mm4\n"
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"paddd %%mm7, %%mm5\n"
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"\n"
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"movq %%mm4, (%3)\n"
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"movq %%mm5, 8(%3)\n"
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"\n"
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"movq %%mm0, %%mm5\n"
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"pmaddwd 176(%1), %%mm0\n"
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"pmaddwd 184(%1), %%mm5\n"
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"\n"
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"movq %%mm1, %%mm7\n"
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"pmaddwd 208(%1), %%mm1\n"
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"pmaddwd 216(%1), %%mm7\n"
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"paddd %%mm1, %%mm0\n"
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"paddd %%mm7, %%mm5\n"
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"\n"
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"movq %%mm2, %%mm7\n"
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"pmaddwd 240(%1), %%mm2\n"
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"pmaddwd 248(%1), %%mm7\n"
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"paddd %%mm2, %%mm0\n"
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"paddd %%mm7, %%mm5\n"
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"\n"
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"movq %%mm3, %%mm7\n"
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"pmaddwd 272(%1), %%mm3\n"
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"pmaddwd 280(%1), %%mm7\n"
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"paddd %%mm3, %%mm0\n"
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"paddd %%mm7, %%mm5\n"
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"\n"
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"movq %%mm0, 16(%3)\n"
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"movq %%mm5, 24(%3)\n"
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:
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: "r" (in), "r" (consts), "r" (&round_c), "r" (out),
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"i" (SBC_PROTO_FIXED8_SCALE)
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: "cc", "memory");
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}
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static inline void sbc_analyze_4b_4s_mmx(int16_t *x, int32_t *out,
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int out_stride)
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{
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/* Analyze blocks */
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sbc_analyze_four_mmx(x + 12, out, analysis_consts_fixed4_simd_odd);
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out += out_stride;
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sbc_analyze_four_mmx(x + 8, out, analysis_consts_fixed4_simd_even);
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out += out_stride;
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sbc_analyze_four_mmx(x + 4, out, analysis_consts_fixed4_simd_odd);
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out += out_stride;
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sbc_analyze_four_mmx(x + 0, out, analysis_consts_fixed4_simd_even);
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asm volatile ("emms\n");
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}
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static inline void sbc_analyze_4b_8s_mmx(int16_t *x, int32_t *out,
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int out_stride)
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{
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/* Analyze blocks */
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sbc_analyze_eight_mmx(x + 24, out, analysis_consts_fixed8_simd_odd);
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out += out_stride;
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sbc_analyze_eight_mmx(x + 16, out, analysis_consts_fixed8_simd_even);
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out += out_stride;
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sbc_analyze_eight_mmx(x + 8, out, analysis_consts_fixed8_simd_odd);
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out += out_stride;
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sbc_analyze_eight_mmx(x + 0, out, analysis_consts_fixed8_simd_even);
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asm volatile ("emms\n");
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}
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static void sbc_calc_scalefactors_mmx(
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int32_t sb_sample_f[16][2][8],
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uint32_t scale_factor[2][8],
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int blocks, int channels, int subbands)
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{
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static const SBC_ALIGNED int32_t consts[2] = {
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1 << SCALE_OUT_BITS,
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1 << SCALE_OUT_BITS,
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};
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int ch, sb;
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intptr_t blk;
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for (ch = 0; ch < channels; ch++) {
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for (sb = 0; sb < subbands; sb += 2) {
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blk = (blocks - 1) * (((char *) &sb_sample_f[1][0][0] -
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(char *) &sb_sample_f[0][0][0]));
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asm volatile (
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"movq (%4), %%mm0\n"
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"1:\n"
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"movq (%1, %0), %%mm1\n"
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"pxor %%mm2, %%mm2\n"
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"pcmpgtd %%mm2, %%mm1\n"
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"paddd (%1, %0), %%mm1\n"
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"pcmpgtd %%mm1, %%mm2\n"
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"pxor %%mm2, %%mm1\n"
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"por %%mm1, %%mm0\n"
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"sub %2, %0\n"
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"jns 1b\n"
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"movd %%mm0, %k0\n"
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"psrlq $32, %%mm0\n"
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"bsrl %k0, %k0\n"
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"subl %5, %k0\n"
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"movl %k0, (%3)\n"
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"movd %%mm0, %k0\n"
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"bsrl %k0, %k0\n"
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"subl %5, %k0\n"
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"movl %k0, 4(%3)\n"
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: "+r" (blk)
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: "r" (&sb_sample_f[0][ch][sb]),
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"i" ((char *) &sb_sample_f[1][0][0] -
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(char *) &sb_sample_f[0][0][0]),
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"r" (&scale_factor[ch][sb]),
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"r" (&consts),
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"i" (SCALE_OUT_BITS)
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: "cc", "memory");
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}
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}
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asm volatile ("emms\n");
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}
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static int check_mmx_support(void)
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{
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#ifdef __amd64__
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return 1; /* We assume that all 64-bit processors have MMX support */
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#else
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int cpuid_feature_information;
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asm volatile (
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/* According to Intel manual, CPUID instruction is supported
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* if the value of ID bit (bit 21) in EFLAGS can be modified */
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"pushf\n"
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"movl (%%esp), %0\n"
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"xorl $0x200000, (%%esp)\n" /* try to modify ID bit */
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"popf\n"
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"pushf\n"
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"xorl (%%esp), %0\n" /* check if ID bit changed */
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"jz 1f\n"
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"push %%eax\n"
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"push %%ebx\n"
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"push %%ecx\n"
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"mov $1, %%eax\n"
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"cpuid\n"
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"pop %%ecx\n"
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"pop %%ebx\n"
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"pop %%eax\n"
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"1:\n"
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"popf\n"
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: "=d" (cpuid_feature_information)
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:
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: "cc");
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return cpuid_feature_information & (1 << 23);
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#endif
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}
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void sbc_init_primitives_mmx(struct sbc_encoder_state *state)
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{
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if (check_mmx_support()) {
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state->sbc_analyze_4b_4s = sbc_analyze_4b_4s_mmx;
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state->sbc_analyze_4b_8s = sbc_analyze_4b_8s_mmx;
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state->sbc_calc_scalefactors = sbc_calc_scalefactors_mmx;
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state->implementation_info = "MMX";
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}
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}
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#endif
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