revert a commit that causes visual corruption & error messages
This commit is contained in:
parent
f3ff43848a
commit
df473fc71d
19
.SRCINFO
19
.SRCINFO
@ -1,6 +1,6 @@
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pkgbase = mesa-git
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pkgbase = mesa-git
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pkgdesc = an open-source implementation of the OpenGL specification, git version
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pkgdesc = an open-source implementation of the OpenGL specification, git version
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pkgver = 19.2.0_devel.111005.e5db87b00b7
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pkgver = 19.2.0_devel.111123.daa85a882e8
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pkgrel = 1
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pkgrel = 1
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url = https://www.mesa3d.org
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url = https://www.mesa3d.org
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arch = x86_64
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arch = x86_64
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@ -38,13 +38,13 @@ pkgbase = mesa-git
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depends = glslang
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depends = glslang
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depends = llvm-libs-minimal-git
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depends = llvm-libs-minimal-git
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optdepends = opengl-man-pages: for the OpenGL API man pages
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optdepends = opengl-man-pages: for the OpenGL API man pages
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provides = mesa=19.2.0_devel.111005.e5db87b00b7-1
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provides = mesa=19.2.0_devel.111123.daa85a882e8-1
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provides = vulkan-intel=19.2.0_devel.111005.e5db87b00b7-1
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provides = vulkan-intel=19.2.0_devel.111123.daa85a882e8-1
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provides = vulkan-radeon=19.2.0_devel.111005.e5db87b00b7-1
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provides = vulkan-radeon=19.2.0_devel.111123.daa85a882e8-1
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provides = libva-mesa-driver=19.2.0_devel.111005.e5db87b00b7-1
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provides = libva-mesa-driver=19.2.0_devel.111123.daa85a882e8-1
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provides = mesa-vdpau=19.2.0_devel.111005.e5db87b00b7-1
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provides = mesa-vdpau=19.2.0_devel.111123.daa85a882e8-1
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provides = vulkan-driver=19.2.0_devel.111005.e5db87b00b7-1
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provides = vulkan-driver=19.2.0_devel.111123.daa85a882e8-1
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provides = opencl-mesa=19.2.0_devel.111005.e5db87b00b7-1
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provides = opencl-mesa=19.2.0_devel.111123.daa85a882e8-1
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provides = opengl-driver
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provides = opengl-driver
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provides = opencl-driver
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provides = opencl-driver
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conflicts = mesa
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conflicts = mesa
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@ -55,10 +55,13 @@ pkgbase = mesa-git
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conflicts = mesa-vdpau
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conflicts = mesa-vdpau
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source = mesa::git://anongit.freedesktop.org/mesa/mesa
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source = mesa::git://anongit.freedesktop.org/mesa/mesa
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source = LICENSE
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source = LICENSE
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source = radeonsi: update buffer descriptors in all contexts after buffer invalidation 78e35df52aa2f7d770f929a0866a0faa89c261a9.patch
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md5sums = SKIP
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md5sums = SKIP
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md5sums = 5c65a0fe315dd347e09b1f2826a1df5a
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md5sums = 5c65a0fe315dd347e09b1f2826a1df5a
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md5sums = 0cf986d1e8a664c2aa231cbfbe3c4b13
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sha512sums = SKIP
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sha512sums = SKIP
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sha512sums = 25da77914dded10c1f432ebcbf29941124138824ceecaf1367b3deedafaecabc082d463abcfa3d15abff59f177491472b505bcb5ba0c4a51bb6b93b4721a23c2
|
sha512sums = 25da77914dded10c1f432ebcbf29941124138824ceecaf1367b3deedafaecabc082d463abcfa3d15abff59f177491472b505bcb5ba0c4a51bb6b93b4721a23c2
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|
sha512sums = e29d60885bcca64333bc0be618d77db3ef02fc653f67ed00204623cb522bd05ea81aaaac0dc3fe0f4a22b3fd9d485c34f152b9f3228947dc0c4ea51179e1e5e6
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pkgname = mesa-git
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pkgname = mesa-git
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13
PKGBUILD
13
PKGBUILD
@ -11,7 +11,7 @@
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pkgname=mesa-git
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pkgname=mesa-git
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pkgdesc="an open-source implementation of the OpenGL specification, git version"
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pkgdesc="an open-source implementation of the OpenGL specification, git version"
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pkgver=19.2.0_devel.111005.e5db87b00b7
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pkgver=19.2.0_devel.111123.daa85a882e8
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pkgrel=1
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pkgrel=1
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arch=('x86_64')
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arch=('x86_64')
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makedepends=('git' 'python-mako' 'xorgproto'
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makedepends=('git' 'python-mako' 'xorgproto'
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@ -25,11 +25,14 @@ conflicts=('mesa' 'opencl-mesa' 'vulkan-intel' 'vulkan-radeon' 'libva-mesa-drive
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url="https://www.mesa3d.org"
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url="https://www.mesa3d.org"
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license=('custom')
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license=('custom')
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source=('mesa::git://anongit.freedesktop.org/mesa/mesa'
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source=('mesa::git://anongit.freedesktop.org/mesa/mesa'
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'LICENSE')
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'LICENSE'
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'radeonsi: update buffer descriptors in all contexts after buffer invalidation 78e35df52aa2f7d770f929a0866a0faa89c261a9.patch')
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md5sums=('SKIP'
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md5sums=('SKIP'
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'5c65a0fe315dd347e09b1f2826a1df5a')
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'5c65a0fe315dd347e09b1f2826a1df5a'
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'0cf986d1e8a664c2aa231cbfbe3c4b13')
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sha512sums=('SKIP'
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sha512sums=('SKIP'
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'25da77914dded10c1f432ebcbf29941124138824ceecaf1367b3deedafaecabc082d463abcfa3d15abff59f177491472b505bcb5ba0c4a51bb6b93b4721a23c2')
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'25da77914dded10c1f432ebcbf29941124138824ceecaf1367b3deedafaecabc082d463abcfa3d15abff59f177491472b505bcb5ba0c4a51bb6b93b4721a23c2'
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'e29d60885bcca64333bc0be618d77db3ef02fc653f67ed00204623cb522bd05ea81aaaac0dc3fe0f4a22b3fd9d485c34f152b9f3228947dc0c4ea51179e1e5e6')
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# MESA_WHICH_LLVM is an environment variable used to determine which llvm package tree is used to built mesa-git against.
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# MESA_WHICH_LLVM is an environment variable used to determine which llvm package tree is used to built mesa-git against.
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# Adding a line to makepkg.conf that sets this value is the simplest way to ensure a specific choice.
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# Adding a line to makepkg.conf that sets this value is the simplest way to ensure a specific choice.
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@ -83,6 +86,8 @@ prepare() {
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if [ -d _build ]; then
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if [ -d _build ]; then
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rm -rf _build
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rm -rf _build
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fi
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fi
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cd mesa
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patch --reverse -Np1 -i $srcdir/'radeonsi: update buffer descriptors in all contexts after buffer invalidation 78e35df52aa2f7d770f929a0866a0faa89c261a9.patch'
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}
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}
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build () {
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build () {
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@ -0,0 +1,324 @@
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From 78e35df52aa2f7d770f929a0866a0faa89c261a9 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= <marek.olsak@amd.com>
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Date: Fri, 10 May 2019 01:14:07 -0400
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Subject: radeonsi: update buffer descriptors in all contexts after buffer
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invalidation
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Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108824
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Cc: 19.1 <mesa-stable@lists.freedesktop.org>
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---
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src/gallium/drivers/radeonsi/si_descriptors.c | 94 ++++++++++++++++++---------
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src/gallium/drivers/radeonsi/si_pipe.h | 2 +
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src/gallium/drivers/radeonsi/si_state_draw.c | 9 ++-
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3 files changed, 72 insertions(+), 33 deletions(-)
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diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
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index 14c1306..501f4c1 100644
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--- a/src/gallium/drivers/radeonsi/si_descriptors.c
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+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
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@@ -1573,7 +1573,9 @@ void si_update_needs_color_decompress_masks(struct si_context *sctx)
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/* BUFFER DISCARD/INVALIDATION */
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-/** Reset descriptors of buffer resources after \p buf has been invalidated. */
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+/* Reset descriptors of buffer resources after \p buf has been invalidated.
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+ * If buf == NULL, reset all descriptors.
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+ */
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static void si_reset_buffer_resources(struct si_context *sctx,
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struct si_buffer_resources *buffers,
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unsigned descriptors_idx,
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@@ -1586,13 +1588,15 @@ static void si_reset_buffer_resources(struct si_context *sctx,
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while (mask) {
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unsigned i = u_bit_scan(&mask);
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- if (buffers->buffers[i] == buf) {
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- si_set_buf_desc_address(si_resource(buf), buffers->offsets[i],
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+ struct pipe_resource *buffer = buffers->buffers[i];
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+
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+ if (buffer && (!buf || buffer == buf)) {
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+ si_set_buf_desc_address(si_resource(buffer), buffers->offsets[i],
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descs->list + i*4);
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sctx->descriptors_dirty |= 1u << descriptors_idx;
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radeon_add_to_gfx_buffer_list_check_mem(sctx,
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- si_resource(buf),
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+ si_resource(buffer),
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buffers->writable_mask & (1u << i) ?
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RADEON_USAGE_READWRITE :
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RADEON_USAGE_READ,
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@@ -1601,9 +1605,12 @@ static void si_reset_buffer_resources(struct si_context *sctx,
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}
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}
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-/* Update all resource bindings where the buffer is bound, including
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+/* Update all buffer bindings where the buffer is bound, including
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* all resource descriptors. This is invalidate_buffer without
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- * the invalidation. */
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+ * the invalidation.
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+ *
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+ * If buf == NULL, update all buffer bindings.
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+ */
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void si_rebind_buffer(struct si_context *sctx, struct pipe_resource *buf)
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{
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struct si_resource *buffer = si_resource(buf);
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@@ -1618,7 +1625,10 @@ void si_rebind_buffer(struct si_context *sctx, struct pipe_resource *buf)
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*/
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/* Vertex buffers. */
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- if (buffer->bind_history & PIPE_BIND_VERTEX_BUFFER) {
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+ if (!buffer) {
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+ if (num_elems)
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+ sctx->vertex_buffers_dirty = true;
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+ } else if (buffer->bind_history & PIPE_BIND_VERTEX_BUFFER) {
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for (i = 0; i < num_elems; i++) {
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int vb = sctx->vertex_elements->vertex_buffer_index[i];
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@@ -1635,21 +1645,23 @@ void si_rebind_buffer(struct si_context *sctx, struct pipe_resource *buf)
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}
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/* Streamout buffers. (other internal buffers can't be invalidated) */
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- if (buffer->bind_history & PIPE_BIND_STREAM_OUTPUT) {
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+ if (!buffer || buffer->bind_history & PIPE_BIND_STREAM_OUTPUT) {
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for (i = SI_VS_STREAMOUT_BUF0; i <= SI_VS_STREAMOUT_BUF3; i++) {
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struct si_buffer_resources *buffers = &sctx->rw_buffers;
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struct si_descriptors *descs =
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&sctx->descriptors[SI_DESCS_RW_BUFFERS];
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+ struct pipe_resource *buffer = buffers->buffers[i];
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- if (buffers->buffers[i] != buf)
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+ if (!buffer || (buf && buffer != buf))
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continue;
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- si_set_buf_desc_address(si_resource(buf), buffers->offsets[i],
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+ si_set_buf_desc_address(si_resource(buffer), buffers->offsets[i],
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descs->list + i*4);
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sctx->descriptors_dirty |= 1u << SI_DESCS_RW_BUFFERS;
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radeon_add_to_gfx_buffer_list_check_mem(sctx,
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- buffer, RADEON_USAGE_WRITE,
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+ si_resource(buffer),
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+ RADEON_USAGE_WRITE,
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RADEON_PRIO_SHADER_RW_BUFFER,
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true);
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@@ -1663,7 +1675,7 @@ void si_rebind_buffer(struct si_context *sctx, struct pipe_resource *buf)
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}
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/* Constant and shader buffers. */
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- if (buffer->bind_history & PIPE_BIND_CONSTANT_BUFFER) {
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+ if (!buffer || buffer->bind_history & PIPE_BIND_CONSTANT_BUFFER) {
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for (shader = 0; shader < SI_NUM_SHADERS; shader++)
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si_reset_buffer_resources(sctx, &sctx->const_and_shader_buffers[shader],
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si_const_and_shader_buffer_descriptors_idx(shader),
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@@ -1672,7 +1684,7 @@ void si_rebind_buffer(struct si_context *sctx, struct pipe_resource *buf)
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sctx->const_and_shader_buffers[shader].priority_constbuf);
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}
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- if (buffer->bind_history & PIPE_BIND_SHADER_BUFFER) {
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+ if (!buffer || buffer->bind_history & PIPE_BIND_SHADER_BUFFER) {
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for (shader = 0; shader < SI_NUM_SHADERS; shader++)
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si_reset_buffer_resources(sctx, &sctx->const_and_shader_buffers[shader],
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si_const_and_shader_buffer_descriptors_idx(shader),
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@@ -1681,7 +1693,7 @@ void si_rebind_buffer(struct si_context *sctx, struct pipe_resource *buf)
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sctx->const_and_shader_buffers[shader].priority);
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}
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- if (buffer->bind_history & PIPE_BIND_SAMPLER_VIEW) {
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+ if (!buffer || buffer->bind_history & PIPE_BIND_SAMPLER_VIEW) {
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/* Texture buffers - update bindings. */
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for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
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struct si_samplers *samplers = &sctx->samplers[shader];
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@@ -1691,26 +1703,28 @@ void si_rebind_buffer(struct si_context *sctx, struct pipe_resource *buf)
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while (mask) {
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unsigned i = u_bit_scan(&mask);
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- if (samplers->views[i]->texture == buf) {
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+ struct pipe_resource *buffer = samplers->views[i]->texture;
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+
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+ if (buffer && (!buf || buffer == buf)) {
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unsigned desc_slot = si_get_sampler_slot(i);
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- si_set_buf_desc_address(si_resource(buf),
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+ si_set_buf_desc_address(si_resource(buffer),
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samplers->views[i]->u.buf.offset,
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descs->list + desc_slot * 16 + 4);
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sctx->descriptors_dirty |=
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1u << si_sampler_and_image_descriptors_idx(shader);
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- radeon_add_to_gfx_buffer_list_check_mem(sctx,
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- buffer, RADEON_USAGE_READ,
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- RADEON_PRIO_SAMPLER_BUFFER,
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- true);
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+ radeon_add_to_gfx_buffer_list_check_mem(
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+ sctx, si_resource(buffer),
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+ RADEON_USAGE_READ,
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+ RADEON_PRIO_SAMPLER_BUFFER, true);
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}
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}
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}
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}
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/* Shader images */
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- if (buffer->bind_history & PIPE_BIND_SHADER_IMAGE) {
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+ if (!buffer || buffer->bind_history & PIPE_BIND_SHADER_IMAGE) {
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for (shader = 0; shader < SI_NUM_SHADERS; ++shader) {
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struct si_images *images = &sctx->images[shader];
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struct si_descriptors *descs =
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@@ -1719,21 +1733,22 @@ void si_rebind_buffer(struct si_context *sctx, struct pipe_resource *buf)
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while (mask) {
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unsigned i = u_bit_scan(&mask);
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+ struct pipe_resource *buffer = images->views[i].resource;
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- if (images->views[i].resource == buf) {
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+ if (buffer && (!buf || buffer == buf)) {
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unsigned desc_slot = si_get_image_slot(i);
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if (images->views[i].access & PIPE_IMAGE_ACCESS_WRITE)
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si_mark_image_range_valid(&images->views[i]);
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- si_set_buf_desc_address(si_resource(buf),
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+ si_set_buf_desc_address(si_resource(buffer),
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images->views[i].u.buf.offset,
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descs->list + desc_slot * 8 + 4);
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sctx->descriptors_dirty |=
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1u << si_sampler_and_image_descriptors_idx(shader);
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radeon_add_to_gfx_buffer_list_check_mem(
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- sctx, buffer,
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+ sctx, si_resource(buffer),
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RADEON_USAGE_READWRITE,
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RADEON_PRIO_SAMPLER_BUFFER, true);
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}
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@@ -1742,16 +1757,17 @@ void si_rebind_buffer(struct si_context *sctx, struct pipe_resource *buf)
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}
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/* Bindless texture handles */
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- if (buffer->texture_handle_allocated) {
|
||||||
|
+ if (!buffer || buffer->texture_handle_allocated) {
|
||||||
|
struct si_descriptors *descs = &sctx->bindless_descriptors;
|
||||||
|
|
||||||
|
util_dynarray_foreach(&sctx->resident_tex_handles,
|
||||||
|
struct si_texture_handle *, tex_handle) {
|
||||||
|
struct pipe_sampler_view *view = (*tex_handle)->view;
|
||||||
|
unsigned desc_slot = (*tex_handle)->desc_slot;
|
||||||
|
+ struct pipe_resource *buffer = view->texture;
|
||||||
|
|
||||||
|
- if (view->texture == buf) {
|
||||||
|
- si_set_buf_desc_address(buffer,
|
||||||
|
+ if (buffer && (!buf || buffer == buf)) {
|
||||||
|
+ si_set_buf_desc_address(si_resource(buffer),
|
||||||
|
view->u.buf.offset,
|
||||||
|
descs->list +
|
||||||
|
desc_slot * 16 + 4);
|
||||||
|
@@ -1760,7 +1776,7 @@ void si_rebind_buffer(struct si_context *sctx, struct pipe_resource *buf)
|
||||||
|
sctx->bindless_descriptors_dirty = true;
|
||||||
|
|
||||||
|
radeon_add_to_gfx_buffer_list_check_mem(
|
||||||
|
- sctx, buffer,
|
||||||
|
+ sctx, si_resource(buffer),
|
||||||
|
RADEON_USAGE_READ,
|
||||||
|
RADEON_PRIO_SAMPLER_BUFFER, true);
|
||||||
|
}
|
||||||
|
@@ -1768,19 +1784,20 @@ void si_rebind_buffer(struct si_context *sctx, struct pipe_resource *buf)
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Bindless image handles */
|
||||||
|
- if (buffer->image_handle_allocated) {
|
||||||
|
+ if (!buffer || buffer->image_handle_allocated) {
|
||||||
|
struct si_descriptors *descs = &sctx->bindless_descriptors;
|
||||||
|
|
||||||
|
util_dynarray_foreach(&sctx->resident_img_handles,
|
||||||
|
struct si_image_handle *, img_handle) {
|
||||||
|
struct pipe_image_view *view = &(*img_handle)->view;
|
||||||
|
unsigned desc_slot = (*img_handle)->desc_slot;
|
||||||
|
+ struct pipe_resource *buffer = view->resource;
|
||||||
|
|
||||||
|
- if (view->resource == buf) {
|
||||||
|
+ if (buffer && (!buf || buffer == buf)) {
|
||||||
|
if (view->access & PIPE_IMAGE_ACCESS_WRITE)
|
||||||
|
si_mark_image_range_valid(view);
|
||||||
|
|
||||||
|
- si_set_buf_desc_address(buffer,
|
||||||
|
+ si_set_buf_desc_address(si_resource(buffer),
|
||||||
|
view->u.buf.offset,
|
||||||
|
descs->list +
|
||||||
|
desc_slot * 16 + 4);
|
||||||
|
@@ -1789,12 +1806,25 @@ void si_rebind_buffer(struct si_context *sctx, struct pipe_resource *buf)
|
||||||
|
sctx->bindless_descriptors_dirty = true;
|
||||||
|
|
||||||
|
radeon_add_to_gfx_buffer_list_check_mem(
|
||||||
|
- sctx, buffer,
|
||||||
|
+ sctx, si_resource(buffer),
|
||||||
|
RADEON_USAGE_READWRITE,
|
||||||
|
RADEON_PRIO_SAMPLER_BUFFER, true);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
+
|
||||||
|
+ if (buffer) {
|
||||||
|
+ /* Do the same for other contexts. They will invoke this function
|
||||||
|
+ * with buffer == NULL.
|
||||||
|
+ */
|
||||||
|
+ unsigned new_counter = p_atomic_inc_return(&sctx->screen->dirty_buf_counter);
|
||||||
|
+
|
||||||
|
+ /* Skip the update for the current context, because we have already updated
|
||||||
|
+ * the buffer bindings.
|
||||||
|
+ */
|
||||||
|
+ if (new_counter == sctx->last_dirty_buf_counter + 1)
|
||||||
|
+ sctx->last_dirty_buf_counter = new_counter;
|
||||||
|
+ }
|
||||||
|
}
|
||||||
|
|
||||||
|
static void si_upload_bindless_descriptor(struct si_context *sctx,
|
||||||
|
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
|
||||||
|
index c3a62e8..db1f755 100644
|
||||||
|
--- a/src/gallium/drivers/radeonsi/si_pipe.h
|
||||||
|
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
|
||||||
|
@@ -530,6 +530,7 @@ struct si_screen {
|
||||||
|
* the counter before drawing and re-emit the states accordingly.
|
||||||
|
*/
|
||||||
|
unsigned dirty_tex_counter;
|
||||||
|
+ unsigned dirty_buf_counter;
|
||||||
|
|
||||||
|
/* Atomically increment this counter when an existing texture's
|
||||||
|
* metadata is enabled or disabled in a way that requires changing
|
||||||
|
@@ -860,6 +861,7 @@ struct si_context {
|
||||||
|
unsigned initial_gfx_cs_size;
|
||||||
|
unsigned gpu_reset_counter;
|
||||||
|
unsigned last_dirty_tex_counter;
|
||||||
|
+ unsigned last_dirty_buf_counter;
|
||||||
|
unsigned last_compressed_colortex_counter;
|
||||||
|
unsigned last_num_draw_calls;
|
||||||
|
unsigned flags; /* flush flags */
|
||||||
|
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
|
||||||
|
index 7eb1dfb..dba9397 100644
|
||||||
|
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
|
||||||
|
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
|
||||||
|
@@ -1421,7 +1421,7 @@ static void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *i
|
||||||
|
struct si_context *sctx = (struct si_context *)ctx;
|
||||||
|
struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
|
||||||
|
struct pipe_resource *indexbuf = info->index.resource;
|
||||||
|
- unsigned dirty_tex_counter;
|
||||||
|
+ unsigned dirty_tex_counter, dirty_buf_counter;
|
||||||
|
enum pipe_prim_type rast_prim, prim = info->mode;
|
||||||
|
unsigned index_size = info->index_size;
|
||||||
|
unsigned index_offset = info->indirect ? info->start * index_size : 0;
|
||||||
|
@@ -1464,6 +1464,13 @@ static void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *i
|
||||||
|
si_update_all_texture_descriptors(sctx);
|
||||||
|
}
|
||||||
|
|
||||||
|
+ dirty_buf_counter = p_atomic_read(&sctx->screen->dirty_buf_counter);
|
||||||
|
+ if (unlikely(dirty_buf_counter != sctx->last_dirty_buf_counter)) {
|
||||||
|
+ sctx->last_dirty_buf_counter = dirty_buf_counter;
|
||||||
|
+ /* Rebind all buffers unconditionally. */
|
||||||
|
+ si_rebind_buffer(sctx, NULL);
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
si_decompress_textures(sctx, u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS));
|
||||||
|
|
||||||
|
/* Set the rasterization primitive type.
|
||||||
|
--
|
||||||
|
cgit v1.1
|
||||||
|
|
Loading…
Reference in New Issue
Block a user